TMC1203

www.fairchildsemi.com TMC1203 Triple Video A/D Converter 8-Bit, 50Msps Features • • • • • • • • • • • 8-bit resolution 50 Msps conversion rate Low power: 100mW per channel @ 20 Msps Integral track/hold Independent clock inputs Integral and differential linearity error 0.5 LSB Differential phase 0.7 degree Differential gain 1.8% Single +5V power supply Three-state TTL/CMOS-compatible outputs Low cost Applications • • • • • • • • Video digitizing (composite and Y-C) VGA and CCD digitizing LCD projection panels Image scanners Personal computer video boards Multimedia systems Low cost, high speed data conversion Digital communications Description Incorporated into the TMC1203 are three analog-to-digital (A/D) converters, each with independent clocks and reference voltages. Analog signals are converted to Triple 8-bit digital words at sample rates up to 50 Msps (Megasamples per second) per channel. Integral Track/Hold circuits deliver excellent performance on signals with full-scale spectral components up to 12 MHz. Innovative two-step architecture conversion architecture and submicron CMOS technology reduce typical power dissipation to 100 mW per converter. Power is derived from a single +5 Volt power supply. Outputs are three-state outputs and TTL/CMOS-compatible. TMC1203 package is a 80-lead Metric Quad Flat Pack (MQFP). Performance specifications are guaranteed from 0°C to 70°C. Block Diagram RTA VINA RBA CLKA RTB VINB RBB CLKB RTC VINC RBC CLKC 65-3720-01 8-bit A/D Converter DA7-0 OEA 8-bit A/D Converter DB7-0 OEB 8-bit A/D Converter DA7-0 OEC Rev. 1.2.0 TMC1203 PRODUCT SPECIFICATION Circuit Function Within the TMC1203 are three 8-bit A/D converters, each employing two-step architecture to convert an analog input to a digital output at rates up to 50 Msps. Input signals are held in integral track/hold stages during the conversion process. Operation is pipelined, with one input sample taken and one output word provided for each CLKX cycle. Each of the three converters function identically. In the following descriptions ‘X’ refers to a generic input/output or clock where ‘X’ is equivalent to A, B or C. The first step in the conversion process is a coarse 4-bit quantization. This determines the range of the subsequent fine 4-bit quantization step. To eliminate spurious codes, the fine 4-bit A/D quantizer output is gray-coded and converted to binary before it is combined with the coarse result to form a complete 8-bit result. Digital Inputs and Outputs Sampling of the applied input signal occurs on the "falling" edge of the CLKX signal (Figure 1). Output data is delayed by 2 1/2 CLKX cycles and is valid following the "rising" edge of CLKX. Previous output data remains valid for tHO (Output Hold Time), satisfying any hold time requirement of the receiving circuit. New data becomes valid tD (Output Delay Time) after this rising edge of CLKX. Whenever the analog input signal is sampled and found to be at a level beyond the A/D conversion range, the output limits at 00h or FFh, as appropriate. Table 1. A/D Output Coding Input Voltage RTX + 1 LSB RTX RTX - 1 LSB ••• RBX + 128 LSB RBX + 127 LSB ••• RBX + 1 LSB RBX RBX - 1 LSB Note: 1 LSB = (RTX - RBX) / 255 Output FF FF FE ••• 80 7F ••• 01 00 00 Analog Input and Voltage References Each A/D accepts analog signals in the range RBX to RTX into digital data. Input signals outside this range produce “saturated” 00h or FFh output codes. The device will not be damaged by signals within the range AGND to VDDA. Input range is very flexible and extends from the +5 Volt power supply to ground. Nominal input range is 2 Volts, extending from 0.6V to 2.6V. Characterization and performance is specified over this range. However, the part will function with a full-scale range from 1.0V to 5.0V. A smaller input range may simplify analog signal conditioning circuitry, at the expense of additional noise sensitivity and some reduced differential linearity performance. External voltage reference sources are connected to the RTX and RBX pins. RBX can be grounded. Within each A/D converter is a reference resistor ladder comprising 255 resistors that are accessed by the TMC1203 comparators. RTX is connected to the top of the ladder, RBX to the bottom. Gain and offset errors are directly related to the accuracy and stability of the applied reference voltages. Because a two-step conversion process is employed, it is important that the references remain stable during the ENTIRE conversion process (two clock cycles). The reference voltage can then be changed, but any conversion in progress during a reference change is invalid. The outputs of the TMC1203 are CMOS- and TTL-compatible, and are capable of driving four low-power Schottky TTL loads. An Output Enable control, OEX, places the A/D outputs in a high-impedance state when HIGH. The outputs are enabled when OEX is LOW. Power and Ground The TMC1203 operates from a single +5 Volt power supply. For optimum performance, it is recommended that AGND and DGND pins of the TMC1203 be connected to the system analog ground plane. 2 PRODUCT SPECIFICATION TMC1203 Pin Assignments 64 65 41 40 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name NC DA5 DA6 DA7 OEA VDD VDD NC CLKA NC VDDA VINA AGND RTA RBA DGND DGND DGND DGND DGND Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name DGND DGND NC NC DGND DGND VDD VDD VDD VDD NC DGND DGND DC0 DC1 DC2 DC3 DC4 DC5 DC6 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name DC7 OEC VDD VDD CLKC NC VDDA VINC AGND RTC RBC RBB RTB AGND VINB VDDA NC CLKB NC VDD Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name VDD OEB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND DGND NC DGND DGND DA0 DA1 DA2 DA3 DA4 80 1 24 65-3720-08 25 3 PRODUCT SPECIFICATION TMC1203 Pin Descriptions Pin Name A/D Converters VINA, VINB, VINC RTA, RTB, RTC RBA, RBB, RBC CLKA, CLKB, CLKC DA7-0 12, 55, 48 14, 53, 50 15, 52, 51 9, 58, 45 RTX to RBX 2.6V 0.6V CMOS Analog Inputs. The input voltage conversion range lies between the voltage applied to the RTX and RBX pins. RTX, RBX. Reference Voltage, Top Inputs. DC voltages applied to RTA, RTB and RTC define highest value of VINX. Reference Voltage, Bottom Inputs. DC voltages applied to RBA, RBB and RBC define highest value of VINX. Convert (Clock) Inputs. A/D converter clock inputs. CMOScompatible. VINX is sampled on the falling edge of CLKX. Clock inputs are separate for the three converters. Data outputs, Converter A (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLKX. Data outputs, Converter B (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLKX. Data outputs, Converter C (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLKX. Output Enable Inputs. CMOS-compatible. When LOW, the A/D output is enabled. When HIGH, the output is in a high-impedance state. Output Enables are separate for the three converters. Analog Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to AGND. Digital Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to AGND. Analog Ground. Ground connections. These pins should be connected to the system analog ground plane. Digital Ground. Ground connections. These pins should be connected to the system analog ground plane. Pin Number Value Pin Function Description 4, 3, 2, 80, 79, 78, 77, 76 63, 64, 65, 66, 67, 68, 69, 70 41, 40, 39, 38, 37, 36, 35, 34 5, 62, 42 CMOS/ TTL CMOS/ TTL CMOS/ TTL CMOS DB7-0 DC7-0 OEA, OEB, OEC Power VDDA VDD 11, 47, 56 6, 7, 27, 28, 29, 30, 43, 44, 60, 61 13, 49, 54 16, 17, 18, 19, 20, 21, 22, 25, 26, 32, 33, 71, 72, 74, 75 1, 8, 10, 23, 24, 31, 46, 57, 59, 73 +5V +5V AGND DGND 0.0V 0.0V No Connect N/C open Not Connected. 4 PRODUCT SPECIFICATION TMC1203 Specification Notes Bandwidth Bandwidth specification of an A/D converter is somewhat different from the normal frequency-response specification used in amplifiers and filters. An understanding of the differences will help in selecting converters properly for particular applications. A/D conversion comprises two distinct processes: sampling and quantizing. Sampling is grabbing a snapshot of the input signal and holding it steady for quantizing. The quantizing process is approximating the analog input to its nearest numerical value within the conversion range. While sampling is a high-frequency process, quantizing operates on a dc signal, held steady by the track/hold circuit. Therefore, the sampling process relates to the dynamic characteristics of an A/D converter. Sampling involves an aperture time, the time needed for the track/hold circuit to capture the input signal and settle on a dc value to hold. It is analogous to the shutter speed of a camera: the shorter the A/D aperture (or faster the shutter) the less the signal (or picture) will be blurred, and the less uncertainty there will be in the quantized value. This is not to be confused with the camera lens opening (aperture), which is entirely different. For example, a 10 MHz sinewave with a 1V peak amplitude (2Vp-p) has a maximum slew rate of 2pfA at zero crossing, or 62.8V/ms. With an 8-bit A/D converter, q (the quantization step size) = 2V/255 = 7.8mV. The input signal will slew one LSB in 124ps. To limit the error (and noise) contribution due to aperture effects to 1/2LSB, the aperture must be shorter than 62ps. This is the primary reason that the signal to noise ratio drops off as full scale frequency increases. Notice that the slew rate is directly proportional to signal amplitude, A. A/Ds will handle lower-amplitude signals of higher bandwidth, but other distortion effects will be worsened. All this is of particular interest in applications such as digitizing analog VGA RGB signals, or the output of a CCD imaging chip. These data are effectively pre-sampled: there is a period of rapid slewing from one pixel value to another, followed by a relatively stable dc level before the signal slews to the next pixel value. The goal is, of course, to sample on these stable pixel values, not on the slewing between pixels. During the aperture time, the A/D sees essentially a dc signal, and bandwidth considerations are less important. As long as the input circuit can slew and settle to the new value in the prescribed period, an accurate conversion will be made. The TMC1203 is capable of slewing a full 2V and settling between samples taken as little as 25ns apart, making it ideal for digitizing analog VGA and CCD outputs. tSTD VINX Sample N Sample N+2 Sample N+3 Sample N+1 tPWL CLKX tDO tHO Hi-Z DX7-0 Data N-3 Data N-2 Data N-1 Data N tPWH 1/fS tDIS tENA OEX 65-3720-02 Figure 1. Timing 5 TMC1203 PRODUCT SPECIFICATION Equivalent Circuits VDD VDD p Digital Input n p Digital Output n 27011B 27014B GND GND Figure 2. Equivalent Digital Input Circuit Figure 3. Equivalent Digital Output Circuit VDDA VRT VIN OE Three-State Outputs AGND 0.5V High Impedance tDIS 0.5V tENA 2.0V 0.8V 7048B 29030 VRB Figure 4. Equivalent Analog Input Circuit Figure 5. Threshold Levels for Three-State Measurements Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Power Supply Voltages VDDA VDDP VDD VDDA VDDP AGND Digital Inputs Applied Voltage Forced current 3, 4 Measured to DGND2 -0.5 -10.0 VDD + 0.5 +10.0 V mA Measured to AGND Measured to DGND Measured to DGND Measured to VDD Measured to VDD Measured to DGND -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 +7.0 +7.0 +7.0 +0.5 +0.5 +0.5 V V V V V V Condition Min Typ Max Unit 6 PRODUCT SPECIFICATION TMC1203 Absolute Maximum Ratings (continued) (beyond which the device may be damaged)1 Parameter Analog Inputs Applied Voltage Forced current 3, 4 Condition Measured to AGND2 Min -0.5 -10.0 Typ Max VDDA+0.5 +10.0 VDD + 0.5 +6.0 1 second Unit V mA V mA Digital Outputs Applied voltage Forced current 3, 4 Measured to DGND2 Single output in HIGH state to ground) -0.5 -6.0 Short circuit duration Temperature Operating, ambient Junction Lead, soldering Vapor Phase soldering Storage Electrostatic Discharge 5 -20 10 seconds 1 minute -65 110 +150 +300 +220 +150 ±150 °C °C °C °C °C V Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 5. EIAJ test method. Operating Conditions Parameter VDD, VDDA, VDDP AGND VRTX VRBX VRTX-VRBX VINX VIH VIL IOH IOL TA Power Supply Voltage Analog Ground (Measured to DGND) Reference Voltage, Top Reference Voltage, Bottom Reference Voltage Differential Analog Input Range Input Voltage, Logic HIGH Input Voltage, Logic LOW Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air 0 0 1.0 VRB 0.7 VDD GND Min. 4.75 -0.1 Nom 5.0 0 2.6 0.6 2.0 5.0 VRT VDD 0.3 VDD -4.0 4.0 70 Max. 5.25 0.1 VDDA Units V V V V V V V V mA mA °C 7 TMC1203 PRODUCT SPECIFICATION Electrical Characteristics Parameter IDD Power Supply Current 1 Conditions fS = 20 Msps fS = 40 Msps fS = 50 Msps Min. Typ1 70 94 105 29 45 300 425 490 4 12 Max. 90 120 135 55 65 470 630 710 Units mA mA mA mA mA mW mW mW pF pF kW VDD = VDDA = VDDP = Max., CLOAD = 35pF, fCK = fS (3 A/Ds) IDDQ Power Supply Current, Quiescent VDD = VDDA = Max. CLKX = LOW CLKX = HIGH PD Total Power Dissipation VDD = VDDA = VDDP = Max., CLOAD = 35pF, fCK = fS (3 A/Ds) fS = 20 Msps fS = 40 Msps fS = 50 Msps CAI RIN RREF ICB IIH IIL IOZH IOZL IOS VOH Input Capacitance, Analog Input Resistance Reference Resistance Input Current, Analog Input Current, HIGH Input Current, LOW Hi-Z Output Leakage Current, Output HIGH Hi-Z Output Leakage Current, Output LOW Short-Circuit Current Output Voltage, HIGH CLKX = LOW CLKX = HIGH 500 200 VDD = Max., VIN = VDD VDD = Max., VIN = 0V VDD = Max., VIN = VDD VDD = Max., VIN = VDD 270 340 ±1 ±5 ±5 ±5 ±5 -35 W mA mA mA mA mA mA V V V IOH = -100mA IOH = -2.5mA IOH = Max. VDD-0.3 3.5 2.4 0.4 4 10 10 VOL CDI CDO Output Voltage, LOW Digital Input Capacitance Digital Output Capacitance IOL = Max. V pF pF Note: 1. Typical values with VDD = VDDA = Nom and TA = Nom, Minimum/Maximum values with VDD = VDDA = Max. and TA = Min.. 8 PRODUCT SPECIFICATION TMC1203 Switching Characteristics Parameter fS Conversion Rate Conditions TMC1203-20 TMC1203-40 TMC1203-50 tPWH CLKX Pulsewidth, HIGH TMC1203-20 TMC1203-40 TMC1203-50 tPWL CLKX Pulsewidth, LOW TMC1203-20 TMC1203-40 TMC1203-50 EAP tSTO tSTS tHO tDO tENA tDIS Aperture Error Sampling Time Offset Sampling Time Skew Output Hold Time Output Delay Time Output Enable Time Output Disable Time CLOAD = 15pF 9 14 27 42 1 14 14 12 8 8 7 30 2 150 5 400 Min. Typ. Max. 20 40 50 Units Msps Msps Msps ns ns ns ns ns ns ps ns ps ns ns ns ns System Performance Characteristics Parameter ELI ELD BW Integral Linearity Error, Independent Differential Linearity Error Bandwidth1 Conditions VRT = 2.6V VRB = 0.6V TMC1203-20 TMC1203-40 TMC1203-50 EOT Offset Voltage, Top (RT - VIN for most positive code transition) Offset Voltage, Bottom (RB - VIN for most negative code transition) Differential Gain VRT = 2.6V, VRB = 0.6V -40 Min.2 Typ1 ±0.5 ±0.5 10 12 12 80 Max.2 Units LSB LSB MHz MHz MHz mV EOB VRT = 2.6V, VRB = 0.6V -95 -30 mV dg fS = 14.3Msps NTSC 40 IRE Mod Ramp VDDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V fS = 14.3Msps NTSC 40 IRE Mod Ramp VDDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V fN = 5.0 MHz 1.8 % dp Differential Phase 0.7 deg XTALK Channel Crosstalk 45 dB 9 TMC1203 PRODUCT SPECIFICATION System Performance Characteristics (continued) Parameter SNR 3 Conditions fN = 1.24MHz fN = 2.48MHz fN = 6.98MHz fN = 10.0MHz Min.2 Typ1 46 46 45 45 42 41 40 38 40 40 40 53 48 44 40 49 44 38 46 40 37 Max.2 Units dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Signal-to-Noise Ratio fS = 20Msps, VRT = 2.6V, VRB = 0.6V fS = 40Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz fN = 6.98MHz fN = 12.0MHz fN = 20.0MHz fS = 50Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz fN = 6.98MHz fN = 12.0MHz SFDR4 Spurious-Free Dynamic Range fS = 20Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz fN = 2.48MHz fN = 6.98MHz fN = 10.0MHz fS = 40Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz fN = 6.98MHz fN = 12.0MHz fS = 50Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz fN = 6.98MHz fN = 12.0MHz Notes: 1. Values shown in Typ. column are typical for VDD = VDDA =+5V and TA = 25°C. 2. Values shown in Min. and Max. columns are for VDD = VDDA and TA over entire range specified under Operating Conditions. 3. SNR values do not include the harmonics of the fundamental frequency. 4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude. 5. Characteristics specified for VRT = 2.6V, VRB = 0.6V. 6. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes. 10 PRODUCT SPECIFICATION TMC1203 Typical Performance Characteristics 35 30 25 IDD 20 15 10 5 0 0 10 20 30 fS (Msps) 40 50 65-3720-03 60 50 SFDR (dB) 40 30 20 10 0 0 5 10 15 20 25 65-3720-04 fS = 20Msps fIN (Msps) Figure 6. Typical IDD vs fS (Single A/D) Figure 7. Typical SFDR vs fIN 50 40 SNR (dB) 30 20 10 0 0 5 10 15 20 25 65-3720-05 50 40 SNR (dB) 30 20 fS = 20Msps 10 0 0 1 2 VIN 3 4 5 65-3720-06 fS = 20Msps fIN (MHz) Figure 8. Typical SNR vs fIN Figure 9. Typical SNR vs Full Scale Input Range 11 TMC1203 PRODUCT SPECIFICATION Application Notes The circuit in Figure 10 employs a band-gap reference to generate a variable RTX reference voltages for the TMC1203 as well as a bias voltage to offset the wideband input amplifiers to mid-range. The operational amplifier in the reference circuitry is a standard 741-type. The voltage reference at RTX can be adjusted from 0.0 to 2.4 volts while RBX is grounded. Schottky diodes are used to restrict the wideband amplifier output to between -0.3V and VDD +0.3V. Diode protection is good practice to limit the analog input voltage at VINX to the safe operating range. 0.1µF LM185-1.2 0.1µF 1k½ +5V Gain Adjust 2k½ 0.1µF VDDA + – 1k½ 1k½ 100 GREEN Video Input 75½ Wideband Op-amp 0.1µF 20½ RTA RTB RTC RBA RBB RBC VINA +5V 0.1µF VDD DA7-0 OEA CLKA + – 1k½ 1k½ GREEN Digital Video Output 10k½ TMC1203 +5V DB7-0 BLUE Digital Video Output 100 BLUE Video Input 75½ + – 1k½ 1k½ Wideband Op-amp VINB OEB CLKB 10k½ +5V DC7-0 OEC CLKC VINC AGND DGND RED Digital Video Output Pixel Clock 100 RED Video Input + 75½ – 1k½ 1k½ Wideband Op-amp 10k½ +5V 65-3720-07 Figure 10. Typical Interface Circuit - High Performance Grounding The TMC1203 has separate analog and digital circuits. To keep digital system noise from the A/D converter, it is recommended that power supply voltages (VDD and VDDA) come from the same source, and that ground connections (DGND and AGND) be made to the analog ground plane, and as close as possible to the device pins. Power supply pins should be individually decoupled at the pin. The digital circuitry that gets its input from the TMC1203 should be referred to the system digital ground plane. Printed Circuit Board Layout Designing with high performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor A/D conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VN, RTX, RBX) as short as possible and as far as possible from all digital signals. The TMC1203 should be located close to the analog input connectors. 12 PRODUCT SPECIFICATION TMC1203 2. Segregate traces: • • • • A/D analog D/A analog Clocks Digital 5. Treat analog inputs as transmission lines. Cleanly route traces over the ground plane bearing in mind that the return currents will flow through the ground plane beneath the traces. Do not route digital traces nearby. A few inches of digital trace less than a few line widths from an analog trace will cross-couple noise into adjacent analog circuits. 3. The power plane for the TMC1203 should be separate from that which supplies the rest of the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the TMC1203 is the same as that of the system's digital circuitry, power to the TMC1203 should be decoupled with ferrite beads and 0.1mF capacitors to reduce noise. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. Decoupling capacitors should be applied liberally to VDD pins. Remember that not all power supply pins are created equal. They supply different circuits on the integrated circuit, each of which generate varying amounts and types of noise. For best results, use 0.1mF ceramic capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC1203, the voltage reference, or the analog inputs. Capacitive coupling of digital power supply noise from this layer to the TMC1203 and its related analog circuitry can have an adverse effect on performance. CLKX should be handled carefully. Jitter and noise on this clock may degrade performance. Terminate the clock line, if needed, to eliminate overshoot and ringing. 6. 7. Related Products • TMC1175A, TMC1275 8-Bit Video A/D Converters • TMC1173A, TMC1273 3V, Low-Power 8-Bit Video A/D Converters • TMC1103 Triple 8-bit A/D with Clamps and PLL • TMC3003/TMC3503 Triple Video D/A Converters • TMC2242B/TMC2243/TMC2246A Digital Filters 4. 13 TMC1203 PRODUCT SPECIFICATION Notes: 14 PRODUCT SPECIFICATION TMC1203 Mechanical Dimensions – 80-Lead MQFP Package Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness. Symbol A A1 A2 B C D D1 E E1 e L N ND NE a ccc Inches Min. — .010 .100 .012 .005 .904 Max. .134 — .120 .018 .009 .923 Millimeters Min. — .25 2.55 .30 .13 22.95 Max. 3.40 — 3.05 .45 .23 23.45 3, 5 5 .783 .791 .667 .687 .547 .555 .0315 BSC .025 .041 80 24 16 0¡ — 7¡ .004 19.90 20.10 16.95 17.45 13.90 14.10 .80 BSC .65 1.03 80 24 16 0¡ — 7¡ 0.10 4 D D1 e Datum Plane E1 E Pin 1 Identifier .13 (.005) R Min. B 0.063" Ref (1.60mm) Lead Detail See Lead Detail A A2 A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C L .20 (.008) Min. 0¡ Min. C a .13 (.30) R .005 (.012) 15 TMC1203 PRODUCT SPECIFICATION Ordering Information Product Number TMC1203KLC20 TMC1203KLC40 TMC1203KLC50 Conversion Rate (Msps) 20 Msps 40 Msps 50 Msps Temperature Range TA = 0°C to 70°C TA = 0°C to 70°C TA = 0°C to 70°C Screening Commercial Commercial Commercial Package 80-Lead MQFP 80-Lead MQFP 80-Lead MQFP Package Marking 1203KLC20 1203KLC40 1203KLC50 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 5/20/98 0.0m 001 Stock# DS70001203 Ó 1998 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.