TMC2011AN2C

www.fairchildsemi.com TMC2011A/2111A Variable-Length Shift Register Features • Low power CMOS • TMC2011A is a pin compatible replacement for the TDC1011 and TMC2011 • TMC2211A is a pin compatible replacement for the TMC2111 • Inputs and outputs are TTL compatible • DC–40MHz clock rate • Selectable delay lengths (TMC2011A: 3 to 18 stages, TMC2111A: 1 to 16 stages) • Special 4-bit wide mixed-delay mode (TMC2011A) • Available in 24-pin CERDIP and plastic DIP and 28-lead Plastic Leadless Chip Carrier Applications • • • • • • Video filtering High speed data registers Local storage registers Digital delay lines Television special effects Pipeline register Description The TMC2011A and TMC2111A are high-speed, byte-wide shift registers with programmable delay lengths. The TMC2011A can be programmed to any length between 3 and 18 stages. It offers a special split-word mode which allows for mixed delay lengths. The TMC2011A, constructed in low-power CMOS, is pin and function compatible with the bipolar TDC1011. The TMC2111A is a byte-wide shift register that can be programmed to lengths of 1 to 16 stages. The TMC2011A and TMC2111A are fully synchronous, with all operations controlled by a single master clock. Input and output registers are positive-edge triggered D-type flipflops. The length and mode controls are also registered. Both devices operate with a maximum clock rate of 40 MHz. Fabricated in a submicron CMOS process, the TMC2011A and TMC2111A are TTL-compatible, and are available in 24-pin CERDIP and Plastic DIP packages as well as a 28-lead Plastic Leadless Chip Carrier. Block Diagrams TMC2011A DI3-0 R1 R2 R3 4 4 L3-0 4 RL 4 4-Bit Wide 1 of 16 Selector 4-Bit Wide 1 of 16 Selector R16 4 4 4 R18 4 4 DO3-0 L3-0 RL 8 4 8-Bit Wide 1 of 16 Selector 8 R17 TMC2111A DI7-0 R1 8 R14 8 8 R16 8 8 DO7-0 R15 4 8 4 MC CLK RI 4 4 R18 4 4 DO7-4 CLK 65-2011A-02 4 4 4 R16 4 DI7-4 4 R1 R2 R3 R17 65-2011A-01 Rev. 1.1.0 TMC2011A/2111A PRODUCT SPECIFICATION Functional Description The TMC2011A consists of two 4-bit wide, programmable length shift registers. The TMC2111A consists of a single 8-bit wide, programmable length shift register. The internal registers of each device share control signals and a common clock. Pin Assignments 24 Lead DIP (B2, N2) Packages DI0 DI1 DI2 DI3 TMC2011A L0 L1 VDD CLK DI4 DI5 DI6 DI7 12 13 1 24 DO0 DO1 DO2 DO3 L2 L3 GND MC DO4 DO5 DO6 DO7 DI0 DI1 DI2 DI3 1 24 DO0 DO1 DO2 DO3 L1 VDD CLK DI4 DI5 DI6 DI7 12 TMC2111A L0 L2 L3 GND GND DO4 DO5 DO6 13 DO7 65-2011A-03 28 Lead PLCC (R3) Package DI2 DI1 DI0 DO0 DO1 DO2 DO3 DI2 DI1 DI0 DO0 DO1 DO2 DO3 1 28 1 28 DI3 L0 L1 VDD CLK DI4 NC TMC2011A NC L2 L3 GND GND MC NC DI3 L0 L1 VDD CLK DI4 NC TMC2111A NC L2 L3 GND GND MC NC DI5 DI6 DI7 DO7 DO6 DO5 DO4 2 DI5 DI6 DI7 DO7 DO6 DO5 DO4 65-2011A-04 PRODUCT SPECIFICATION TMC2011A/2111A Pin Descriptions – TMC2011A Pin Number Pin Name Power VDD GND Data Inputs DI7-0 12,11,10, 9,4,3,2,1 14,13,12, 10,5,4,3,2 Data Input. Eight inputs are provided for the data, which pass through the shift register unchanged. The eight inputs on the TMC2011A are divided into two groups of four bits to allow mixed delay operation. The lengths of these two groups are different when the Mode Control (MC) is HIGH (see Table 1). When MC is LOW both groups have equal delays. Data Output. The outputs of the shift register are delayed relative to the input signals. The amount of the delay is programmable (see Table 1). The outputs remain valid for a minimum of tHO nanoseconds after the leading edge of CLK. This allow the data to be latched into circuits with non-zero hold time requirements. Master Clock. All inputs and outputs are synchronous and operate from a single master clock. All operations occur on the rising edge of the master clock. Length Select. The length select input is used to determine the register delay of the TMC2011A. This input is registered and affects the output tDO after the clock edge after it is input to the device (see Timing Diagram). Delay lengths are specified in Table 1. Mode Control. The Mode Control is used to select the special 4-bit wide split mode. When HIGH, the delay on DO7-4 is fixed at 18 stages, while DO3-0 have the delay specified by the length select. When MC is LOW, all eight bits have equal delays as specified by the length select. 7 18 8 21,22 Supply Voltage. The TMC2011A and operates from a single +5V supply. All power and ground lines must be connected. Ground. The TMC2011A operates from a single +5V supply. All power and ground lines must be connected. DIP PLCC Pin Function Description Data Outputs DO7-0 13,14,15, 16,21,22, 23,24 15,16,17, 18,26,27, 28,1 Controls CLK 8 9 L3-0 19,20,6,5 23,24,7,6 MC 17 20 3 TMC2011A/2111A PRODUCT SPECIFICATION Pin Descriptions – TMC2111A Pin Number Pin Name Power VDD GND Data Inputs DI7-0 12,11,10, 9,4,3,2,1 14,13,12, 10,5,4,3,2 Data Input. Eight inputs are provided for the data, which pass through the shift register unchanged. The TMC2111A consists of a single group of eight bits with all data bits having equal delays. Data Output. The outputs of the shift register are delayed relative to the input signals. The amount of the delay is programmable (see Table 1). The outputs remain valid for a minimum of tHO nanoseconds after the leading edge of CLK. This allow the data to be latched into circuits with non-zero hold time requirements. Master Clock. All inputs and outputs are synchronous and operate from a single master clock. All operations occur on the rising edge of the master clock. Length Select. The length select input is used to determine the register delay of the TMC2111A. This input is registered and affects the output tDO after the clock edge after it is input to the device (see Timing Diagram). Delay lengths are specified in Table 1. 7 17,18 8 20,21,22 Supply Voltage. The TMC2111A operates from a single +5V supply. All power and ground lines must be connected. Ground. The TMC2111A operates from a single +5V supply. All power and ground lines must be connected. DIP PLCC Pin Function Description Data Outputs DO7-0 13,14,15, 16,21,22, 23,24 15,16,17, 18,26,27, 28,1 Controls CLK 8 9 L3-0 19,20,6,5 23,24,7,6 Table 1. Programming Length Controls TMC2011A Input Code L3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 4 L2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 L1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 L0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Mode (MC) =0 DO3-0 Length DO7-4 Length 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Mode (MC) =1 DO3-0 Length DO7-4 Length 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 TMC2111A DO7-0 Length 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PRODUCT SPECIFICATION TMC2011A/2111A Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage Output, Applied Voltage2 Output, Externally Forced Current3,4 Output, Short Circuit Duration (single output in HIGH state to ground) Operating, Ambient Temperature Junction Temperature Storage Temperature Lead Soldering (10 seconds) -65 -20 Min -0.5 -0.5 -0.5 -3.0 Typ Max 7.0 VDD + 0.5 VDD + 0.5 6.0 1 110 140 150 300 Unit V V V mA sec °C °C °C °C Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Operating Conditions Parameter VDD fCLK tPWH tPWL tS tH VIH VIL IOH IOL TA Power Supply Voltage Clock frequency CLK pulse width, HIGH CLK pulse width, LOW Input Data Set-up Time Input Data Hold Time Input Voltage, Logic HIGH Input Voltage, Logic LOW Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air 0 DI7-0, L3-0, MC CLK TMC2011A, 2111A TMC2011A-1, 2111A-1 12 12 6 1 2.0 2.6 0.8 -2.0 4.0 70 V mA mA °C Min 4.75 Nom 5.0 Max 5.25 30 40 ns ns ns ns V Units V MHz 5 TMC2011A/2111A PRODUCT SPECIFICATION Electrical Characteristics Parameter IDDU IDDQ CPIN IIH IIL IOS VOH VOL Power Supply Current, Unloaded Power Supply Current, Quiescent I/O Pin Capacitance Input Current, HIGH Input Current, LOW Short-Circuit Current Output Voltage, HIGH Output Voltage, LOW DO7-0, IOH = Max DO7-0, IOL = Max 2.4 0.4 VDD = Max, VIN = VDD VDD = Max, VIN = 0 V Conditions VDD = Max, fCLK=30 MHz VDD = Max, fCLK=40 MHz VDD = Max, CLK = LOW 5 ±10 ±10 -100 Min Typ Max 30 40 0.5 Units mA mA mA pF mA mA mA V V Switching Characteristics Parameter tDO tHO Output Delay Time Output Hold Time Conditions CLOAD = 25 pF CLOAD = 25 pF 3 Min Typ Max 15 Units ns ns 6 PRODUCT SPECIFICATION TMC2011A/2111A Timing Diagrams 1/f CLK 1 tS DI7-0 tS MC, L3-0 tH Controls tHO DO7-0 L is Length from Table 1. Data N-1 Data N Controls tDO Data N+1 Data N+2 65-2011A-05 tPWH 3 4 tPWL 5 2 tH Data N+L Data N+L-1 Data N+L+1 Data N+L+2 Controls Controls Controls Figure 1. Preset Length Controls CLK DI7-0 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 L3-0 0010 0010 0011 0011 0011 0011 0011 TMC2011A DO7-0 (MC=0) TMC2111A DO3-0 (MC=1) Data 5 Data 7 Data 6 Data 8 Data 7 Data 9 Data 8 Data 10 Data 8 Data 10 Data 9 Data 11 Data 10 Data 12 65-2011A-06 Figure 2. Length Control Operation Equivalent Circuits VDD VDD p Data or Control Input n p Output n 27011B 27014B GND GND Figure 3. Equivalent Digital Input Circuit Figure 4. Equivalent Digital Output Circuit 7 TMC2011A/2111A PRODUCT SPECIFICATION Notes: 8 PRODUCT SPECIFICATION TMC2011A/2111A Mechanical Dimensions 24-Lead Ceramic DIP Package Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 12, 13 and 24 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within ±.010 (.25mm) of its exact longitudinal position relative to pins 1 and 24. 6. Applies to all four corners (leads number 1, 12, 13, and 24). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90¡. 8. All leads – Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Twenty-two spaces. Symbol — .200 .014 .023 .045 .065 .008 .015 — 1.280 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 — 90¡ 105¡ — 5.08 .36 .58 1.14 1.65 .20 .38 — 32.51 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 — 90¡ 105¡ D 12 1 NOTE 1 E 13 24 s1 e Q A a L b2 b1 c1 eA 9 TMC2011A/2111A PRODUCT SPECIFICATION Mechanical Dimensions (continued) 24-Lead Plastic DIP Package Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N — .015 .115 Max. .210 — .195 Millimeters Min. — .38 2.53 Max. 5.33 — 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2 Symbol .014 .022 .045 .070 .008 .015 1.125 1.275 .005 — .300 .325 .240 .280 .100 BSC — .430 .115 .160 24 .36 .56 1.14 1.78 .20 .38 28.58 32.39 .13 — 7.62 8.26 6.10 7.11 2.54 BSC — 10.92 2.92 4.06 24 2 5 D 12 1 E1 D1 13 24 E e A A1 L B1 B eB C 10 PRODUCT SPECIFICATION TMC2011A/2111A Mechanical Dimensions (continued) 28-Lead PLCC Package Inches Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45¡ 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm) Symbol .165 .180 .090 .120 .020 — .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 — .004 4.19 4.57 2.29 3.05 .51 — .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 — 0.10 3 2 E E1 J D D1 D3/E3 B1 e J A A1 A2 B –C– LEAD COPLANARITY ccc C 11 TMC2011A/2111A PRODUCT SPECIFICATION Ordering Information Product Number TMC2011AB2C TMC2011AB2C1 TMC2011AN2C TMC2011AN2C1 TMC2011AR3C TMC2011AR3C1 TMC2111AB2C TMC2111AB2C1 TMC2111AN2C TMC2111AN2C1 TMC2111AR3C TMC2111AR3C1 Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Speed Grade 30 MHz 40 MHz 30 MHz 40 MHz 30 MHz 40 MHz 30 MHz 40 MHz 30 MHz 40 MHz 30 MHz 40 MHz Screening Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Package 24 Pin 0.3" CerDIP 24 Pin 0.3" CerDIP 24 Pin 0.3" Plastic DIP 24 Pin 0.3" Plastic DIP 28 Lead PLCC 28 Lead PLCC 24 Pin 0.3" CerDIP 24 Pin 0.3" CerDIP 24 Pin 0.3" Plastic DIP 24 Pin 0.3" Plastic DIP 28 Lead PLCC 28 Lead PLCC Package Marking 2011AB2C 2011AB2C1 2011AN2C 2011AN2C1 2011AR3C 2011AR3C1 2111AB2C 2111AB2C1 2111AN2C 2111AN2C1 2111AR3C 2111AR3C1 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30002011A Ó 1998 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.