TMC2081KBC

www.fairchildsemi.com TMC2081 Digital Video Mixer Features • Mixes 24//16-bit GBR/YCBCR444//YCBCR422 and 8-bit color-index sources • 24//16-bit GBR/YCBCR444//YCBCR422 output • 255-step proportional mixing via a7-0 inputs • 256-step mixing with a8-0 for a=100h unity gain • 256 x 8-bit look-up table on a channel • Lap-dissolve and fade effects • a and crosspoint controls for soft and color-border wipe generation • Mask register and three 256 x 8 bypassable CLUTs with overlay on A-channel • Analog preview output with sync on Green/Y • D/A power-down modes • Single +5 volt power supply operation • Pin compatible with TMC22080 Digital Mixer Description The TMC2081 is a Digital Video Mixer that performs M = ( a ) V1 + ( 1-a ) V2 (for 0 £ a £ 1) cross-fading at speeds faster than 40 Mpps proportionally controlled by a 9-bit a-channel input. Variable rate dissolves and fades may be implementedwith unity gain at the a endpoints. With the a-Look-Up Table (aLUT), mixing may be controlled by a single bit of the a-channel input. Setup is via a microprocessor interface. Supported video formats are 24-bit GBR, YCBCR444, and 16-bit YCBCR422 component video. Dissimilar pixel formats may be mixed using on-chip interpolation and decimation filters and GBR/YCBCR and YCBCR/GBR color-space conversion matrices. An additional format accepted by the A-channel is 8-bit color-indexed pixel data which addresses three bypassable 256 x 8 color look-up tables (CLUTs). A 15 color overlay palette and a 24-bit fill register are also included. Digital and Analog outputs may be programmed to view either mixer inputs, V1 or V2 or mixer output, M. Packaged in a 128-lead plastic metric quad flat-pack (MQFP), the TMC2081 is fabricated with a sub-micron CMOS process. Performance is guaranteed over the commercial, 0°C to 70°C temperature range. Applications • • • • Mixing computer graphics and live video Lap-dissolve between video sources Fade to black or to user-selectable fill color Window/wipe processing Logic Symbol DATA INPUTS PDA23-0 PDB23-0 a8-0 AV PASSEN SIG0 CLK OL3-0 SMX2-0 SYNC BLANK D7-0 D2-0 CS R/W COMP VREF RREF D/A SETUP M23-0 PASS14 SIG14 AVOUT VIDEO OUTPUT TIMING INPUTS MICROANALOG OVERLAY PROCESSOR TIMING & CONTROL INTERFFACE TMC2081 DIGITAL VIDEO MIXER ANALOG OUTPUTS G/Y B/CB R/CR 65-2081-01 Rev. 1.3.0 Block Diagram VREF RREF COMP 2 Delay PASS14 SIG14 AVOUT Delay Delay Unity Gain Switch a LUT 256x8x3 CLUT RGB YCbCr Matrix Source Select 444 422 Decimator/ Filter A 15x8x3 Overlay Table F Crosspoint Switch V2 V1 Fill Register A M B Triple Dual Input 9-bit a-Mixer 444 422 Formatter M23-0 422 444 Interpolator/ Filter YCbCr RGB Matrix B M D/A A B YCbCr RGB Matrix DAC Formatter 2's OSB D/A D/A B/CB R/CR REF G/Y 65-2081-02 TMC2081 PASSEN SIG0 Register AV SMX2-0 a8-0 a Register PDA23-0 A Register/ Formatter Mask Register OL3-0 PDB23-0 B Register/ Formatter SYNC BLANK Delay (2/15 clock) CLK PRODUCT SPECIFICATION D7-0 A2-0 CS R/W Microprocessor Interface PRODUCT SPECIFICATION TMC2081 Functional Description The TMC2081 is a monolithic digital video processor that proportionally mixes digital video in GBR, YCBCR, or colorindex formats. Some of the variety of input and output data format combinations are shown in Table 1. The A-channel data path has transformation circuits that can look up 24-bit GBR values from 8-bit color-index inputs, convert GBR-to-YCBCR format, and decimate YCBCR444 to YCBCR422. The B-channel path includes circuits that convert YCBCR to GBR and interpolate YCBCR422 to YCBCR444. Prior to mixing, incoming pixel data streams must be converted to matching formats by setting the A and B channel control registers. Data enters the TMC2081 through the PDA23-0, PDB23-0, a8-0, and OL3-0 ports. Data and video controls (PASSEN and AV) are simultaneously registered on the rising edge of PXCLK. Pipeline latency is 14 clock cycles to the mixed digital video output. Although PDA23-0, PDB23-0, and M23-0 data formats may be different, V1 and V2 data formats at the a-Mixer input must be matched: unsigned magnitude for GBR and Y components; 2’s complement for CB and CR components. Data formats converted within the TMC2081 are determined by the control bits programmed into the internal registers. Output format may be GBR, YCBCR444 or YCBCR422. Either crosspoint switch input, A and B or the Mixer output may be selected at the M23-0 port. Table 2, Table 3 and Table 4 show examples of the M23-0 output for 9-bit a-mixing. In Table 3, CBCR is accepted at the CB input. Table 4 exemplifies format conversion. Mixer output and inputs may be previewed by three video D/A converters. Analog outputs may be either GBR or YCBCR. For initialization and control, internal registers and tables may be accessed through a microprocessor interface. Power may be conserved by disabling the D/A converters or sections of the TMC2081 via internal Control Registers. In the latter mode, the microprocessor interface remains active and Control Register settings are retained but CLUT locations are not accessible. Table 1. Input and Output Data Format Examples A Input Format B Input Format A A A B B M CLUT GBR-YCBCR Decimate Interpolate YCBCR-GBR Format Bypass Bypass Bypass Bypass Bypass Bypass Enable Bypass Enable Bypass Bypass Bypass Enable Bypass Bypass Bypass Bypass Bypass Enable Bypass Bypass Enable Bypass Bypass Bypass Bypass Bypass Enable Bypass Bypass Bypass Bypass Bypass Bypass Bypass Enable Bypass Enable Bypass Bypass Low Low High High Low Low Low Low High Low M Output Format YCBCR444 YCBCR444 YCBCR422 YCBCR422 YCBCR444 GBR YCBCR444 GBR YCBCR422 GBR YCBCR444 YCBCR444 Bypass YCBCR444 YCBCR422 Bypass YCBCR444 YCBCR422 Bypass YCBCR422 YCBCR422 Bypass YCBCR422 YCBCR422 Bypass GBR, CI GBR, CI GBR, CI GBR, CI GBR, CI YCBCR444 Enable YCBCR444 Enable YCBCR422 Enable YCBCR422 Enable GBR Enable Table 2. GBR Mixing Example (9-bit a) a (hex) 000 040 080 100 PDA (hex) G BB BB BB BB B CC CC CC CC R AA AA AA AA G EE EE EE EE PDB (hex) B FF FF FF FF R DD DD DD DD G EE E1 D5 BB M (hex) B FF F2 E6 CC R DD D0 C4 AA 3 TMC2081 PRODUCT SPECIFICATION Table 3. YCBCR422 Mixing Example (CB and CR in 2’s Complement) a (hex) 40 80 40 40 A0 B0 A0 B0 Y 10 10 10 10 30 30 30 30 PDA (hex) CB F4 F4 F4 FE 60 80 C0 E0 CR XX XX XX XX XX XX XX XX Y 20 20 20 20 40 40 40 40 PDB (hex) CB 4 4 4 2 70 90 D0 F0 CR XX XX XX XX XX XX XX XX Y 1C 18 1C 1C 36 35 36 35 M (hex) CB 00 00 00 01 66 86 C6 E5 CR 00 00 00 00 00 00 00 00 Table 4. YCBCR422-to-YCBCR444 Mixing Example a (hex) 40 40 40 40 A0 B0 A0 B0 Y 10 10 10 10 30 30 30 30 PDA (hex) CB F4 F4 F4 FE 60 80 C0 E0 CR XX XX XX XX XX XX XX XX Y 20 20 20 20 40 40 40 40 PDB (hex) CB 4 4 4 2 70 90 D0 F0 CR XX XX XX XX XX XX XX XX Y 1C 1C 1C 1C 36 35 36 35 M (hex) CB 00 00 00 00 66 66 C6 C6 CR 00 00 01 01 86 86 E5 E5 Input Formats Data is accepted by PDA and PDB channels in one pair of the following formats: 1. 2. 3. 4. YCBCR444 YCBCR422 GBR 8-bit color-index mapped to a palette of 256x256x256 colors. (A-channel only) Details of bits assignments are shown in Figure 1. Pixel Data Formats with the expected data ranges are shown in Table 5. Table 5. YCBCR and GBR Data Types and Ranges Signal GBR Y CBCR Min. 0 16 -112 Max. 255 235 +112 Format Unsigned Binary Unsigned Binary 2’s Complement Offset Binary 23 YCBCR444 YCBCR422 GBR Color Index (A-channel only) Y7 Y7 G7 16 15 Y0 CB7 C Y0 CB7 R7 G0 B7 8 7 0 CR0 CB0 CR7 CB0 CR0 B0 R7 P7 R0 P0 65-2081-03 Figure 1. Pixel Data Formats 4 PRODUCT SPECIFICATION TMC2081 A-Channel Operation A-channel pixel data, PDA, is registered on the rising edge of CLK. CBCR data is either passed or format converted (from offset binary to 2’s complement) by MSB inversion. 16-bit YCBCR422 data is converted to 24-bit YCBCR data by pixel replication of CBCR data. Each of the three A channel bytes is logically-ANDed with the contents of the Mask Register. The CLUT in the A-channel pixel data path comprises three 256-word x 8-bit sections. When the CLUT is enabled, pixel data addresses the CLUT, which outputs the address contents for subsequent processing. The CLUT may also be bypassed, passing incoming pixel data directly to subsequent circuits. For 24-bit GBR operation, each of the 256-word by 8-bit CLUTs is independently addressed by green, blue, and red bytes from PDA23-0. For Color-index operation, each of the 256 x 8 CLUTs is addressed by the same pixel data from PDA7-0. CLUT locations may hold GBR or YCBCR color values. V1 and V2 mixer input formats must match CLUT formats. The PDA overlay palette is addressed by four Overlay inputs, OL3-0 and is enabled via the Control Register. Each valid Overlay address produces one of 15 24-bit colors selected from stored 8-bit red, green, and blue values. If all four overlay inputs are LOW, CLUT data is selected. If any overlay input is HIGH, OL3-0 is decoded into the corresponding color which is selected at the RGB/YCBCR matrix. OL3-0 may be changed on a pixel-by-pixel basis. Table 7. B-Channel YCBCR-GBR Mapping for Fully-Saturated Colors Input Values Color White Yellow Cyan Green Magenta Red Blue Black Y 235 210 169 144 106 81 41 16 CB 0 -112 38 -74 74 -38 112 0 CR 0 18 -112 -94 94 112 -18 0 Output Values R 255 255 0 0 255 255 0 0 G 255 255 255 255 0 0 0 0 B 255 0 255 0 255 0 255 0 B-Channel Operation YCBCR444, YCBCR422, or GBR are accepted by the B-channel. PDB23-0 pixel data is registered on the rising edge of CLK. 16-bit YCBCR422 data is converted to 24-bit YCBCR444 data by pixel replication of CBCR data in the Register/Formatter. 24-bit data is passed to an interpolation filter followed by a color-space converter to ensure that the B-channel data format matches that of the A-channel prior to mixing. Table 1 illustrates the setup of color-space converters, decimation, and interpolation filters. Pipeline latencies of the A and B-channels are matched. Interpolation and Decimation Filters Digital interpolation and decimation filters in the A- and B-channels suppress unwanted artifacts in the chrominance components. Maximum passband attenuation is 0.06 dB. Minimum stopband rejection is 41 dB. When the input format is YCBCR422, the incoming pixel following AV transitioning HIGH is assumed to be the CB pixel. (See Figure 11.) Table 6. A-Channel GBR-to-YCBCR Mapping for Fully-Saturated Colors Input Values Color White Yellow Cyan Green Magenta Red Blue Black R 255 255 0 0 255 255 0 0 G 255 255 255 255 0 0 0 0 B 255 0 255 0 255 0 255 0 Output Values Y 235 210 169 144 106 81 41 16 CB 0 -112 38 -74 74 -38 112 0 CR 0 18 -112 -94 94 112 -18 0 a-Channel Operation Nine bits of a data are registered on a pixel-by-pixel basis from a8-0. Either 9-bit or 8-bit a values can be selected by setting Control Register Bit aGAIN. Table 8 shows the differences between the 8-bit and 9-bit gain settings for a 0FF input. Bits a7-0 address a 256 x 8-bit lookup table (aLUT). The aLUT may be used to redefine the function of incoming a data for special effects or low resolution dissolves and fades. Bit a8 controls a unity gain switch. If a8 = 1, then a is set to unity gain. a8 functions independently of the a gain bit register 0. For 8-bit a mixing, set a8 = 0. By setting control register bit aLUTEN = 0, the aLUT may be completely bypassed, allowing a8-0 to directly control the mixing of A, B and F. aLUT locations may be accessed via the D7-0 microprocessor port. 5 TMC2081 PRODUCT SPECIFICATION Table 8. Alpha Channel Gains a value (hex) 000 001 .. 07F 080 .. 0FE 0FF 100 1XX 254/256 256/256 256/256 256/256 254/256 255/256 256/256 256/256 127/256 128/256 127/256 128/256 8-bit Gain 0/256 1/256 9-bit Gain 0/256 1/256 For an A-to-B dissolve transition, as the value of the eight LSBs of the a-channel change from 00h to FFh, (or 000h to 100h in the 9-bit mode), an increasing level of A-channel contribution and a decreasing level of B-channel contribution becomes evident at the output, M. Bit a8 of the a-channel can correct for the 255/256 gain factor in the A-channel that occurs when the 8-bit a value is FFh. When a8 =1, bits a7-0 are ignored, A-channel gain is set to 256/256 and B-channel gain is set to 0/256. Modified transfer functions may be selected for background/ foreground and drop-shadow effects by programming control register bits, MIXTFN. A Foreground Key may be created such that: M = ( a ) V1 Fill Color Registers Three registers, 03, 04, and 05, store a solid fill color, F. Either GBR values or YCBCR values may be stored but the format must match the data format of the A- and B-channels at the input to the crosspoint switch. Fill color registers are accessed through the D7-0 microprocessor port. Fill color may be used as an alternative video source for fades. A Background Key may be created such that: M = ( a ) V1 + V2 By using foreground and background mixers in series, drop shadow effects can be implemented. a may change at pixel rates up to 40 Mpps on a pixel-bypixel basis, allowing smooth transitions from one video source to another. Transition time interval may vary from many frames to only a few or a single pixel depending upon the a-channel data rate. a8 may be used like a key input. Either unity gain V1 or ( 1-a )V2 may be selected. A- and B-channel pixels may be mixed by switching a8 on a pixel-by-pixel basis. Pipeline latencies of the a-, A- and B-channels are matched. a-Mixer There are three sources of data for the mixer: A-channel pixels, B-channel pixels, and the stored fill color, F. One pair of inputs, either AB, BF or FA are selected by the Crosspoint Switch to be passed to the V1 and V2 inputs of the a-Mixer. Prior to mixing, V1 and V2 data formats must be matched (see Table 1). Within the a-Mixer are three dual input 9-bit mixers which mix each of the component channels of V1 and V2. By varying the value on the a-channel from 000h to 100h, the Mixer performs a 256-step transition from one digital video source to the other. Six dissolve transitions are supported: A-to-B, A-to-F, B-to-A, B-to-F, F-to-A, and F-to-B. Type of dissolve is selected by directing the A-, B-, or F pixels to the V1 or V2 mixer input via the ABF Crosspoint Switch. This is done either by internal Control Registers via the microprocessor port or directly through the SMX2-0 inputs. SMX2-0 input pins are enabled via SMX Control Register bits. When enabled, SMX2-0 directly control the ABF Crosspoint Multiplexer on a pixel-by-pixel basis, for externally derived wipe patterns. Rate of dissolve is controlled directly through the a-channel. Transfer function of the mixer is: M = ( a ) V1 + ( 1-a ) V2 where V1 and V2 are two of the three inputs A, B or F selected by the crosspoint switch. Passing of Non-Pixel Data In the PASSON mode, the TMC2081 is transparent to data accepted during the PASSEN = LOW period (see Figure 10 and Figure 11). Either PDA or PDB data may be selected to pass on reference signals containing time codes, subcarrier phase and frequency data from upstream video processors. Digital Outputs Data at the M23-0 output port, may be selected from either the mixer or, for digital preview, the A or B crosspoint switch inputs. The 444-to-422 formatter may be bypassed for 24-bit output. To convert 24-bit YCBCR data to the 16-bit YCBCR422 format, the formatter needs to be enabled. Except for color index, all data formats shown in Figure 1 are available: • YCBCR444 • YCBCR422 • GBR 6 PRODUCT SPECIFICATION TMC2081 M23-0 bits are clocked synchronously with the rising edge of CLK. M23-0 data outputs may be disabled to a high-impedance state by setting the MOUT Control Register bit LOW. 128 max.: 255 IU 0 blank: 128 IU Analog Preview Either crosspoint switch input (A or B) or the mixed pixel data output (M23-0 ) can be monitored by D/A con-verters. D/A outputs may be either YCBCR or GBR. A YCBCR-to-GBR matrix prior to the D/A converters can be selected for color-space conversion. To view A or B data originating in the CBCR format, the DACFRM Control Register bit must be set to convert 2’scomplement data to the offset binary format. With the DACSLP bit, D/A converters can be powered down and with the DACOVL bit, the D/A overlay RAM can be powered down. -127 min.: 0 IU 65-2081-05 Figure 3. CBCR DAC Output Levels in Current Units To translate IUs to millivolts, VREF and RSET must be set to the correct values, nominally VREF = 1.235 volt and RSET = 681 ohms. In each table below, G and the Y outputs have been normalized to 1000 mV with Data = 255. Since VREF and RREF are common to all D/A converters, B and R full scale outputs track G. CB CR full scale outputs track Y. RREF may be trimmed to set the G or Y full scale voltage to 1000 mV. In the equations for the GBR and YCBCR outputs that follow, symbols are defined as: + = plus * = multiply & = logical AND ! = logical complement D/A Converter Outputs Each D/A converter comprises an array of current sources referenced to VDD and controlled by the data, BLANK, and SYNC inputs. When BLANK = HIGH, the SETUP Control Register bit determines if a pedestal is activated. With nominal RREF and VREF, outputs match SMPTE 170M levels when terminated with a 37.5W resistive load (75W at the source and destination). By doubling RREF, a 75W load can be accommodated. Full scale current is set by an external resistor, RSET, connected between the RREF pin and AGND and the reference voltage, VREF. VREF may be derived from either a 1.235 volt internal source or an external voltage reference connected to VREF. Nominal outputs (see Figure 2 and Figure 3) are expressed in Current Units (IU) where 1 IU is equivalent to the current activated by one unit of D/A input data (Gdata/Ydata, Bdata/ CRdata, or Rdata/CBdata). SETUP = HIGH activates a 21 IU pedestal when BLANK= H. SYNC = LOW disables a 110 IU sync pulse. SETUP is programmed through Register 7 bit 2. GBR Output Expressed in IUs, the GBR transformation from data to current is as follows: G = (Gdata + SETUP * 21) & BLANK + SYNC * 110 B = (Bdata + SETUP * 21) & BLANK R = (Rdata + SETUP * 21) & BLANK Sample outputs are listed in Table 9 and Table 10. Table 9. GBR DAC Transfer Characteristic without Pedestal (SETUP = L) data: 255 IU max. D/A Input Data SYNC BLANK 255 128 0 X X 128 1 1 1 1 0 0 1 1 1 0 0 1 G IU 365 238 110 110 0 128 mV 1000 652 301 301 0 351 B or R IU 255 128 0 0 0 128 mV 699 351 0 0 0 351 pedestal: 21 IU sync: 110 IU 65-2081-04 Figure 2. GBR/Y DAC Output Levels in Current Units 7 TMC2081 PRODUCT SPECIFICATION Table 10. GBR DAC Transfer Characteristic with Pedestal (SETUP = H) D/A Input Data SYNC BLANK 255 128 0 X X 128 1 1 1 1 0 0 1 1 1 0 0 1 G IU 386 259 131 110 0 149 mV 1000 671 339 285 0 386 B or R IU 276 149 21 0 0 149 mV 715 386 54 0 0 386 Dissolve and Crossfade Operation Video transitions such as dissolve and fades may be executed by direct a-channel control. Rate and start time for the transition depends entirely upon the value of the a8-0 inputs. Transitions may be executed as quickly or slowly as values are presented to the a-channel. Transitions may remain partially executed by keeping a-values constant. It is possible to mix modes, bringing data in either 444 or 422 format and outputting data in 422 or 444 format. In the 444/444 mode (see Figure 7), a is applied to each YCBCR or GBR pixel pair at the input of the mixer. The YCBCR444 output is mixed at the full a rate. In the 422/422 mode (see Figure 8), a mixes the Y component of incoming PDA and PDB pixels. Only odd indexed a values mix CBCR components. a-values applied to CBCR change synchronously with CB data. Consequently, full bandwidth a data is applied to the luminance channel but the chrominance channel a values are decimated by dropping the even values that are synchronous with CR data. In the 422/444 mode (see Figure 9), YCBCR422 data is accepted at the PDA and PDB port but the output at the M23-0 port is YCBCR444. a may change from pixel-to-pixel with mixing at the M23-0 outputs tracking both Y and CBCR. Although odd values of CB and CR are repeated at half the pixel rate, a transitions are applied to CB and CR at the pixel rate. YCBCR Output Data inputs are unsigned Ydata and offset-binary format CBdata and CRdata. BLANK = L sets CB and CR outputs to 128, the value for zero chrominance data. YCBCR transfer equations are: Y = (Ydata + SETUP * 21) & BLANK + SYNC * 110 CB = (Cdata + SETUP * 21) & BLANK + 128 & !BLANK CR = (Cdata + SETUP * 21) & BLANK + 128 & !BLANK Sample outputs are listed in Table 11 and Table 12. Table 11. YCrCb DAC Transfer Characteristic without Pedestal (SETUP = L) D/A Input Data SYNC BLANK 255 128 64 0 X X 64 1 1 1 1 1 0 0 1 1 1 1 0 0 1 Y IU 365 238 174 110 110 0 64 mV 1000 652 477 301 301 0 175 CB or CR IU 255 128. 64 0 128 128 64 mV 699 351 175 0 351 351 175 Microprocessor Interface Internal Control Registers, CLUT, aLUT, and the overlay palette are accessed through a bi-directional microprocessor port, D7-0. Table 13 shows how address bits, A2-0, select the registers to be accessed. Table 13. Microprocessor Port Address Map A2-0 000 001 010 Action RAM Address Register for CLUT, aLUT, and overlay palette for write operations Directs RAM R/W operations selected by the two MSBs of Control Address Register Reserved RAM Address Register for CLUT, aLUT, and overlay palette for read operations Reserved Directs Control Register R/W operations selected by the four LSBs of the Control Address Register Mask Register (Default: Load with FF) Control Address Register Table 12. YCrCb DAC Transfer Characteristic with Pedestal (SETUP = H) D/A Data SYNC BLANK 255 128 64 0 X X 64 8 1 1 1 1 1 0 0 1 1 1 1 0 0 1 IU 386 259 195 131 110 0 85 Y mV 1000 670 505 339 285 0 220 CB or CR IU 276 149 85 21 149 149 85 mV 715 386 220 54 386 386 220 011 100 101 110 111 PRODUCT SPECIFICATION TMC2081 As shown in Table 14, to access a control register, Control Address Register bits D3-0 must be set to specify one of the nine control registers shown in Table 17. For access to LUTs and Overlay palettes, Control Address Register bits D7-6 must be set to select the address of one of the four RAMs shown in Table 14. When accessing the A-channel CLUT, or A-channel Overlay palette, each address location must be written/read three consecutive times for red (R/CR), green (G/Y), and blue (B/CB) data. After accessing the blue data, the address pointer autoincrements. In Table 16, note that: Table 14. Control Address Register Bit Definitions RAM Select Reserved Control Register Address D7 00 01 10 11 D6 D5 D4 D3 D2 D1 D0 A-channel CLUT A-channel Overlay palette Reserved aLUT 1. 2. To read the a-LUT, Control Register 06h, bit 5 must be set to enable the a-LUT. To read the CLUT and Overlay Table, Control Register 00h, bit 4 (CLUT) must be set to enable both the CLUT and Overlay Table. Data may be written to the CLUT or aLUT with Control Register bits set to enable or bypass. When writing to the a-LUT, the address pre-increments. The address pointer is set to FFh, one address before address 00h. Load mask register to pass PDA data. 3. 4. Figure 4 and Figure 5 show the microprocessor port read and write timing cycles. Table 15 shows the Control Register read and write sequences. When loading or reading look-up tables or the overlay palette, with the exception of a-LUT write, the address pointer is auto-incremented after each read or write operation. For a-LUT write, the address pointer is pre-incremented, so that the address must be set one address before the required address. For a-LUT read, the address pointer is postincremented. 5. Power and Ground The TMC2081 operates from a single +5 Volt power supply. Multiple power and ground pins are assigned and must be connected. Table 15. Control Register Read/Write Sequences Step 1 2 . 15 16 1 2 . 3 R/W 0 0 .. 0 0 0 1 .. 0 A2-0 111 101 .. 111 101 111 101 .. 101 D7-0 x0 aa .. 07 bb x2 aa .. bb Function Writes 0 to Address Control Register (selects the A-channel Control Register) Writes aa into A-channel Control Register Repeat steps 1 and 2 incrementing data to Address Control Register Writes 07 to Address Control Register (selects the D/A Control Register) Writes bb into D/A Control Register Writes 02 to Address Control Register (selects the Mixer Control Register) Mixer Control Register contents, aa, available on D7-0. System modifies aa to get bb. Writes bb into Mixer Control Register Write to all Control Registers Read/Modify/Write Mixer Control Register 9 TMC2081 PRODUCT SPECIFICATION Table 16. CLUT Read/Write Sequences Step 1 2 3 4 5 . 768 769 770 1 2 3 4 5 1 2 3 . 258 1 2 3 4 5 . 260 R/W 0 0 0 0 0 .. 0 0 0 0 0 0 0 0 0 0 0 .. 0 0 1 0 0 1 .. 1 A2-0 111 000 001 001 001 .. 001 001 001 111 000 001 001 001 111 000 001 .. 001 111 101 101 011 001 .. 001 D7-0 0x 00 r0 g0 b0 .. r255 g255 b255 4x an rn gn bn Cx FF aa .. zz C6 aa bb 00 cc .. zz Selects A-CLUT for write. Presets RAM Address Register to 00. r0 written into red (R/CR) CLUT address 00. g0 written into green (G/Y) CLUT address 00. b0 written into blue (B/CB) CLUT address 00. repeat steps 3,4,5 until A-CLUT is full. r255 written into red (R/CR) CLUT address FF. g255 written into green (G/Y) CLUT address FF. b255 written into blue (B/CB) CLUT address FF. Select A-channel Overlay. Write an into RAM Address Register. rn written into red (R/CR) CLUT address. gn written into green (G/Y) CLUT address. bn written into blue (B/CB) CLUT address. Select aLUT. Write FF into RAM Address Register (sets address to FF for pre-increment). Write aa to aLUT location 00. Repeat step 3, 254 times for locations 01h-FEh. Write zz, to aLUT location FF. Select aLUT and Register 06 in Address Control Register. Read Control Register 06. bb = (aa OR 20h) to set bit 5. Restores aa with aLUT enabled. Write 00 into RAM Address Register (sets address to 00). Read contents of aLUT, cc, from location 00. Repeat step 5, 254 times for locations 01h-FEh. Read contents of aLUT, zz, from last location FF. Function Write Entire A-Channel CLUT from Address 00 Write GBR Data to A-Overlay Location Address Write all aLUT Locations starting from 00 Read All aLUT Locations Starting from 00 10 PRODUCT SPECIFICATION TMC2081 Pin Assignments 128 Pin Plastic Quad Flat Pack (PQFP) Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name Pin D5 33 D4 34 D3 35 D2 36 D1 37 D0 38 CS 39 R/W 40 A0 41 A1 42 A2 43 SIG0 44 PASSEN 45 AV 46 OL3 47 VDD 48 DGND 49 50 OL2 51 OL1 52 OL0 53 PDA23 54 PDA22 55 PDA21 56 PDA20 57 PDA19 58 PDA18 59 PDA17 60 PDA16 61 PDA15 62 PDA14 63 PDA13 64 PDA12 Name PDA11 PDA10 PDA9 PDA8 PDA7 PDA6 PDA5 PDA4 PDA3 PDA2 PDA1 PDA0 a8 a7 VDD DGND a6 a5 a4 a3 a2 a1 a0 SMX2 SMX1 SMX0 CLK BLANK SYNC VREF RREF AGND Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name R/CR B/CB AGND G/Y COMP VDDA VDDA PDB23 PDB22 PDB21 PDB20 PDB19 PDB18 PDB17 PDB16 PDB15 PDB14 PDB13 PDB12 PDB11 PDB10 PDB9 PDB8 PDB7 PDB6 PDB5 PDB4 PDB3 PDB2 PDB1 PDB0 M23 Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Name M22 M21 M20 M19 M18 M17 M16 DGND VDD M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 AVOUT PASS14 SIG14 DGND VDD D7 D6 128 1 97 96 32 34 65 64 65-2081-06 11 TMC2081 PRODUCT SPECIFICATION Pin Descriptions Name Clock CLK 59 TTL Clock Input. TTL-compatible clock. All pixel data is registered on the rising edge of CLK. CLK synchronizes the flow of pixel data through the TMC2081 and the operation of the a-input. A-Channel Pixel Inputs. A-channel pixel inputs are registered on the rising edge of CLK and specify which of the CLUT locations are addressed after masking. The CLUT in the A-Channel may be bypassed. PDA7-0 are applied to all three CLUT sections when colorindex pixel data is used. B-Channel Pixel Inputs. B-channel pixel inputs are registered on the rising edge of CLK and are applied to the mixer after color-space conversion, and interpolation, if selected. a-Channel Inputs. The a-channel inputs are registered on the rising edge of CLK and control proportional mixing at pixel rates up to 40 Mpps. a8 acts as a key input, switching A- and B-channel pixel data on a pixel-by-pixel basis. a0 is the LSB. ABF Crosspoint Mux Control. When enabled by setting the SMX Control Register bits to 111, these inputs control the ABF Crosspoint Switch which directs the A- or B-channel pixels or the fill color register values to the V1 or V2 inputs to the mixer. SMX2-0 input pins are ignored when the SMX Control Register bits are not 111. SMX2-0 are registered on the rising edge of CLK. ABF Crosspoint Switch control is according to the following: SMX2-0 000 001 010 011 100 101 110 111 OL3-0 15,18-20 TTL V1 A A B B F F V2 B F A F A B Pin Number Value Pin Function Description Pixel I/O PDA23-0 21-44 TTL PDB23-0 72-95 TTL a8-0 45,46,49-55 TTL SMX2-0 56-58 TTL Overlay Inputs. Overlay inputs select one of 15 overlay colors from the PDA overlay palette. OL3-0 are registered on the rising edge of CLK. When PDA or overlay is enabled and OL3-0 > 0, the contents of the addressed palette are selected in place of the pixel data. Overlay is inactive when OL3-0 = 0h or when disabled via the Control Registers. OL0 is the LSB. Mixed Pixel Outputs. Mixer output or digital preview of the V1 and V2 Crosspoint Switch outputs are synchronized to the rising edge of CLK. M23-0 date is passed on for further processing (mixing, encoding, etc.). Pipeline latency is 14 clock cycles. M23-0 96-103, 106-121 TTL 12 PRODUCT SPECIFICATION TMC2081 Pin Descriptions (continued) Name PASSEN SIG0 PASS14 SIG14 AV Pin Number 13 12 123 124 14 Value TTL TTL TTL TTL TTL Pin Function Description Pass Enable Input. Data selected by A/BPASS is enabled by PASSEN. Signal 0 Input. Input to a 14 CLK delay. Output is at SIG14. Pass Enable Output (14 Clock Delay). PASSEN delayed by 14 CLK cycles to match the pipeline latency of pixels Signal 0 Output (14 Clock Delay). SIG0 delayed to match the 14 CLK cycles pipeline latency of pixels Active Video Input. When HIGH, AV enables data from the PDA and PDB ports. When LOW, at the M23-0 output, GBR data is set to zero and YCBCR data is set to 10h 80h 80h in the offset binary format and 10h 00h 00h in 2’s complement format. In the 422 mode, AV transitioning HIGH defines the next pixel to be the first CB pixel. Delayed AV Output. AV delayed by either 12 or 14 clock cycles. A 14 clock cycle delay matches the pipeline delay of the A and B channels. A 12 clock cycle delay is useful for interfacing with Fairchild Encoders. Sync Enable for G/Y D/A. D/A Converter sync enable. SYNC= LOW, disables a current source at the G/Y output, forcing the sync tip to zero volts. SYNC = HIGH, activates the sync current at the G/Y output. SYNC is delayed either 2 or 15 clock cycles according to the status of the DACDLY bit. To disable sync on G/Y, ground SYNC. Blanking Control for D/As. D/A Converter blanking input. BLANK = LOW disables the data and pedestal output currents. If BLANK = HIGH, data and pedestal currents are added to the SYNC current. BLANK is delayed either 2 or 15 clock cycles according to the status of the DACDLY bit. For blank levels, see Tables 9, 10, 11, and 12. Read/Write Control. Read-Write control input. R/W controls the direction of the D7-0 port. If R/W = HIGH and CS is LOW, registers or CLUTs may be read. If R/W = LOW and CS = LOW, data may be written to control registers or CLUTs via the D7-0 port. R/W is latched on the falling edge of CS. Chip Select. Chip Select Input. If CS = HIGH, port, D7-0, is set to highimpedance. If CS = LOW, port D7-0 is enabled. Read data (R/W = HIGH) is enabled on the falling edge of CS. Write data is latched into the TMC2081 on the rising edge of the CS. CLUT, aLUT, or overlay read/write operations require CS to be HIGH for at least 4 CLK cycles after CS = LOW. Register Select Controls. Address bits input. A2-0 select registers or tables to be accessed (see Table 13) via D7-0. A2-0 are latched on the falling edge of CS. Data I/O Port. Bi-directional data port. D0 is the LSB. Control Registers, CLUT, aLUT and Overlay locations are accessed via D7-0. Green/Luminance Video. The green/luminance analog video output. Sync pulses are included on this output. Blue/CB Video. Blue/CB analog video output. Red/CR Video. Red/CR analog video output. Video Controls AVOUT 122 TTL SYNC 61 TTL BLANK 60 TTL Microprocessor I/O R/W 8 TTL CS 7 TTL A2-0 11-9 TTL D7-0 Video Output G/Y B/CB R/CR 127,128, 1-6 68 66 65 TTL 1 V P-P 0.7 V P-P 0.7 V P-P 13 TMC2081 PRODUCT SPECIFICATION Pin Descriptions (continued) Name Reference VREF 62 +1.23 V Voltage Reference Input/Output. An internal voltage source of +1.2 Volts (nominal) is applied to the VREF terminal. This is the reference for all three D/A converters of the TMC2081. Decoupling VREF to AGND with a 0.1mF ceramic capacitor is recommended. This pin may also be used as an input for an external voltage reference source. Current-Setting Resistor. Full-scale output current of the TMC2081 is determined by the value of the resistor connected between RREF and AGND. Varying this resistor will vary the “white” output level for all three D/A converters. The TMC2081 is not designed for operation with an external current reference. Compensation Capacitor. A 0.1 mF ceramic capacitor is connected between the COMP and VDDA at pin 70 or 71. Analog Power Supply. The TMC2081 operates from a single +5V supply. All power pins must be connected. VDDA and VDD must be derived from a common power supply. Digital Power Supply. The TMC2081 operates from a single +5V supply. All power pins must be connected. VDDA and VDD must be derived from a common power supply. Analog Ground. All ground pins must be connected. Digital Ground. All ground pins must be connected. Pin Number Value Pin Function Description RREF 63 681 W COMP Power, Ground VDDA 69 0.1 mF 70,71 +5 V VDD 16,47,105,126 +5 V AGND DGND 64,67 17,48,104,125 0.0 V 0.0 V 14 PRODUCT SPECIFICATION TMC2081 Control Register Map Reg 00 00 00 00 00 00 00 Bit 7 6 5 4 3 2 1-0 Name AOVLEN ADEC AMAT CLUT AMSB aGAIN AFORMAT Function A-channel Overlay enable/disable Decimator bypass/enable A-channel GBR-to-YCBCR bypass/enable Bypass/enable CLUT (power down) Inverts CB/CR MSB Alpha Channel 9-/8-bit gain A Pixel data path setup (4 formats) Reserved MSOURCE BMAT BINT BMSB BFORMAT M23-0 pixel source Bypass/enable the Bchannel YCBCR-to-GBR Bypass/enable Interpolator Inverts CB/CR MSB B Pixel data path setup (4 formats) Mixer format select Selects data source for the internal D/A converters Chooses video source to be directed to the mixer imputs, V1 and V2 Used to alter the mixer transfer function Value for Red/CR Value for Green/Y Value for Blue/CB 08 09 7-0 7-0 REVID CHIPID 07 07 07 2 1 0 DMAT SETUP 06 06 06 07 07 07 2 1 0 7-6 5 4 DACDLY DACFMT MOUT MMSB MFORMAT Reg 06 06 06 06 06 Bit 7 6 5 4 3 aLUTEN PASSON A/BPASS Name AVPIPE Function Sets pipeline latency of AV Reserved aLUTEN power down enable Sets pixel activity subject to mixer transfer function Selects A or B data in PASSON mode Bits M23-0 enable Inverts CB, CR MSBs Sets output data format Reserved Selects SYNC and BLANK pipe delay CB/CR translate from 2’s complement to offset binary D/A converters enable/ disable Sets IRE blanking levels Reserved D/A converter input data YCBCR/GBR conversion Chip revision ID Chip type ID = 2F A-Channel Control Register Output Control Register B-Channel/Mixer Control Register 01 01 01 01 01 01 7 6-5 4 3 2 1-0 D/A Control Register 07 3 AWAKE Mixer Control Register 02 02 02 7 6-5 4-2 MIXFMT DSOURCE SMX Identification (read-only) 02 1-0 MIXTFN Control Register Definitions Fill Color Registers 03 04 05 7-0 7-0 7-0 REDVAL GRNVAL BLEVAL 15 TMC2081 PRODUCT SPECIFICATION A-Channel Control Register (00) 7 AOVLEN Reg 00 00 Bit 7 6 6 ADEC Name AOVLEN ADEC 5 AMAT Description When HIGH, the Overlay palette in the PDA pixel path is enabled and controlled by the OL3-0 inputs. When LOW, the PDA Overlay palette is disabled. When HIGH, this bit causes A-channel pixel data to be decimated from YCBCR444 to YCBCR422 format. When LOW, no decimation takes place and the data is passed through. When HIGH, the A-channel pixel data is converted from GBR to YCBCR format. When LOW, no conversion takes place and the data is passed through. When HIGH, the A-channel CLUT is enabled and addressed by pixel data. When LOW the CLUT is bypassed. When LOW,the MSBs of the A-channel CB and CR (PDA15 and PDA7) are passed though. When HIGH, the MSBs of the CB and CR are inverted. a-channel gain. LOW selects 9-bit unity gain. HIGH selects 8-bit gain. For 8-bit a mixing, set a8 = 0. These two bits set up the A channel data path to accommodate four different formats: 0 0 YCBCR444 0 1 YCBCR422 1 0 8-bit color index 1 1 24-bit GBR 4 CLUT 3 AMSB 2 aGAIN 1 AFORMAT 0 00 00 00 00 00 5 4 3 2 1-0 AMAT CLUT AMSB aGAIN AFORMAT Control Register Definitions (continued) B-Channel Control Register (01) 7 Reserved Reg 01 01 Bit 7 6-5 MSOURCE 6 MSOURCE Name Description Reserved. Source of pixels to be connected to port M23-0. 0 0 Mixer Pixels 0 1 A pixels 1 0 B pixels 1 1 Reserved When HIGH, the B-channel pixel data is converted from YCBCR to GBR format. When LOW, no conversion takes place and the data is passed through. When HIGH, B-channel pixel data is interpolated from the YCBCR422 to the YCBCR444 format. When LOW, no interpolation takes place and the data is passed through. When LOW, the MSBs of the B-channel CB and CR bytes (PDB15 and PDB7) are passed through. When HIGH, the MSBs of the CB and CR bytes are inverted. B-channel pixel data format select bits. 0 0 YCBCR444 0 1 YCBCR422 1 0 Reserved 1 1 24-bit GBR 5 4 BMAT 3 BINT 2 BMSB 1 BFORMAT 0 01 01 4 3 BMAT BINT 01 01 2 1-0 BMSB BFORMAT 16 PRODUCT SPECIFICATION TMC2081 Control Register Definitions (continued) Mixer Control Register (02) 7 MIXFMT Reg 02 02 Bit 7 6-5 Name MIXFMT DSOURCE 6 DSOURCE Description When LOW, the mixer is set for YCBCR format. When HIGH, the mixer expects GBR format. The data source for the internal D/A converters is selected by two control bits. 0 0 A-pixels 0 1 B-pixels 1 0 Mixed pixels 1 1 Reserved These three control bits determine which video sources (A-pixels, B-pixels, fill color registers) are directed to the two mixer inputs, V1 and V2, through the ABF Crosspoint Mux: 0 0 0 A to V1, B to V2 0 0 1 A to V1, F to V2 0 1 0 B to V1, A to V2 0 1 1 B to V1, F to V2 1 0 0 F to V1, A to V2 1 0 1 F to V1, B to V2 1 1 0 Reserved 1 1 1 Enables SMX2-0 inputs for external source select These two bits are used to alter the mixer transfer function: 0 0 (V1 – V2)a + V2 0 1 (V1) a + V2 1 0 (V1) a 1 1 Reserved 5 4 3 SMX 2 1 MIXFTN 0 02 4-2 SMX 02 1-0 MIXTFN Fill Color Registers (03–05) Reg 03 04 05 Bit 7-0 7-0 7-0 Name REDVAL GRNVAL BLUVAL Description Value for Red/CR Value for Green/Y Value for Blue/CB 17 TMC2081 PRODUCT SPECIFICATION Control Register Definitions (continued) Output Control Register (06) 7 AVPIPE Reg 06 06 06 Bit 7 6 5 aLUTEN 6 Reserved Name AVPIPE 5 aLUTEN 4 PASSON 3 A/BPASS 2 MOUT 1 MMSB 0 MFORMAT Description When LOW the pipeline latency from AV, to AVOUT is 14 CLK cycles. When HIGH, the pipeline latency is 12 CLK cycles. Reserved. When LOW (write only), the aLUTEN is powered down. Data from a8-0 bypasses the aLUT to control the mixer directly. When HIGH, a7-0 addresses the aLUT which controls the mixer. When HIGH, either PDA or PDB data may be selected to pass through the mixer without modification. When LOW the mixer transfer function is enabled if the PASSEN input is HIGH. The PASSON feature allows Genlock or Decoder reference signals to be passed downstream for subsequent processing. Selects A or B data in PASSON mode. LOW allows all pixels from PDA23-0 during PASSEN = LOW to pass to M23-0. HIGH allows all pixels from PDB23-0 during PASSEN = LOW to pass to M23-0. Digital outputs M23-0 are enabled when this bit is HIGH. These outputs are in a high-impedance state when MOUT is LOW. When LOW, the MSBs of the CB and CR M23-0 output positions (M15 and M7) are not inverted. When HIGH, the MSBs of the CB and CR output positions are inverted. When LOW, 24-bit GBR or YCBCR444 output data formats are enabled. When HIGH, the multiplexer in the M23-0 path is enabled producing 16-bit YCBCR422. 06 4 PASSON 06 3 A/BPASS 06 06 2 1 MOUT MMSB 06 0 MFORMAT D/A Control Register (07) 7 Reserved Reg 07 07 07 07 07 07 07 Bit 7-6 5 4 3 2 1 0 DMAT DACDLY DACFMT AWAKE SETUP Name 6 5 DACDLY 4 DACFMT 3 AWAKE 2 SETUP 1 DOVLEN 0 DMAT Description Reserved. Selects SYNC and BLANK pipe delay. LOW = 15 clocks, HIGH = 2 clocks. Translates CB/CR format from 2’s complement to CB/CR offset binary. LOW passes CB/CR unchanged. HIGH inverts CB/CR MSB. D/A converters are enabled when HIGH. The D/A converters are powered-down when AWAKE is LOW. When LOW, 0 IRE blanking levels are present on the D/A converter outputs. When HIGH, blanking levels are 7.5 IRE units. Reserved. When HIGH, D/A converter input data is converted from YCBCR to GBR format. When LOW, no conversion takes place and the data is passed through. 18 PRODUCT SPECIFICATION TMC2081 Control Register Definitions (continued) Identification Registers (08-09) Reg 08 09 Bit 7-0 7-0 Name REVID PARTID Description Chip revision identification. Chip type identification = 2F. Absolute Maximum Ratings Parameter Power Supply Voltage Input Voltage Digital Inputs Applied voltage2 Externally forced current 3, 4 Digital Outputs Applied voltage2 Externally forced current3, 4 (beyond which the device may be damaged)1 Min. -0.5 -0.5 -0.5 -20.0 -0.5 -20.0 Max. +7.0 (VDD + 0.5) (VDD+ 0.5) 20.0 (VDD+ 0. 5) 20.0 1 second infinite -60 +130 +150 300 +220 -65 150 °C °C °C °C °C Unit V V V mA V mA Short Circuit Duration (Single output in HIGH state to GND) Analog Output Short Circuit Duration (Single output to GND) Temperature Operating, case Operating, Junction, Plastic package Lead, soldering (10 seconds) Vapor phase soldering (1 minute) Storage Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 19 TMC2081 PRODUCT SPECIFICATION Operating Conditions Parameter VDD VIH Power Supply Voltage Input Voltage, Logic HIGH TTL Inputs, all but CLK, CE CLK, CE VIL IOH IOL VREF IREF RREF ROUT TA Input Voltage, Logic LOW TTL Inputs Output Current, Logic HIGH Output Current, Logic LOW External Reference Voltage D/A Converter Reference Current (IREF = VREF / RREF, sourced from RREF pin) Reference Resistor @ VREF = Nom. Total Output Load Resistance Ambient Temperature, Still Air 0 681 37.5 70 W W °C 1.235 1.8 GND 0.8 -2.0 4.0 V mA mA V mA 2.0 2.4 VDD VDD V V Min. 4.75 Nom 5.0 Max. 5.25 Units V Electrical Characteristics Parameter IDD IDDQ IDAC ICLUT IaLUT IDDSE VRO IBR IIH IIL VOH VOL IOZH IOZL CI CO VOC ROUT COUT Power Supply Current1 Power Supply Current1 DAC Supply Current CLUT Supply Current aLUT Supply Current Power Supply Current Voltage Reference Output Input Bias Current, VREF Input Current, Logic HIGH Input Current, Logic LOW Output Voltage, Logic HIGH Output Voltage, Logic LOW High-Z Leakage Current, HIGH High-Z Leakage Current, LOW Digital Input Capacitance Digital Output Capacitance Video Output Compliance Voltage Video Output Resistance Video Output Capacitance IOUT = 0mA, f = 1MHz VREF = Nom VDD = Max, VIN = 4.0V VDD = Max, VIN = 0.4V IOH = Max IOL = Max VDD = Max, VIN = VDD VDD = Max, VIN = GND TA = 25°C, f = 1MHz TA = 25°C, f = 1MHz -0.4 15 15 25 -5 -5 15 15 2.0 Sleep Mode (D/A, CLUT, aLUT, and D/A overlay disabled) 0.98 -100 -5 -5 2.4 0.4 5 5 Conditions fCLK = 25MHz, DAC, CLUT and aLUT enabled fCLK = 0 DAC, CLUT and aLUT enabled fCLK = 25MHz Min. Typ. 300 260 80 85 30 5 1.2 Max. 360 330 100 100 45 15 1.48 40 5 5 Units mA mA mA mA mA mA V mA mA mA V V mA mA pF pF V KW pF Note: 1. Typical IDD measured at VDD = +5.0 Volts and TA = 25°C, Maximum IDD measured at VDD = + 5.25 Volts and TA = 0°C. 20 PRODUCT SPECIFICATION TMC2081 Switching Characteristics Parameter Microprocessor Interface tPWLCS tPWHCS tSA tHA tSD tHD tDOZ tDOM tHOM fPXL tCYPX tPWH tPWL tSP tHP tHO tDO PIPES tR tF tDOV SKEW CS Pulse Width, LOW CS Pulse Width, HIGH Address Setup Time Address Hold Time Data Setup Time (write) Data Hold Time (write) Output Delay, CS to low-Z Output Delay, CS to Data Valid Output Hold Time, CS to High-Z Pixel Rate Pixel Cycle Period CLK Pulse Width, HIGH CLK Pulse Width, LOW For PDA, PDB, a, SMX, OL, PASSEN, SIG0, AV inputs: Setup Time Hold Time Output Hold Time, CLK to data disabled Output Delay, CLK to data valid Pipeline Delay D/A Output Current Risetime (10% - 90%) D/A Output Current Falltime (10% - 90%) Analog Output Delay D/A to D/A Output Skew 15 6 3 20 1 6 2 6 17 ns ns ns ns CLKs ns ns ns ns 25 6 6 7 40 0 4 6 3 16 110 95 4/fPXL ns ns ns ns ns ns ns ns ns Mpps ns ns ns Min. Nom. Max. Units Pixel Interface Analog Outputs Notes: 1. Timing reference points are at the 50% level. 2. Analog and digital CLOAD = 15pF. 3. TTL input levels are 0.0 and 3.0 Volts, 10% - 90% rise and fall times < ns. System Performance Characteristics Parameter VVID VSYNC RES ELI ELD EG Conditions Video Amplitude with 37.5 W load Sync Amplitude with 37.5 W load D/A Converter Resolution D/A Integral Linearity Error D/A Differential Linearity Error D/A Gain Error Min. Typ. 0.7 0.3 8 0.75 0.75 ±11 Max. Units Volt Volt Bits LSB LSB % FS 21 TMC2081 PRODUCT SPECIFICATION Timing Diagrams tPWLCS tHD tSA CS R/W A[2:0] D[7:0] 65-2081-07 tSA tSD tPWHCS Figure 4. Microprocessor Port Write Timing tPWLCS tDOM tSA CS R/W A[2:0] D[7:0] 65-2081-08 tHA tDOZ tPWHCS tHOM Figure 5. Microprocessor Port Read Timing tSP tHP CLK PDA, PDB, alpha, SMX OL, PASSEN, SIG0 tHO tDO 14 clock delay M, PASS14, SIG14 AV 12 (Raytheon Encoders) or 14 clock delay AVOUT 15 clock delay ANALOG 65-2081-09 tPWL tPWH tPXL Figure 6. Pixel Timing 22 PRODUCT SPECIFICATION TMC2081 Timing Diagrams (continued) CLK AV alpha PDAY PDACB PDACR PDBY PDBCB PDBCR a1 a2 a3 a4 AY1 AY2 AY3 AY4 ACb1 ACb2 ACb3 BCb4 ACr1 ACr2 ACr3 BCr4 BY1 BY2 BY3 BY4 BCb1 BCb2 BCb3 BCb4 BCr1 BCr2 BCr3 BCr4 14 Clock Pipeline Delay MY MCB MCR 16 a1, AY1 ,BY1 a1, ACb1, BCb1 a1, ACr1, BCr1 a2, AY2, BY2 a2, ACb2, BCb2 a2, ACr2, BCr2 a3, AY3, BY3 a3, ACb3, BCb3 a3, ACr3, BCr3 a4, AY4, BY4 a4, ACb4, BCb4 a4, ACr4, BCr4 65-3701-05 128 128 Figure 7. Pixel/Alpha Data Timing – 444/444 Mode CLK AV alpha PDAY PDACBCR PDBY PDBCBCR a1 a2 a3 a4 AY1 AY2 AY3 AY4 ACb1 ACr1 ACb3 ACr3 BY1 BY2 BY3 BY4 BCb1 BCr1 BCb3 BCr3 14 Clock Pipeline Delay MY MCBCR 16 a1, AY1 ,BY1 a1, ACb1, BCb1 a2, AY2, BY2 a1, ACr1, BCr1 a3, AY3, BY3 a3, ACb3, BCb3 a4, AY4, BY4 a3, ACr3, BCr3 65-3701-06 128 Figure 8. Pixel/Alpha Data Timing – 422/422 Mode 23 TMC2081 PRODUCT SPECIFICATION Timing Diagrams (continued) CLK AV alpha PDAY PDACBCR PDBY PDBCBCR a1 a2 a3 a4 AY1 AY2 AY3 AY4 ACb1 ACr1 ACb3 ACr3 BY1 BY2 BY3 BY4 BCb1 BCr1 BCb3 BCr3 14 Clock Pipeline Delay MY MCB MCR 16 a1, AY1 ,BY1 a2, AY2, BY2 a3, AY3, BY3 a4, AY4, BY4 128 a1, ACb1, BCb1 a1, ACr1, BCr1 a2, ACb1, BCb1 a2, ACr1, BCr1 a3, ACb3, BCb3 a3, ACr3, BCr3 a4, ACb3, BCb3 a4, ACr3, BCr3 65-3701-07 128 Figure 9. Pixel/Alpha Data Timing – 422/444 Mode CLK 0 clock min. PASSEN AV PDBY/G PDBCB/B PDBCR/R alpha(8..0) 14 clock delay MY/G MCB/B MCR/R DY(1) DY(2) DY(1) DY(2) Y(1) Y(2) 0 clock min. DCB(1) DCB(2) CB(1) CB(2) DCR(1) DCR(2) CR(1) CR(2) alpha(1) alpha(2) DCB(1) DCB(2) DCR(1) DCR(2) 65-3701-08 Figure 10. PASSON Timing – 444 Mode (Control bits: PASSON = HIGH, A/BPASS = HIGH) 24 PRODUCT SPECIFICATION TMC2081 Timing Diagrams (continued) CLK 1 clock min. PASSEN 1 clock min. AV PDBY PDBCBCR alpha(8..0) 14 clock delay MY MCBCR DY(1) DY(2) DY(1) DY(2) Y(1) Y(2) DCB(1) DCB(2) CB(1) CB(2) alpha(1) alpha(2) DC B(1) DC B(2) 65-3701-09 Figure 11. PASSON Timing – 422 mode (Control bits: PASSON = HIGH, A/BPASS = HIGH) Equivalent Circuits VDD VDD p Digital Input n p Digital Output n 27011B 27014B GND GND Figure 12. Equivalent Digital Input Circuit Figure 13. Equivalent Digital Output Circuit 25 TMC2081 PRODUCT SPECIFICATION Equivalent Circuits (continued) VDD VDD p RREF VREF p n VDD p OUT GND 27012B GND 27013B Figure 14. Equivalent Analog Input Circuit Figure 15. Equivalent Analog Output Circuit tENA OEN tDIS 0.5V 2.0V 0.8V Three-State Outputs High Impedance 0.5V 7048A Figure 16. Threshold Levels for Three-State Measurement Application Information Graphics Preview Computer/ Graphics a, SMX RGB RGB Analog Preview PDA TMC22053 Digital Decoder YCBCR PDB Microprocessor Bus Composite Analog Video TMC2081 Digital Video Mixer TMC22x90 Digital Video Encoder Studio Quality Video TMC22071A Genlocking Video Digitizer 65-3701-10 Figure 17. Mixing Video and Computer Graphics – Basic Multimedia System 26 PRODUCT SPECIFICATION TMC2081 Application Notes (continued) a1, SMX1 Mix Controller a2, SMX2 PDA PDB YCBCR422 or YCBCR444 Composite Digital Video TMC2081 Digital Video Mixer 1 YCBCR444 Analog Preview 1 Analog Preview 2 PDA PDB TMC2081 Digital Video Mixer 2 TMC22x90 Digital Video Encoder YCBCR444 Studio Quality Video 65-3701-11 Figure 19. Multilevel Video Mixer with Special Effects a, SMX Mix Controller Genlock Computer Digital Video Source 1 RGB Analog Preview PDA Computer Digital Video Source 1 RGB PDB RGB/YCBCR444 TMC2081 Digital Video Mixer TMC22x90 Digital Video Encoder Studio Quality Video 65-3701-12 Figure 20. Mixing Two Computer Graphics Sources 27 TMC2081 PRODUCT SPECIFICATION Application Notes (continued) VDDA PDA 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 20 19 18 15 55 54 53 52 51 50 49 46 45 58 57 56 ACTIVE VIDEO PASSON ENABLE SIG0 CLOCK 14 13 12 PDA0 PDA1 PDA2 PDA3 PDA4 PDA5 PDA6 PDA7 PDA8 PDA9 PDA10 PDA11 PDA12 PDA13 PDA14 PDA15 PDA16 PDA17 PDA18 PDA19 PDA20 PDA21 PDA22 PDA23 PDB0 PDB1 PDB2 PDB3 PDB4 PDB5 PDB6 PDB7 PDB8 PDB9 PDB10 PDB11 PDB12 PDB13 PDB14 PDB15 PDB16 PDB17 PDB18 PDB19 PDB20 PDB21 PDB22 PDB23 OL0 OL1 OL2 OL3 ALPHA0 ALPHA1 ALPHA2 ALPHA3 ALPHA4 ALPHA5 ALPHA6 ALPHA7 ALPHA8 SMX0 SMX1 SMX2 AV PASSEN SIG0 CLK M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 G/Y B/CB R/CR VREF COMP RREF SYNC BLANK AVOUT PASS14 SIG14 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 103 102 101 100 99 98 97 96 68 66 65 62 69 63 61 60 122 123 124 R4 681 D1 LM185-1.2 AV+14 CLKS PASS_EN+14 CLKS SIG0+14 CLKS C1 0.1 MIXER OUTPUT PDB 75 ohm external load expected for correct output voltages Total expected load is 37.5 ohms. G/Y OUT B/CB OUT R/CR OUT R1 75 R2 75 R3 75 OL VDDA L7 C1 BEAD 0.1 VDD ALPHA C1 0.1 C1 0.1 C1 0.1 C1 0.1 C1 0.1 SMX D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 R/W CS 6 5 4 3 2 1 128 127 9 10 11 8 7 Use single ground plane for analog and digital power. Isolate analog lands from digital lands. TMC2081KB MICROBUS BLANK* SYNC* 65-3701-13 Figure 21. Recommended TMC2081 Connections Related Products • • • • • TMC2072 Genlocking Video Digitizer TMC22190/191 Digital Video Encoder TMC2242A/TMC2246A Digital Filter TMC2272A Color Space Converter TMC22053 Decoder 28 PRODUCT SPECIFICATION TMC2081 Mechanical Dimensions – 128-Lead MQFP Package Symbol A A1 B C D/E D1/E1 e L N ND a ccc Inches Min. — .010 .012 .005 1.219 Max. .160 — .018 .009 1.238 Millimeters Min. — .25 .30 .13 30.95 Max. 4.07 — .45 .23 31.45 3, 5 5 Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness. 4 1.098 1.106 .0315 BSC .029 .041 128 32 0¡ — 7¡ .004 27.90 28.10 .80 BSC .73 1.03 128 32 0¡ — 7¡ 0.10 D D1 e PIN 1 IDENTIFIER E Datum Plane E1 0.063" Ref (1.60mm) Lead Detail L .20 (.008) Min. 0¡ Min. .13 (.005) R Min. .13/.30 R .005/.012 C a See Lead Detail A A1 B Seating Plane Base Plane -CLEAD COPLANARITY ccc C 29 TMC2081 PRODUCT SPECIFICATION Notes: 30 PRODUCT SPECIFICATION TMC2081 Notes: 31 TMC2081 PRODUCT SPECIFICATION Ordering In formation Product Number TMC2081KBC Temperature Range TA = 0°C to 70°C Screening Commercial Package 128-Lead MQFP Package Marking 2081KBC LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 5/20/98 0.0m 001 Stock# DS70002081 Ó 1998 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.