TMC2490A

www.fairchildsemi.com TMC2490A Multistandard Digital Video Encoder Features • All-digital video encoding • Internal digital subcarrier synthesizer • 8-bit parallel CCIR-601/CCIR-656/ANSI/SMPTE 125M input format • CCIR-624/SMPTE-170M compliant output • Switchable chrominance bandwidth • Switchable pedestal with gain compensation • Pre-programmed horizontal and vertical timing • 13.5 Mpps pixel rate • Master or slave (CCIR656) operation • MPEG interface • Internal interpolation filters simplify output reconstruction filters • 10-bit D/A converters for video reconstruction • Supports NTSC and PAL standards • Closed-caption waveform insertion • Simultaneous S-Video (Y/C) output • Controlled edge rates • Single +5V power supply • 44 lead PLCC package • Parallel and serial control interface Applications • Set-top digital cable television receivers • Set-top digital satellite television receivers • Studio parallel CCIR-601 to analog conversion Description The TMC2490A video encoder converts digital component video (in 8-bit parallel CCIR-601/656 or ANSI/SMPTE 125M format) into a standard analog baseband television (NTSC, NTSC-EIA, and all PAL standards) signal with a modulated color subcarrier. Both composite (single lead) and S-Video (separate chroma and luma) formats are active simultaneously at all three analog outputs. Each video output generates a standard video signal capable of driving a singlyor doubly-terminated 75 Ohm load. The TMC2490A is intended for all non-Macrovision encoder applications. The TMC2490A is fabricated in a submicron CMOS process and is packaged in a 44-lead PLCC. Performance is guaranteed over the full 0°C to 70°C operating temperature range. Block Diagram LPF B-Y PD7-0 PIXEL DATA DEMUX AND SYNC EXTRACT PXCK Y HSYNC VSYNC, B/T SELC PDC/CBSEL DIGITAL SYNC AND BLANK GENERATOR INTERPOLATION FILTER REF SERIAL/PARALLEL CONTROL GLOBAL CONTROL VREF CBYP RREF 65-2490(1)A-01 INTERPOLATOR 4:2:2 TO 4:4:4 R-Y LPF CHROMA MODULATOR INTERPOLATION FILTER 10-BIT D/A CHROMA S-VIDEO LUMA COMPOSITE SUBCARRIER SYNTHESIZER 10-BIT D/A 10-BIT D/A SERIAL PARALLEL SA1 SA0 ADR SDA R/W SCL CS D7-0 D7-0 SER RESET REV. 1.0.2 2/27/02 TMC2490A PRODUCT SPECIFICATION Functional Description The TMC2490A is a fully-integrated digital video encoder with simultaneous composite and Y/C (S-Video) outputs, compatible with NTSC, NTSC-EIA, and all PAL television standards. Digital component video is accepted at the PD port in 8-bit parallel CCIR-601/656 format. It is demultiplexed into luminance and chrominance components. The chrominance components modulate a digitally synthesized subcarrier. The luminance and chrominance signals are then separately interpolated to twice the input pixel rate and converted to analog signals by 10-bit D/A converters. They are also digitally combined and the resulting composite signal is output by a third 10-bit D/A converter. The TMC2490A operates from a single clock at 27 MHz, twice the system pixel rate. Programmable control registers allow software control of subcarrier frequency and phase parameters. Incoming YCBCR422 digital video is interpolated to YCBCR444 format for encoding. Internal control registers can be accessed over a standard 8-bit parallel microprocessor port or a 2-pin (clock and data) serial port. Chroma Modulator A digital subcarrier synthesizer generates the reference for a quadrature modulator, producing a digital chrominance signal. The chroma bandwidth may be programmed to 650 kHz or 1.3 MHz. Interpolation Filters Interpolation filters on the luminance and chrominance signals double the pixel rate to 27Mpps before D/A conversion. This low-pass filtering and oversampling process reduces sin(x)/x roll-off, and greatly simplifies the analog reconstruction filter required after the D/A converters. D/A Converters Analog outputs of the TMC2490A are driven by three 10-bit D/A converters, The outputs drive standard video levels into 37.5 or 75 Ohm loads. An internal voltage reference is used to provide reference current for the D/A converters. An external fixed or variable voltage reference source can also be used. The video signal levels from the TMC2490A may be adjusted to overcome the insertion loss of analog low-pass output filters by varying RREF or VREF. Parallel and Serial Microprocessor Interfaces The parallel microprocessor interface employs 11 pins. These are shared with the serial interface. A single pin, SER, selects between the two interface modes. In parallel interface mode, one address pin is decoded to enable access to the internal control register and its pointer. Controls are reached by loading a desired address through the 8-bit D7-0 port, followed by the desired data (read or write) for that address. The control register address pointer auto-increments to address 22h and then remains there. A 2-line serial interface is also provided on the TMC2490A for initialization and control. The same set of registers accessed by the parallel port is available to the serial port. The RESET pin sets all internal state machines and control registers to their initialized conditions, disables the analog outputs, and places the encoder in a reset mode. At the rising edge of RESET, the encoder is automatically initialized in NTSC-M format. Sync Generator The TMC2490A operates in master or slave mode. In slave mode, it extracts its horizontal and vertical sync timing and field information from the CCIR-656 SAV (Start of Active Video) and EAV (End of Active Video) signal in the incoming data stream. In master mode, it generates a 13.5 MHz timebase and sends line and field synchronizing signals to the host system. Horizontal and vertical synchronization pulses in the analog output are digitally generated by the TMC2490A with controlled rise and fall times on all sync edges, the beginning and end of active video, and the burst envelope. MSB PD7 PD7 PD7 PD7 CB (n) Y (n) CR (n) Y (n+1) Figure 1. Pixel Data Format LSB PD0 PD0 PD0 PD0 2 REV. 1.0.2 2/27/02 PRODUCT SPECIFICATION TMC2490A Pin Assignments SDA/R/W SA0/ADR SA1 PD0 GND VDD PD1 PD2 PD3 PD4 PD5 6 5 4 3 2 1 44 43 42 41 18 19 20 21 22 23 24 25 26 27 HSYNC VSYNC,T/B CBSEL,PDC SELC RESET VDD GND PXCK VDD VREF RREF 28 SCL/CS SER D7 D6 D5 D4 GND D3 D2 D1 D0 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 TMC2490A PD6 PD7 VDD GND CHROMA VDDA CBYP LUMA GND COMPOSITE GND 65-2490(1)A-02 Pin Descriptions Pin Name Clock PXCK 25 TTL Pixel Clock Input. This 27.0 MHz clock is internally divided by 2 to generate the internal pixel clock. PXCK drives the entire TMC2490A, except the asynchronous microprocessor interface. All internal registers are strobed on the rising edge of PXCK. Pixel Data Inputs. Video data enters the TMC2490A on PD7-0 (Figure 1). Data I/O, General Purpose I/O, Chroma Input Port. When SER is HIGH, all control parameters are loaded into and read back over this 8-bit port. When SER = LOW, D0 can serve as a composite sync output, D1 outputs a burst flag during the back porch, D2-5 are General Purpose Outputs, and D6-7 are General Purpose Inputs. Master Reset Input. Bringing RESET LOW forces the internal state machines to their starting states and disables all outputs. Serial/Parallel Port Select. When SER is LOW, SA1 in conjunction with SA0 selects one of four addresses for the TMC2490A. Serial/Parallel Port Select. When SER is LOW, SA0 in conjunction with SA1 selects one-of-four addresses for the TMC2490A. When SER is HIGH, this control governs whether the parallel microprocessor interface selects a table address or reads/writes table contents. Pin Number Value Pin Function Description Data Input Port PD7-0 38–44, 3 TTL Microprocessor Interface D7-0 9–12, 14–17 TTL RESET SA1 22 4 TTL TTL SA0, ADR 5 TTL 3 TMC2490A PRODUCT SPECIFICATION Pin Descriptions (continued) Pin Name SDA, R/W Pin Number 6 Value R-Bus/TTL Pin Function Description Serial Data/Read/Write Control. When SER is LOW, SDA is the data line of the serial interface. When SER is HIGH, the pin is the read/write control for the parallel interface. When R/W and CS are LOW, the microprocessor can write to the control registers over D7-0. When R/W is HIGH and CS is LOW, it can read the contents of any selected control register over D7-0. Serial Clock/Chip Select. When SER is LOW, SCL is the clock line of the serial interface. When SER is HIGH, the pin is the chip select control for the parallel interface. When CS is HIGH, the microprocessor interface port, D7-0, is set to HIGH impedance and ignored. When CS is LOW, the microprocessor can read or write parameters over D7-0. Serial/Parallel Port Select. When LOW, the 2-line serial interface is activated. Pins 5, 6, and 7 function as SA0, SDA, and SCL respectively. When HIGH, the parallel interface port is active and pins 5, 6, and 7 function as ADR, R/W, and CS respectively. Chrominance-only Video. Analog output of chrominance D/A converter. Maximum output is 1.35 volts peak-to-peak into a doubly terminated 75 Ohm load. Composite NTSC/PAL Video. Analog output of composite D/A converter. Maximum output is 1.35 volts peak-to-peak into a doubly terminated 75 Ohm load. Luminance-only Video. Analog output of luminance D/A converter. Maximum output is 1.35 volts peak-to-peak into a doubly terminated 75 Ohm load. Reference Bypass Capacitor. Connection point for 0.1 µF decoupling capacitor to VDD at pin 34. Current-setting Resistor. Connection point for external currentsetting resistor for D/A converters. The resistor is connected between RREF and GND. Output video levels are inversely proportional to the value of RREF. Voltage Reference Input. External voltage reference input, internal voltage reference output, nominally 1.235 V. Horizontal Sync Output. Vertical Sync Output or Odd/Even Field ID Output. Pixel Data Phase Output or Video Blanking Output. Luma/Chroma MUX Control. Power Supply. Positive power supply. Ground. Analog Power Supply. Positive power supply. SCL, CS 7 R-Bus/TTL SER 8 TTL Outputs CHROMA 35 1.35V p-p COMPOSITE 30 1.35V p-p LUMA 32 1.35V p-p Analog Interface CBYP RREF 33 28 0.1µF 787Ω VREF SYNC Out HSYNC VSYNC, T/B CBSEL, PDC SELC Power Supply VDD GND VDDA 27 +1.235V 18 19 20 21 1, 23, 26, 37 2, 13, 24, 29, 31, 36 34 TTL TTL TTL TTL +5V 0.0V +5V REV. 1.0.2 2/27/02 4 PRODUCT SPECIFICATION TMC2490A Control Registers The TMC2490A is initialized and controlled by a set of registers which determine the operating modes. An external controller is employed to write and read the Control Registers through either the 8-bit parallel or 2-line serial interface port. The parallel port, D7-0, is governed by pins CS, R/W, and ADR. The serial port is controlled by SDA and SCL. Table 1. Control Register Map Reg 00 01 02 03 04 04 04 04 04 04 04 05 05 05 05 05 05 05 05 06 06 06 070D Bit 7-0 7-0 7-0 7-0 7 6 5 4 3 2 1-0 7 6 5 4 3 2 1 0 7-6 5-3 2-0 7-0 Mnemonic PARTID2 PARTID1 PARTID0 REVID MASTER NGSEL YCDELAY RAMPEN YCDIS COMPDIS FORMAT PALN BURSTF CHRBW SYNCDIS BURDIS LUMDIS CHRDIS PEDEN Reserved FIELD Reserved Reserved Function Reads back 97h Reads back 24h Reads back 90h (91h) Silicon revision # Master Mode NTSC Gain Select Luma to chroma delay Modulated ramp enable LUMA, CHROMA disable COMPOSITE disable Television standard select Select PAL-N Subcarrier Burst flag disable Chroma bandwidth select Sync pulse disable Color burst disable Luminance disable Chrominance disable Pedestal enable Program LOW Field ID (Read only) Program LOW Program LOW 20 21 22 22 22 22 22 101F 7-0 Reg 0E 0E 0E 0E 0F 0F 0F 0F 0F Bit 7 6 1 0 7 5 4 3 1-0 Mnemonic PORT7-6 PORT5-2 BURSTF CSYNC PED21 VSEL CBSEL VBIEN HDSEL Reserved Function General purpose Inputs General purpose Outputs Burst Flag Output Composite Sync Output VBI Pedestal Enable Vertical Sync Select CBSEL/PDC Pin Function VBI Pixel Data Enable HSYNC Delay May be left unprogrammed TMC2490A Identification Registers (Read only) General Purpose Port Register Global Control Register General Control Register Reserved Registers Video Output Control Register Closed-Caption Insertion Registers 7-0 7-0 7 6 5 4 3-0 CCD1 CCD2 CCON CCRTS CCPAR CCFLD CCLINE First Byte of CC Data Second Byte of CC Data Enable CC Data Packet Request To Send Data Auto Parity Generation CC Field Select CC Line Select Field ID Register Notes: 1. For each register listed above, all bits not specified are reserved and should be set to logic LOW to ensure proper operation. Reserved Registers REV. 1.0.2 2/27/02 5 TMC2490A PRODUCT SPECIFICATION Table 2. Default Register Values on Reset Reg 00 01 02 03 Dflt 97 24 90(91) xx Reg 04 05 06 07 Dflt 00 01 00 00 Reg 08 09 0A 0B Dflt 00 00 00 00 Reg 0C 0D 0E 0F Dflt 00 00 00 F2 Reg 20 21 22 Dflt 80 80 00 Control Register Definitions Reg 00 01 02 03 Bit 7–0 7–0 7–0 7–0 Name PARTID2 PARTID1 PARTID0 REVID Description Reads back 97h Reads back 24h Reads back 90h (91h) Reads back a value corresponding to the revision letter of the silicon. Global Control Register (04) 7 MASTER Reg 04 Bit 7 6 NGSEL Name MASTER 5 YCDELAY 4 RAMPEN 3 YCDIS 2 COMPDIS 1 FORMAT 0 Description Master Mode. When MASTER = 1, the encoder generates its own video timing and outputs signals VSYNC (or T/B), HSYNC, SELC, and PDC (or CBSEL). When MASTER = 0, the TMC2490A extracts timing from the embedded EAV codeword in the video datastream and optionally outputs signals VSYNC (or T/B), HSYNC, SELC, and PDC (or CBSEL). NTSC Gain Selection. Luma to chroma delay. When HIGH, the luminance path within the TMC2490A is delayed by one PXCK period. The delay applies to both COMPOSITE and LUMA outputs and may be used to compensate for group delay variation of external filters. When LOW, luminance and chrominance have the same latency. Modulated ramp enable. When HIGH, the TMC2490A outputs a modulated ramp test signal. When LOW, incoming digital video is encoded. LUMA, CHROMA disable. When HIGH, the LUMA and CHROMA outputs are disabled. Set LOW for normal enabled operation. COMPOSITE disable. When HIGH, the COMPOSITE output is disabled. Set LOW for normal enabled operation. Television standard select. Selects basic H&V timing parameters and subcarrier frequency. Pedestal level and chrominance bandwidth are independently programmed. 0 0 1 1 0 1 0 1 NTSC PAL-B,G,H,I,N PAL-M Reserved 04 04 6 5 NGSEL YCDELAY 04 04 04 04 4 3 2 1 –0 RAMPEN YCDIS COMPDIS FORMAT REV. 1.0.2 2/27/02 6 PRODUCT SPECIFICATION TMC2490A Control Register Definitions (continued) Video Output Control Register (05) 7 PALN Reg 05 Bit 7 6 BURSTF Name PALN 5 CHRBW 4 SYNCDIS 3 BURDIS 2 LUMDIS 1 CHRDIS 0 PEDEN Description Select PAL-N Subcarrier. When HIGH, selects PAL-N subcarrier frequency. When LOW, the encoder produces the PAL-B,G,H,I subcarrier. Program LOW for NTSC and PAL-M video. Burst flag disable. When BURSTF is LOW, a clamp gate signal is produced on the D1 output and register 0E bit 1. Chroma bandwidth select. When LOW, the chrominance bandwidth is ±650 kHz. When HIGH, the chrominance bandwidth is ±1.3 MHz. Sync pulse disable. When HIGH, horizontal and vertical sync pulses on the COMPOSITE video output are suppressed (to blanking level). Color burst, active video, and the CSYNC output remain active. Set LOW for normal composite video operation. Color burst disable. When HIGH, color burst is suppressed to the blanking level. Set LOW for normal operation. Luminance disable. When HIGH, incoming Y values are forced to black level. Color burst, CHROMA, and sync are not affected. Set LOW for normal operation. Chrominance disable. When HIGH, incoming color components CB and CR are suppressed, enabling monochrome operation. Output color burst is not affected. Set LOW for normal color operation. Pedestal enable. When LOW, black and blanking are the same level for ALL lines. When HIGH, a 7.5 IRE pedestal is inserted into the output video for NTSC and PAL-M lines 23-262 and 286-525 only. Chrominance and luminance gain factors are adjusted to keep video levels within range. PEDEN is valid for NTSC and PAL-M only and should be LOW for all other formats. 05 05 05 6 5 4 BURSTF CHRBW SYNCDIS 05 05 3 2 BURDIS LUMDIS 05 1 CHRDIS 05 0 PEDEN Field Data Register (06) 7 Reserved Reg 06 06 06 Bit 7–6 5–3 2–0 Name Reserved FIELD Reserved 6 5 4 FIELD Description Program LOW. Field ID (Read only). A value of 000 corresponds to field 1 and 111 corresponds to field 8. Program LOW. 3 2 1 Reserved 0 7 TMC2490A PRODUCT SPECIFICATION Control Register Definitions (continued) Reserved Registers (07–0D) 7 6 5 4 Reserved Reg 07– 0D Bit 7–0 Name Reserved Description Program LOW. 3 2 1 0 General Purpose Port Register (0E) 7 PORT7 Reg 0E 0E Bit 7 –6 5–2 6 PORT6 Name PORT7–6 PORT5–2 5 PORT5 4 PORT4 3 PORT3 2 PORT2 1 BURSTF 0 CSYNC Description General purpose Inputs. When in serial control mode, these register readonly bits indicate the state present on data port pins D7 and D6. General purpose Outputs. When in serial control mode or when reading register 0E in parallel control mode, these register read/write bits drive data pins D5–D2 to the state contained in the respective register bits. Burst Flag Output. Produces Burst Flag on data pin D1 when in serial control mode, or when reading register 0E. Composite Sync Output. Produces Composite Sync on data pin D0 when in serial control mode, or when reading register 0E. 0E 0E 1 0 BURSTF CSYNC REV. 1.0.2 2/27/02 8 PRODUCT SPECIFICATION TMC2490A Control Register Definitions (continued) General Control Register (0F) 7 PED21 Reg 0F Bit 7 6 Reserved Name PED21 5 VSEL 4 CBSEL 3 VBIEN 2 1 Reserved 0 Description VBI Pedestal Enable. When HIGH and FORMAT is 00 (NTSC) or 10 (PAL-M), pedestal is added to lines 21, 22, 283, 284, 285. When LOW, no pedestal is placed on these lines. PED21 is valid for NTSC and PAL-M only and should be LOW for all other formats. Program HIGH. Vertical Sync Select. When LOW, the TMC2490A outputs a traditional vertical sync on VSYNC. When HIGH, the chip outputs odd/even field identification on the VSYNC pin, with 0 denoting an odd field. CBSEL/PDC pin function. When CBSEL = 0, the PDC signal is produced on the CBSEL/PCD pin. When CBSEL = 1, the CBSEL signal is produced on the CBSEL/PDC pin. VBI Pixel Data Enable. When VBIEN = 0, the vertical interval lines are blanked. When VBIEN = 1, Pixel data is encoded into the VBI lines. Program LOW. Sync Delay. HDEL shifts the falling edge of the H and V syncs relative to the PD port. HDEL Result 00 H and V syncs are aligned with luminance pixel 735 (Y735) 01 H and V syncs are aligned with Blue color difference pixel 735 (Cb736) 10 H and V syncs are aligned with luminance pixel 736 (Y736) 11 H and V syncs are aligned with Red color difference pixel 735 (Cr736) Refer to Figure 2a, HDEL Timing 0F 0F 6 5 Reserved VSEL 0F 4 CBSEL 0F 0F 0F 3 2 1 –0 VBIEN Reserved HDEL Reserved Registers (10–1F) 7 6 5 4 Reserved Reg 10– 1F Bit 7–0 Name Reserved Description May be left unprogrammed 3 2 1 0 9 PRODUCT SPECIFICATION TMC2490A Control Register Definitions (continued) Closed-Caption Insertion (20) 7 6 5 4 CCD1 Reg 20 Bit 7–0 Name CCD1 Description First Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity bit if CCPAR is HIGH. 3 2 1 0 Closed-Caption Insertion (21) 7 6 5 4 CCD2 Reg 21 Bit 7–0 Name CCD2 Description Second Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity bit if CCPAR is HIGH. 3 2 1 0 Closed-Caption Insertion (22) 7 CCON Reg 22 22 Bit 7 6 6 CCRTS Name CCON CCRTS 5 CCPAR 4 CCFLD 3 2 CCLINE 1 0 Description Enable CC Data Packet. Command the CC data generator to send either CC data or a NULL byte whenever the specified line is transmitted. Request To Send Data. This bit is set HIGH by the user when bytes 20 and 21 have been loaded with the next two bytes to be sent. When the encoder reaches the falling edge of the HSYNC preceding the line specified in bits 4-0 of this register, data will be transferred from registers 20 and 21, and RTS will be reset LOW. A new pair of bytes may then be loaded into registers 20 and 21. If CCON = 1 and CCRTS = 0 when the CC line is to be sent, NULL bytes will be sent. Auto Parity Generation. When set HIGH, the encoder replaces the MSB of bytes 20 and 21 with a calculated ODD parity. When set LOW, the CC processor transmits the 16 bits exactly as loaded into registers 20 and 21. CC Field Select. When LOW, CC data is transmitted on the selected line of ODD fields. When HIGH, it is sent on EVEN fields. CC Line Select. Defines (with an offset) the line on which CC data is transmitted. 22 5 CCPAR 22 22 4 3 –0 CCFLD CCLINE 10 PRODUCT SPECIFICATION TMC2490A General Purpose Port The TMC2490A provides a general purpose I/O port for system utility functions. Input, output, and sync functions are implemented. Register 0E is the General Purpose Register. Full functionality is provided when the encoder is in Serial control mode (SER = LOW). Most of the functions are available in parallel interface mode (SER = HIGH). In serial control mode, these same data output pins (D1-0) always act as a burst flag and composite sync TTL outputs, the conditions of the serial control notwithstanding. The states of the flags may be read over the serial port, but due to the low frequency of the serial interface, it may be difficult to get meaningful information. Pixel Interface The TMC2490A interfaces with an 8-bit 13.5 Mpps (27 MHz) video datastream. It will automatically synchronize with embedded Timing Reference Signals, per CCIR-656. It also includes a master sync generator on-chip, which can produce timing reference outputs. General Purpose Input (serial mode only) Bits 7 and 6 of Register 0E are general purpose inputs. When the encoder is in serial control mode, data bits D7 and D6 are mirrored to these register locations. When Register 0E is read, the states of bits 7 and 6 reflect the TTL logic levels present on D7 and D6, respectively, at the time of read command execution. Writing to these bits has no effect. This function is not available when the encoder is in parallel control mode. CCIR-656 Mode When operating in CCIR-656 Mode (MASTER = 0), the TMC2490A identifies the SAV and EAV 4-byte codewords embedded in the video datastream to derive all timing. Both SAV and EAV are required. General Purpose Output Register 0E read/write bits 5-2 are connected to pins D5-2, respectively, when the encoder is in serial control mode. The output pins continually reflects the values most recently written into register 0E (1 = HIGH, 0 = LOW). Note that these pins are always driven outputs when the encoder is in serial control mode. When register 0E is read, these pins report the values previously stored in the corresponding register bits, i.e., it acts as a read/write register. When the encoder is in parallel control mode, this reading produces the output bit values on the corresponding data pins, just as in the serial control mode. However, the values are only present when reading register 0E. The controller can command a continuous read on this register to produce continuous outputs from these pins. MASTER Mode When in MASTER Mode (MASTER = 1), the Encoder produces its own timing, and provides HSYNC, VSYNC (or B/T), SELC, and PDC (or CBSEL) to the Pixel Data Source. SELC Output The SELC output toggles at 13.5 MHz (1/2 the pixel rate), providing a phase reference for the multiplexed luma/chroma CCIR-656 datastream. It is HIGH during the rising edge of the clock intended to load chroma data. This is useful when interfacing with a 16-bit data source, and can drive a Y/C multiplexer. CBSEL Output The CBSEL output identifies the CB element of the CB-YCR-Y CCIR-656 data sequence. It is HIGH during the rising edge of the clock to load CB data. This will prevent unintentionally swapping the CB and CR color components when operating in MASTER mode and reading data from a framestore. Burst Flag and Composite Sync (output/ read-only) Register 0E bit 1 is associated with the encoder burst flag. It is a 1 (HIGH) from just before the start of the color burst to just after the end of the burst. It is a 0 (LOW) at all other times. Register 0E bit 0 outputs the encoder composite sync status. It is a 0 (LOW) during horizontal and vertical sync tips. It is a 1 (HIGH) at all other times. These register bits may be read at any time over either the serial or parallel control port. Since they are dynamic, their states will change as appropriate during a parallel port read. In fact, if the parallel control port is commanded to read register 0E continually, the pins associated with these bits behave as burst flag and composite sync timing outputs. PDC Output The PDC output is a blanking signal, indicating when the encoder expected to receive pixel data. When PDC is HIGH, the incoming PD is encoded. REV. 1.0.2 2/27/02 11 TMC2490A PRODUCT SPECIFICATION 1464 1472 PXCK 1592 1600 1727 1715 0 0 625-line 525-line PD7-0 CB732 Y732 CR732 Y733 CB734 Y734 CR734 Y735 CB736 Y736 CR736 CB800 Y800 CR800 Y801 CB801 CR856 Y857 CB0 Y0 CR0 Y1 CB2 CBSEL HYSNC HDEL = 00 HDEL = 01 HDEL = 10 HDEL = 11 65-2490A-03 Figure 2a. HDEL TIming 1430 1435 PXCK 1440 1440 1464 1472 1724 1712 1727 1715 0 0 17 3 625-line 525-line tSP PD7-0 FF 00 EAV HSYNC (Output) HDEL = 2 tDO PDC 00 FV1 tDO tHS FF 00 00 FV0 CB0 tHP Y0 SAV tDO 65-2490A-04 Figure 2b. CCIR-656 Horizontal Interval Timing Detail 1430 1435 PXCK 1440 1440 1464 1472 1727 1715 0 0 17 3 625-line 525-line tS PD7-0 tDO HSYNC (Output) HDEL = 2 tDO PDC tHS CB0 tH Y0 tDO 65-2490A-05 Figure 3. Master Mode Horizontal Interval Timing Detail Horizontal and Vertical Timing Horizontal and vertical video timing in the TMC2490A is preprogrammed for line-locked systems with a 2x pixel clock of 27.0 MHz. Table 3 and Table 4 show timing parameters for NTSC and PAL standards and the resulting TMC2490A analog output timing. The user provides exactly 720 pixels of active video per line. In master mode, the TMC2490A precisely controls the duration and activity of every segment of the horizontal line and vertical field group. In external sync slave mode, it holds the end-of-line blank state (e.g. front porch for active video lines) until it receives the next horizontal sync signal. In CCIR-656 slave mode, it likewise holds each end-of-line blank state until it receives the next end of active video (EAV) signal embedded in the incoming data stream. The vertical field group comprises several different line types based upon the Horizontal line time. H = (2 x SL) + (2 x SH) [Vertical sync pulses] = (2 x EL) + (2 x EH) [Equalization pulses] SMPTE 170M NTSC and Report 624 PAL video standards call for specific rise and fall times on critical portions of the video waveform. The chip does this automatically, requiring no user intervention. The TMC2490A digitally defines 12 REV. 1.0.2 2/27/02 PRODUCT SPECIFICATION TMC2490A slopes compatible with SMPTE 170M NTSC or CCIR Report 624 PAL on all vital edges: 1. 2. Sync leading and trailing edges. Burst envelope. 3. 4. Active video leading and trailing edges. All vertical interval equalization pulse and sync edges. Table 3. Horizontal Timing Standards and Actual Values for 60 fps Video Standards ( µs) NTSC (SMPTE 170M) Parameter Front porch Horiz. Sync Breezeway Color Burst Color Back porch Blanking Active Video Line Time Equalization HIGH Equalization LOW Sync HIGH Sync LOW Sync rise and fall times FP SY BR BU CBP BL VA H EH EL SH SL 10.5 52.56 2.235 Min 1.4 4.6 Nom 1.5 4.7 0.608 2.514 1.378 10.7 52.86 63.556 29.5 2.3 4.7 27.1 140±20ns 11.0 53.06 2.794 Max 1.6 4.8 PAL-M (CCIR 624) Min 1.27 4.6 0.9 2.237 0.503 10.7 52.46 10.9 52.66 63.556 29.5 2.3 4.7 27.1