TMC3533R2C50

www.fairchildsemi.com TMC3533 Triple Video D/A Converter 8 bit, 80 Msps, 3.3V Features • • • • • • • 8-bit resolution 80, 50, and 30 megapixels per second ±0.5 LSB linearity error Sync, blank, and white controls Independent sync current output 1.0V p-p video into 37.5Ω or 75Ω load Enhancement of the ADV7120 – Internal bandgap voltage reference – Double-buffered data for low distortion – Power-down sleep mode Double-buffered data for low distortion TTL-compatible inputs Low glitch energy Single +3.3V±5% Volt power supply Description The TMC3533 is a high-speed triple 8-bit D/A converter especially suited for video and graphics applications. It offers 8-bit resolution, TTL-compatible inputs, low power consumption, a power-down sleep mode, and requires only a single +3.3V±5% Volt power supply. It has single-ended current outputs, SYNC and BLANK control inputs, and a separate current source for adding sync pulses to any D/A converter output. WHITE and SLEEP control inputs are available on PLCC parts. It is ideal for generating analog RGB from digital RGB and driving computer display and video monitors. Three speed grades are available: 30, 50, and 80 Msps. The TMC3533 triple D/A converter is available in a 44-lead plastic J-leaded PLCC. It is also available in a 48-lead plastic LQFP package. It is fabricated on a sub-micron CMOS process with performance guaranteed from 0°C to 70°C. • • • • Applications • • • • • Video and graphics displays Image processing systems Video signal conversion Broadcast television equipment Digital synthesis Block Diagram SYNC BLANK WHITE [PLCC only] 8 SYNC IOS [LQFP only] 8 bit D/A Converter IOG G7-0 B7-0 8 8 bit D/A Converter IOB R7-0 SLEEP [PLCC only] CLOCK 8 8 bit D/A Converter IOR COMP RREF VREF 65-3533-01 +1.235V Ref 1 REV. 0.9.1 11/24/99 TMC3533 PRODUCT SPECIFICATION Functional Description The TMC3533 is a low-cost triple 8-bit CMOS D/A converter designed to directly drive computer CRT displays at pixel rates up to 80 Msps. It comprises three identical 8-bit D/A converters with registered data inputs, common clock, and internal voltage reference. An independent current source allows sync to be added to any D/A converter output. SLEEP The SLEEP control, when HIGH, places the TMC3533 in a power-down state. This function operates asynchronously. D/A Outputs Each D/A output is a current source. To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. Normally, a source termination resistor of 75 Ohms is connected between the D/A current output pin and GND near the D/A converter. A 75 Ohm coaxial cable may then be connected with another 75 Ohm termination resistor at the far end of the cable. This "double termination" presents the D/A converter with a net resistive load of 37.5 Ohms. The TMC3533 may also be operated with a single 75 Ohm terminating resistor. To lower the output voltage swing to the desired range, the value of the resistor on RREF should be increased. Digital Inputs All digital inputs are TTL-compatible. Data are registered on the rising edge of the CLK signal. The analog output changes tDO after the rising edge of CLK. There is one stage of pipeline delay on the chip. The guaranteed clock rates of the TMC3533 are 80, 50, and 30 MHz. SYNC and BLANK SYNC and BLANK inputs control the output level (Figure 1 and Table 1) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC turns off a separate current source which is brought off the chip through the IOS pin. data: 660 mV max. Voltage Reference The TMC3533 has an internal bandgap voltage reference of +1.235 Volts. An external voltage reference may be connected to the VREF pin, overriding the internal voltage reference. All three D/A converters are driven from the same reference. A 0.1µF capacitor must be connected between the COMP pin and VDD to stabilize internal bias circuitry and ensure low-noise operation. pedestal: 54 mV sync: 286 mV 65-3503-02 Figure 1. Nominal Output Levels IOS may be connected to any one D/A output, or used independently. It is commonly tied to the green D/A converter for “Sync on Green” operation. This connection adds a 40 IRE sync pulse to the D/A output and brings that D/A output to 0.0 Volts during the sync tip. SYNC and BLANK are registered on the rising edge of CLK. BLANK gates the D/A inputs and sets the pedestal voltage. If BLANK = HIGH, the D/A inputs are added to a pedestal which offsets the current output. If BLANK = LOW, data inputs and the pedestal are disabled. Power and Ground The TMC3533 D/A converter requires a single +3.3 Volt power supply. The analog (VDD) power supply voltage should be decoupled to GND to reduce power supply induced noise. 0.1µF decoupling capacitors should be placed as close as possible to the power pins. The high slew-rate of digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance. WHITE The WHITE control drives all three D/As to full-scale, overriding the data inputs. It is overridden by the BLANK input, and is independent of SYNC. 2 REV. 0.9.1 11/24/99 PRODUCT SPECIFICATION TMC3533 Table 1. Output Voltage versus Input Code, SYNC, BLANK, and WHITE VREF = 1.235 V, RREF = 572 Ω, RL = 37.5 Ω RGB7-0 (MSB…LSB) XXXX XXXX 1111 1111 1111 1110 1111 1101 • • 0000 0000 1111 1111 • • 0000 0010 0000 0001 0000 0000 XXXX XXXX XXXX XXXX All D/As SYNC X X X X • • X X • • X X X X X BLANK 1 1 1 1 • • 1 1 • • 1 1 1 0 0 WHITE 1 0 0 0 • • 0 0 • • 0 0 0 X X VOUT 0.714 0.714 0.711 0.709 • • 0.385 0.383 • • 0.059 0.057 0.054 0.000 0.000 SYNC 1 1 1 1 • • 1 1 • • 1 1 1 1 0 D/A with IOS Connected BLANK 1 1 1 1 • • 1 1 • • 1 1 1 0 0 WHITE 1 0 0 0 • • 0 0 • • 0 0 0 X X VOUT 1.000 1.000 0.997 0.995 • • 0.671 0.669 • • 0.345 0.343 0.340 0.286 0.000 Pin Assignments PLCC Package R7 R6 R5 R4 R3 R2 R1 R0 RREF VREF COMP LQFP Package GND R7 R6 R5 R4 R3 R2 R1 R0 GND GND NC 39 38 37 36 35 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 G0 G1 G2 G3 G4 G5 G6 G7 BLANK SYNC VDD 7 8 9 10 11 12 13 14 15 16 17 TMC3533 34 33 32 31 30 29 IOR IOG IOS VDD VDD VDD IOB GND GND GND GND 48 47 46 45 44 43 42 41 40 39 38 37 GND G0 G1 G2 G3 G4 G5 G6 G7 BLANK SYNC VDD 1 2 3 4 5 6 7 8 9 10 11 12 TMC3533 36 35 34 33 32 31 30 29 28 27 26 25 RREF VREF COMP IOR IOG OVDD VDD IOB GND GND CLOCK NC 13 14 15 16 17 18 19 20 21 22 23 24 B0 B1 B2 B3 B4 B5 B6 B7 WHITE CLK SLEEP 65-3533-03 65-3533-06 Notes (LQFP Package Only): 1. Pin functions White and Sleep are not available. 2. IOS function is internally tied to IOG pin. NC GND GND B0 B1 B2 B3 B4 B5 B6 B7 NC REV. 0.9.1 11/24/99 3 TMC3533 PRODUCT SPECIFICATION Pin Descriptions Pin Name CLK Pin Number LQFP 26 PLCC 27 Value TTL Pin Function Description Clock Input. The clock input is TTL-compatible and all pixel data is registered on the rising edge of CLK. It is recommended that CLK be driven by a dedicated TTL buffer to avoid reflection induced jitter, overshoot, and undershoot. Red, Green, and Blue Pixel Inputs. The R, G, and B digital inputs are TTL-compatible and registered on the rising edge of CLK. Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA) current source which forms a sync pulse on any D/A converter output connected to IOS. SYNC is registered on the rising edge of CLK along with pixel data and has the same pipeline latency as BLANK and pixel data. SYNC does not override any other data and should be used only during the blanking interval. If the system does not require sync pulses, SYNC and IOS should be connected to GND. Blanking Input. When BLANK is LOW, pixel inputs are ignored and the D/A converter outputs are driven to the blanking level. BLANK is registered on the rising edge of CLK and has the same two-pipe latency as SYNC and Data. Force Full Scale Input. When WHITE is HIGH, pixel inputs are ignored and the D/A converter outputs are driven to their fullscale output level. A BLANK input overwrites a WHITE input. WHITE is register on the rising edge of CLK and has the same two-pipe latency as SYNC and Data. Power-down Control Input. When HIGH, SLEEP places the D/ A converter in a low-power-dissipation mode. The D/A current sources and the digital processing are disabled. The last data loaded into the input and D/A registers is retained. This control is asynchronous. Red, Green, and Blue Data Outputs. The current source outputs of the D/A converters are capable of driving RS-343A/ SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Sync pulses may be added to any D/A output. SYNC Current Output. When this pin is connected to any of the D/A converter outputs, a 40 IRE offset can be added to the video level. When the SYNC input is LOW, the current is turned off, bring the sync tip voltage to 0.0V. If no sync pulse is required, IOS should be grounded. When SYNC is HIGH, the current flowing out of IOS is: IOS = 3.64 (VREF / RREF) Voltage Reference VREF 35 41 +1.235 V Voltage Reference Input/Output. An internal voltage source of +1.235 Volts is output on this pin. An external +1.235 Volt reference may be applied here which overrides the internal reference. Decoupling VREF to GND with a 0.1µF ceramic capacitor is required. Clock and Pixel I/O R7-0 G7-0 B7-0 Controls SYNC 47-40 9-2 23-16 11 6-1, 44-43 14-7 25-18 16 TTL TTL BLANK 10 15 TTL WHITE — 26 TTL SLEEP — 28 TTL Video Outputs IOR IOG IOB IOS 33 32 29 32 (connected to IOG) 39 38 33 37 0.714 Vp-p 0.714 Vp-p 4 REV. 0.9.1 11/24/99 PRODUCT SPECIFICATION TMC3533 Pin Descriptions (continued) Pin Name RREF Pin Number LQFP 36 PLCC 42 Value 572 Ω Pin Function Description Current-setting Resistor. The full-scale output current of each D/A converter is determined by the value of the resistor connected between RREF and GND. The nominal value for RREF is found from: RREF = 9.1 (VREF/IFS), but is optimized to be 572 Ω. IFS is the full-scale (white) output current (amps) from an output without sync. Sync current is 0.4 IFS. D/A full-scale (white) current may also be calculated from: IFS = VFS/RL Where VFS is the white voltage level and RL is the total resistive load (ohms) on each D/A converter. VFS is the blank to full-scale voltage. COMP 34 40 0.1 µF Compensation Capacitor. A 0.1 µF ceramic capacitor must be connected between COMP and VDD to stabilize internal bias circuitry. Power Supply. Ground. Power, Ground VDD GND 12, 30, 31 17, 34–36 1, 14, 15, 27, 28, 38, 39, 48 13, 24, 25, 37 29–32 +3.3 V 0.0V NC — — No Connect Equivalent Circuits VDD VDD p Digital Input n OUT GND GND 27014D 27013B n VDD p Figure 2. Equivalent Digital Input Circuit Figure 3. Equivalent Analog Output Circuit REV. 0.9.1 11/24/99 5 TMC3533 PRODUCT SPECIFICATION Equivalent Circuits (continued) VDD p RREF VREF p GND 27012B Figure 4. Equivalent Analog Input Circuit Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Power Supply Voltage VDD (Measured to GND) Inputs Applied Voltage (measured to GND)2 Forced Current3,4 Outputs Applied Voltage (measured to GND)2 Forced Current3,4 Short Circuit Duration (single output in HIGH state to ground) Temperature Operating, Ambient Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage -65 -20 110 150 300 220 150 °C °C °C °C °C -0.5 -60.0 VDD + 0.5 60.0 infinite V mA second -0.5 -10.0 VDD + 0.5 10.0 V mA -0.5 7.0 V Min Typ Max Unit Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 6 REV. 0.9.1 11/24/99 PRODUCT SPECIFICATION TMC3533 Operating Conditions Parameter VDD fS Power Supply Voltage Conversion Rate TMC3533-30 TMC3533-50 TMC3533-80 tPWH tPWL ts th VREF CC RL VIH VIL TA CLK Pulsewidth, HIGH CLK Pulsewidth, LOW Input Data Setup Time Input Date Hold Time Reference Voltage, External Compensation Capacitor Output Load Input Voltage, Logic HIGH Input Voltage, Logic LOW Ambient Temperature, Still Air 2.0 GND 0 4 4 3 2 1.0 1.235 0.1 37.5 VDD 0.8 70 1.5 Min 3.135 Nom 3.3 Max 3.465 30 50 80 Units V Msps Msps Msps ns ns ns ns V µF Ω V V °C Electrical Characteristics Parameter IDD Power Supply Current2 Conditions3 VDD = Max TMC3533-30 TMC3533-50 TMC3533-80 VDD = Max VDD = Max TMC3533-30 TMC3533-50 TMC3533-80 100 IOUT = 0mA VDD = Max, VIN = 3.0V VDD = Max, VIN = 0.4V 0 1.235 Referred to VDD -0.4 0 4 +1.5 10 30 -1 1 ±100 Min Typ1 Max 95 95 105 3 Units mA mA mA mA IDDS PD Power Supply Current, Sleep Mode Total Power Dissipation2 330 330 346 mW mW mW kΩ pF µA µA µA V V pF RO CO IIH IIL IREF VREF VOC CDI Output Resistance Output Capacitance Input Current, HIGH Input Current, LOW VREF Input Bias Current Reference Voltage Output Output Compliance Digital Input Capacitance Notes: 1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C 2. Minimum/Maximum values with VDD = Max and TA = Min 3. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 572Ω REV. 0.9.1 11/24/99 7 TMC3533 PRODUCT SPECIFICATION Switching Characteristics Parameter tD tSKEW tR tF tSET Clock to Output Delay Output Skew Output Risetime Output Falltime Output Settling Time 10% to 90% of Full Scale 90% to 10% of Full Scale to 3%/FS Conditions2 VDD = Min Min Typ1 10 1 3 3 15 Max 15 2 4 4 Units ns ns ns ns ns Notes: 1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C. 2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 572Ω. System Performance Characteristics Parameter ELI ELD EDM IOFF PSRR Integral Linearity Error Differential Linearity Error DAC to DAC Matching Output Off Current Power Supply Rejection Ratio Conditions2 VDD, VREF = Nom VDD, VREF = Nom VDD, VREF = Nom VDD = Max, R, G, B = 000h SYNC = BLANK = 0 Min Typ1 ±0.1 ±0.1 7 Max ±0.25 ±0.25 10 20 0.05 Units %/FS %/FS % nA %/% Notes: 1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C. 2. VREF = 1.235V, RLOAD = 37.5Ω, RREF = 572Ω. Timing Diagram t PWL CLK t PWH 1/f S tS PIXEL DATA & CONTROLS DataN tH DataN+1 DataN+2 3%/FS 90% tD OUTPUT 50% t SET tF 10% tR 65-3503-04 8 REV. 0.9.1 11/24/99 PRODUCT SPECIFICATION TMC3533 Application Notes Figure 4 illustrates a typical TMC3533 interface circuit. In this example, an optional 1.2 Volt bandgap reference is connected to the VREF output, overriding the internal voltage reference source. 2. The power plane for the TMC3533 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the TMC3533 is the same as that of the system's digital circuitry, power to the TMC3533 should be decoupled with 0.1µF and 0.01µF capacitors and isolated with a ferrite bead. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC3533, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the TMC3533 and its related analog circuitry can have an adverse effect on performance. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. Grounding It is important that the TMC3533 power supply is well-regulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The TMC3533 has separate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages (VDD) come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. 3. 4. Printed Circuit Board Layout Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG, IOB) as short as possible and as far as possible from all digital signals. The TMC3533 should be located near the board edge, close to the analog output connectors. 5. Related Products • • • • • TMC3003 Triple 10-bit 80 Msps D/A Converter TMC2242C/TMC2243/TMC2246A Video Filters TMC2081 Digital Video Mixer TMC3503 Triple Video D/A Converter, 5V TMC22x5y Video Decoder +3.3V 10µF 0.1µF VDD RED PIXEL INPUT GREEN PIXEL INPUT BLUE PIXEL INPUT CLOCK SYNC BLANK WHITE SLEEP R7-0 G7-0 B7-0 CLK SYNC BLANK WHITE SLEEP GND Red IO R IO S IO G IO B ZO=75Ω 75Ω 75Ω 75Ω 75Ω 75Ω 75Ω Green w/Sync ZO=75Ω Blue ZO=75Ω TMC3533 Triple 8-bit D/A Converter COMP 0.1µF VREF RREF +3.3V 3.3kΩ 572Ω LM185-1.2 (Optional) 0.1µF 65-3533-05 Figure 4. Typical Interface Circuit REV. 0.9.1 11/24/99 9 TMC3533 PRODUCT SPECIFICATION Mechanical Dimensions – 44-pin PLCC Package Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45° 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm) .165 .180 .090 .120 .020 — .013 .021 .026 .032 .685 .695 .650 .656 .500 BSC .050 BSC .042 .056 11 44 — .004 4.19 4.57 2.29 3.05 .51 — .33 .53 .66 .81 17.40 17.65 16.51 16.66 12.7 BSC 1.27 BSC 1.07 1.42 11 44 — 0.10 3 2 E E1 J D D1 D3/E3 B1 e J A A1 A2 B –C– LEAD COPLANARITY ccc C 10 REV. 0.9.1 11/24/99 PRODUCT SPECIFICATION TMC3533 Mechanical Dimensions – 48-pin LQFP Package Symbol A A1 A2 B D/E D1/E1 e L N ND α ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Pin 1 identifier is optional. 7 8 2 6 4 5 4. Dimension ND: Number of terminals. 5. Dimension ND: Number of terminals per package edge. 6. "L" is the length of terminal for soldering to a substrate. 7. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum B dimension by more than 0.08mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. 8. To be determined at seating place —C— .055 .063 .001 .005 .053 .057 .006 .010 .346 .362 .268 .284 .019 BSC .017 .029 48 12 0° 7° .004 1.40 1.60 .05 .15 1.35 1.45 .17 .27 8.8 9.2 6.8 7.2 .50 BSC .45 .75 48 12 0° 7° 0.08 D D1 e E E1 PIN 1 IDENTIFIER C α L 0.063" Ref (1.60mm) See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C REV. 0.9.1 11/24/99 11 TMC3533 PRODUCT SPECIFICATION Ordering Information Product Number TMC3533R2C30 TMC3533R2C50 TMC3533R2C80 TMC3533KRC30 TMC3533KRC50 TMC3533KRC80 Conversion Rate (Msps) 30 Msps 50 Msps 80 Msps 30 Msps 50 Msps 80 Msps Temperature Range TA = 0˚C to 70˚C TA = 0˚C to 70˚C TA = 0˚C to 70˚C TA = 0˚C to 70˚C TA = 0˚C to 70˚C TA = 0˚C to 70˚C Screening Commercial Commercial Commercial Commercial Commercial Commercial Package 44-Lead PLCC 44-Lead PLCC 44-Lead PLCC 48-Lead LQFP 48-Lead LQFP 48-Lead LQFP Package Marking 3533LR2C30 3533LR2C50 3533LR2C80 3533LKRC30 3533LKRC50 3533LKRC80 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 11/24/99 0.0m 002 Stock#DS30003533 © 1999 Fairchild Semiconductor Corporation