USB1T1103MHX

USBIT1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator July 2006 USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator Features ■ Complies with Universal Serial Bus Specification 2.0 ■ Integrated 5V to 3.3V voltage regulator for powering Description This chip provides a USB Transceiver functionality with a voltage regulator that is compliant to USB Specification Rev 2.0. this integrated 5V to 3.3V regulator allows interfacing of USB Application specific devices with supply voltages ranging from 1.65V to 3.6V with the physical layer of Universal Serial Bus. It is capable of operating at 12Mbits/s (full speed) data rates and hence is fully compliant to USB Specification Rev 2.0. The Vbusmon terminal allows for monitoring the Vbus line. The USB1T1103 also provides exceptional ESD protection with 15kV contact HBM on D+,D- terminals VBus ■ Utilizes digital inputs and outputs to transmit and receive USB cable data ■ Supports full speed (12Mbits/s) data rates ■ Ideal for portable electronic devices ■ MLP technology package (16 terminal) with HBCC footprint ■ 15kV contact HBM ESD protection on bus terminals ■ Supports disable mode and is functionally equivalent to Philips ISP1102 Applications ■ PDA ■ PC Peripherals ■ Cellular Phones ■ MP3 Players ■ Digital Still Camera ■ Information Appliance Ordering Information Part Number USB1T1103MPX Package Number MLP14D Product code Pb-Free Top Mark $Y&Z&2&T USB1103 $Y&Z&2&T USB1103 Yes Package Description 14-Terminal Molded Leadless Package (MLP), 2.5mm Square 16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217,3mm Square Packing Method 3K Units on Tape and Reel 3K Units on Tape and Reel USB1T1103MHX MLP16HB Yes Pb-Free package per JEDEC J-STD-020B. © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com USB1T1103 Rev. 1.0.2 USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator Typical Application Figure 1. Logic Diagram Connection Diagrams Figure 2. MLP16 GND Exposed Diepad (Bottom View) Figure 3. MLP14 GND Exposed Diepad (Bottom View) © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com USB1T1103 Rev. 1.0.2 2 USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator Terminal Descriptions Terminal Terminal Number Name MLP14 MLP16 1 1 OE I/O I Terminal Description Output Enable: Active LOW enables the transceiver to transmit data on the bus. When not active the transceiver is in the receive mode (CMOS level is relative to VCCIO) Receive Data Output: Non-inverted CMOS level output for USB differential Input (CMOS output level is relative to VCCIO). Driven LOW when SUSPN is HIGH; RCV output is stable and preserved during SE0 condition. Single-ended D+ receiver output VP (CMOS level relative to VCCIO): Used for external detection of SE0, error conditions, speed of connected device; Terminal also acts as drive data input Vpo (see Table 1 and Table 2). Output drive is 4 mA buffer. Single-ended D- receiver output Vm (CMOS level relative to VCCIO): Used for external detection of SE0, error conditions, speed of connected device; Terminal also acts as drive data input Vmo (see Table 1 and Table 2). Output drive is 4 mA buffer. Suspend: Enables a low power state (CMOS level is relative to VCCIO). While the SUSPND terminal is active (HIGH) it will drive the RCV terminal to logic “0” state. No Connect Supply Voltage for digital I/O terminals (1.65V to 3.6V): When not connected the D+ and D- terminals are in 3-STATE. This supply bus is totally independent of VCC (5V) and VREG (3.3V), and must never exceed the VREG (3.3) voltage. For VCCIO disconnected the O+/O- terminals are HIGH Impedance and the VPU (3.3V) is turned off. 2 2 RCV O 3 3 Vp/Vpo I/O 4 4 Vm/Vmo I/O 5 5 SUSPND I — 6 6 7 NC VCCIO 7 8 Vbusmon O Vbus monitor output (CMOS level relative to VCCIO): When Vbus > 4.1V then Vbusmon = HIGH and when Vbus < 3.6V then Vbusmon = LOW. If SUSPND = HIGH then Vbusmon is pulled HIGH. Data +, Data -: Differential data bus conforming to the USB standard. Terminals are HIGH Impedance for bus powered mode when Vbus < 3.6V. For ByPass Mode then HIGH Impedance when VREG/ Vbus < VREG minimum. No Connect No Connect Internal Regulator Option: Regulated supply output voltage (3.0V to 3.6V) during 5V operation; decoupling capacitor of at least 0.1 µF is required. Regulator ByPass Option: Used as supply voltage input for 3.3V operation. Internal Regulator Option: Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB line Vbus. Regulator ByPass Option: Connected to VREG (3.3V) Pull-up Supply Voltage (3.3V ± 10%): Connect an external 1.5kΩ resistor on D+ (FS data rate); Terminal function is controlled by Config input terminal: Config = LOW - VPU (3.3V) is floating (HIGH Impedance) for zero pull-up current. Config = HIGH - VPU (3.3V) = 3.3V; internally connected to VREG (3.3V). VPU is OFF in disable mode. 9, 8 10, 9 D+, D- AI/O 10 — 11 11 12 13 NC NC VREG (3.3V) 12 14 VCC (5.0V) 13 15 VPU (3.3V) 14 Exposed Diepad 16 Exposed Diepad Config GND I GND USB connect or disconnect software control input. Configures 3.3V to external 1.5kΩ resistor on D+ when HIGH. GND supply down bonded to exposed diepad to be connected to the PCB GND. © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com USB1T1103 Rev. 1.0.2 3 USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator Functional Description The USB1T1103 transceiver is designed to convert CMOS data into USB differential bus signal levels and to convert USB differential bus signal to CMOS data. To minimize EMI and noise the outputs are edge rate controlled with the rise and fall times controlled and defined for full speed data rates only (12Mbits/s). The rise, fall times are balanced between the differential terminals to minimize skew. The USB1T1103 differs from earlier USB Transceiver in that the Vp/Vm and Vpo/Vmo terminals are now I/O terminals rather than discrete input and output terminals. Table 1 describes the specific terminal functionality selection. Table 2 and Table 3 describe the specific Truth Tables for Driver and Receiver operating functions. The USB1T1103 also has the capability of various power supply configurations, including a disable mode for VCCIO disconnected, to support mixed voltage supply applications (see Table 4) and Section 2.1 for detailed descriptions. Functional Tables Table 1. Function Select SUSPND L L H H OE L H L H D+, DDriving & Receiving Receiving (1) Driving 3 STATE(1) RCV Active Active Inactive(2) Inactive(2) Vp/Vpo Vpo Input Vp Output Vpo Input Vp Output Vm/Vmo Vmo Input Vm Output Vmo Input Vm Output Function Normal Driving (Differential Receiver Active) Receiving Driving during Suspend (Differential Receiver Inactive) Low Power State Notes: 1. Signal levels is function of connection and/or pull-up/pull-down resistors. 2. For SUSPND = HIGH mode the differential receiver is inactive and the output RCV is forced LOW. The out-of-suspend signaling (K) is detected via the single-ended receivers of the Vp/Vpo and Vm/Vmo terminals. Table 2. Driver Function (OE = L) using Differential Input Interface Vm/Vmo L L H H Vp/Vpo L H L H Data (D+ / D-) SE0 (3) Differential Logic 1 Differential Logic 0 Illegal State Notes: 3. SE0 = Single Ended Zero Table 3. Receiver Function (OE = H) D+, DDifferential Logic 1 Differential Logic 0 SE0 RCV H L X Vp/Vpo H L L Vm/Vmo L H L Notes: 4. X = Don't Care 5. RCV(0) denotes the signal level on output RCV just prior to the SE0 or SE1 event. This level is stable during the SE0 or SE1 event period. © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com USB1T1103 Rev. 1.0.2 4 USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator Power Supply Configurations and Options The three modes of power supply operation are: Normal Mode: Regulated Output and Regulator Bypass 1. Regulated Output: VCCIO is connected and VCC(5.0) is connected to 5V (4.0V to 5.5V) and the internal voltage regulator then produces 3.3V for the USB connections. Internal Regulator Bypass Mode: VCCIO is connected and both VCC(5.0) and VREG(3.3) are connected to a 3.3V source (3.0V to 3.6V). external signals up to 3.6V to share the D+ and D- bus lines. Internally the circuitry limits leakage from D+ and D- terminals (maximum 10µA) and VCCIO such that device is in low power (suspended) state. Terminals Vbusmon and RCV are forced LOW as an indication of this mode with Vbusmon being ignored during this state. Disable Mode: VCCIO is not connected. VCC is connected, or VCC and VREG are connected. 0V to 3.3V in this mode D+ and D- are 3-STATE and VPU is HIGH Impedance (switch is turned off). The USB1T1103 allows external signals up to 3.6V to share the D+ and D- bus lines. Internally the circuitry limits leakage from D+ and D- pins (maximum 10µ A). A summary of the Supply Configurations is described in Table 4. 2. In both cases, for normal mode, the VCCIO is an independent voltage source (1.65V to 3.6V) that is a function of the external circuit configuration. Sharing Mode: VCCIO is only supply connected. VCC and VREG are not connected. In this mode, the D+ and D- terminals are 3-STATE and the USB1T1103 allows Table 4. Power Supply Configuration Options Terminals VCC (5V) Disable Connected to 5V source Sharing Not Connected or