LM339

LM339 Quad Voltage Comparator QUAD VOLTAGE COMPARATORS These comparators are designed for use in level detection, low–level sensing and memory applications in consumer automotive and industrial electronic applications. FEATURES l l l l l l l PIN ARRANGEMENT 14 DIP LM339CD Single or dual supplies Low Input Bias Current - 25nA(Typ) Low Input Offset Voltage - +1.0mV(Typ) Low Input Offset Current - +5.0nA(Typ) Input common-mode voltage range to GND Output Compatible with TTL, MOS, 14 SOP LM339CS and CMOS Low output saturation voltage - 130mV(Typ) @ 4.0mA ABSOLUTE MAXIMUM RATINGS Item Power Supply Voltage Input Differential Voltage Range Input Common Mode Voltage Range Output Short Circuit-to-Ground Power Dissipation @ 25oC Derate above 25oC Operating Ambient Temperature Range Storage Temperature Range Symbol VCC VIDR VICR ISC PD TA TS Rating +36 or +18 36 -0.3 to +36 Continuous 1.0 8.0 0 to 70 -65 to 150 Unit V V V mA W mW/oC o o C C Notes: 1. The max. output current may be as high as 20 mA, independent of the magnitude of VCC , output short circuits to VCC can cause excessive heating and eventual destruction. 2. This magnitude of input current will only occur if the leads are driven more negative than ground or the negative supply voltage. This is due to the input PNP collector base junction becooming forward biased, acting as an input clamp diode. There is also a lateral PNP parasitic transistor action which can cause the output voltage of the comparators to go to the VCC voltage level (or ground if overdrive is large) during the time that an input is driven negative. This will not destroy the device when limited to the max rating and normal output states will recover when inputs become > ground or negative supply. 3. At output switch point, V O = 1.4 Vdc, RS = 100 Ω with VCC from 5.0 Vdc to 30 Vdc, and over the full input common mode range (0V to VCC = –1.5V). 4. Due to the PNP transistor inputs, bias current will flow out of the inputs. This current is essentially constant, independent of the output state, therefore, no loading changes will exist on the input lines. 5. Response time is specified with a 100mV step and 5.0mV of overdrive. For larger signals, 300ns is typical. 6. Positive excursions of input voltage may exceed the power supply level. As long as one of the inputs remain within the common-mode range, the comparator will provide the proper output state. 5-3 LM339 Quad Voltage Comparator ELECTRICAL CHARACTERISTICS VCC = 5.0Vdc, 0oC < TA < 25oC (unless otherwise noted) Item Symbol Input Offset Voltage (3) VIO TA = 25oC TA = 0oC to 70oC Input Bias Current (3,4) IIB TA = 25oC TA = 0oC to 70oC Input Offset Current (3) IIO TA = 25oC TA = 0oC to 70oC Input Common Mode Voltage Range (6) VICR TA = 25oC TA = 0oC to 70oC Supply Current ICC RL = , TA = 25oC RL = , VCC = 30Vdc Voltage Gain AVOL RL > 15K, VCC = 15 Vdc Large Signal Response Time --V1 = TTL Logic Swing. Vref = 1.4 Vdc VRL = 5.0 Vdc, RL = 5.1K Response Time (6) tTLH VRL = 5.0 Vdc, RL = 5.1K Output Sink Current ISink V1(-) > 1.0 Vdc, V1(+) = 0 Vdc Vo < 1.5 Vdc Saturation Voltage VSAT V1(-) > 1.0 Vdc, V1(+) = 0 Vdc ISink < 4.0 mA, TA = 25oC 0oC < TA < 70oC Output Leakage Current IOL V1(-) = 0 Vdc, V1(+) > 1.0 Vdc Vo = 5.0 Vdc, TA = 25oC V1(-) = 0 Vdc, V1(+) > 1.0 Vdc Vo = 30 Vdc, 0oC < TA < 70oC Input Differential Voltage (6) VID All Vin > GND or V-Supply 0oC < TA < 70oC 8 8 Min ------------0 0 --------- Typ +2.0 --25 --+50 ------0.8 --200 300 Max +5.0 +9.0 Unit mV nA 250 400 nA +50 +150 V VCC-1.5 VCC-2.0 mA 2.0 ------- V/mV ns --6.0 13 16 ----- µs mA mV ----------130 --0.1 ----400 700 nA --1000 VCC V 5-4 LM339 Quad Voltage Comparator CIRCUIT SCHEMATIC (Diagram shown is for 1 comparator) NORMALIZED INPUT OFFSET VOLTAGE Input Bias Current (nA) Offset Voltage (Volts) INPUT BIAS CURRENT Ambient Temperature (oC) Supply Voltage (Vdc) Output Current (mA) Output Saturation Voltage (mV) 5-5 LM339 Quad Voltage Comparator APPLICATIONS INFORMATION These dual comparators feature high gain, wide bandwidth characteristics. This gives the device oscillation tendencies if the outputs are capacitively coupled to the inputs via stray capacitance. This oscillation manifests itself during output transitions (VOL to VOH ). To alleviate this situation, input resistors