LNK362-364

LNK362-364 LinkSwitch-XT Family ® Energy Efficient, Low Power Off-Line Switcher IC Product Highlights Optimized for Lowest System Cost • Proprietary IC trimming and transformer construction techniques enable Clampless™ designs with LNK362 for lower system cost, component count and higher efficiency • Fully integrated auto-restart for short circuit and open loop protection • Self-biased supply – saves transformer auxiliary winding and associated bias supply components • Frequency jittering greatly reduces EMI • Meets HV creepage requirements between DRAIN and all other pins both on the PCB and at the package • Lowest component count switcher solution Features Superior to Linear/RCC • Accurate hysteretic thermal shutdown protection – automatic recovery improves field reliability • Universal input range allows worldwide operation • Simple ON/OFF control, no loop compensation needed • Eliminates bias winding – simpler, lower cost transformer • Very low component count – higher reliability and single side printed circuit board • Auto-restart reduces delivered power by 95% during short circuit and open loop fault conditions • High bandwidth provides fast turn-on with no overshoot and excellent transient load response EcoSmart – Extremely Energy-Efficient • Easily meets all global energy efficiency regulations with no added components • No-load consumption 1). 6. A primary clamp (RCD or Zener) is used. 7. The part is board mounted with SOURCE pins soldered to a sufficient area of copper to keep the SOURCE pin temperature at or below 100 °C. 8. Ambient temperature of 50 °C for open frame designs and an internal enclosure temperature of 60 °C for adapter designs. Below a value of 1, KP is the ratio of ripple to peak primary current. Above a value of 1, KP is the ratio of primary MOSFET OFF time to the secondary diode conduction time. Due to the flux density requirements described below, typically a LinkSwitch-XT design will be discontinuous, which also has the benefits of allowing lower cost fast (instead of ultra-fast) output diodes and reducing EMI. Clampless Designs Clampless designs rely solely on the drain node capacitance to limit the leakage inductance induced peak drain-to-source voltage. Therefore, the maximum AC input line voltage, the value of VOR, the leakage inductance energy, a function of leakage inductance and peak primary current, and the primary winding capacitance determine the peak drain voltage. With no significant dissipative element present, as is the case with an external clamp, the longer duration of the leakage inductance ringing can increase EMI. The following requirements are recommended for a universal input or 230 VAC only Clampless design: 1. A Clampless design should only be used for PO ≤ 2.5 W, using the LNK362† and a VOR** ≤ 90 V. LNK362-364 Input Filter Capacitor Y1Capacitor TOP VIEW D T r a n s f o r m e r LinkSwitch-XT FB S BP S S S CBP - HV DC + INPUT S S Optocoupler + DC OUT Output Filter Capacitor Maximize hatched copper areas ( ) for optimum heatsinking PI-4155-102705 Figure 6. Recommended Printed Circuit Layout for LinkSwitch-XT using P Package in a Flyback Converter Configuration. Bypass Capacitor CBP The BYPASS pin capacitor should be located as near as possible to the BYPASS and SOURCE pins. Primary Loop Area The area of the primary loop that connects the input filter capacitor, transformer primary and LinkSwitch-XT together should be kept as small as possible. Primary Clamp Circuit A clamp is used to limit peak voltage on the DRAIN pin at turn-off. This can be achieved by using an RCD clamp or a Zener (~200 V) and diode clamp across the primary winding. In all cases, to minimize EMI, care should be taken to minimize the circuit path from the clamp components to the transformer and LinkSwitch-XT. Thermal Considerations The copper area underneath the LinkSwitch-XT acts not only as a single point ground, but also as a heatsink. As this area is connected to the quiet source node, it should be maximized for 2-6 6 6 Rev. D 02/07 good heat sinking of LinkSwitch-XT. The same applies to the cathode of the output diode. Y-Capacitor The placement of the Y-type cap should be directly from the primary input filter capacitor positive terminal to the common/ return terminal of the transformer secondary. Such a placement will route high magnitude common-mode surge currents away from the LinkSwitch-XT device. Note that if an input pi (C, L, C) EMI filter is used, then the inductor in the filter should be placed between the negative terminals of the input filter capacitors. Optocoupler Place the optocoupler physically close to the LinkSwitch-XT to minimize the primary-side trace lengths. Keep the high current, high-voltage drain and clamp traces away from the optocoupler to prevent noise pick up. Output Diode For best performance, the area of the loop connecting the secondary winding, the output diode and the output filter LNK362-364 TOP VIEW Y1Capacitor Input Filter Capacitor D LinkSwitch-XT T r a n s f o r m e r FB BP S S S S - + HV DC INPUT CBP Optocoupler Maximize hatched copper areas ( ) for optimum heatsinking Output Filter Capacitor + DC OUT PI-4585-021607 Figure 7. Recommended Printed Circuit Layout for LinkSwitch-XT using D Package in a Flyback Converter Configuration. capacitor should be minimized. In addition, sufficient copper area should be provided at the anode and cathode terminals of the diode for heat sinking. A larger area is preferred at the quiet cathode terminal. A large anode area can increase high frequency radiated EMI. Quick Design Checklist As with any power supply design, all LinkSwitch-XT designs should be verified on the bench to make sure that component specifications are not exceeded under worst-case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – Verify that VDS does not exceed 650 V at the highest input voltage and peak (overload) output power. The 50 V margin to the 700 V BVDSS specification gives margin for design variation, especially in Clampless designs. 2. Maximum drain current – At maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading-edge current spikes at startup. Repeat under steady state conditions and verify that the leadingedge current spike event is below ILIMIT(MIN) at the end of the tLEB(MIN). Under all conditions, the maximum drain current should be below the specified absolute maximum ratings. 3. Thermal Check – At specified maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifications are not exceeded for LinkSwitch-XT, transformer, output diode and output capacitors. Enough thermal margin should be allowed for part-to-part variation of the RDS(ON) of LinkSwitch-XT as specified in the data sheet. Under low line, maximum power, a maximum LinkSwitch-XT SOURCE pin temperature of 105 °C is recommended to allow for these variations. Design Tools Up-to-date information on design tools can be found at the Power Integrations web site: www.powerint.com. 2-7 7 Rev. D 02/07 LNK362-364 ABSOLUTE MAXIMUM RATINGS(1,5) DRAIN Voltage .................................. .............-0.3 V to 700 V Peak DRAIN Current: LNK362................200 mA (375 mA)(2) LNK363/364.........400 mA (750 mA)(2) FEEDBACK Voltage ...........................................-0.3 V to 9 V FEEDBACK Current ...................................................100 mA BYPASS Voltage.................................................. -0.3 V to 9 V Storage Temperature .....................................-65 °C to 150 °C Operating Junction Temperature(3) ................-40 °C to 150 °C Lead Temperature(4) ....................................................... 260 °C Notes: 1. All voltages referenced to SOURCE, TA = 25 °C. 2. The higher peak DRAIN current is allowed while the DRAIN voltage is simultaneously less than 400 V. 3. Normally limited by internal circuitry. 4. 1/16 in. from case for 5 seconds. 5. Maximum ratings specified may be applied, one at a time, without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. THERMAL IMPEDANCE Thermal Impedance: P or G Package: (θJA) ........................... 70 °C/W(3); 60 °C/W(4) (θJC)(1) ............................................... 11 °C/W D Package: (θJA) ..................... .... 100 °C/W(3); 80 °C/W(4) (θJC)(2) ............................................... 30 °C/W Notes: 1. Measured on pin 2 (SOURCE) close to plastic interface. 2. Measured on pin 8 (SOURCE) close to plastic interface. 3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad. 4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad. Conditions Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 8 (Unless Otherwise Specified) Average Peak-Peak Jitter S2 Open Min Typ Max Units CONTROL FUNCTIONS Output Frequency Maximum Duty Cycle FEEDBACK Pin Turnoff Threshold Current FEEDBACK Pin Voltage at Turnoff Threshold DRAIN Supply Current fOSC DCMAX IFB TJ = 25 °C 124 132 9 140 kHz % 60 TJ = 25 °C TJ = 0 °C to 125 °C LNK362 LNK363-364 30 1.55 1.53 49 1.65 1.63 200 68 1.75 μA VFB V 1.73 250 μA IS1 VFB ≥2 V (MOSFET Not Switching) See Note A FEEDBACK Open (MOSFET Switching) VBP = 0 V, TJ = 25 °C See Note C VBP = 4 V, TJ = 25 °C See Note C -5.5 -3.8 5.55 0.8 IS2 ICH1 ICH2 VBP VBPH 250 -3.5 -2.3 5.8 1.0 300 -1.8 μA BYPASS Pin Charge Current BYPASS Pin Voltage BYPASS Pin Voltage Hysteresis 2-8 8 8 Rev. D 02/07 mA -1.0 6.10 1.2 V V LNK362-364 Conditions Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 8 (Unless Otherwise Specified) Min Typ Max Units CONTROL FUNCTIONS (cont) BYPASS Pin Supply Current IBPSC See Note D 68 μA CIRCUIT PROTECTION di/dt = 30 mA/μs TJ = 25 °C LNK362 LNK363 LNK364 LNK362 LNK363 LNK364 LNK362 LNK363/364 130 195 233 2199 4948 7425 300 170 140 210 250 2587 5821 8250 375 250 125 ns A2Hz 150 225 268 mA Current Limit ILIMIT (See Note E) di/dt = 42 mA/μs TJ = 25 °C di/dt = 50 mA/μs TJ = 25 °C di/dt = 30 mA/μs TJ = 25 °C Power Coefficient I2f di/dt = 42 mA/μs TJ = 25 °C di/dt = 50 mA/μs TJ = 25 °C Leading Edge Blanking Time Current Limit Delay Thermal Shutdown Temperature Thermal Shutdown Hysteresis OUTPUT tLEB tILD TJ = 25 °C See Note F TJ = 25 °C See Note F ns TSD 135 142 150 °C TSHD See Note G 75 °C LNK362 ID = 14 mA TJ = 25 °C TJ = 100 °C TJ = 25 °C TJ = 100 °C TJ = 25 °C TJ = 100 °C 48 76 29 46 24 38 55 88 33 54 28 45 50 μA Ω ON-State Resistance RDS(ON) LNK363 ID = 21 mA LNK364 ID = 25 mA OFF-State Drain Leakage Current IDSS VBP = 6.2 V, VFB ≥2 V, VDS = 560 V, TJ = 125 °C 2-9 9 Rev. D 02/07 LNK362-364 Conditions Parameter OUTPUT (cont) Breakdown Voltage DRAIN Supply Voltage Output Enable Delay Output Disable Setup Time Auto-Restart ON-Time Auto-Restart Duty Cycle tEN tDST tAR DCAR TJ = 25 °C See Note I LNK362 LNK363-364 See Figure 10 BVDSS VBP = 6.2 V, VFB ≥ 2 V, See Note H, TJ = 25 °C 700 V Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 8 (Unless Otherwise Specified) Min Typ Max Units 50 V μs μs ms 10 0.5 40 45 5 % NOTES: A. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is ≥2 V (MOSFET not switching) and the sum of IS2 and IDSS when FEEDBACK pin is shorted to SOURCE (MOSFET switching). B Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BYPASS pin current at 6 V. C. See Typical Performance Characteristics section Figure 15 for BYPASS pin startup charging waveform. D. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK pins and not any other external circuitry. E. For current limit at other di/dt values, refer to Figure 14. F. This parameter is guaranteed by design. G. This parameter is derived from characterization. H. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not exceeding minimum BVDSS. I. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). 2-10 10 10 Rev. D 02/07 LNK362-364 470 Ω 5W D FB 470 kΩ S2 BP S S S S S1 50 V 0.1 μF 50 V PI-3490-060204 Figure 8. LinkSwitch-XT General Test Circuit. t2 t1 DCMAX (internal signal) tP HV 90% DRAIN VOLTAGE 10% t D= 1 t2 90% FB VDRAIN tP = PI-2048-033001 tEN 0V 1 fOSC PI-3707-112503 Figure 9. LinkSwitch-XT Duty Cycle Measurement. Figure 10. LinkSwitch-XT Output Enable Timing. 2-11 11 Rev. D 02/07 LNK362-364 Typical Performance Characteristics PI-2213-012301 PI-2680-012301 1.1 1.2 1.0 0.8 0.6 0.4 0.2 Breakdown Voltage (Normalized to 25 °C) 1.0 Output Frequency (Normalized to 25 °C) 0.9 -50 -25 0 25 50 75 100 125 150 0 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Figure 11. Breakdown vs. Temperature. 1.4 1.2 Junction Temperature (°C) Figure 12. Frequency vs. Temperature. PI-4091-081505 1.0 0.8 0.6 0.4 0.2 0 -50 Normalized Current Limit 1.2 1.0 0.8 0.6 0.4 0.2 0 Normalized Tdi/dt = 1 BD LNK362 30 mA/μs LNK363 42 mA/μs LNK364 50 mA/μs Normalized Current Limit = 1 140 mA 210 mA 250 mA Current Limit (Normalized to 25 °C) 0 50 100 150 1 2 3 4 5 Temperature (°C) Figure 13. Current Limit vs. Temperature. 7 6 Normalized di/dt Figure 14. Current Limit vs. di/dt. 400 350 PI-2240-012301 BYPASS Pin Voltage (V) DRAIN Current (mA) 5 4 3 2 1 0 300 250 200 150 100 50 0 25 °C 100 °C Scaling Factors: LNK362 0.5 LNK363 0.8 LNK364 1.0 0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10 12 14 16 18 20 Time (ms) Figure 15. BYPASS Pin Startup Waveform. DRAIN Voltage (V) Figure 16. Output Characteristics. 2-12 12 12 Rev. D 02/07 PI-4093-081605 PI-4092-081505 1.4 LNK362-364 Typical Performance Characteristics (cont.) PI-4094-081605 1000 Drain Capacitance (pF) 100 Scaling Factors: LNK362 0.5 LNK363 0.8 LNK364 1.0 10 1 0 100 200 300 400 500 600 Drain Voltage (V) Figure 17. COSS vs. Drain Voltage. PART ORDERING INFORMATION LinkSwitch Product Family XT Series Number Package Identifier G P D N Plastic Surface Mount DIP Plastic DIP Plastic SO-8 Pure Matte Tin (Pb-Free) Lead Finish Tape & Reel and Other Options Blank Standard Configurations LNK 364 G N - TL TL Tape & Reel, 1 k pcs minimum for G Package. 2.5 k pcs for D Package. Not available for P Package. 2-13 13 Rev. D 02/07 LNK362-364 DIP-8B ⊕ D S .004 (.10) -E.137 (3.48) MINIMUM .240 (6.10) .260 (6.60) Pin 1 -D.367 (9.32) .387 (9.83) .057 (1.45) .068 (1.73) (NOTE 6) .015 (.38) MINIMUM Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 4. Pin locations start with Pin 1, and continue counter-clockwise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 6 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T. .125 (3.18) .145 (3.68) -TSEATING PLANE .120 (3.05) .140 (3.56) .048 (1.22) .053 (1.35) .014 (.36) .022 (.56) ⊕ T E D S .010 (.25) M .008 (.20) .015 (.38) .300 (7.62) BSC (NOTE 7) .300 (7.62) .390 (9.91) .100 (2.54) BSC P08B PI-2551-121504 SMD-8B ⊕ D S .004 (.10) -E.137 (3.48) MINIMUM Notes: 1. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 2. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. .420 3. Pin locations start with Pin 1, and continue counter-clock.046 .060 .060 .046 wise to Pin 8 when viewed from the top. Pin 6 is omitted. 4. Minimum metal to metal .080 spacing at the package body Pin 1 for the omitted lead location is .137 inch (3.48 mm). .086 5. Lead width measured at .186 package body. .286 6. D and E are referenced Solder Pad Dimensions datums on the package body. .240 (6.10) .260 (6.60) .372 (9.45) .388 (9.86) ⊕ E S .010 (.25) Pin 1 .100 (2.54) (BSC) -D- .367 (9.32) .387 (9.83) .057 (1.45) .068 (1.73) (NOTE 5) .125 (3.18) .145 (3.68) .032 (.81) .037 (.94) .048 (1.22) .053 (1.35) .004 (.10) .009 (.23) .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) 0°- 8° G08B PI-2546-121504 2-14 14 14 Rev. D 02/07 LNK362-364 SO-8C 4 B 2 4.90 (0.193) BSC 0.10 (0.004) C A-B 2X DETAIL A A 8 4 5 D GAUGE PLANE 2 3.90 (0.154) BSC 6.00 (0.236) BSC SEATING PLANE C 1.04 (0.041) REF 0-8 o 0.25 (0.010) BSC 0.10 (0.004) C D 2X Pin 1 ID 1.27 (0.050) BSC 1 4 0.20 (0.008) C 2X 7X 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) M C A-B D 1.25 - 1.65 (0.049 - 0.065) 0.10 (0.004) C 7X SEATING PLANE C 0.40 (0.016) 1.27 (0.050) 1.35 (0.053) 1.75 (0.069) 0.10 (0.004) 0.25 (0.010) DETAIL A H 0.17 (0.007) 0.25 (0.010) Reference Solder Pad Dimensions + Notes: 1. JEDEC reference: MS-012. 2. Package outline exclusive of mold flash and metal burr. 3. Package outline inclusive of plating thickness. 4. Datums A and B to be determined at datum plane H. 5. Controlling dimensions are in millimeters. Inch dimensions are shown in parenthesis. Angles in degrees. PI-4526-040207 2.00 (0.079) 4.90 (0.193) + + + 0.60 (0.024) D07C 1.27 (0.050) 2-15 15 Rev. D 02/07 LNK362-364 Revision Notes B C D 1) Released Final Data Sheet. 1) Corrected Application Example section. 1) Added SO-8C package. Date 11/05 12/05 2/07 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. PATENT INFORMATION The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. LIFE SUPPORT POLICY POWER INTEGRATIONS’ PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, Clampless, EcoSmart, E-Shield, Filterfuse, StackFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©Copyright 2007, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations WORLD HEADQUARTERS 5245 Hellyer Avenue San Jose, CA 95138, USA. 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