CMP0417AA0-F70I

CMP0417AA0-I Document Title 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM CMOS LPRAM Revision History Revision No. 0.0 0.1 0.2 0.3 Initial Draft Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions Removed 60ns descriptions Added Power Up Sequence History Draft date May. 2nd, 2004 Oct. 26th, 2005 Aug. 22nd, 2006 Sep. 6th, 2006 Remark Final Final Final Final 1 Revision 0.3 Sep. 2006 CMP0417AA0-I FEATURES • Process Technology : Full CMOS • Organization : 256K x 16 • Power Supply Voltage : 2.7~3.3V • Three state output and TTL Compatible • Package Type : 48-FBGA-6.00x8.00 mm2 • Separated I/O power(VCCQ) & Core Power(VCC) • Easy memory expansion with /CS1, CS2, and /OE features • Automatic power-down when deselected CMOS LPRAM 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM PRODUCT FAMILY Operating Temperature Operating Voltage (V) Speed Min. Typ. Max. CMP0417AA0-F70I Industrial (-40~85’C) 2.7 3.0 3.3 70ns Typ. 1.5mA Power Dissipation ICC1 f = 1MHz Max. 3mA ICC2 f = fmax Typ. 12mA Max. 20mA ISB1 (CMOS Standby Current) Typ. 30uA Max. 70uA Product Family 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER PIN DESCRIPTION 1 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Precharge circuit. A B C D E F G H /LB I/O9 /OE /UB A0 A3 A1 A4 A2 /CS CS2 I/O1 Clk gen. VCC VSS Memory array I/O10 VSS I/O11 I/O12 A5 A17 A6 A7 A16 I/O2 I/O4 I/O5 I/O3 VCC VSS Row Addresses Row select VCCQ I/O15 I/O16 NC I/O13 I/O14 NC A8 DNU A14 A12 A9 A15 A13 A10 I/O6 I/O7 I/O8 I/O1~I/O8 Data cont I/O Circuit Column select /WE A11 NC I/O9~I/O16 Data cont 48-FBGA : Top View(Ball Down) Name CS2 /CS1 /OE /WE A0~A17 I/O1~I/O16 NC Function Chip Select Input Chip Select Input Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs No Connection Name VCC VCCQ VSS /UB /LB DNU Function Core Power I/O Power Ground Upper Byte(I/O9~16) Lower Byte(I/O 1~8) Do Not Use /CS1 CS2 /OE /WE /UB /LB Control Logic Data cont Column Addresses 2 Revision 0.3 Sep. 2006 CMP0417AA0-I PRODUCT LIST Industrial Temperature Products(-40~85’C) Part Name CMP0417AA0-F70I 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER CMOS LPRAM Function 48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) FUNCTIONAL DESCRIPTION /CS1 H X1) X1) L CS2 H L H H H /OE X1) X1) X1) H H /WE X1) X1) X1) H H /LB X1) X1) H L X1) L L L H X1) L H H L L H L 1. X means don’t care.(Must be low or high state) /UB X1) X1) H X1) L H L L H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT Vcc PD TSTG TA Ratings -0.2 to Vcc+0.3V -0.2 to 3.6 1.0 -65 to 150 -40 to 85 Unit V V W ’C ’C 1. Str es s e s g r e ate r tha n th o s e l i st e d u n d er “ A bsolute Maxim um Ratings” may cause permanent dam age to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for Industrial periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage I/O operating voltage (VCCQ ≤ VCC) Ground Input high voltage Input low voltage Symbol VCC VCCQ VSS VIH VIL CMP0417AA0 Min 2.7 2.7 0 0.8VCCQ -0.23) Max 3.3 3.3 0 VCC+0.22) 0.2VCCQ Min 2.7 2.25 0 0.8VCCQ -0.23) Max 3.3 2.75 0 VCC+0.22) 0.2VCCQ Min 2.7 1.65 0 0.8VCCQ -0.23) Max 3.3 1.95 0 VCC+0.22) 0.2VCCQ Unit V V V V V Note : 1.TA=-40 to 85’C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 3. Undershoot : -1.0V in case of pulse width≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. 3 Revision 0.3 Sep. 2006 CMP0417AA0-I CAPACITANCE1) (f=1MHz , TA=25’C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. CMOS LPRAM Symbol CIN CIO Test Condition VIN=0V VIO=0V Min Max 8 8 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 VIN=VSS to VCC /CS=VIH, CS2=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, CS2=VIH, VIN≤0.2V or VIN≥VCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, CS2=VIH, VIN=VIL or VIH IOL=0.5mA IOH=-0.5mA /CS=VIH, CS2=VIH, Other inputs=VIH or VIL /CS≥VCC-0.2V, CS2≤0.2V, Other inputs=0~VCC 0.8VCCQ 0.3 70 Test Conditions Min -1 -1 Typ 1.5 15 Max 1 1 3 25 0.2VCCQ Unit uA uA mA mA V V mA uA 4 Revision 0.3 Sep. 2006 CMP0417AA0-I AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level : 0.2 to VCC-0.2V Input rising and falling time : 5ns Input and output reference voltage : 0.5*VCCQ Output load(see right) : CL=30pF+1TTL 30pf CMOS LPRAM 1TTL AC CHARACTERISTICS(VCC=2.7V~3.3V, Industrial product : TA=-40 to 85’C) Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output /UB, /LB Access Time Read Chip Select to Low-Z Output /UB, /LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High- Z Output /UB, /LB Disable to High- Z Output Output Disable to High- Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write /UB, /LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z /CS High Pulse Width1) tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW tCP 70 10 10 5 0 0 0 5 70 60 0 60 60 50 0 0 20 0 5 10 70ns Max 70 70 25 70 5 5 5 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. 5 Revision 0.3 Sep. 2006 CMP0417AA0-I Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=VIH CMOS LPRAM Standby Mode State machines Power On /CS=VIH Wait min.200us Initial State /CS=VIL, /ZZ=VIH /UB or/and /LB=VIL Active Mode /CS=VIlL /ZZ=VIH /CS=VIH (or/and /UB=/LB=VIH) /ZZ=VIH Standby Mode Standby Mode Characteristics Mode Standby Memory Cell Data Valid Standby Current(uA) 70 (ISB1) Wait Time(us) 0 6 Revision 0.3 Sep. 2006 CMP0417AA0-I READ CYCLE (1) Address tOH tAA CMOS LPRAM tRC (Address controlled,/CS1=/OE=VIL, CS2=/WE=VIH, /UB or/and /LB=VIL) Data Out Previous Data Valid Data Valid READ CYCLE (2) Address (CS2=/WE=VIH) tRC tAA tCO tOH /CS1 CS2 tHZ /UB, /LB /OE tOLZ tBLZ tLZ tBA tBHZ tOE tOHZ Data Out High-Z Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 7 Revision 0.3 Sep. 2006 CMP0417AA0-I WRITE CYCLE (1) Address tCW(2) CMOS LPRAM tWC (/WE controlled) /CS1 CS2 /UB, /LB /WE tAS(3) tDW tAW tBW tWP(1) tWR(4) tDH High-Z tOW Data in Data Out High-Z tWHZ Data Valid Data Undefined WRITE CYCLE (2) Address (/CS1 controlled) tWC tAS(3) tCW(2) tWR(4) /CS1 CS2 tAW /UB, /LB /WE Data in Data Out High-Z tBW tWP(1) tDW tDH Data Valid High-Z WRITE CYCLE (3) Address (CS2 controlled) tWC tCW(2) tWR(4) /CS1 CS2 tAW /UB, /LB tAS(3) tBW tWP(1) /WE Data in Data Out tDW tDH Data Valid High-Z High-Z 8 Revision 0.3 Sep. 2006 CMP0417AA0-I WRITE CYCLE (4) Address tCW(2) tWR(4) CMOS LPRAM tWC (/UB, /LB controlled) /CS1 CS2 tAW /UB, /LB tAS(3) tBW tWP(1) /WE Data in Data Out tDW tDH Data Valid High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 9 Revision 0.3 Sep. 2006 CMP0417AA0-I PACKAGE DIMENSION 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View B B B1 CMOS LPRAM Unit : millimeters A1 INDEX MARK 0.05 0.05 6 A B 5 4 3 2 1 #A1 C D C1 E C1/2 F G H B/2 Detail A 0.25/Typ. A Y Max 6.10 8.10 0.40 0.30 0.08 NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) Side View E2 D E1 E 0.30 C C A B B1 C C1 D E E1 E2 Y Min 5.90 7.90 0.30 0.20 - Typ 0.75 6.00 3.75 8.00 5.25 0.35 1.00 0.75 0.25 - 0.85/Typ. 10 Revision 0.3 Sep. 2006 C