CMS4A16LAH

CMS4A16LAx–75xx 128M(8Mx16) Low Power SDRAM Revision 0.4 Nov. 2006 Rev. 0.4, Nov. ‘06 CMS4A16LAx–75xx Document Title 128M(8Mx16) Low Power SDRAM Revision History Revision No. 0.0 0.1 0.2 0.3 0.4 Initial Draft I/O voltage modified, minor changes Added H(Pb-Free & Halogen Free) descriptions Revised IDD6 400uA to 450uA Revised VDDQ 1.65V to 1.7V History Draft date Apr.25th, 2005 Sep.09th, 2005 Nov.1st , 2005 Jan.9th , 2006 Nov.12th , 2006 Remark Preliminary Rev. 0.4, Nov. ‘06 2 CMS4A16LAx–75xx 128M(8Mx16) Low Power SDRAM Features - Functionality - Standard SDRAM Functionality - Programmable burst lengths : 1, 2, 4, 8, or full page - JEDEC Compatibility - Low Power Features - Low voltage power supply : 2.5V - Auto TCSR(Temperature Compensated Self Refresh) - Partial Array Self Refresh power-saving mode - Deep Power Down Mode - Driver Strength Control - Operating Temperature Ranges: - Special (-10℃ to +60℃) - Commercial (0℃ to +70℃) - Extended (-25℃ to +85℃) - Industrial (-40℃ to +85℃) - LVCMOS Compatible IO Interface - 54ball FBGA with 0.8mm ball pitch - CMS4A16LAF : Normal - CMS4A16LAG : Pb-Free - CMS4A16LAH : Pb-Free & Halogen Free Functional Description The CMS4A16LAF Family is high-performance CMOS Dynamic RAMs (DRAM) organized as 8M x 16. These devices feature advanced circuit design to provide low active current and extremely low standby current. The device is compatible with the JEDEC standard LP-SDRAM specifications. Logic Block Diagram CKE CLK /CS /WE /CAS /RAS Control Logic Refresh Counter Row Address Mux Mode Register Extended Mode Register Bank 0 Bank 0 Row Row Address Addr Latch/ Latch/ Decoder Decoder Bank 3 Bank 2 Bank 1 Bank 0 Memory Array 8Kx4K Data Output Register LDQM UDQM Sense Amp Bank Control Logic A0-A11 BA0-BA1 Address Register Column Address Latch Column Column Decoder Column Decoder Column Decoder Decoder Write Drivers DQM Mask DQ0 DQ15 Data Input Register Selection Guide Voltage Device VDD CMS4A16LAx-75xx 2.3-3.3V VDDQ 133MHz 1.70-VDD 100MHz 7ns 20ns 20ns Frequency CL=2 CL=3 6ns 18ns 18ns Access Time(tAC) tRCD tRP Rev. 0.4, Nov. ‘06 3 CMS4A16LAx–75xx Pin Configuration 54 ball 0.8mm pitch FBGA (8mm x 8mm) Top View 1 2 3 4 5 6 7 8 9 A B C D E F G H J VSS DQ15 VSSQ VDDQ DQ0 VDD DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 DQ8 NC VSS VDD LDQM DQ7 UDQM CLK CKE /CAS /RAS /WE NC A11 A9 BA0 BA1 /CS A8 A7 A6 A0 A1 A10 VSS A5 A4 A3 A2 VDD Rev. 0.4, Nov. ‘06 4 CMS4A16LAx–75xx Pin Description Symbol CLK Type Input Description Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF Refresh operation(all banks idle), ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered. Input/Output Mask:L(U)DQM is sampled HIGH and is an input mask signal for write accesses and an output disable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM corresponds to DQ0 – DQ7, UDQM corresponds to DQ8–DQ15. Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. Address Inputs: A0–A11 are sampled during the ACTIVE command (row- address A0–A11) and READ/WRITE command (column-address A0–A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (A10 LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output : Data bus No Connect DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: Voltage dependant on option. Ground. CKE Input /CS Input /CAS, /RAS, /WE Input LDQM,UDQM Input BA0, BA1 Input A0-A11 Input DQ NC VDDQ VSSQ VDD VSS I/O Supply Supply Supply Supply Rev. 0.4, Nov. ‘06 5 CMS4A16LAx–75xx FUNCTIONAL DESCRIPTION The Fidelix 128Mb SDRAM is a quad-bank DRAM that operates at 1.8V or 2.5V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK ). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0- A11 select the row). The address bits (A0-A8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.The SDRAM must be initialized prior to normal operation. The following sections provide detailed information regarding device initialization, register definition, command descriptions and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable (meets the clock specifications in the AC characteristics), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. The COMMAND INHIBIT or NOP should be applied at least once during the 100µs delay. After the 100µs delay, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Refer Figure 1. Rev. 0.4, Nov. ‘06 6 CMS4A16LAx–75xx Figure 1. Initialize and Load Mode Register[1.2.3.] 0 CLK CKE /CS /RAS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 /CAS ADDR Key Key Key BA0 RAa BA1 RAa A10/AP DQ /WE DQM tRP High level is necessary tRC tRC HiZ HiZ Key Precharge (All Bank) Auto Refresh Auto Refresh Normal MRS Extended MRS Row Active a Bank Note : 1. The two AUTO REFRESH commands at T4 and T9 may be applied before either LOAD MODE REGISTER (LMR) command. 2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address 3. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order; However, all must occur prior to an Active command. Register Definition There are two mode registers which contain settings to achieve low power consumption. The two registers : Mode Register and Extended Mode Register are discussed below. burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the width burst mode, M10, M11, M12 and M13 should be set to zero. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Table 1. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode Register bits M0-M2 specify the burst length, M3 specifies the type of Rev. 0.4, Nov. ‘06 7 Burst Length Read and write accesses to the SDRAM are burst oriented. The burst length is programmable, as shown in Table 2. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1,2, 4, or 8 locations are available for both the CMS4A16LAx–75xx sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 when the burst length is set to two; by A2-A8 when the burst length is set to four; and by A3-A8 when the burst length is set to eight. The remaining(least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type The burst type can be set to either Sequential or Interleaved by using the M3 bit in the Mode register. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 2. [4.5.6.7.8.9.10.] Table 1. Mode Register Definition. M13BA1 M12BA0 M11A11 M10A10 M9-A9 WB M8-A8 M7-A7 M6-A6 M5-A5 M4-A4 M3-A3 BT M2-A2 M1-A1 Burst Length M0-A0 Reserved(Set to ‘0’) Op Mode Burst Length CAS Latency M2 M1 M0 M3=0 000 001 010 011 100 101 110 111 M6 M5 M4 000 001 010 011 100 101 110 111 1 2 4 8 Reserved Reserved Reserved Full Page CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved M3=1 1 2 4 8 Reserved Reserved Reserved Reserved M8 0 M7 0 - M3 0 1 M9 0 1 Burst Type Sequential Interleaved Write Burst Mode Prog. Burst Length Single Mode Access M6-M0 Defined - Operating Mode Standard Operation All other states reserved Note : 4. For full-page accesses: y = 512 5. For a burst length of two, A1-A8 select the block-of-two burst; A0 selects the starting column within the block. 6. For a burst length of four, A2-A8 select the block-of-four burst; A0-A1 select the starting column within the block. 7. For a burst length of eight, A3-A8 select the block-of-eight burst; A0-A2 select the starting column within the block. 8. For a full-page burst, the full row is selected and A0-A8 select the starting column. 9. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 10. For a burst length of one, A0-A8 select the unique column to be accessed,and mode register bit M3 is ignored. Rev. 0.4, Nov. ‘06 8 CMS4A16LAx–75xx Table 2. Burst Length Definition. Order of Accesses within a Burst Burst Length Starting Column Address Type=Sequential A0 2 0 1 A1 A0 00 4 01 10 11 A2 A1 A0 000 001 010 8 011 100 101 110 111 Full Page(y) n=A0-A8(location 0-y) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Bn, Bn+1, Bn+2…..Bn,… 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1 1-0 0-1 1-0 Type=Interleaved Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes.Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. If a READ command is registered at clock edge r, and the latency is q clocks, the data will be available by clock edge r + q. The DQs will start driving as a result of the clock edge one cycle earlier (r + q- 1), and provided that the relevant access times are met, the data will be valid by clock edge r + q. For example, assumi ng th at th e clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 3 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Write Burst Mode When M9=0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9=1, the programmed burst length applies to READ bursts, but write accesses are single-location (non-burst) accesses. Rev. 0.4, Nov. ‘06 9 CMS4A16LAx–75xx T0 T1 T2 CLK Command Read tLZ NOP tOH Dout tAC DQ CAS Latency=1 T0 T1 T2 T3 CLK Command Read NOP tLZ NOP tOH Dout tAC DQ CAS Latency=2 T0 T1 T2 T3 T4 CLK Command Read NOP NOP tLZ NOP tOH Dout tAC DQ CAS Latency=3 Figure 2. CAS Latency Rev. 0.4, Nov. ‘06 10 CMS4A16LAx–75xx Table 3. CAS Latency. Allowable Operating Frequency (MHz) Speed CAS Latency = 1 133MHz 100MHz ≤ 50 ≤ 40 CAS Latency = 2 ≤ 100 ≤ 83 CAS Latency = 3 ≤ 133 ≤ 100 EXTENDED MODE REGISTER The Extended Mode Register controls additional functions such as Partial Array Self Refresh (PASR) and Driver Strength (DS). The Extended Mode Register is programmed via the Mode Register Set command (BA1=1, BA0=0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be programmed with M8 through M11 set to “0”. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time initiating any subsequent operation. Violating either of these requirements results in unspecified operation. AUTO TEMPERATURE COMPENSATED SELF REFRESH Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. In order to save power consumption, according to the temperature, Mobile-SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically. PARTIAL ARRAY SELF REFRESH The Partial Array Self Refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are all banks (banks 0, 1, 2, and 3); two banks(banks 0 and 1 or 2 and 3 by M7); and one bank (bank 0 or 2 by M7). WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in PASR will be refreshed during SELF REFRESH. The data in the deselected bank will be lost. Driver Strength Control The driver strength feature allows one to reduce the drive strength of the I/O’s on the device during low frequency operation. This allows systems to reduce the noise associated with the I/O’s switching. EM13BA1 1 EM12BA0 0 EM11A11 EM10A10 EM9A9 EM8A8 EM7A7 Bank Up/Down EM6A6 EM5A5 EM4A4 0 EM3A3 0 EM2A2 EM1A1 PASR EM0A0 All must be set to ‘0’ Driver Strength Rev. 0.4, Nov. ‘06 11 CMS4A16LAx–75xx Table 5. Extended Mode Register Table[11.12.]. A7 0 A2 0 0 0 0 1 1 0 0 0 0 1 Note : 11. 12. EM13 and EM12 (BA1 and BA0) must be “1, 0” to select the Extended Mode Register(vs. the base Mode Register). RFU: Reserved for Future Use A1 0 0 1 1 X 0 0 1 1 X A0 0 1 0 1 X 0 1 0 1 X Self Refresh Coverage Four Banks Two Banks (Bank0 & 1) One Bank (Bank 0) RFU RFU Four Banks Two Banks (Bank2 & 3) One Bank (Bank2) RFU RFU A6 0 0 1 1 A5 0 1 0 1 Driver Strength 100% 75% 50% 25% Table 6. Commands[13.14.15.16.17.18.19.20.] . Name(Function) COMMAND INHIBIT(NOP) NO OPERATION(NOP) ACTIVE(Select bank and activate row)[15.] READ(Select bank and column, and start READ burst)[16.] WRITE(Select bank and column, and start WRITE burst)[16.] BURST TERMINATE PRECHARGE(Deactivate row in bank or banks) [17.] CKE X H H H H H H H H H H L /CS H L L L L L L L L L /RAS X H L H H H L L L H /CAS X H H L L H H L L H /WE X H H H L L L H L L DQM X X X L/H L/H X X X X L H X ADDR X X Bank/ Row Bank/ Col Bank/ Col X Code X Opcode - DQ X X X X Valid Active X X X Active High Z AUTO REFRESH or SELF REFRESH(Enter Self Refresh Mode) )[18. 19.] LOAD MODE REGISTER)[14.] Write Enable/Output Enable) Write Inhibit/Output High-Z) [20.] [20.] Deep Power Down(Enter DPD Mode) X X Rev. 0.4, Nov. ‘06 12 CMS4A16LAx–75xx Note : 13. CKE is HIGH for all commands shown except SELF REFRESH and Deep Power Down. 14. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. 15. A0-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 16. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 17. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 18. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 19. A0-A9 define the op-code written to the mode register and BA0, BA1 determine Normal MRS and Extended MRS. 20. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). LDQM controls DQ0-7 and UDQM controls DQ8-15. Commands Table 6. provides a reference of all the commands available with the state of the control signals for executing a specific command. COMMAND INHIBIT The COMMAND INHIBIT function effectively deselects the SDRAM by preventing new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (/CS is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode register is loaded via inputs A0-A11, BA0, BA1. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. Table 1, Table 4 And Table 5 provide the definition for the Mode Register and Extended Mode Register. ACTIVE The ACTIVE command is used to activate a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. If auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. Rev. 0.4, Nov. ‘06 13 WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst. If auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the active row in a particular bank or the active row in all banks. The bank(s) will be available for a subsequent row access after a specified time (tRP) from the issued PRECHARGE command. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE AUTO PRECHARGE is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. AUTO PRECHARGE thus performs the same PRECHARGE command described above , without requiring an explicit command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE does not apply in the full page mode burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated. CMS4A16LAx–75xx AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command. The addressing is generated by the internal refresh controller. The address bits thus are a “Don’t Care” during an AUTO REFRESH command. The Fidelix 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms. DEEP POWER DOWN Deep Power Down Mode is an operating mode to achieve extreme power reduction by cutting the power of the whole memory array of the device. Data will not be retained once the device enters DPD Mode. Full initialization is required when the device exits from DPD Mode. [Figure 29.30] SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM( without external clocking), even if the rest of the system is powered down. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that.The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (meet the clock specifications in the AC characteristics) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize he row refresh counter. Rev. 0.4, Nov. ‘06 14 CMS4A16LAx–75xx Maximum Ratings Voltage on VDD/VDDQ Supply Relative to VSS ……. …….……………………….... –1V to + 4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS …….. …….…………………………. -1V to + 4.6V Storage Temperature(plastic) ………….………. -55℃ to + 150℃ Power Dissipation ………………………….….………………1W *Stresses greater than those listed under “Maximum Ratings” may cause permanent damage to the device.This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Range Device CMS4A16LAx-xxxS CMS4A16LAx-xxxC CMS4A16LAx-xxxE CMS4A16LAx-xxxI Range Special Commercial Extended Industrial Ambient Temperature -10℃ to +60℃ 0℃ to +70℃ -25℃ to +85℃ -40℃ to +85℃ 2.3V to 3.3V 1.70V to VDD VDD VDDQ DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS [21.22.] Parameter / Condition Supply Voltage I/O Supply Voltage Input High Voltage : Logic 1 All Inputs Input Low Voltage : Logic 0 All Inputs [23.] [23.] Symbol VDD VDDQ VIH VIL VOH VOL II lOZ Min 2.3 1.70 0.8* VDDQ -0.3 0.9* VDDQ Max 3.3 3.3 VDDQ +0.3 0.3 Units V V V V V Data Output High Voltage : Logic 1 : All Inputs(-0.1mA) Data Output Low Voltage : Logic 0 : All Inputs(0.1mA) Input Leakage Current : Any Input 0V=VIN=VDD (All other pins not under test=0V) Output Leakage Current : DQs are disabled ; 0V= VOUT=VDDQ 0.2 -5 -5 5 5 V ㎂ ㎂ Table 7. AC OPERATING CONDITIONS[21.22.23.24.25.26.] Parameter / Condition Input High Voltage : Logic 1 All Inputs Input Low Voltage : Logic 0 All Inputs Input and Output Measurement Reference Level Symbol VIH VIL Value 0.9* VDDQ 0.2 0.5*VDDQ Units V V V Rev. 0.4, Nov. ‘06 15 CMS4A16LAx–75xx Table 8. IDD Specifications and Conditions [21.22.26.27.]. Parameter IDD1 IDD2P IDD2N IDD3P IDD3N IDD4 IDD5 IDD6 Description Operating Current: Active Mode; Burst =2 ; Read or Write ; tRC ≥ tRC(min); CAS Latency =3 [28.29.30.] , tCK=10ns Precharge Standby Current in power down mode : CKE ≤ VIL(max) , tCK=10ns Precharge Standby Current in non power down mode : CKE ≥ VIH(min), /CS ≥ VIH(min) [28.29.30,31.] , tCK=10ns Active Standby Current in power down mode; CKE ≤ VIL(max) [28.29,30.31.], tCK=10ns Active Standby Current in non power down mode (One Bank Active); CKE ≥ VIH(min), /CS ≥ VIH(min) [28.29,30.31.], tCK=10ns Operating Current: Burst Mode: Continuous Burst ; Read or Write : All banks Active, CAS Latency =3[28.29.30.] , tCK=10ns Auto Refresh Current : tRC ≥ tRC(min), tCK=10ns Self Refresh Current : CKE ≤ 0.2V, 4 Banks, tCK= ∞ Self Refresh Current : CKE ≤ 0.2V, 2 Banks , tCK= ∞ Self Refresh Current : CKE ≤ 0.2V, 1 Banks, tCK= ∞ IDD7 Note : 21. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40°C = TA = +85°C for IT parts) is ensured. 22. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 23. All states and sequences not shown are illegal or reserved. 24. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 25. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 26. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover point. If the input transition time is longer than tT (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point. 27. IDD specifications are tested after the device is properly initialized. 28. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 29. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 30. Input signals are changed one time during 20ns. 31. Unless otherwise note, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). 32. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD 6 limit is actually a nominal value and does not result in a fail value -75 55 0.4 12 3 20 55 130 450 350 300 10 Units ㎃ ㎃ ㎃ ㎃ ㎃ ㎃ ㎃ ㎂ ㎂ ㎂ ㎂ Deep power down, tCK= ∞ Capacitance[] Parameter CIN COUT Description Input Capacitance TA=25℃, f=1Mhz, VDD(typ) Output Capacitance 6 pF Test Conditions Max 4 Units pF AC Test Loads VDDQ/2 50Ω Z0=50Ω OUTPUT 30pF Rev. 0.4, Nov. ‘06 16 CMS4A16LAx–75xx AC Characteristics AC Characteristics Parameter Clock Period[33.] Clock High Time Clock Low Time Address Setup Time to Clock Address Hold Time to Clock CKE Setup Time to Clock CKE Hold Time to Clock CL=3 Clock Access Time[34, 35] CL=2 CL=1 Output Hold Time from Clock Data In Setup Time to Clock Data In Hold Time to Clock /CS, /RAS, /CAS, /WE, /DQM Setup Time to Clock /CS, /RAS, /CAS, /WE, /DQM Hold Time to Clock Data High Impedance Time[25.] Active to Precharge Command Active to Active Command Period Active to Read/Write Delay Refresh Period(4096 rows) Auto Refresh Period Precharge Command Period Active Banka to Active Bankb Command Transition Time[36.] Write Recovery Time [37.] Symbol tCLKS3 tCLKS2 tCH tCL tCAS tCAH t CKS -75 Min 7.5 10 2.5 2.5 2.0 1.0 2.0 1.0 6 7 20 2.5 2.0 1.0 2.0 1.0 3 45 70 18 64 70 18 15 0.5 1tCK + 3ns 80 1 1 1 0 0 2 0 4 1 1 1.2 5.4 120000 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns tCK ns tCK tCK tCK tCK tCK tCK tCK ns tCK tCK tCKH tAC(3) tAC(2) tAC(1) tOH tCDS tCDH tCMS tCMH tHZ tRAS tRC tRCD tREF tRFC tRP tRRD tT tWR tXSR [39.] Exit Self Refresh to Active Command[38.] READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode [40.] tCCD tCKED tPED tDQD tDQM CKE to clock enable or power-down exit setup mode[40.] DQM to input data delay [39.] DQM to data mask during WRITEs[39.] DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command[41.] Data-in to PRECHARGE command [42.] [39.] [39.] tDQZ tDWD tDAL tDPL tBDL Last data-in to burst STOP command[39.] Rev. 0.4, Nov. ‘06 17 CMS4A16LAx–75xx AC Characteristics AC Characteristics Parameter Last data-in to new READ/WRITE command[39.] Last data-in to PRECHARGE command [42.] Symbol tCDL tRDL tMRD tROH(3) tROH(2) tROH(1) -75 Min 1 2 2 3 2 1 Max Units tCK tCK tCK tCK tCK tCK LOAD MODE REGISTER command to ACTIVE or REFRESH command[43.] CL=3 Data-out to high-impedance from PRECHARGE command [40.] CL=2 CL=1 Note : 33. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 34. tAC for -133Mhz at CL=3 with no load is 4.5ns and is guaranteed by design. 35. tAC for -133Mhz at CL=3 and VDD of 1.8V is 6.5ns. 36. AC characteristics assume tT = 1ns. 37. Auto precharge mode only. The precharge timing budget (tRP) begins at 7ns for -133Mhz after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 38. CLK must be toggled a minimum of two times during this period. 39. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 40. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 41. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 42. Timing actually specified by tWR. ( tDPL is 1CLK at 100Mhz or tDPL is 2CLK at 133Mhz ) 43. JEDEC and PC100 specify three clocks. Rev. 0.4, Nov. ‘06 18 CMS4A16LAx–75xx Operation BANK / ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened” (activated). This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. A READ or WRITE command may then be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t tRRD. READs READ bursts are initiated with a READ command, as shown in Figure 3. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 2. shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (The burst will wrap around at the end of the page). A continuous flow of data can be maintained by having additional Read Burst or single Read Command. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 4. for CAS latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Full-speed random read accesses can be performed to the same bank, as shown in Figure 5. , or each subsequent READ may be performed to a different bank. Read Command CLK CKE High /CS /RAS /CAS /WE Column Address A0-A8 A9, A11 Enable Auto Precharge A10 Disable Auto Precharge BA0, 1 Bank Address Don’t Care Figure 3. Read Command Rev. 0.4, Nov. ‘06 19 CMS4A16LAx–75xx T0 T1 T2 T3 T4 T5 CLK Command Read NOP NOP NOP Read X=0cycles NOP Address Bank Col n Bank Col b DQ Dout n CAS Latency=1 Dout n+1 Dout n+2 Dout n+3 Dout b T0 T1 T2 T3 T4 T5 T6 CLK X=1cycles Command Read NOP NOP NOP Read NOP NOP Address Bank Col n Bank Col b DQ Dout n CAS Latency=2 Dout n+1 Dout n+2 Dout n+3 Dout b Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 Rev. 0.4, Nov. ‘06 20 CMS4A16LAx–75xx T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read NOP NOP NOP Read X=2cycles NOP NOP NOP Address Bank Col n Bank Col b DQ Dout n CAS Latency=3 Dout n+1 Dout n+2 Dout n+3 Dout b Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 T0 T1 T2 T3 T4 CLK Command Read Read Read Read NOP Address Bank Col n Bank Col a Bank Col x Bank Col m DQ Dout n CAS Latency=1 Dout a Dout x Dout m Figure 5. Random Read Accesses for CAS Latency =1,2,3 Rev. 0.4, Nov. ‘06 21 CMS4A16LAx–75xx T0 T1 T2 T3 T4 T5 CLK Command Read Read Read Read NOP NOP Address Bank Col n Bank Col a Bank Col x Bank Col m DQ CAS Latency=2 Dout n Dout a Dout x Dout m T0 T1 T2 T3 T4 T5 T6 CLK Command Read Read Read Read NOP NOP NOP Address Bank Col n Bank Col a Bank Col x Bank Col m DQ CAS Latency=3 Dout n Dout a Dout x Dout m Figure 5. Random Read Accesses for CAS Latency =1,2,3 A Read Burst can be terminated by a subsequent Write command, and data from a fixed length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figure 6. and Figure 7. . The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM Rev. 0.4, Nov. ‘06 22 CMS4A16LAx–75xx was active on the clock just prior to the WRITE command that truncated the READ command. The DQM signal must be asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 6. shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 7. shows the case with the additional NOP cycle. T0 T1 T2 T3 T4 CLK DQM tCK Command Read NOP NOP NOP Write Address Bank Col n tHZ Bank Col b DQ CAS Latency=3 Dout n Din b tDS Figure 6. Read to Write Rev. 0.4, Nov. ‘06 23 CMS4A16LAx–75xx T0 T1 T2 T3 T4 T5 CLK DQM tCK Command Read NOP NOP NOP NOP Write Address Bank Col n tHZ Bank Col b DQ CAS Latency=3 Dout n Din b tDS Figure 7. Read to Write with extra clock cycle T0 CLK CMD T1 T2 T3 T4 T5 T6 T7 T8 Read Write Read masked by write DQM DQ Din n Din n+1 Din n+2 Din n+3 CMD Read Write Read masked by DQM DQM DQ Din n Din n+1 Din n+2 Din n+3 CMD Read DQM Write Read CAS=2 DQ Dout n Din n Din n+1 Din n+2 Din n+3 Figure 8. Read Interrupted by Write with DQM ; CAS Latency =2 Rev. 0.4, Nov. ‘06 24 CMS4A16LAx–75xx A fixed-length READ burst or a full-page burst may be followed by, or truncated with, a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 9. for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 10. for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. T0 T1 T2 T3 T4 T5 T6 T7 CLK tRP Read NOP NOP NOP Precharge X=0cycles NOP NOP Active Command Address Bank a Col n Bank (a or all) Bank a Row DQ Dout n CAS Latency=1 Dout n+1 Dout n+2 Dout n+3 T0 T1 T2 T3 T4 T5 T6 T7 CLK tRP Read NOP NOP NOP Precharge X=1cycles NOP NOP Active Command Address Bank a Col n Bank (a or all) Bank a Row DQ Dout n CAS Latency=2 Dout n+1 Dout n+2 Dout n+3 Figure 9. Read to Precharge Rev. 0.4, Nov. ‘06 25 CMS4A16LAx–75xx T0 T1 T2 T3 T4 T5 T6 T7 CLK tRP Command Read NOP NOP NOP Precharge X=2cycles Address Bank a Col n Bank (a or all) Bank a Row NOP NOP Active DQ Dout n CAS Latency=3 Dout n+1 Dout n+2 Dout n+3 Figure 9. Read to Precharge T0 T1 T2 T3 T4 T5 T6 T7 CLK Burst Terminate X=0cycles Address Bank a Col n Command Read NOP NOP NOP NOP NOP NOP DQ Dout n CAS Latency=1 Dout n+1 Dout n+2 Dout n+3 Figure 10. Terminating a Read Burst Rev. 0.4, Nov. ‘06 26 CMS4A16LAx–75xx T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read NOP NOP NOP Burst Terminate X=1cycles NOP NOP NOP Address Bank a Col n DQ CAS Latency=2 Dout n Dout n+1 Dout n+2 Dout n+3 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read NOP NOP NOP Burst Terminate X=2cycles NOP NOP NOP Address Bank a Col n DQ Dout n CAS Latency=3 Dout n+1 Dout n+2 Dout n+3 Figure 10. Terminating a Read Burst Rev. 0.4, Nov. ‘06 27 CMS4A16LAx–75xx 0 CLOCK CKE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HIGH *note 45. tRC /CS tRCD /RAS *note 46. tRP /CAS ADDR RAa CAa RAb CAb BA0 BA1 A10/AP RAa tOH RAb CL=2 tRAC *note 47. Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 DQ tAC tOH tHZ *note 48. tDPL CL=3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 tRAC *note 47. tAC tHZ *note 48. tDPL /WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) Don’t Care Note : 45. Minimum row cycle times is required to complete internal DRAM operation. 46. Row precharge can interrupt burst on any cycle.[CAS Latency -1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ) after the clock. 47. Access time from Row active command. tCLK *(tRCD + CAS latency - 1) + tAC 48. Out put will be Hi-Z after the end of burst. (1,2,3,8 & Full page bit burst) Figure 11. Read & Write Cycle at Same Bank @Burst Length=4, tDPL = 1CLK (100Mhz) / tDPL = 2CLK (133Mhz) Rev. 0.4, Nov. ‘06 28 CMS4A16LAx–75xx 0 CLOCK CKE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HIGH *note 45. tRC /CS tRCD /RAS *note 46. tRP /CAS ADDR RAa CAa RAb CAb BA0 BA1 A10/AP RAa tOH RAb CL=2 tRAC *note 47. Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 tAC tOH tHZ *note 48. DQ tDPL CL=3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 tRAC *note 47. tAC tHZ *note 48. tDPL /WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Don’t Care Figure 12. Read & Write Cycle at Same Bank @Burst Length=4, tDPL= 1CLK (100Mhz) / tDPL= 2CLK (133Mhz) Rev. 0.4, Nov. ‘06 29 CMS4A16LAx–75xx 0 CLOCK CKE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HIGH /CS /RAS *note 49. /CAS ADDR RAa RBb CAa RCc CBb RDd CCc CDd BA0 BA1 A10/AP RAa RBb RCc RDd CL=2 DQ CL=3 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 /WE DQM Row Active (A-Bank) Read (A-Bank) Row Active (B-Bank) Read (B-Bank) Row Active (C-Bank) Precharge (A-Bank) Read (C-Bank) Read (D-Bank) Precharge (C-Bank) Precharge (D-Bank) Precharge (B-Bank) Don’t Care Note : 49. Row precharge will interrupt writing. Last data input, tDPL before Row precharge, will be written. Figure 13. Page Read Cycle at Same Bank @ Burst Length=4 WRITE WRITE bursts are initiated with a WRITE command,as shown Rev. 0.4, Nov. ‘06 30 in Figure 14. The starting column and bank addresses are provided with the WRITE command, and auto precharge is CMS4A16LAx–75xx either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixedlength burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 15.). A full-page burst will continue until terminated. (wrap around at the end of the page) An example is shown in Figure 16. . Data n + 1 is either the last of a burst of two or the last desired of a longer burst. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 17. , or each subsequent WRITE may be performed to a different bank. Write Command CLK CKE High /CS /RAS /CAS /WE A0-A8 Column Address A9, A11 Enable Auto Precharge A10 Disable Auto Precharge Bank Address BA0, 1 Don’t Care Figure 14. Write Command Rev. 0.4, Nov. ‘06 31 CMS4A16LAx–75xx T0 T1 T2 T3 CLK Command Write NOP NOP NOP Address Bank Col n DQ Din n Din n+1 Figure 15. Write Burst - Burst length of 2 T0 T1 T2 CLK Command Write NOP Write Address Bank Col n Bank Col b DQ Din n Din n+1 Din b Figure 16. Write to Write - Transition from a burst of 2 to a single write Data for a fixed-length WRITE burst a full-page WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank.The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge Rev. 0.4, Nov. ‘06 32 prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 19. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. CMS4A16LAx–75xx T0 T1 T2 T3 CLK Command Write Write Write Write Address Bank Col n Bank Col a Bank Col x Bank Col m DQ Din n Din a Din x Din m Figure 17. Random Write Cycles T0 T1 T2 T3 T4 T5 CLK Command Write NOP Read NOP NOP NOP Address Bank Col n Bank Col b DQ Din n Din n+1 Dout b Dout b+1 Figure 18. Write to Read Burst of 2 Write and Read(CAS Latency =2) Rev. 0.4, Nov. ‘06 33 CMS4A16LAx–75xx T0 T1 T2 T3 T4 T5 T6 CLK tWR @ tCK >=15ns DQM tRP Command Write NOP Precharge NOP Active NOP NOP Address Bank Col n tWR Bank (a or all) Bank a Row DQ Din n tWR @ tCK =tCKS Command NOP NOP Active All banks Idle Input buffers gated off tRCD tRAS tRC Enter Power Down Mode Exit Power Down Mode Figure 22. Power Down CLOCK SUSPEND The clock suspend mode occurs when a column access/ burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burstcounters are not incremented, as long as the clock is suspended. (See examples in Figure 23. and Figure 24. .) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. BURST READ/SINGLE WRITE In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. READ commands access columns according to the programmed burst length and sequence. Rev. 0.4, Nov. ‘06 37 CMS4A16LAx–75xx T0 T1 T2 T3 T4 T5 CLK CKE Internal CLK Command NOP Write NOP NOP Address Bank Col n DQ Din n Din n+1 Din n+2 Figure 23. Clock Suspend During Write Burst Rev. 0.4, Nov. ‘06 38 CMS4A16LAx–75xx T0 T1 T2 T3 T4 T5 T6 CLK CKE Internal CLK Command Read NOP NOP NOP NOP NOP Address Bank Col n DQ Dout n Dout n+1 Dout n+2 Dout n+3 Figure 24. Clock Suspend During Read Burst - Burst of 4 (CAS latency =2) Concurrent Auto Precharge If an access command with Auto Precharge is being executed ; an access command (either a Read or Write ) is not allowed by SDRAM’s. If this feature is allowed then the SDRAM supports Concurrent Auto Precharge. Fidelix SDRAMs support Concurrent Auto Precharge. Four cases where Concurrent Auto Precharge occurs are defined below. Read With Auto Precharge 1. Interrupted by a Read(with or without auto precharge): A read to bank m will interrupt a Read on bank n, CAS latency later. The precharge to bank n will begin when the Read to bank m is registered. (Figure 25. ) 2. Interrupted by a Write(with or without auto precharge): A Write to bank m will interrupt a Read on bank n when registered. DQM should be used two clocks prior to the Write command to prevent bus contention. The Precharge to bank n will begin when the write to bank m is registered. (Figure 26. ) Write with Auto Precharge 3. Interrupted by a Read(with or without auto precharge): A Read to bank m will interrupt a Write on bank n when registered , with the data-out appearing CAS latency later. The Precharge to bank n will begin after tWR is met, where tWR begins when the Read to bank m is registered. The last valid Write to bank n will be data-in registered one clock prior to the Read to bank m.(Figure 27. ) 4. Interrupted by a Write ( with or without auto Precharge): A Write to bank m will interrupt a Write on bank n when registered. The Precharge to bank n will begin after tWR is met ,where tWR begins when the Write to bank m is registered. The latest valid data Write to bank n will be data registered one clock prior to a Write to bank m.( Figure 28. ) Rev. 0.4, Nov. ‘06 39 CMS4A16LAx–75xx T0 CLK Command Internal States T1 T2 T3 T4 T5 T6 T7 NOP Read-AP Bank n NOP Read-AP Bank m NOP NOP NOP NOP tRP - Bank m Idle tRP - Bank n Page Active Page Active Read with a Burst of 4 Interrupt Burst, Precharge Bank n Bank m Read with Burst of 4 Precharge Address Bank n Col a Bank m Col d Dout a CAS Latency=3(Bank n) CAS Latency=3(Bank m) Dout a+1 Dout d Dout d+1 DQ Figure 25. Read with Auto Precharge Interrupted by a Read(CAS Latency =3) T0 CLK Command Read-AP Bank n T1 T2 T3 T4 T5 T6 T7 NOP NOP NOP Write-AP Bank m NOP NOP NOP tWR - Bank m Idle Internal States tRP - Bank n Page Active Page Active Read with a Burst of 4 Interrupt Burst, Precharge Bank n Bank m Write with Burst of 4 Write-Bank Address Bank n Col a Bank m Col d DQM DQ CAS Latency=3(Bank n) Dout a Din d Din d+1 Din d+2 Din d+3 Figure 26. Read With Auto Precharge Interrupted by a Write(Read CAS Latency =3) 40 Rev. 0.4, Nov. ‘06 CMS4A16LAx–75xx T0 CLK Command Internal States T1 T2 T3 T4 T5 T6 T7 NOP Write-AP Bank n NOP Read-AP Bank m tWR- Bank n NOP NOP NOP NOP tRP - Bank m Bank n Page Active Write with a Burst of 4 Interrupt Burst, Write-Bank Precharge tRP - Bank n Bank m Page Active Read with Burst of 4 Precharge Address Bank n Col a Din a Din a+1 Bank m Col d Dout d CAS Latency=3(Bank m) Dout d+1 DQ Figure 27. Write with Auto Precharge Interrupted by a Read(CAS Latency =3) T0 CLK Command Internal States T1 T2 T3 T4 T5 T6 T7 NOP Write-AP Bank n NOP NOP Write-AP Bank m tWR -Bank n NOP NOP NOP tRP -Bank n Precharge tWR - Bank m Bank n Page Active Write with a Burst of 4 Interrupt Burst, Write-Bank Bank m Page Active Write with Burst of 4 Write-Bank Address Bank n Col a Bank m Col d DQ Din a Din a+1 Din a+2 Din d Din d+1 Din d+2 Din d+2 Figure 28. Write with Auto Precharge Interrupted by a Write Rev. 0.4, Nov. ‘06 41 CMS4A16LAx–75xx DEEP POWER DOWN MODE ENTRY The Deep Power Down Mode is entered by having burst termination command, while CKE is low. The Deep Power Down Mode has to be maintained for a minimum of 100us. The following diagram illustrates Deep Power Down mode entry. CLK CKE tRP Command NOP Precharge All Bank NOP NOP Burst Terminate Precharge If needed Deep Power Down Entry Figure 29. Deep Power Down Mode Entry DEEP POWER DOWN MODE EXIT SEQUENCE The Deep Power Down Mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command 1. Maintain NOP input conditions for a minimum of 200us 2. Issue precharge commands for all banks of the device 3. Issue 8 or more auto refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue a extended mode register set command to initialize the extended mode register The following timing diagram illustrates deep power down exit sequence CLK CKE Command Precharge All Bank NOP AREF MRS NOP EMRS NOP Active Address 200 us Deep Power Down Exit A10 tRP Precharge All Bank Figure 30. Deep Power Down Mode Exit Key Key Bank a Row Normal MRS Extended MRS Row Active A Bank Rev. 0.4, Nov. ‘06 42 CMS4A16LAx–75xx Table 9. CKE[50.51.52.53.] . CKEn-1 CKEn Current State Power Down L L Self Refresh Clock Suspend Power Down[54.] Self Refresh[55.] Clock Suspend[56.] All Banks Idle H L All Banks Idle Reading or Writing Commandn X X X Command Inhibit or NOP Command Inhibit or NOP X Command Inhibit or NOP Auto Refresh Valid See Table 10. Actionn Maintain Power Down Maintain Self Refresh Maintain Clock Suspend Exit Power Down Exit Self Refresh Exit Clock Suspend Power Down Entry Self Refresh Entry Clock Suspend Entry L H H Note : 50. 51. 52. 53. 54. 55. H CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current State is the state of the SDRAM immediately prior to the clock edge n. Commandn is the command registered at clock edge n , and Actionn is a result of Commandn. All states and sequences not shown are illegal or reserved. Exiting power down at clock edge n will put the device in all the banks idle state in time for clock edge n+1(provided the tCKS is met) Exiting self refresh at clock edge n will put the device in all the banks idle state once tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum of two NOP commands must be provided during the tXSR period. 56. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1. Table 10. Current State Bank n, Command to Bank n[57.58.59.60.61.62.] . Current State Any L L L Idle L L Note : 57. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 9. ) and after tXSR has been met (if the previous state was self refresh). 58. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 59. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 60. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 10. and according to Table 11. . Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 61. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 62. All states and sequences not shown are illegal or reserved. 63. Not bank-specific; requires that all banks are idle. 64. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 65. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 66. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 67. Does not affect the state of the bank and acts as a NOP to that bank. CS# H RAS# X H L L L L CAS# X H H L L H WE# X H H H L L Command(Action) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH[63.] LOAD MODE REGISTER [63.] PRECHARGE [67.] Rev. 0.4, Nov. ‘06 43 CMS4A16LAx–75xx Table 10. Current State Bank n, Command to Bank n[57.58.59.60.61.62.] . Current State Row Active CS# L L L L Read(Auto Precharge Disabled) Write (Auto Precharge Disabled) L L L L L L L RAS# H H L H H L H H H L H CAS# L L H L L H H L L H H WE# H L L H L L L H L L L Command(Action) READ (Select column and start READ burst)[66.] WRITE (Select column and start WRITE burst)[66.] PRECHARGE (Deactivate row in bank or banks)[64.] READ (Select column and start new READ burst)[66.] WRITE (Select column and start WRITE burst)[66.] PRECHARGE (Truncate READ burst, start RECHARGE)[64.] BURST TERMINATE[65.] READ (Select column and start READ burst)[66.] WRITE (Select column and start new WRITE burst)[66.] PRECHARGE (Truncate WRITE burst, start PRECHARGE)[64.] BURST TERMINATE[65.] Table 11. Current State Bank n, Command to Bank m[68.69.70.71.72.73.] . Current State Any L Idle Row Activating, Active, or Precharging X L L L L L Read(Auto Precharge Disabled) L L L L Write(Auto Precharge Disabled) L L L H X L H H L L H H L L H H L H X H L L H H L L H H L L H H X H H L L H H L L H H L L NO OPERATION (NOP/Continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (Select and activate row) READ (Select column and start READ burst)[74.] WRITE (Select column and start WRITE burst)[74.] PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst)[74.78.] WRITE (Select column and start WRITE burst)[74.79.] PRECHARGE[76.] ACTIVE (Select and activate row) READ (Select column and start READ burst)[74.79.] WRITE (Select column and start new WRITE burst)[76.80.] PRECHARGE[76.] CS# H RAS# X CAS# X WE# X Command(Action) COMMAND INHIBIT (NOP/Continue previous operation) Rev. 0.4, Nov. ‘06 44 CMS4A16LAx–75xx Table 11. Current State Bank n, Command to Bank m[68.69.70.71.72.73.] . Current State Read (With Auto Precharge) CS# L L L L L Write (With Auto Precharge) Note : 68. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSR has been met (if the previous state was self refresh). 69. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 70. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 71. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 72. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 73. All states and sequences not shown are illegal or reserved. 74. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 75. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m’s burst. 76. Burst in bank n continues as initiated. 77. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. 78. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used twwo clock prior to the WRITE command to prevent bus contention. 79. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 80. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 81. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 25.) . 82. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 26. ). 83. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m(Figure 27. ). 84. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 28. ). RAS# L H H L L H H L CAS# H L L H H L L H WE# L H L L H H L L Command(Action) ACTIVE (Select and activate row) READ (Select column and start new READ burst)[74.75.81.] WRITE (Select column and start WRITE burst)[74.75.82.] PRECHARGE[76.] ACTIVE (Select and activate row) READ (Select column and start READ burst)[74.75.83.] WRITE (Select column and start new WRITE burst)[74.75.84.] PRECHARGE[76.] L L L Rev. 0.4, Nov. ‘06 45 CMS4A16LAx–75xx PACKAGE DIMENSION 54 BALL FINE PITCH BGA Unit : millimeters Top View Bottom View A1 INDEX MARK E E1 1 A B 2 3 4 5 6 7 8 9 A 9 8 7 6 5 4 3 2 1 e B C D D1 D E F G H J D/2 #A1 C D E F G H J e E/2 Side View b A1 A z E A A1 E E1 D D1 e b z Min 0.30 0.40 - Typ 0.35 8.00 6.40 8.00 6.40 0.80 0.45 - Unit : mm Max 1.20 0.40 0.50 0.10 Rev. 0.4, Nov. ‘06 46