CMS6416LAG

CMS6416LAx-15Ex 64M(4Mx16) Low Power SDRAM Revision 1.3 November, 2005 Rev1.3, Nov. 2005 CMS6416LAx-15Ex Document Title 64M(4Mx16) Low Power SDRAM Revision History Revision No. 0.0 0.1 Initial Draft Correct typo. Add Write Burst Mode description Add commercial & extended temperature options Add package dimension Extend Vddmax limit for 2.5V product Change IDD specifications Add Pb & Halogen free package item Change from manual TCSR to auto TCSR Change IDD2N specifications Change Setup/Hold time Change IDD3p/Idd6 specification Add H(Pb-Free & Halogen Free) descriptions History Draft date Jun.25th, 2004 Aug.13th, 2004 Remark Preliminary Preliminary 0.2 0.3 0.4 Oct.6th, 2004 Oct.20th, 2004 Dec.6th, 2004 Preliminary Preliminary Preliminary 1.0 Jan.5th, 2005 Preliminary 1.1 1.2 1.3 Jan.10th, 2005 Feb, 2005 Nov. 1st, 2005 Final Rev1.3, Nov. 2005 CMS6416LAx-15Ex Features - Functionality - Standard SDRAM Functionality - Programmable burst lengths : 1, 2, 4, 8, or full page - JEDEC Compatibility - Low Power Features - Low voltage power supply : 1.8V - Auto TCSR(Temperature Compensated Self Refresh) - Partial Array Self Refresh power-saving mode - Deep Power Down Mode - Driver Strength Control - Operating Temperature Ranges: - Special (-10℃ to +60℃) - Commercial (0℃ to +70℃) - Extended (-25℃ to +85℃) - Industrial (-40℃ to +85℃) - LVCMOS Compatible IO Interface - 54ball FBGA with 0.8mm ball pitch - CMS6416LAF : Normal - CMS6416LAG : Pb-Free - CMS6416LAH : Pb-Free & Halogen Free Functional Description The CMS6416LAx-xxxx family is high-performance CMOS Dynamic RAMs (DRAM) organized as 4M x 16. These devices feature advanced circuit design to provide ultra-low active current and extremely low standby current.This is ideal for providing More Battery Life in portable applications such as wireless handsets. The device is compatible with the JEDEC standard LP-SDRAM specifications. Logic Block Diagram CKE CLK /CS /WE /CAS /RAS Bank 3 Bank 2 Bank 1 Bank 0 Control Logic Refresh Counter Mode Reg Enhanced Mode Reg Bank 0 Bank 0 Row Memory Row Addr Row Array Addr Latch/ Add Latch/ Decoder Mux 4Kx4K - CMS6432LBH : Pb-Free & Halogen Free Decoder LDQM UDQM Data Output Reg Sense Amp Bank Control Logic A0-A11 BA0-BA1 Addr Reg Column Column Decoder Column Decoder Column Decoder Decoder Write Drivers DQM Mask READ DATA LATCH DQ0 DQ15 Data Output Reg Column Address Latch Selection Guide Voltage Device VDD CMS6416LAx-15Ex 1.65-1.95V VDDQ 100MHz 1.65-VDD 83MHz 8ns Frequency Access Time(tAC) CL=2 CL=3 7ns 20ns 20ns 20ns 20ns tRCD tRP Rev1.3, Nov. 2005 CMS6416LAx-15Ex Pin Configuration for X16 54 ball FBGA(8mm x 8mm) 1 2 3 4 5 6 7 8 9 A B C D E F G H J VSS DQ15 VSSQ VDDQ DQ0 VDD DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 DQ8 NC VSS VDD LDQM DQ7 UDQM CLK CKE /CAS /RAS /WE NC A11 A9 BA0 BA1 /CS A8 A7 A6 A0 A1 A10 VSS A5 A4 A3 A2 VDD Rev1.3, Nov. 2005 CMS6416LAx-15Ex Pin Description Symbol CLK Type Input Description Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle), ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered. Input/Output Mask: L(U)DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM corresponds to DQ0 – DQ7 and UDQM corresponds to DQ8–DQ15. Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. Address Inputs: A0–A11 are sampled during the ACTIVE command (row-address A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (A10 LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output : Data bus No Connect DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: Voltage dependent on option. Ground. CKE Input /CS Input /CAS, /RAS, /WE Input LDQM, UDQM Input BA0, BA1 Input A0-A11 Input DQ NC VDDQ VSSQ VDD VSS I/O Supply Supply Supply Supply Rev1.3, Nov. 2005 CMS6416LAx-15Ex FUNCTIONAL DESCRIPTION The Fidelix 64Mb SDRAM is a quad-bank DRAM that o per a te s a t 1 .8 V an d i nclu des a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0- A11 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.The SDRAM must be initialized prior to normal operation. The following sections provide detailed information regarding device initialization, register definition, command descriptions and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable (meets the clock specifications in the AC characteristics), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. The COMMAND INHIBIT or NOP should be applied at least once during the 100µs delay. After the 100µs delay, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Refer to Figure 1. Rev1.3, Nov. 2005 CMS6416LAx-15Ex Figure 1. Initialize and Load Mode Register[1.2.3.] 0 CLK CKE /CS /RAS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 /CAS /WE ADDR Key Key Key BA0 BA0 BA1 BA1 A10/AP DQ DQM tRP HiZ HiZ RAa High level is necessary tRC tRC Precharge (All Bank) Auto Refresh Auto Refresh Normal MRS Extended MRS Row Active a Bank Note : 1. The two AUTO REFRESH commands at T4 and T9 may be applied before either LOAD MODE REGISTER (LMR) command. 2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address 3. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order; However, all must occur prior to an Active command. Register Definition There are two mode registers which contain settings to achieve low power consumption. The two registers : Mode Register and Extended Mode Register are discussed below. burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, M10, M11, M12 and M13 should be set to zero.The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Table 1. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode Register bits M0-M2 specify the burst length, M3 specifies the type of Rev1.3, Nov. 2005 Burst Length Read and write accesses to the SDRAM are burst oriented. The burst length is programmable, as shown in Table 2. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1,2, 4, or 8 locations are available for both the CMS6416LAx-15Ex sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two; by A2-A7 when the burst length is set to four; and by A3-A7 when the burst length is set to eight. M13BA1 M12BA0 M11A11 M10A10 The remaining(least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type The burst type can be set to either Sequential or Interleaved by using the M3 bit in the Mode register. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 2. [4.5.6.7.8.9.10.] M9-A9 WB M8-A8 M7-A7 M6-A6 M5-A5 M4-A4 M3-A3 BT M2-A2 M1-A1 Burst Length M0-A0 Reserved(Set to ‘0’) Op Mode Burst Length CAS Latency M2 M1 M0 000 001 010 011 100 101 110 111 M6 M5 M4 000 001 010 011 100 101 110 111 Note : M3 M3=1 1 2 4 8 Reserved Reserved Reserved Reserved 0 1 M9 0 1 Burst Type Sequential Interleaved Write Burst Mode Prog. Burst Length Single Mode Access M3=0 1 2 4 8 Reserved Reserved Reserved Full Page CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved M8 0 - M7 0 - M6-M0 Defined - Operating Mode Standard Operation All other states reserved 4. For full-page accesses: y = 256 5. For a burst length of two, A1-A7 select the block-of-two burst; A0 selects the starting column within the block. 6. For a burst length of four, A2-A7 select the block-of-four burst; A0-A1 select the starting column within the block. 7. For a burst length of eight, A3-A7 select the block-of-eight burst; A0-A2 select the starting column within the block. 8. For a full-page burst, the full row is selected and A0-A7 select the starting column. 9. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 10. For a burst length of one, A0-A7 select the unique column to be accessed,and mode register bit M3 is ignored. Table 1. Mode Register Definition. Rev1.3, Nov. 2005 CMS6416LAx-15Ex Burst Length Starting Column Address A0 2 0 1 A1 A0 00 4 01 10 11 A2 A1 A0 000 001 010 8 011 100 101 110 111 Full Page(y) Table 2. Burst Length Definition. n=A0-A8(location 0-y) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Bn, Bn+1, Bn+2…..Bn,… 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1 1-0 0-1 1-0 Order of Accesses within a Burst Type=Sequential Type=Interleaved Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Write Burst Mode When M9=0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9=1, the programmed burst length applies to READ bursts, but write accesses are single-location (non-burst) accesses. CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. If a READ command is registered at clock edge r, and the latency is q clocks, the data will be available by clock edge r + q. The DQs will start driving as a result of the clock edge one cycle earlier (r + q- 1), and provided that the relevant access times are met, the data will be valid by clock edge r + q. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Rev1.3, Nov. 2005 CMS6416LAx-15Ex T0 T1 T2 CLK Command Read tLZ NOP tOH Dout tAC DQ CAS Latency=1 T0 T1 T2 T3 CLK Command Read NOP tLZ NOP tOH Dout tAC DQ CAS Latency=2 T0 T1 T2 T3 T4 CLK Command Read NOP NOP tLZ NOP tOH Dout tAC DQ CAS Latency=3 Figure 2. CAS Latency Rev1.3, Nov. 2005 CMS6416LAx-15Ex EXTENDED MODE REGISTER The Extended Mode Register controls additional functions such as the Temperature Compensated Self Refresh (TCSR) Control, Partial Array Self Refresh (PASR), and Output Drive Strength.The Extended Mode Register is programmed via the Mode Register Set command (BA1=1, BA0=0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be programmed with M8 through M11 set to “0”. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time initiating any subsequent operation. Violating either of these requirements results in unspecified operation. PARTIAL ARRAY SELF REFRESH The Partial Array Self Refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are all banks (banks 0, 1, 2, and 3); two banks(banks 0 and 1 or 2 and 3 by M7); and one bank (bank 0 or 2 by M7). WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in PASR will be refreshed during SELF REFRESH. The data in banks 2 and 3 will be lost when the two bank option with M7=0 is used. Similarly the data will be lost in banks 1, 2, and 3 when the one bank option with M7=0 is used down . Driver Strength Control The driver strength feature allows one to reduce the drive strength of the I/O’s on the device during low frequency operation. This allows systems to reduce the noise associated with the I/O’s switching. AUTO TEMPERATURE COMPENSATED SELF REFRESH Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. In order to save power consumption, according to the temperature, Mobile-SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically. Table 4. Extended Mode Register Definition EM13BA1 1 EM12BA0 0 EM11A11 EM10A10 EM9A9 EM8A8 EM7A7 Bank Up/Down EM6A6 EM5A5 EM4A4 0 EM3A3 0 EM2A2 EM1A1 PASR EM0A0 All must be set to ‘0’ Driver Strength Rev1.3, Nov. 2005 CMS6416LAx-15Ex Table 5. Extended Mode Register Table[11.12.]. A7 0 A2 0 0 0 0 1 1 0 0 0 0 1 Note : 11. 12. EM13 and EM12 (BA1 and BA0) must be “1, 0” to select the Extended Mode Register(vs. the base Mode Register). RFU: Reserved for Future Use A1 0 0 1 1 X 0 0 1 1 X A0 0 1 0 1 X 0 1 0 1 X Self Refresh Coverage Four Banks Two Banks (Bank0 & 1) One Bank (Bank 0) RFU RFU Four Banks Two Banks (Bank2 & 3) One Bank (Bank2) RFU RFU A6 0 0 1 1 A5 0 1 0 1 Driver Strength 100% 75% 50% 25% Table 6. Commands[13.14.15.16.17.18.19.20.] . Name(Function) COMMAND INHIBIT(NOP) NO OPERATION(NOP) ACTIVE(Select bank and activate row)[15.] READ(Select bank and column, and start READ burst)[16.] WRITE(Select bank and column, and start WRITE burst)[16.] BURST TERMINATE PRECHARGE(Deactivate row in bank or banks)[17.] AUTO REFRESH or SELF REFRESH(Enter Self Refresh Mode) ) LOAD MODE REGISTER)[14.] Write Enable/Output Enable)[20.] Write Inhibit/Output High-Z) [20.] [18. 19.] CKE X H H H H H H H H H H L /CS H L L L L L L L L L /RAS X H L H H H L L L H /CAS X H H L L H H L L H /WE X H H H L L L H L L DQM X X X L/H L/H X X X X L H X ADDR X X Bank/ Row Bank/ Col Bank/ Col X Code X Opcode - DQ X X X X Valid Active X X X Active High Z Deep Power Down(Enter DPD Mode) X X Rev1.3, Nov. 2005 CMS6416LAx-15Ex Table 6. Commands[13.14.15.16.17.18.19.20.]. Note : 13. 14. 15. 16. 17. 18. 19. 20. CKE is HIGH for all commands shown except SELF REFRESH. A0-A10 define the op-code written to the mode register. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). LDQM controls DQ0-7 and UDQM controls DQ8-15. Commands Table 6. provides a reference of all the commands available with the state of the control signals for executing a specific command. COMMAND INHIBIT The COMMAND INHIBIT function effectively deselects the SDRAM by preventing new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. Operations already in progress are not affected. LOAD MODE REGISTER The mode register is loaded via inputs A0-A11, BA0, BA1. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. Table 1. and Table 4. provide the definition for the Mode Register and Extended Mode Register. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (/CS is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ACTIVE The ACTIVE command is used to activate a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. If auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. Rev1.3, Nov. 2005 WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst. If auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the active row in a particular bank or the active row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE AUTO PRECHARGE is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. AUTO PRECHARGE thus performs the same PRECHARGE command described above , without requiring an explicit command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE does not apply in the full page mode burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated. CMS6416LAx-15Ex AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command. The addressing is generated by the internal refresh controller. The address bits thus are a “Don’t Care” during an AUTO REFRESH command. The Fidelix 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms. DEEP POWER DOWN Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the device. Data will not be retained once the device enters DPD Mode. Full initialization is required when the device exits from DPD Mode. The DC value of DPD Mode can’t be zero due to transistor’s leakage current; a reverse PN diode leakage current which is called ‘Junction leakage current’ and a punch-through leakage current. [Figure29.30] SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM(without external clocking), even if the rest of the system is powered down. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (meet the clock specifications in the AC characteristics) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize he row refresh counter. Rev1.3, Nov. 2005 CMS6416LAx-15Ex Absolute Maximum Ratings Voltage on VDD/VDDQ Supply Relative to VSS …………………………………...-0.5V to + 2.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ……………………………….…. –0.5V to +2.6V Storage Temperature(plastic) ………….……. -55℃ to + 150℃ Power Dissipation ……………………….….………………1W *Stresses greater than those listed under “Maximum Ratings” may cause permanent damage to the device.This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Range Device CMS6416LAx-15ES CMS6416LAx-15EC CMS6416LAx-15EE CMS6416LAx-15EI Range Special Commercial Extended Industrial Ambient Temperature -10℃ to +60℃ 0℃ to +70℃ -25℃ to +85℃ -40℃ to +85℃ 1.65V to 1.95V 1.65V to VDD VDD VDDQ DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS[21,22] Parameter / Condition Supply Voltage I/O Supply Voltage Input High Voltage : Logic 1 All Inputs [23.] Input Low Voltage : Logic 0 All Inputs [23.] Data Output High Voltage : Logic 1 : All Inputs(-0.1mA) Data Output Low Voltage : Logic 0 : All Inputs(0.1mA) Input Leakage Current : Any Input 0V=VIN=VDD (All other pins not under test=0V) Output Leakage Current : DQs are disabled ; 0V= VOUT=VDDQ Symbol VDD VDDQ VIH VIL VOH VOL II lOZ -5 -5 Min 1.65 1.65 0.8* VDDQ -0.3 0.9* VDDQ 0.2 5 5 Max 1.95 1.95 VDDQ +0.3 0.3 Units V V V V V V ㎂ ㎂ Table 7. AC OPERATING CONDITIONS[21.22.23.24.25.26.] Parameter / Condition Input High Voltage : Logic 1 All Inputs Input Low Voltage : Logic 0 All Inputs Input and Output Measurement Reference Level Symbol VIH VIL Value 0.9* VDDQ 0.2 0.5*VDDQ Units V V V Rev1.3, Nov. 2005 CMS6416LAx-15Ex Table 8. IDD Specifications and Conditions [21.22.26.27.]. Parameter IDD1 IDD2p IDD2n IDD3p IDD3n IDD4 IDD5 IDD6 Description Operating Current : Active Mode ; Burst =1 ; Read or Write ; tRC= tRC(min); CAS Latency =3 [28.29.30.] Precharge Standby Current in Power Down Mode ; CKE=LOW ; All banks Idle Precharge Standby Current in non ower down Mode; CKE=HIGH ; All banks Idle Active Standby Current in Power Down Mode ; CS#=HIGH ; CKE=LOW ; All banks active after tRCD met ; No access in progress[28.30.31.] Active Standby Current in non Power Down Mode ; CS#=HIGH ; CKE=HIGH ; All banks active after tRCD met ; No access in progress[28.30.31.] Operating Current : Burst Mode ; Continuous Burst ; Read or Write ; All banks Active ; CAS Latency =3[28.29.30.] Auto Refresh Current : tRC=tRC(min) CAS Latency=3 ; CKE,CS#=HIGH[28.29.30.32.32.] Self Refresh Current : CKE