FAMP0417CAX-W70E

FMP0417CAx-W70E CMOS LPRAM FMP0417CAx-W70E Customer • Do not leave this document unattended. • All information contained within this document is covered by the non-discloser agreement. • Do not reproduce this document. • This document is Fidelix Co., Ltd. property and it can be required to be returned at any time. Fidelix Co., Ltd. 1 Revision 0.0 Feb. 2008 FMP0417CAx-W70E Document Title 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM CMOS LPRAM Revision History Revision No. 0.0 Generated new datasheet History Draft date Feb.21st, 2008 Remark Preliminary 2 Revision 0.0 Feb. 2008 FMP0417CAx-W70E CMOS LPRAM 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM FEATURES • Process Technology : Full CMOS • Organization : 256K x 16 • Power Supply Voltage : 2.7~3.3V • Three state output and TTL Compatible • Separated I/O power(VCCQ) & Core power(VCC) • Automatic power-down when deselected • Low Power & Page Modes FMP0417CA1 : support the PASR/DPD function FMP0417CA2 : support the Direct DPD function FMP0417CA4 : support the PASR/DPD/PAGE function FMP0417CA5 : support the Direct DPD/PAGE function • Page read/write operation by 16 words (FMP0417CA4, FMP0417CA5) • DPD mode by using MRS only (FMP0417CA1, FMP0417CA4) • Direct DPD mode when /ZZ goes low (FMP0417CA2, FMP0417CA5) PRODUCT FAMILY Operating Voltage (V) Speed Min. Typ. Max. Extended (-25~85’C) Typ. 70ns 1.5mA Power Dissipation ICC1 f = 1MHz Max. 3mA ICC2 f = fmax Typ. 15mA Max. 25mA ISB1 (CMOS Standby Current) Typ. 30uA Max. 70uA Product Family Operating Temperature FMP0417CAx-W70E 2.7 3.0 3.3 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER PIN DESCRIPTION Name /ZZ /CS /OE /WE A0~A17 I/O1~I/O16 Function Low Power Modes Chip Select Input Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Name VCC VCCQ VSS /UB /LB DNU Function Core Power I/O Power Ground Upper Byte(I/O9~16) Lower Byte(I/O 1~8) Do Not Use FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. VCC VSS Row Addresses Row select Memory array I/O1~I/O8 Data cont I/O Circuit Column select I/O9~I/O16 Data cont Data cont Column Addresses /CS /ZZ /OE /WE /UB /LB Control Logic 3 Revision 0.0 Feb. 2008 FMP0417CAx-W70E PRODUCT LIST Extended Temperature Products(-25~85’C) Part Name FMP0417CAx-W70E 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER CMOS LPRAM Function Wafer, 70ns, VCC=3.0V, VCCQ=3.0V FUNCTIONAL DESCRIPTION /CS H X1) H X1) L H H H X1) L L L H L X1) L H L 1. X means don’t care.(Must be low or high state) 2. In case of FMP0417CA2 & FMP0417CA5 product 3. In case of FMP0417CA1 & FMP0417CA4 product /ZZ H L L H H /OE X1) X1) X1) X1) H /WE X1) X1) X1) X1) H /LB X1) X1) X1) H L /UB X1) X1) X1) H X1) L H L L H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Direct DPD2) Low Power Modes3) Standby Active Active Active Active Active Active Active Active H H L ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT Vcc PD TSTG TA Ratings -0.2 to Vcc+0.3V -0.2 to 3.6 1.0 -65 to 150 -25 to 85 Unit V V W ’C ’C 1 . S t re s s e s gr e a t e r t h a n t h o s e l i st e d u n d e r “A b s olute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for Industrial periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS1) FMP0417CAx Item Supply voltage I/O operating voltage Ground Input high voltage Input low voltage Note : 1.TA=-25 to 85’C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 3. Undershoot : -1.0V in case of pulse width≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Symbol Min VCC VCCQ VSS VIH VIL 2.7 2.7 0 0.8VCCQ -0.23) Max 3.3 3.3 0 VCC+0.22) 0.2VCCQ Unit V V V V V 4 Revision 0.0 Feb. 2008 FMP0417CAx-W70E CAPACITANCE1) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. CMOS LPRAM (f=1MHz , TA=25’C) Symbol CIN CIO Test Condition VIN=0V VIO=0V Min Max 8 8 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 ISB0 ISB0a Low Power Modes ISB0b ISB0c Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH, VIN=VIL or VIH IOL=0.5mA IOH=-0.5mA /CS=VIH, /ZZ=VIH, Other inputs=VIH or VIL /CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC /ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD) /ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection /ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection /ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection 0.8VCCQ 0.3 70 10 55 60 70 15 25 0.2VCCQ mA V V mA uA uA uA uA uA VIN=VSS to VCC /CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH, VIN≤0.2V or VIN≥VCC-0.2V Test Conditions Min -1 -1 Typ 1.5 Max 1 1 3 Unit uA uA mA AC Input/Output Reference Waveform VCCQ Input1 VSS NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. VCCQ/2 2 Test Points VCCQ/23 Output AC Output Load Circuit Test Point DUT 50Ω VCCQ/2 30pF 5 Revision 0.0 Feb. 2008 FMP0417CAx-W70E AC CHARACTERISTICS(VCC=2.7V~3.3V, Extended product : TA=-25 to 85’C) Parameter List 70ns Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output /UB, /LB Access Time Chip Select to Low-Z Output Read /UB, /LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High- Z Output /UB, /LB Disable to High- Z Output Output Disable to High- Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write /UB, /LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Page Mode Cycle Time Page Page Mode Address Access Time Maximum Cycle Time /CS High Pulse Width1) tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW tPC tPAA tMRC tCP 10 5 0 0 0 5 70 60 0 60 60 50 0 0 20 0 5 25 10 5 5 5 20K 5 25 20k tRC tAA tCO tOE tBA tLZ 70 10 Max 20K 70 70 25 70 - CMOS LPRAM Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. 6 Revision 0.0 Feb. 2008 FMP0417CAx-W70E Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=VIH CMOS LPRAM Standby Mode State Machines Power On /CS=VIH Wait 200us Initial State /CS=VIH, /ZZ=VIH /CS=VIL, /ZZ=VIH /UB or/and /LB=VIL /CS=VIH, /ZZ=VIL Active Mode /CS=VIL /ZZ=VIH /CS=VIH (or/and /UB=/LB=VIH) /ZZ=VIH /CS=VIH /ZZ=VIL /CS=VIL /ZZ=VIH /CS=VIH, /ZZ=VIL Standby Mode Low Power Modes 1 (4M/2M/1M bits) Low Power Modes 2 (Data Invalid) /CS=VIH, /ZZ=VIL Standby Mode Characteristics Mode Standby Memory Cell Data Valid Invalid ¼ valid Low Power Modes ½ valid valid 60 (ISB0b) 70 (ISB0c) 0 0 Standby Current(uA) 70 (ISB1) 10 (ISB0) 55 (ISB0a) Wait Time(us) 0 200 0 7 Revision 0.0 Feb. 2008 FMP0417CAx-W70E READ CYCLE (1) Address tAA tOH CMOS LPRAM (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL) tRC Data Out Previous Data Valid Data Valid READ CYCLE (2) Address (/ZZ=/WE=VIH) tRC tAA tCO tOH /CS tHZ tBA /UB, /LB /OE tOLZ tBLZ tLZ tBHZ tOE tOHZ Data Out High-Z Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access) tMRC tRC tPC tPC tPC tPC tPC tPC tPC A0~A3 tAA A4~A17 tOH tCO /CS tHZ /UB, /LB /OE tBLZ tBA tBHZ tOE tOLZ tPAA tPAA tPAA tPAA tPAA tPAA tPAA tOHZ Data Valid Data Out High-Z tLZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec. 8 Revision 0.0 Feb. 2008 FMP0417CAx-W70E WRITE CYCLE (1) Address tCW(2) tWR(4) CMOS LPRAM tWC (/WE controlled, /ZZ=VIH) /CS tAW tBW tWP(1) /UB, /LB /WE tAS(3) tDW tDH High-Z tOW Data in Data Out High-Z tWHZ Data Valid Data Undefined WRITE CYCLE (2) Address (/CS controlled, /ZZ=VIH) tWC tAS(3) tCW(2) tAW tWR(4) /CS /UB, /LB /WE tDW tDH tBW tWP(1) Data in Data Out Data Valid High-Z High-Z WRITE CYCLE (3) Address (/UB, /LB controlled, /ZZ=VIH) tWC tCW(2) tWR(4) /CS tAW /UB, /LB tAS(3) tBW tWP(1) /WE tDW tDH Data in Data Out Data Valid High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 9 Revision 0.0 Feb. 2008 FMP0417CAx-W70E PAGE WRITE CYCLE (Address controlled, /ZZ=VIH) tMRC tWC tPC tPC tPC tPC tPC tPC CMOS LPRAM tPC A0~A3 A4~A17 /CS /UB, /LB tAS(3) /WE tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH Data in High-Z tWHZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid High-Z tOW Data Out Data Undefined 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 6. In case page address is over 3ns, write to the invalid address can occur. 10 Revision 0.0 Feb. 2008 FMP0417CAx-W70E LOW POWER MODES 1. Mode Register Set A17 ~ A5 A4 A3 A2 A1 CMOS LPRAM A0 0 ZZ Enable/Disable Array On/Off on /ZZ Half Selection Array Refresh Area /ZZ Enable/Disable A4 0 1 Type Deep Power Down Enable DPD Disable (Default) Array On/Off on /ZZ A3 0 1 Type Partial Array Refresh Mode (Default) Reduced Memory Size Mode Note: If the register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that /ZZ is driven low and there is no MRS update. When /ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power Down Disabled). Note: The RMS(Reduced Memory Size) mode is enabled after /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten. Half Selection (Top / Bottom) A2 0 1 Type Bottom (Default) Top Array Refresh Area A1 0 0 1 1 A0 0 1 0 1 Type Full Array (Default) RFU ½ Array ¼ Array 2. MRS Update tWC Address tAS(3) tCW(2) tWR(4) /CS tAW /UB, /LB tBW tWP(1) /WE tZZWE /ZZ Register Write Start Register Write Complete Register Update Complete The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates. 11 Revision 0.0 Feb. 2008 FMP0417CAx-W70E 3. Deep Power Down Mode Entry/Exit tWC CMOS LPRAM A4 tAS(3) tCW(2) tWR(4) /CS tAW /UB, /LB tBW tWP(1) /WE tZZWE tR tZZmin Next Cycle /ZZ Register Write(DPD) Deep Power down start Deep Power down exit Parameter tZZWE tR(Deep Power Down Mode only) tZZmin Description ZZ low to Write Enable Low Operation Recovery Time Low Power Mode Time Min 0 200 10 Max 1 - Units us us us 4. Address Information Partial Array Refresh Mode (A3=0, A4=1) A2 0 0 X 1 1 A1,A0 11 10 00 11 10 Refresh Section 1/4 1/2 Full 1/4 1/2 Address 00000h-0FFFFh 00000h-1FFFFh 00000h-3FFFFh 30000h-3FFFFh 20000h-3FFFFh Size 64Kbx16 128Kbx16 256Kbx16 64Kbx16 128Kbx16 Density 1Mb 2Mb 4Mb 1Mb 2Mb Reduced Memory Size Mode (A3=1, A4=1) A2 0 0 1 1 A1,A0 11 10 11 10 Refresh Section 1/4 1/2 1/4 1/2 Address 00000h-0FFFFh 00000h-1FFFFh 30000h-3FFFFh 20000h-3FFFFh Size 64Kbx16 128Kbx16 64Kbx16 128Kbx16 Density 1Mb 2Mb 1Mb 2Mb 12 Revision 0.0 Feb. 2008