FMP1216ACX

FMP1216ACx Document Title 8M x 16 bit Super Low Power and Low Voltage Full CMOS RAM 16 bit Super Low Power and Low Voltage Full CMOS RAM CMOS LPRAM Revision History Revision No. 0.0 0.1 Initial Draft Revise MRS Code for Array Refresh Area History Draft date Jul. 20th, 2010 Oct. 12th, 2010 Remark Preliminary Preliminary 1 Revision 0.1 Oct. 2010 FMP1216ACx CMOS LPRAM 8M x 16 bit Super Low Power and Low Voltage Full CMOS RAM FEATURES • Process Technology : Full CMOS • Organization : 8M x 16 • Power Supply Voltage : 1.7~1.95V • Three state output and TTL Compatible • Separated I/O power(VCCQ) & Core power(VCC) • Operating Temperature Ranges: Special (-10’C to +60’C) Commercial (0’C to +70’C) Extended (-25’C to +85’C) Industrial (-40’C to +85’C) •Package Type : 54-FBGA-6.00x8.00 mm2 FMP1216ACx-HxxX : Pb-Free & Halogen Free • Low Power & Page Modes FMP1216AC1 : support the PASR/DPD function FMP1216AC2 : support the Direct DPD function FMP1216AC4 : support the PASR/DPD/PAGE function FMP1216AC5 : support the Direct DPD/PAGE function • Page read/write operation by 16 words (FMP1216AC4, FMP1216AC5) • DPD mode by using MRS only mode by using MRS only (FMP1216AC1, FMP1216AC4) • Direct DPD mode when /ZZ goes low (FMP1216AC2, FMP1216AC5) PRODUCT FAMILY Operating Voltage (V) Product Family Min. Typ. Max. FMP1216ACx-H70E 1.7 1.8 1.95 70ns Speed Typ. 1.5mA Power Dissipation ICC1 f = 1MHz Max. 3mA ICC2 f = fmax Typ. 12mA Max. 25mA ISB1 (CMOS Standby Current) Typ. 180uA Max. 200uA 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. H=FBGA(Pb-Free & Halogen Free), W=WAFER 3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) PIN DESCRIPTION Name /ZZ /CS /OE /WE A0~A22 I/O1~I/O16 Function Low Power Modes Chip Select Input Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Inputs/Outputs Name VCC VCCQ VSS /UB /LB NC Function Core Power I/O Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) No Connect Connect FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. VCC VSS Memory array Row Addresses Row select I/O1 ~ I/O8 Data cont I/O Circuit Column select I/O9 ~ I/O16 Data cont Data cont Column Addresses /CS /OE /WE /UB /LB /ZZ Control Logic 2 Revision 0.1 Oct. 2010 FMP1216ACx PRODUCT LIST Part Name Name FMP1216ACx-H70E 1. H=FBGA(Pb-Free & Halogen Free), W=WAFER 2. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) CMOS LPRAM Function 70ns, VCC=1.8V, VCCQ=1.8V FUNCTIONAL DESCRIPTION /CS H X1) H L /ZZ H L L H /OE X1) X1) X1) H /WE X1) X1) X1) H /LB X1) X1) X1) X1) H L H L H L H X1) L L H L 1. X means don’t care.(Must be low or high state) 2. In case of FMP1216AC2 & FMP1216AC5 product FMP1216AC2 FMP1216AC5 3. In case of FMP1216AC1 & FMP1216AC4 product /UB X1) X1) X1) X1) H H L L H H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z Din High-Z Din I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Write-abort4) Lower Byte Write Upper Byte Write Word Write Power Standby Direct DPD2) Low Power Modes3) Active Active Active Active Active Active Active Active Active L H ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Symbol VIN, VOUT Vcc PD TSTG Ratings -0.5 to Vcc+0.3V -0.2 to 2.45 1.0 -55 to 150 Unit V V W ’C 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS FMP1216ACx Item Supply voltage I/O operating voltage (VCCQ ≤ VCC) Ground Input high voltage Input low voltage Note : 1. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 2. Undershoot : -1.0V in case of pulse width≤20ns. 3. Overshoot and undershoot are sampled, not 100% tested. Symbol Min VCC VCCQ VSS VIH VIL 1.7 1.7 0 0.8VCCQ -0.22) Max 1.95 1.95 0 VCC+0.21) 0.2VCCQ Unit V V V V V 3 Revision 0.1 Oct. 2010 FMP1216ACx CAPACITANCE1) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. CMOS LPRAM Symbol CIN CIO Test Condition VIN=0V VIO=0V Min Max 8 8 Unit pF pF (f=1MHz , TA=25’C) DC AND OPERATING CHARACTERISTICS Item Input leakage current leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 ISB0 Low Power Modes ISB0a ISB0b ISB0c VIN=VSS to VCC /CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH, VIN≤0.2V or VIN≥VCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH, VIN=VIL or VIH IOL=0.5mA IOH=-0.5mA /CS=VIH, /ZZ=VIH, Other inputs=VIH or VIL /ZZ VIL /CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC /ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD) /ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection /ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection /ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection 0.8VCCQ 0.3 200 10 155 170 200 Test Conditions Min -1 -1 Typ Max 1 1 3 25 0.2VCCQ Unit uA uA mA mA V V mA uA uA uA uA uA Operating Range Range Device FMP1216ACx-XxxS FMP1216ACx-XxxC FMP1216ACx-XxxE FMP1216ACx-XxxI Range Special Commercial Extended Industrial Ambient Temperature -10℃ to +60℃ 0℃ to +70℃ 1.7V to 1.95V -25℃ to +85℃ -40℃ to +85℃ 1.7V to VCC VCC VCCQ AC Input/Output Reference Waveform VCCQ Input1 VSS NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. Inp timing begins at VCCQ/2 3. Output timing ends at VCCQ/2. VCCQ/2 2 Test Points VCCQ/23 Output AC Output Load Circuit Test Point DUT 50Ω 30pF VCCQ/2 4 Revision 0.1 Oct. 2010 FMP1216ACx AC CHARACTERISTICS(VCC=1.7V~1.95V) CHARACTERISTICS Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output /UB, /LB Access Time Read Chip Select to Low-Z Output /UB, /LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High- Z Output /UB, /LB Disable to High- Z Output Output Disable to High- Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write /UB, /LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time Ti End Write to Output Low-Z Page Mode Cycle Time Page Page Mode Address Access Time Maximum Cycle Time /CS High Pulse Width 1. /CS High Pulse W idth is defined by /CS. /CS High Pulse Width is defined by /CS CMOS LPRAM 70ns Max 20k 70 70 25 25 5 5 5 20k 5 25 20k - Units tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW tPC tPAA tMRC tCP 70 10 10 5 0 0 0 5 70 60 0 60 60 50 0 0 20 0 5 25 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 Revision 0.1 Oct. 2010 FMP1216ACx Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 150us with /CS=/ZZ=VIH CMOS LPRAM Standby Mode State machines Power On /CS=/ZZ=VIH Wait 150us 150us Initial State State /CS=VIH, /ZZ=VIH /CS=VIL, /ZZ=VIH Active Mode /CS=VIH, /ZZ=VIL /CS=VIL /ZZ=VIH /CS=VIH /ZZ=VIH /CS=VIH /ZZ=VIL /CS=VIL /ZZ=VIH Standby Mode /CS=VIH, /ZZ=VIL Low Power Modes 1 (128M/64M/32M bits) Low Power Modes 2 (Data Invalid) /CS=VIH, /ZZ=VIL Standby Mode Characteristics Mode Standby Memory Cell Data Valid Invalid ¼ valid Low Power Modes ½ valid valid 170 (ISB0b) 200 (ISB0c) 0 0 Standby Current(uA) 200 (ISB1) 10 (ISB0) 155 (ISB0a) Wait Time(us) 0 150 0 6 Revision 0.1 Oct. 2010 FMP1216ACx READ CYCLE (1) Address tOH tAA CMOS LPRAM tRC (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL) Data Out Previous Data Valid Data Valid READ CYCLE (2) Address (/ZZ=/WE=VIH) tRC tAA tCO tOH /CS tHZ tBA tBHZ /UB, /LB /OE tOLZ tBLZ tLZ tOE tOHZ Data Out High-Z Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. ti th tRC(tWC) 20 PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access) tMRC tRC tPC tPC tPC tPC tPC tPC tPC A0~A3 tAA A4~A22 tOH tCO /CS tHZ /UB, /LB /OE tBLZ tBA tBHZ tOE tOLZ tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid Data Valid tOHZ Data Out High-Z tLZ 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. de 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec. 7 Revision 0.1 Oct. 2010 FMP1216ACx WRITE CYCLE (1) Address tCW(2) tWR(4) CMOS LPRAM tWC (/WE controlled, /ZZ=VIH) /CS tAW tBW tWP(1) /UB, /LB /WE tAS(3) tDW tDH High-Z tOW Data in Data Out High-Z tWHZ Data Valid Data Undefined WRITE CYCLE (2) Address (/CS controlled, /ZZ=/WE=VIH) tWC tAS(3) tCW(2) tAW tWR(4) /CS /UB, /LB /WE tDW tDH tBW tWP(1) Data in Data Out High-Z Data Valid High-Z WRITE CYCLE (3) Address (/UB, /LB controlled, /ZZ=VIH) tWC tCW(2) tWR(4) /CS tAW /UB, /LB tAS(3) tBW tWP(1) /WE tDW tDH Data in Data Out Data Valid High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 8 Revision 0.1 Oct. 2010 FMP1216ACx LOW POWER MODES 1. Mode Register Set A22 ~ A5 A4 A3 A2 A1 CMOS LPRAM A0 0 ZZ Enable/Disable Array On/Off on /ZZ Half Selection Array Refresh Area /ZZ Enable/Disable A4 0 1 Type Deep Power Down Enable DPD Disable (Default) Array On/Off on /ZZ A3 0 1 Type Partial Array Refresh Mode (Default) Reduced Memory Size Mode Note: If the register is written to enable the Deep If th th Power Down, the part will go into Deep Power Down during the following time that /ZZ is driven low and there is no MRS update. When /ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power Down Disabled). Note: The RMS(Reduced Memory Size) mode is enabled after Th RMS(R Si /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten. Half Selection (Top / Bottom) A2 0 1 Type Bottom (Default) Top Array Refresh Area A1 0 0 1 1 A0 0 1 0 1 Type Full Array (Default) RFU ½ Array ¼ Array 2. MRS Update tWC Address tAS(3) tCW(2) tWR(4) /CS tAW /UB, /LB tBW tWP(1) /WE tZZWE /ZZ Register Write Start Register Write Complete Register Update Complete The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates. 9 Revision 0.1 Oct. 2010 FMP1216ACx 3. Deep Power Down Mode Entry/Exit tWC CMOS LPRAM A4 tAS(3) tCW(2) tWR(4) /CS tAW /UB, /LB tBW tWP(1) /WE tZZWE tR tZZmin Next Cycle /ZZ Register Write(DPD) Write(DPD) Deep Power down start down start Deep Power down exit down exit Parameter tZZWE tR(Deep Power Down Mode only) tZZmin Description ZZ low to Write Enable Low Operation Recovery Time Low Power Mode Time Min 0 150 10 Max 1 - Units us us us 4. Address Information Partial Array Refresh Mode (A3=0, A4=1) A2 0 0 X 1 1 A1,A0 11 10 00 11 10 Refresh Section 1/4 1/2 Full 1/4 1/2 Address 000000h-1FFFFFh 000000h-3FFFFFh 000000h-7FFFFFh 600000h-7FFFFFh 400000h-7FFFFFh Size 2Mbx16 4Mbx16 8Mbx16 2Mbx16 4Mbx16 Density 32Mb 64Mb 128Mb 32Mb 64Mb Reduced Memory Size Mode (A3=1, A4=1) A2 0 0 1 1 A1,A0 11 10 11 10 Refresh Section 1/4 1/2 1/4 1/2 Address 000000h-1FFFFFh 000000h-3FFFFFh 600000h-7FFFFFh 400000h-7FFFFFh Size 2Mbx16 4Mbx16 2Mbx16 4Mbx16 Density 32Mb 64Mb 32Mb 64Mb 10 Revision 0.1 Oct. 2010 FMP1216ACx 54Ball FBGA Ball Assignment FBGA Ball Assignment 1 2 3 4 5 6 CMOS LPRAM A LB# OE# A0 A1 A2 /ZZ B I/O9 UB# A3 A4 CE# I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSSQ I/O12 A17 A7 I/O4 VCC E VCCQ I/O13 A21 A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 A19 A12 A13 WE# I/O8 H A18 A8 A9 A10 A11 A20 J NC NC NC A22 NC NC 54-FBGA : Top View(Ball Down) 11 Revision 0.1 Oct. 2010 FMP1216ACx PACKAGE DIMENSION 54 BALL FINE PITCH BGA(0.75mm ball pitch) BALL FINE PITCH BGA Top View Bottom View B B B1 CMOS LPRAM Unit : millimeters A1 INDEX MARK 0.05 0.05 6 A B 5 4 3 2 1 #A1 C D E F C1/2 G H J C1 B/2 Detail A 0.25/Typ. A Y NOTES. 1. Bump counts : 54(9row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical Typ Typical 5. Y is coplanarity : 0.08(Max) Side View D E1 E 0.30 E2 C C A B B1 C C1 D E E1 E2 Y Min 5.90 7.90 0.30 0.20 - Typ 0.75 6.00 3.75 8.00 6.00 0.35 0.8 0.7 0.25 - Max 6.10 8.10 0.40 1.00 0.30 0.08 12 0.7/Typ. Revision 0.1 Oct. 2010 C