FMP1617CA7-FXXX

FMP1617CA0(7) Document Title 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM CMOS LPRAM Revision History Revision No. 0.0 0.1 Initial Draft Revised P/N according to the new P/N system History Draft date Apr.19th, 2006 Jun.01st , 2006 Remark Preliminary Preliminary 1 Revision 0.1 Jun. 2006 FMP1617CA0(7) FEATURES • Process Technology : Full CMOS • Organization : 1M x 16 • Power Supply Voltage : 2.7~3.3V • Dual CS & Page Modes FMP1617CA0 : Dual CS FMP1617CA7 : Page mode with Dual CS CMOS LPRAM 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM • Three state output and TTL Compatible • Package Type : 48-FBGA-6.00x8.00 mm2 FMP1617CA0(7)-FxxX : Normal FMP1617CA0(7)-GxxX : Pb-Free FMP1617CA0(7)-HxxX : Pb-Free & Halogen Free • Operating Temperature Ranges: Special (-10’C to +60’C) Commercial (0’C to +70’C) Extended (-25’C to +85’C) Industrial (-40’C to +85’C) • Separated I/O power(VCCQ) & Core Power(VCC) • Easy memory expansion with /CS1, CS2, and /OE features • Automatic power-down when deselected PRODUCT FAMILY Operating Voltage (V) Product Family Min. Typ. Max. FMP1617CA0(7)-G60E FMP1617CA0(7)-G70E 60ns 70ns Speed Typ. 1.5mA Power Dissipation ICC1 f = 1MHz Max. 3mA ICC2 f = fmax Typ. 15mA 12mA Max. 20mA ISB1 (CMOS Standby Current) Typ. 70uA Max. 100uA 2.7 3.0 3.3 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER 3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) PIN DESCRIPTION 1 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Precharge circuit. A B C D E F G H /LB I/O9 /OE /UB A0 A3 A1 A4 A2 /CS1 CS2 I/O1 Clk gen. VCC VSS Memory array I/O10 VSS I/O11 I/O12 A5 A17 A6 A7 A16 I/O2 I/O4 I/O5 I/O3 VCC VSS Row Addresses Row select VCCQ I/O15 I/O16 A18 I/O13 I/O14 A19 A8 DNU A14 A12 A9 A15 A13 A10 I/O6 I/O7 I/O8 I/O1~I/O8 Data cont I/O Circuit Column select WE A11 NC I/O9~I/O16 Data cont 48-FBGA : Top View(Ball Down) Data cont Column Addresses Name CS2 /CS1 /OE /WE A0~A19 I/O1~I/O16 Function Chip Select Input Chip Select Input Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Name VCC VCCQ VSS /UB /LB DNU Function Core Power I/O Power Ground Upper Byte(I/O9~16) Lower Byte(I/O 1~8) Do Not Use /CS1 CS2 /OE /WE /UB /LB Control Logic 2 Revision 0.1 Jun. 2006 FMP1617CA0(7) PRODUCT LIST Part Name FMP1617CA0(7)-G60E FMP1617CA0(7)-G70E Function CMOS LPRAM 48-FBGA, 60ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) 48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER 2. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) FUNCTIONAL DESCRIPTION /CS1 H X1) X1) L CS2 H L H H H /OE X1) X1) X1) H H /WE X1) X1) X1) H H /LB X1) X1) H L X1) L L L H X1) L H H L L H L 1. X means don’t care.(Must be low or high state) /UB X1) X1) H X1) L H L L H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Symbol VIN, VOUT Vcc PD TSTG Ratings -0.2 to Vcc+0.3V -0.2 to 3.6 1.0 -65 to 150 Unit V V W ’C 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS Item Supply voltage I/O operating voltage (VCCQ ≤ VCC) Ground Input high voltage Symbol VCC VCCQ VSS VIH FMP1617CA Min 2.7 2.7 0 0.8VCCQ -0.22) Max 3.3 3.3 0 VCC+0.211 ) Min 2.7 2.25 0 0.8VCCQ -0.22) Max 3.3 2.75 0 VCC+0.21) 0.2VCCQ Min 2.7 1.65 0 0.8VCCQ -0.22) Max 3.3 1.95 0 VCC+0.21) 0.2VCCQ Unit V V V V V Input low voltage VIL Note : 1. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 2. Undershoot : -1.0V in case of pulse width≤20ns. 3. Overshoot and undershoot are sampled, not 100% tested. 0.2VCCQ 3 Revision 0.1 Jun. 2006 FMP1617CA0(7) CAPACITANCE1) (f=1MHz , TA=25’C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. CMOS LPRAM Symbol CIN CIO Test Condition VIN=0V VIO=0V Min Max 8 8 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 VIN=VSS to VCC /CS=VIH, CS2=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, CS2=VIH, VIN≤0.2V or VIN≥VCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, CS2=VIH, VIN=VIL or VIH IOL=0.5mA IOH=-0.5mA /CS=VIH, CS2=VIH, Other inputs=VIH or VIL /CS≥VCC-0.2V, CS2≤0.2V, Other inputs=0~VCC 0.8VCCQ 0.3 100 Test Conditions Min -1 -1 Typ Max 1 1 3 20 0.2VCCQ Unit uA uA mA mA V V mA uA Operating Range Device FMP1617CA0(7)-XxxS FMP1617CA0(7)-XxxC FMP1617CA0(7)-XxxE FMP1617CA0(7)-XxxI Range Special Commercial Extended Industrial Ambient Temperature -10℃ to +60℃ 0℃ to +70℃ 2.7V to 3.3V -25℃ to +85℃ -40℃ to +85℃ 1.65V to Vcc VDD VDDQ 4 Revision 0.1 Jun. 2006 FMP1617CA0(7) AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level : 0.2 to VCC-0.2V Input rising and falling time : 5ns Input and output reference voltage : 0.5*VCCQ Output load(see right) : CL=30pF+1TTL 30pf CMOS LPRAM 1TTL AC CHARACTERISTICS(VCC=2.7V~3.3V) Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output /UB, /LB Access Time Read Chip Select to Low-Z Output /UB, /LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High- Z Output /UB, /LB Disable to High- Z Output Output Disable to High- Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write /UB, /LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Page Mode Cycle Time Page Page Mode Address Access Time Maximum Cycle Time /CS High Pulse Width tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW tPC tPAA tMRC tCP 60 10 10 5 0 0 0 5 60 50 0 50 50 50 0 0 20 0 5 20 10 60ns Max 20k 60 60 25 60 5 5 5 20k 5 20 20k Min 70 10 10 5 0 0 0 5 70 60 0 60 60 50 0 0 20 0 5 25 10 70ns Max 20k 70 70 25 70 5 5 5 20k 5 25 20k ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. 5 Revision 0.1 Jun. 2006 FMP1617CA0(7) Power Up Sequence 1. Apply Power. 2. Maintain stable power for a minimum of 200us with /CS1=VIH and CS2=VIH. CMOS LPRAM Timing Waveform of Power Up Min. 200us VCC Vcc(Min ) /CS1 CS2 Power up mode Normal Operation 6 Revision 0.1 Jun. 2006 FMP1617CA0(7) READ CYCLE (1) Address tOH tAA CMOS LPRAM tRC (Address controlled,/CS1=/OE=VIL, CS2=/WE=VIH, /UB or/and /LB=VIL) Data Out Previous Data Valid Data Valid READ CYCLE (2) Address (CS2=/WE=VIH) tRC tAA tCO tOH /CS1 CS2 tHZ /UB, /LB /OE tOLZ tBLZ tLZ tBA tBHZ tOE tOHZ Data Out High-Z Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. PAGE READ CYCLE (CS2=/WE=VIH, 16 words access) tMRC tRC tPC tPC tPC tPC tPC tPC tPC A0~A3 tAA A4~A20 tOH /CS1 CS2 tCO tHZ tBA /UB, /LB tBHZ /OE tBLZ tOE tOLZ tLZ tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid Data Valid tOHZ Data Out High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec. 7 Revision 0.1 Jun. 2006 FMP1617CA0(7) WRITE CYCLE (1) Address tCW(2) CMOS LPRAM tWC (/WE controlled) /CS1 CS2 /UB, /LB /WE tAS(3) tDW tAW tBW tWP(1) tWR(4) tDH High-Z tOW Data in Data Out High-Z tWHZ Data Valid Data Undefined WRITE CYCLE (2) Address (/CS1 controlled) tWC tAS(3) tCW(2) tWR(4) /CS1 CS2 tAW /UB, /LB /WE Data in Data Out High-Z tBW tWP(1) tDW tDH Data Valid High-Z WRITE CYCLE (3) Address (CS2 controlled) tWC tCW(2) tWR(4) /CS1 tAS(3) CS2 tAW /UB, /LB /WE Data in Data Out tBW tWP(1) tDW tDH Data Valid High-Z High-Z 8 Revision 0.1 Jun. 2006 FMP1617CA0(7) WRITE CYCLE (4) Address tCW(2) tWR(4) CMOS LPRAM tWC (/UB, /LB controlled) /CS1 CS2 tAW /UB, /LB tAS(3) tBW tWP(1) /WE Data in Data Out tDW tDH Data Valid High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. PAGE WRITE CYCLE (Address controlled, CS2=VIH) tMRC tWC tPC tPC tPC tPC tPC tPC tPC A0~A3 A4~A20 /CS1 CS2 /UB, /LB tAS(3) /WE tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH Data in High-Z tWHZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid High-Z tOW Data Out Data Undefined 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 6. In case page address is over 3ns, write to the invalid address can occur. 9 Revision 0.1 Jun. 2006 FMP1617CA0(7) PACKAGE DIMENSION 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View B B B1 CMOS LPRAM Unit : millimeters A1 INDEX MARK 0.05 0.05 6 A B 5 4 3 2 1 #A1 C D C1 E C1/2 F G H B/2 Detail A 0.25/Typ. A Y Max 6.10 8.10 0.40 1.20 0.30 0.08 NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) Side View E2 D E1 E 0.30 C C A B B1 C C1 D E E1 E2 Y Min 5.90 7.90 0.30 0.20 - Typ 0.75 6.00 3.75 8.00 5.25 0.35 1.10 0.85 0.25 - 0.85/Typ. 10 Revision 0.1 Jun. 2006 C