FTLX1341E2

FTLX1341E2

  • 厂商:

    FINISAR

  • 封装:

    -

  • 描述:

    TXRX OPT SFP+ 10 GB/S 220M

  • 数据手册
  • 价格&库存
FTLX1341E2 数据手册
Product Specification RoHS-6 Compliant 10GBASE-LRM X2 Transponder FTLX1341E2 PRODUCT FEATURES Hot pluggable X2 MSA form factor Total power consumption: 4.0 W maximum RoHS-6 compliant (lead-free) Temperature range 0°C to 70°C Transmission distance up to 220m* Uncooled 1310 nm directly modulated Fabry-Perot (FP) laser Built In Advanced Electronic Dispersion Compensation (EDC) SC connector, multimode fiber Full duplex transmission mode Digital Optics Monitoring (DOM) Power supply: +5.0 V, +3.3 V Adaptable Power Supply (APS: +1.2 V) XAUI electrical interface - 4 x 3.125 Gb/s Ethernet Management and control via MDIO 2-wire bus 70-pin connector Separated signal/chassis ground Mid Pak module variance for front panel mounting De-latch mechanism with low extraction force APPLICATIONS IEEE 802.3aq-2006 10 Gb/s Ethernet transmission on legacy multimode fiber. The Finisar FTLX1341E2 transponder incorporates Electronic Dispersion Compensation (EDC) which provides correction for the severe modal dispersion that may occur during propagation through links up to 220m on legacy installed FDDI multimode fiber. The EDC device incorporates a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). The EDC also contains sophisticated clock recovery architecture for extracting a robust clock from extremely distorted signals. PRODUCT SELECTION FTLX1341E2 * Maximum reach as defined by IEEE. Longer reach possible depending upon link implementation. © Finisar Corporation – October 2008 Rev B Page 1 FTLX1341E2 Product Specification – October 2008 I. Pin Description Signal Name Level Management and Monitoring Ports MDIO Open Drain (output) 1.2V CMOS (input) MDC 1.2 V CMOS PRTAD4 1.2 V CMOS PRTAD3 1.2 V CMOS PRTAD2 1.2 V CMOS PRTAD1 1.2 V CMOS PRTAD0 1.2 V CMOS LASI Open Drain I/O I/O Pin No. 17 Description Management Data I/O. Requires external 10 - 22 kΩ pull-up to the APS on host. Management Data Clock Input Port Address Input bit 4 Port Address Input bit 3 Port Address Input bit 2 Port Address Input bit 1 Port Address Input bit 0 Link Alarm Status Interrupt Output. Open Drain Compatible Output with 10 - 20 kΩ pull-up on host. Logic high = Normal Operation Logic low = Status Flag Triggered Reset Input. Open Drain Compatible Input with 22 kΩ pull-up to APS internal to transponder. Logic high = Normal Operation Logic low = RESET Vendor Specific Pins. Leave unconnected when not used. TX ON/OFF Input. Open Drain Compatible Input with 22 kΩ pull-up to APS internal to transponder. Logic high = Transmitter On Logic low = Transmitter Off Module Detect. Pulled low inside transponder through a 1 kΩ resistor to Ground Reserved For Future Use Reserved For Future Use Module XAUI Input Lane 3– Module XAUI Input Lane 3+ Module XAUI Input Lane 2– Module XAUI Input Lane 2+ Module XAUI Input Lane 1– Module XAUI Input Lane 1+ Module XAUI Input Lane 0– Module XAUI Input Lane 0+ I 1 I I I I O 18 19 20 21 22 23 9 RESET 1.2 V CMOS I 10 Vendor Specific TX ON/OFF 1.2 V CMOS I 11,15,16,24 12 MOD DETECT O 14 Transmit Functions Reserved Reserved TX LANE 3– AC-coupled, TX LANE 3+ Internally biased differential TX LANE 2– XAUI TX LANE 2+ TX LANE 1– TX LANE 1+ TX LANE 0– TX LANE 0+ I I I I I I I I I I 68 67 65 64 62 61 59 58 56 55 © Finisar Corporation – October 2008 Rev B Page 2 FTLX1341E2 Product Specification – October 2008 Receive Functions Reserved Reserved RX LANE 0+ AC-coupled, RX LANE 0– Internally biased differential RX LANE 1+ XAUI RX LANE 1– RX LANE 2+ RX LANE 2– RX LANE 3+ RX LANE 3– DC Power GND 0 V DC O O O O O O O O O O 38 39 41 42 44 45 47 48 50 51 1, 2, 3, 33, 34, 35, 36, 37, 40, 43, 46, 49, 52, 53, 54, 57, 60, 63, 66, 69, 70 7, 8, 28, 29 27 25 Reserved For Future Use Reserved For Future Use Module XAUI Output Lane 0+ Module XAUI Output Lane 0– Module XAUI Output Lane 1+ Module XAUI Output Lane 1– Module XAUI Output Lane 2+ Module XAUI Output Lane 2– Module XAUI Output Lane 3+ Module XAUI Output Lane 3– Ground connection for signal ground on the module APS APS SENSE APS SET 3.3 V 5.0 V Reserved Reserved +1.2 V +1.2 V +3.3 V DC +5.0 V DC 5, 6, 30, 31 4, 32 26 13 Input from Adaptive Power Supply APS Sense Output. Connected to the APS input inside transponder. Feedback input from APS. Connected to GND through a 1180Ω resistor inside the transponder. DC Power Input, +3.3 V DC, Nominal DC Power Input, +5.0 V DC, Nominal Reserved for APD. Reserved. © Finisar Corporation – October 2008 Rev B Page 3 FTLX1341E2 Product Specification – October 2008 Electrical Pad Layout Figure 1- X2 Transponder Electrical Pad Layout II. Absolute Maximum Ratings Parameter Storage Temperature1) Supply Voltage +5.0 V Supply Voltage +3.3 V Supply Voltage APS Static Discharge Voltage, All Pins2) Average Receive Optical Power Notes: 1) Non-condensing 2) HBM Symbol TS V5 V3 Vaps S Td RxP max Limit Values min. max. -40 85 0 6 0 4 0 1.5 500 1.5 Unit °C V V V V dBm Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. © Finisar Corporation – October 2008 Rev B Page 4 FTLX1341E2 Product Specification – October 2008 III. Electrical Characteristics Recommended Operating Conditions Parameter Operating Case Temperature1) Transponder Total Power Consumption Supply Voltage +5.0 V Supply Current +5.0 V Supply Voltage +3.3 V Supply Current +3.3 V Supply Voltage APS Supply Current APS 1) Symbol TC P VCC5 ICC5 VCC3 ICC3 VCC aps ICC aps min. 0 4.75 3.14 1.152 Values typ. max. 70 4 5.25 10 3.47 830 1.248 850 Unit °C W V mA V mA V mA 5.0 3.3 1.2 Measured at reference thermal location, see Figure 3. See also Environmental Performance. Electrical DC Characteristics (VCC5 = 4.75 V to 5.25 V, VCC3 = 3.14 V to 3.47 V, VCC aps = 1.152 V to 1.248 V, TC = 0°C to 70°C) Values typ. Parameter Symbol min. 1.2 V CMOS (1.8 V CMOS Compatible1)) I/O DC Characteristics (PRTAD; LASI; RESET; TX_ONOFF) External Pull-up Resistor for Open Drain Rpullup 10 Output High Voltage2) Voh 1 Output Low Voltage2) Vol Input High Voltage Vih 0.84 Input Low Voltage Vil Input Pull-down Current3) Ipd 20 MDIO I/O Characteristics (MDIO; MDC) MDIO Data Hold Time MDIO Data Setup Time Delay from MDC Rising Edge to MDIO Data Change MDC Clock Rate Output Low Voltage5) Output Low Current Input High Voltage Input Low Voltage Pull-up Supply Voltage Input Capacitance Load Capacitance External Pull-up Resistance Power-On Reset AC Characteristics Power-On Reset and TX_ONOFF Characteristics 1) 2) 3) 4) 5) max. 22 0.15 1.5 0.36 120 Unit kΩ V V V V µA ns ns ns MHz V mA V V V pF pF Ω tHOLD tSU tDELAY ƒMAX VOL IOL VIH VIL VPU CIN CLOAD RLOAD 10 10 300 –0.3 0.84 –0.3 0.84 200 1.2 1.2 2.5 0.2 20 1.5 0.36 1.5 10 470 According to XENPAK MSA Issue 3.0 Draft 4.0, 2002-9-9 For 1.8 V CMOS Voh = 1.65 V min., Vol = 0.15 V max., Vih = 1.17 V min., Vil = 0.63 V max. Rpull-up = 10 kΩ to 1.8 V. Vin = 1.8 V. AC coupled. IOL = 100 µA. © Finisar Corporation – October 2008 Rev B Page 5 FTLX1341E2 Product Specification – October 2008 Electrical AC Characteristics (VCC5 = 4.75 V to 5.25 V, VCC3 = 3.14 V to 3.47 V, VCC aps = 1.152 V to 1.248 V, TC = 0°C to 70°C) Values typ. 3.125 –100 80 10 100 100 120 75 0.65 ppm Ω dB ps UIp-p Gbit/s 3.125 –100 100 According to IEEE 802.3ae 80 100 120 10 ppm Ω dB Parameter Symbol XAUI Input AC Characteristics (TXLANE[0..3]) Baud Rate RXAUIIN Ethernet Baud Rate Tolerance RTOLXAUI Differential Input Impedance ZINXAUI Differential Return Loss1) |S11| Input Differential Skew2) tSKEWIN Jitter Amplitude Tolerance3) JXAUITOL XAUI Output AC Characteristics (RXLANE[0..3]) Baud Rate RXAUIOUT Ethernet Baud Rate Variation RXAUIVAR XAUI Eye Mask (far-end) Output Differential Impedance ZOUTXAUI Differential Output Return Loss1) |S22| 1) 2) 3) min. max. Unit Gbit/s 100 MHz to 2.5 GHz. At crossing point. Per IEEE Std 802.3ae. IV. Optical Characteristics RMS Spectral Width Mask Figure 2-Transmitter Maximum RMS Spectral Width © Finisar Corporation – October 2008 Rev B Page 6 FTLX1341E2 Product Specification – October 2008 Optical Specifications Parameter Transmitter Optical Modulation Amplitude (OMA) Average Launch Power Peak Launch Power Optical Wavelength Symbol POMA PAVE PMAX λ λrms @1260nm λrms @ 1260nm1300nm λrms @ 1300nm1355nm ER TWDP POFF Txj RIN20OMA
FTLX1341E2 价格&库存

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