F16267R

F16267 8-bit Microcontroller with CIR Receiver Release Date: Feb, 2009 Version: 0.20P Fintek Feature Integration Technology Inc. F16267 F16267 Datasheet Revision History Version 0.10P Date Dec, 2007 Page Preliminary version 7 Revision History Add the lost description of pin 15 Add current consumption description Add all the register descriptions Add internal 12Mhz clock description Revise register address Revise register description Register address: 7.38-7.53 Correct descriptions of Alarm Register 0x0087-0x008B Remove the redundant register 0x8F RAM Data Register –Index 00B090h~00EFCFh (Total 64 Bytes) 0.11P Mar, 2008 10 13 11 0.12P 0.13P 0.14P Apr, 2008 13-23 Jul, 2008 Oct, 2008 13-15 20-24 21-24 24 0.15P Oct, 2008 26 Package Dimensions (2816-SSOP) Correct the typo F16167R as F16267R Revise pin configuration, swap pin 9 and 10 Add Register 0x002F description Add 6.5 Watchdog timer function description Add table 3 INT0, INT1 behavior Add 6.6.3 power saving mode description 0.16P 0.17P 0.18P Oct, 2008 Oct, 2008 Nov, 2008 25 6 19 11 13 0.19P Nov, 2008 15 23 24 17 18 Remove Register 0x0000~0x0007 description Description of bit7 in Register 0x008E: FPPF*PIE = “1” Name of Register 0x00FD: Time_MiddleLow_Byte Register 0x0012, bit0: RX Delay Ready 80h Register 0x0015, 0x0017 default: 04h 0.20P Feb, 2009 19-20 20 Register 0x0030, exchange the descriptions of bit 1 and 0 Register 0x0032, 0x0033 typo revised 1 V0.20P Fintek Feature Integration Technology Inc. F16267 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. 2 V0.20P Fintek Feature Integration Technology Inc. F16267 Table of Contents 1 2 3 4 GENERAL DESCRIPTION ........................................................................................................................................................ 6 FEATURE ..................................................................................................................................................................................... 6 PIN CONFIGURATION .............................................................................................................................................................. 7 PIN DESCRIPTION..................................................................................................................................................................... 8 4.1. 4.2. 4.3. 4.4. 4.5. 5 6 POWER PIN ........................................................................................................................................................................... 8 GPIO PIN .............................................................................................................................................................................. 8 RTC PIN................................................................................................................................................................................ 8 I2C INTERFACE PIN ............................................................................................................................................................... 9 IR PIN ................................................................................................................................................................................... 9 ELECTRICAL CHARACTERISTIC....................................................................................................................................... 10 FUNCTIONAL DESCRIPTION ............................................................................................................................................... 12 6.1 6.2 6.3 6.4 6.5 6.6 CIR FUNCTION ....................................................................................................................................................................... 12 RTC FUNCTION ...................................................................................................................................................................... 12 I2C FUNCTION ........................................................................................................................................................................ 12 GPIO FUNCTION .................................................................................................................................................................... 12 WATCHDOG TIMER FUNCTION ................................................................................................................................................ 13 MCU FUNCTION ..................................................................................................................................................................... 13 7 REGISTER DESCRIPTION (I2C ADDRESS = 0X9C).......................................................................................................... 15 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 DATA MEMORY STRUCTURE AND SPECIAL FUNCTION REGISTER (SFR) STRUCTURE.............................................................. 15 RESERVED – INDEX 0000H~0007H ......................................................................................................................................... 16 RESERVED – INDEX 0008H...................................................................................................................................................... 16 RESERVED – INDEX 0009H...................................................................................................................................................... 16 RESERVED – INDEX 000AH ..................................................................................................................................................... 16 RESERVED – INDEX 000BH ..................................................................................................................................................... 17 RESERVED – INDEX 000CH ..................................................................................................................................................... 17 RESERVED – INDEX 000DH ..................................................................................................................................................... 17 CIR – CIR FIFO REGISTER – INDEX 0010H............................................................................................................................ 17 CIR – INTERRUPT ENABLE REGISTER – INDEX 0011H......................................................................................................... 17 CIR – INTERRUPT STATUS REGISTER – INDEX 0012H .......................................................................................................... 17 CIR – BAUD RATE LOW BYTE REGISTER – INDEX 0013H ................................................................................................... 17 CIR – BAUD RATE HIGH BYTE REGISTER – INDEX 0014H .................................................................................................. 18 3 V0.20P Fintek Feature Integration Technology Inc. F16267 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 7.41 7.42 7.43 7.44 7.45 7.46 7.47 7.48 7.49 CIR – WAVEFORM LOGIC 1 DATA REGISTER – INDEX 0015H .............................................................................................. 18 CIR – WAVEFORM LOGIC 0 DATA REGISTER – INDEX 0016H .............................................................................................. 18 CIR – WAVEFORM LOGIC 1 COUNT REGISTER – INDEX 0017H ............................................................................................ 18 CIR – WAVEFORM LOGIC 0 COUNT REGISTER – INDEX 0018H ............................................................................................ 18 CIR – RX PROTOCOL REGISTER – INDEX 0019H ................................................................................................................. 18 GPIO – GPIO CONTROL REGISTER – INDEX 0020H ............................................................................................................ 18 GPIO – GPIO CAP REGISTER – INDEX 0021H .................................................................................................................... 19 GPIO – GPIO MULTI-FUNCTION REGISTER – INDEX 0022H ............................................................................................... 19 GPIO – GPIO DATA OUTPUT REGISTER – INDEX 0023H ..................................................................................................... 19 GPIO – GPIO INPUT INTERRUPT REGISTER – INDEX 0024H ............................................................................................... 19 GPIO – GPIO STATUS REGISTER – INDEX 0025H ............................................................................................................... 19 GPIO – GPIO LEVEL REGISTER – INDEX 002FH................................................................................................................. 19 I2C MASTER – I2C INTERRUPT ENABLE REGISTER – INDEX 0030H .................................................................................... 19 I2C MASTER – I2C STATUS REGISTER – INDEX 0031H ........................................................................................................ 20 I2C MASTER – I2C DEVICE REGISTER – INDEX 0032H ....................................................................................................... 20 I2C MASTER – I2C READ REGISTER – INDEX 0033H .......................................................................................................... 20 I2C MASTER – I2C INDEX ID REGISTER – INDEX 0034H .................................................................................................... 20 I2C MASTER – I2C ADDRESS – INDEX 0035H ..................................................................................................................... 20 RTC – SECOND REGISTER – INDEX 0080H .......................................................................................................................... 20 RTC – MINUTE REGISTER – INDEX 0081H .......................................................................................................................... 21 RTC – HOUR REGISTER – INDEX 0082H.............................................................................................................................. 21 RTC – DAY OF WEEK REGISTER – INDEX 0083H................................................................................................................. 21 RTC – DATE OF MONTH REGISTER – INDEX 0084H ............................................................................................................ 21 RTC – MONTH REGISTER – INDEX 0085H ........................................................................................................................... 21 RTC – YEAR REGISTER – INDEX 0086H .............................................................................................................................. 21 ALARM – SECOND ALARM REGISTER – INDEX 0087H ......................................................................................................... 22 ALARM – MINUTE ALARM REGISTER – INDEX 0088H ......................................................................................................... 22 ALARM – HOUR ALARM REGISTER – INDEX 0089H ............................................................................................................ 22 ALARM – DATE OF MONTH ALARM REGISTER – INDEX 008AH .......................................................................................... 22 ALARM – MONTH ALARM REGISTER – INDEX 008BH ......................................................................................................... 22 CONTROL REGISTER– CONTROL REGISTER 1 – INDEX 008CH ............................................................................................. 23 CONTROL REGISTER– CONTROL REGISTER 1 – INDEX 008DH ............................................................................................ 23 CONTROL REGISTER– STATUS REGISTER – INDEX 008EH ................................................................................................... 24 RESERVED – INDEX 008FH .................................................................................................................................................. 25 RAM DATA REGISTER –INDEX 0090H~00CFH (TOTAL 64 BYTES) ..................................................................................... 25 WATCHDOG TIMER ENABLE REGISTER – INDEX 00FAH ...................................................................................................... 25 4 V0.20P Fintek Feature Integration Technology Inc. F16267 7.50 7.51 7.52 8 9 WATCHDOG TIMER HIGH NIBBLE REGISTER – INDEX 00FBH.............................................................................................. 25 WATCHDOG TIMER MIDDLE BYTE REGISTER – INDEX 00FCH ............................................................................................ 25 WATCHDOG TIMER LOW BYTE REGISTER – INDEX 00FDH ................................................................................................. 25 ORDERING INFORMATION .................................................................................................................................................. 26 PACKAGE DIMENSIONS (16-SSOP) ..................................................................................................................................... 26 10 APPLICATION CIRCUIT ........................................................................................................................................................ 28 5 V0.20P Fintek Feature Integration Technology Inc. F16267 1 General Description The F16267 is an 80C31 instruction compatible microcontroller for general purpose system management. With external I2C serial EEPROM(2K bytes), The F16267 provides the best extendable flexibility by different customized features and memory size, loading program through two wires I2C serial port will be easily to implement. Furthermore, the F16267 supports one I2C slave serial ports to connect system chipset. The F16267 also supports 8 suits general purpose input / output pins and a low current consumption RTC. These functions of F16267 are implemented for different kinds of applications. Major application fields are small home appliances or computer peripheral applications. The F16267 is in SSOP-16 package and powered by 3.3VCC. 2 Feature Compatible with 80C31 instructions Supports CIR for receive 2K bytes RAM for loading the program from external EEPROM 64 bytes RAM of uC Supports RTC with 64 bytes SRAM by 32.768KHz Supports 8 suits general purpose input / output Hardware I2C Slave Functions Used extend I2C EEPROM storage code Supports firmware power down /idle mode Powered by 3.3VCC and packaged in SSOP-16 6 V0.20P Fintek Feature Integration Technology Inc. F16267 3 Pin Configuration Figure1. F16267 pin configuration 7 V0.20P Fintek Feature Integration Technology Inc. F16267 4 Pin Description P INst5V I/OD12st5V Power pins - TTL level input pin with schmitt trigger - TTL level bi-directional pin with schmitt trigger, Open-drain output with 12 mA sink capability, 5V tolerance I/O12st5v AIN AOUT - Output pin with 12mA sink/driving capability.5V tolerance - Input pin (Analog). - Output pin (Analog). 4.1. Power Pin Pin No. 5 8 16 Pin Name VBAT VSS VCC P Type Description Power source of RTC supplied from 3.3V battery Ground Power supply input 3.3V 4.2. GPIO Pin Pin No. 4 11 12 13 14 15 Pin Name GPIO5 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 Type I/O12st5v I/O12st5v I/O12st5v I/O12st5v I/O12st5v I/O12st5v PWR VDD VDD VDD VDD VDD VDD Description General purpose input/output bit 5 General purpose input/output bit 0 General purpose input/output bit 1 General purpose input/output bit 2 General purpose input/output bit 3 General purpose input/output bit 4 4.3. RTC Pin Pin No. 6 7 Pin Name XTAL_32K_IN XTAL_32K_IN Type AIN AIN PWR VBAT VBAT 32.768KHz clock input 32.768KHz clock output Description 8 V0.20P Fintek Feature Integration Technology Inc. F16267 4.4. I2C Interface Pin Pin No. 2 Pin Name I2CS_SCL/GPIO7 Type I/OD12st5v PWR VDD Description I2C serial clock for slave function/ General purpose input output bit 7 VDD I2C serial data for slave function/ General purpose input output bit 6 VDD I2C serial data for load external ROM function or other I2C salve device VDD I2C serial clock for load external ROM function or other I2C salve device 3 I2CS_SDA/GPIO6 I/OD12st5V 9 I2CM_SDA I/OD12st5V 10 I2CM_SCL I/OD12st5V 4.5. IR Pin Pin No. 1 Pin Name RX_IN Type INst5V PWR VDD Description IR receiver input 9 V0.20P Fintek Feature Integration Technology Inc. F16267 5 Electrical Characteristic 5.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature RATING -0.5 to 5.5 -0.5 to VDD+0.5 0 to +70 -55 to 150 UNIT V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device 5.2 DC Characteristics (Ta = 0° C to 70° C, VCC = 3.3V ± 10%, VSS = 0V) PARAMETER Operating Voltage Battery Voltage Operating Current Idle State Current Battery Current SYM. VDD VBAT ICC ISTY IBAT MIN. 3.0 2.4 TYP. 3.3 3.3 35 5 4 MAX. 3.6 3.6 UNIT V V mA uA uA CONDITIONS VCC=3.3V VBAT=3.3V VCC=3.3V VBAT=3.3V VCC=3.3V VBAT=3.3V I/OD12st5v - TTL level and schmitt trigger bi-directional pin with 12 mA source-sink capability 5V tolerance Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Hysteresis 0.5 V Output Low Current IOL +12 mA VOL = 0.4V Input High Leakage ILIH -1 +1 μA Input Low Leakage ILIL -1 +1 μA I/O12 – Output pin with12mA source-sink capability ,5V tolerance Input Low Voltage VIL 0.8 V VDD = 3.3 V Input High Voltage VIH 2.0 V VDD = 3.3 V Hysteresis 0.5 V Output High Current IOH 12 mA VOH = 2.0 V Input High Leakage ILIH -1 +1 μA Input Low Leakage ILIL -1 +1 μA INts_5v – TTL level input pin and schmitt trigger, 5V tolerance Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Hysteresis 0.5 V Input High Leakage ILIH +1 μA 10 V0.20P Fintek Input Low Leakage ILIL -1 Feature Integration Technology Inc. F16267 μA 5.3 AC Characteristics t SCL t t R R SCL t HD;STA t HD;DAT t t SU;DAT SU;STO SDA IN VALID DATA t DEL;DAT SDA OUT Serial Bus Timing Diagram Figure 2 SMBus timing diagram Serial Bus Timing PARAMETER SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time DATA OUT to SCL delay time SCL and SDA rise time SCL and SDA fall time SYMBOL t-SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tDEL:DATA tR tF MIN 3 50 50 50 5 200 200 200 MAX UNIT uS nS nS nS nS ns nS nS 11 V0.20P Fintek Feature Integration Technology Inc. F16267 6 Functional Description 6.1 CIR Function The CIR is used in Consumer Remote Control equipment. It is programmable amplitude shift keyed (ASK) serial communication protocol. By adjusting frequency, baud rate divisors, and sensitivity ranges, the CIR register are able to support the popular protocols such as ITT, NEC, NOKIA, SHARP, SONY and PHILIPS RC5./RC6 Software driver programming can support new protocol. The CIR builds 8 bytes FIFO for data reception. 6.2 RTC Function The F16267 provides a Real-Time-Clock with 64 bytes of RAM. The RTC provides a time-of-day clock in two data formats (Binary or BCD) and two hour formats (24 HR or AM/PM). The clock/calendar provides seconds, minutes, hours, day, date, month, year, and century information. It also provides a special time update and corrections for leap years. It has one alarm and three programmable interrupts. The F16267 is designed with either a crystal oscillator or external clock. The F16267 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across XTAL_32K_IN pin and XTAL_32K_OUT pin. In addition, an external clock should be connected to XTAL_32K_IN pin and XTAL_32K_OUT pin should be unconnected. Recommend to be connected with 32.768KHz input. 6.3 I2C Function The F16267 provides two I2C serial ports for transmission. The pins, I2C_SDA_M and I2C_SDA_M, are connected to external serial EEPROM for different customized requirement to transmit or receive I2C salve device data. The pins, I2C_SDA_S and I2C_SDA_S, are for I2C slave function. The I2C slave function support byte read, byte write, continuous read (256 bytes), and continuous write (256 bytes) mode and it defaults to address at 8’h9C and its address can be programmed by the register. The I2C slave function supports real-time read or write internal data of RTC/CIR/GPIO. 6.4 GPIO Function The F16267 provides 8 suits general purpose input/output. This function provides drives or sinks and input detects capability. The GPIO6 and GPIO7 are the multi-function pins with I2C_SDA_S and I2C_SCL_S. They can be switched by the register. 12 V0.20P Fintek Feature Integration Technology Inc. F16267 6.5 Watchdog Timer Function The F16267 contains a watchdog timer which will reset the IC when it counts down the set value in Register 0x00FB ~ 0x00FD (20 bits) to zero. The watchdog timer is based on 12MHz clock. 6.6 MCU Function The F16267 is an 8031 based micro processor for general purpose system management. The instruction set of the F16267 is fully compatible with the standard 8031, but not provides timer1/UART function and multiplication/division operation. The F16267 utilizes the external 32.768KHz crystal to oscillate 12Mhz internally instead of the external 12MHz crystal. The rest of the functions are as below description. The F16267 separates the memory into two separate sections, the Program Memory and the Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is used to store data or for memory mapped devices. 6.6.1 Program Memory The Program Memory on the F16267 can be up to 2Kbytes long. All instructions are fetched for execution from this memory area. The MOVC instruction can also access this memory region. 6.6.2 Data Memory The F16267 can access internal device function (RTC/CIR/GPO) of external Data Memory mapping. This memory region is accessed by the MOVX instructions. And internal device is mapping in data memory region. In addition, the F16267 has the 128 bytes of on-chip Scratchpad RAM. This can be accessed either by direct addressing or by indirect addressing. There are also some Special Function Registers (SFRs), which can only be accessed by direct addressing. Since the Scratchpad RAM is only 128 bytes. Table 1 3 source interrupt information INTERRUPT SOURCE External Interrupt 0 Timer 0 Interrupt External Interrupt 1 VECTOR ADDRESS 03H 0bH 13H ENABLE REQUIRED SETTINGS IE.0 IE.1 IE.2 INTERRUPT TYPE EDGE/LEVEL TCON.0 TCON.5 TCON.2 13 V0.20P Fintek Feature Integration Technology Inc. F16267 Table 2 2 source interrupt information INTERRUPT SOURCE External Interrupt 0 External Interrupt 1 VECTOR ADDRESS 03H 13H Function CIR RTC/I2C Master/GPIO 6.6.3 Power Saving Mode Normal State: All internal devices are working, and the internal clock is on Idle Mode: When set SFR index 8’h87 bit 0=1, the F16267 goes into idle mode, and the clock will stop. If the internal devices like GPIO, RTC, and CIR are asserted interrupt, the micro processor will resume the normal mode. Power Down Mode: When set SFR index 8’h87 bit 1=1, the F16267 goes into power down mode, and the clock will stop. If the micro processor wants to be resumed the normal mode, power off or software reset (Register 16’h0005 bit 0) is necessary. 14 V0.20P Fintek Feature Integration Technology Inc. F16267 7 Register Description (I2C Address = 0x9C) 7.1 Data Memory Structure and Special Function Register (SFR) Structure 00FFh Direct Addressing (SFR) 0080h 007Fh Direct/Indirect Addressing 0000h Figure 3 Data memory structure 15 V0.20P Fintek Feature Integration Technology Inc. F16267 Table 3 F16267 SFR memory allocation SFR WDT CLB WDT MLB WDTHLB WDT EN ACC PSW IP P3 IE P2 P1 TH0 TL0 TMOD TCON PCON DPH DPL SP P0 P07 P06 P05 P04 P03 P02 P01 P00 SMOD GATE C/T M1 TF0 M0 TR0 GATE IE1 GF1 C/T IT1 GF0 M1 IE0 PD M0 IT0 IDL P37 EA P27 P17 P26 P16 P25 P15 P24 P14 P23 P13 P22 P12 P36 P35 P34 P33 P32 CLB7 MLB7 HLB7 EN ACC7 CY ACC6 AC ACC5 F0 ACC4 RS1 ACC3 RS0 ACC2 OV PT0 P31 ET0 P21 P11 ACC1 CLB6 MLB6 HLB6 CLB5 MLB5 HLB5 CLB4 MLB4 HLB4 CLB3 MLB3 HLB3 CLB2 MLB2 HLB2 CLB1 MLB1 HLB1 CLB0 MLB0 HLB0 STATUS ACC0 P PX0 P30 EX0 P20 P10 Address FDh FCh FBh FAh E0h D0h B8h B0h A8h A0h 90h 8Bh 8Ah 89h 88h 87h 83h 82h 81h 80h 7.2 Bit 7-0 Reserved – Index 0000h~0007h Name Reserved R/W Default 0 Reserved Description 7.3 Bit 7-0 Reserved – Index 0008h Name Reserved R/W Default R Reserved Description 7.4 Bit 7-0 Reserved – Index 0009h Name Reserved R/W Default R Reserved Description 7.5 Bit Reserved – Index 000Ah Name R/W Default Description 16 V0.20P Fintek 7-0 Reserved R 34h Reserved Feature Integration Technology Inc. F16267 7.6 Bit 7-0 Reserved – Index 000Bh Name Reserved R/W Default R 19h Reserved Description 7.7 Bit 7-0 Reserved – Index 000Ch Name Reserved R/W Default R 20h Reserved Description 7.8 Bit 7-0 Reserved – Index 000Dh Name Reserved R/W Default R 07h Reserved Description 7.9 Bit CIR – CIR FIFO Register – Index 0010h Name R/W Default Description Receiver Buffer Register is read only. When the CIR pulse train has been 7-0 CIR_FIFO R 00h detected and passed by the internal signal filter, the data sampled and shifted into shifter register will be written into Receiver Buffer Register 7.10 CIR – Interrupt Enable Register – Index 0011h Bit 7 6-0 Name Interrupt_EN Reserved R/W Default R/W 0 0 Description Write 1 to enable CIR interrupt. Reserved 7.11 CIR – Interrupt Status Register – Index 0012h Bit 7-4 3 2 1 0 Name FIFO_CNT FIFO_RST Reserved Data_Lost Ready R/W Default R R/W R/W R R 0 0 0 0 0 Description This nibble indicates that how many byte RX data will be read. Write 1 to reset CIR FIFO Reserved This bit indicates FIFO data lost, and write 1 to clear This bit indicates RX data ready, and write 1 to clear 7.12 CIR – Baud Rate Low Byte Register – Index 0013h Bit 7-0 Name Baud_Lo R/W Default R/W A5h Description The registers of BLL are baud rate divisor latch. 17 V0.20P Fintek 7.13 CIR – Baud Rate High Byte Register – Index 0014h Bit 7-0 Name Baud_Hi R/W Default R/W 01h Feature Integration Technology Inc. F16267 Description The registers of BHL are baud rate divisor latch. 7.14 CIR – Waveform Logic 1 Data Register – Index 0015h Bit 7-0 Name WaveH R/W Default R/W 80h Description The registers of WaveH indicate RX logic 1 waveform 7.15 CIR – Waveform Logic 0 Data Register – Index 0016h Bit 7-0 Name WaveL R/W Default R/W 02h Description The registers of WaveL indicate RX logic 0 count number 7.16 CIR – Waveform Logic 1 Count Register – Index 0017h Bit 7-0 Name WaveH_Count R/W Default R/W 80h Description The registers of WaveH_Count indicate RX logic 1 count number 7.17 CIR – Waveform Logic 0 Count Register – Index 0018h Bit 7-0 Name WaveL_Count R/W Default R/W 02h Description The registers of WaveL_Count indicate RX logic 0 count number 7.18 CIR – Rx Protocol Register – Index 0019h Bit 7 6-5 4 3 Name Low_Frequency Reserved RXINV Bypass R/W Default R/W R/W R/W 1 demodulation 000 : ITT 001 : NEC 010 : NOKIA 2-0 Protocol R/W 001 011 : Sharp 100 : SONY 101 : Philips RC5 1 indicate RX carry frequency from 400k to 500k. 00 1 Reserved Write 1 to indicate invert RX input, or to indicate by pass RX. Write 1 to indicate RX input is demodulation , or to indicate RX is unDescription Write 1 to indicate RX carry frequency from 20k to 100k, and write 0 to 7.19 GPIO – GPIO Control Register – Index 0020h Bit Name R/W Default Description 18 V0.20P Fintek Feature Integration Technology Inc. F16267 Every bit indicates the corresponding pad of GPIO capability 7-0 GPIO_CNTL R/W 00h 0 : Open drain, 1: Drive/sink capability 7.20 GPIO – GPIO CAP Register – Index 0021h Bit 7-0 Name GPO_CAP R/W Default R/W 00h 0 : Input ,1: Output Description Every bit indicates the corresponding pad of GPIO direction 7.21 GPIO – GPIO Multi-function Register – Index 0022h Bit 7 6-1 0 Name Int_Global_EN Reserved GPIO/I2C R/W Default R/W R/W 0 00h Description Set to 1 to enable GPIO global interrupt enable ,or to disable interrupt. Reserved 0 : I2C function 1 : GPIO function 7.22 GPIO – GPIO Data Output Register – Index 0023h Bit 7-0 Name GPIO_PDOUT R/W Default R/W FFh GPIO data output for PAD. Description 7.23 GPIO – GPIO Input Interrupt Register – Index 0024h Bit 7-0 Name GPIO_INT_EN R/W Default R/W 00h 0: Disable, 1: Enable Description Every bit indicates the corresponding input pad of GPIO interrupt enable. 7.24 GPIO – GPIO Status Register – Index 0025h Bit 7-0 Name GPIO_Status R/W Default R/W 00h clear. Description Every bit indicates the corresponding input pad of GPIO status Write 1 to 7.25 GPIO – GPIO Level Register – Index 002Fh Bit 7-0 Name GPIO_Level R/W Default R/W 00h Description Every bit indicates the corresponding input GPIO pad level. 7.26 I2C Master – I2C Interrupt Enable Register – Index 0030h Bit 7 6-2 1 Name R/W Default 0 0 Description This bit indicates global interrupt enable Reserved This bit indicates I2C read finish interrupt enable I2C_Global_INT_EN R/W Reserved I2C_Read_INT_EN R/W 19 V0.20P Fintek 0 I2C_Write_INT_EN R/W 0 Feature Integration Technology Inc. F16267 This bit indicates I2C write finish interrupt enable. 7.27 I2C Master – I2C Status Register – Index 0031h Bit 7 6-4 3 2 1 0 Name I2C_NAK Reserved Read_Start Read_Status Write_Start Write_Status R/W Default R/W R/W R/W R/W R/W 0 0 function finish. 0 0 function finish. 0 This bit indicates I2C write finish status, and writes 1 to clear This bit indicates I2C read finish status, and writes 1 to clear Write 1 to start I2C write function and be cleared to 0 when I2C write Description This bit indicates NAK response from I2C device, and be written 1 to clear. Reserved Write 1 to start I2C read function and be cleared to 0 when I2C read 7.28 I2C Master – I2C Device Register – Index 0032h Bit 7-0 Name Device_Data R/W Default R/W 00h Description Write this byte to indicate I2C start transmit this byte data to device. 7.29 I2C Master – I2C Read Register – Index 0033h Bit 7-0 Name Read_Data R/W Default R 00h Description This byte indicates receive data from I2C device. 7.30 I2C Master – I2C Index ID Register – Index 0034h Bit 7 6-4 3-0 Name Reserved Device_New_ID Device_ID R/W R/W Default 0 0 Reserved This nibble indicates slave address the A0A1A2 of protocol. This nibble indicates slave address the highest nibble of protocol. Description 7.31 I2C Master – I2C Address – Index 0035h Bit 7 Name I2C_Address R/W Default R 00h Description This byte indicates address of I2C protocol 7.32 RTC – Second Register – Index 0080h Bit 7 6-0 Name Reserved Second R/W Default R/W 0 0 Reserved To write this bit, “SET” bit (CR8C[7]) must be set to 1. Description 20 V0.20P Fintek 7.33 RTC – Minute Register – Index 0081h Bit 7 6-0 Name Reserved Minute R/W Default R/W 0 0 Reserved Feature Integration Technology Inc. F16267 Description To write this MIN, “SET” bit (CR8C[7]) must be set to 1. 7.34 RTC – Hour Register – Index 0082h Bit Name R/W Default Description This bit is used to indicate that hour is at AM or PM. It only makes sense 7 PM_Flag R/W 0 when “M24” bit (CR8C[1]) is set to 0. To write this bit, “SET” bit (CR8C[7]) must be set to 1. 0: AM, 1: PM 6 6-0 Reserved Hour R/W 0 12h Reserved To write this bit, “SET” bit (CR8C[7]) must be set to 1. 7.35 RTC – Day of Week Register – Index 0083h Bit 7-3 Name Reserved R/W Default 0 Reserved To write this bit, “SET” bit (CR8C[7]) must be set to 1. 001: Sunday 010: Monday 2-0 Week R/W 1 011: Tuesday 101: Thursday 110: Friday 111: Saturday Description 7.36 RTC – Date of Month Register – Index 0084h Bit 6-4 5-0 Name Reserved Date R/W Default R/W 0 1 Reserved To write this bit, “SET” bit (CR8C[7]) must be set to 1. Description 7.37 RTC – Month Register – Index 0085h Bit 6-4 5-0 Name Reserved Month R/W Default R/W 0 1 Reserved To write this bit, “SET” bit (CR8C[7]) must be set to 1. Description 7.38 RTC – Year Register – Index 0086h Bit 6-4 Name Reserved R/W Default 0 Reserved Description 21 V0.20P Fintek 5-0 Year R/W 07h Feature Integration Technology Inc. F16267 To write this bit, “SET” bit (CR8C[7]) must be set to 1. 7.39 Alarm – Second Alarm Register – Index 0087h Bit Name R/W Default Description Seconds Alarm Enable. To enable second alarm function to compare 7 SEC_ALARM_EN R/W 0 SEC_ALARM data set in [6:0] with second, this bit must be set to 1. If this bit is not set to 1, it means that second alarm is not concerned. 6-0 SEC_ALARM R/W 00h Seconds Alarm data. 7.40 Alarm – Minute Alarm Register – Index 0088h Bit Name R/W Default Description Minutes Alarm Enable. To enable minute alarm function to compare 7 MIN_ALARM_EN R/W 0 MIN_ALARM data set in [6:0] with Minute, this bit must be set to 1. If this bit is not set to 1, it means that minute alarm is not concerned. 6-0 MIN_ALARM R/W 00h Minutes Alarm data. 7.41 Alarm – Hour Alarm Register – Index 0089h Bit Name R/W Default Description Hour Alarm Enable. To enable hour alarm function to compare PM_ALARM data set in bit 6 and HRS_ALARM data set in [5:0] with 7 HRS_ALARM_EN R/W 0 PM/HRS_FLAG, this bit must be set to 1. If this bit is not set to 1, it means that hour alarm is not concerned. 6 5-0 PM_ALARM HRS_ALARM R/W R/W 0 00h PM Flag Alarm data Hours Alarm data 7.42 Alarm – Date of Month Alarm Register – Index 008Ah Bit Name R/W Default Description Date Alarm Enable. To enable date alarm function to compare 7 DATE_ALARM_EN R/W 0 DATE_ALARM data set in [5:0], this bit must be set to 1. If this bit is not set to 1, it means that date alarm is not concerned. 6 5-0 Reserved DATE_ALARM R R/W 0 00h Reserved Date of Month Alarm data 7.43 Alarm – Month Alarm Register – Index 008Bh Bit Name R/W Default Description Month Alarm Enable. To enable month alarm function to compare 7 MTH_ALARM_EN R/W 0 MTH_ALARM data set in [4:0], this bit must be set to 1. If this bit is not set to 1, it means that month alarm is not concerned. 6-5 Reserved R 0 Reserved 22 V0.20P Fintek 4-0 MTH_ALARM R/W 00h Month Alarm data Feature Integration Technology Inc. F16267 7.44 Bit Control Register– Control Register 1 – Index 008Ch Name R/W Default Set Calendar Registers (SET) Description 7 SET R/W 0 This bit must be set to 1 to while writing calendar registers. When this bit is set, the calendar update process will be stop. Periodic Interrupt Enable (PIE) 6 PIE R/W 0 The bit is set to 1 to enable the generation of interrupt by PF (CR8E[6]). Alarm Interrupt Enable (AIE) 5 AIE R/W 0 This bit is set to 1 to enable the generation of interrupt by UF (CR8E[5]). Update-Ended Interrupt Enable (UIE) 4 3 UIE Reserved R/W R 0 This bit is set to 1 to enable the generation of interrupt by UF (CR8E[4]) 0 Reserved Data Mode (DM) 2 DM R/W 0 0: Binary Coded Decimal Mode (BCD mode) 1: Binary Mode 24/12 Hours Mode (M24) 1 M24 R/W 0 0: AM/PM 12 Hours Mode 1: 24 Hours Mode Daylight Saving Enable (DSE) 0: Disable Special Updates 1: Enable Special Updates: 0 DSE R/W 0 (a) The first Sunday of April, the time increases from AM 01:59:59 to AM 03:00:00. (b) The last Sunday of October, the time decreases from AM 01:59:59 to AM 01:00:00 7.45 Control Register– Control Register 1 – Index 008Dh Bit 7 6-4 Name UIP Reserved R/W Default R R/W 0 cycle or when “SET” (CR8C[7]) is 1. 010b Reserved Description Update Cycle In Progress (UIP). UIP is cleared in the end of an update 23 V0.20P Fintek Feature Integration Technology Inc. F16267 Periodic Interrupt Rate (PIR) 0000: NONE 0001: 16 kHz 0010: 8 kHz 0011: 4 kHz 0100: 2 kHz 0101: 1 kHz 0110: 512 Hz 3-0 PIR R/W 0000b 0111: 256 Hz 1000: 128 Hz 1001: 64 Hz 1010: 32 Hz 1011: 16 Hz 1100: 8 Hz 1101: 4 Hz 1110: 2 Hz 1111: 1 Hz 7.46 Control Register– Status Register – Index 008Eh Bit Name R/W Default Description RTC Interrupt Request Flag (RTC_INT_N). The interrupt request flag is set to 0 if one of the following cases are true: 7 RTC_INT_N R 1 PF*PIE = “1” AF*AIE = “1” UF*UIE = “1” Periodic Interrupt Flag (PF) This bit is set to 1 when a rising edge is detected on the selected PIR 6 PF R 0 clock. PF is set to 1 regardless of the state of PIE bit. This bit is cleared after CR8E is read. Alarm Interrupt Flag (AF) This bit is set to 1 when the current time has reached the alarm time. AF is 5 AF R 0 set to 1 regardless of the state of AIE bit. This bit is cleared after CR8E is read. Update-Ended Interrupt Flag (UF) 4 UF R 0 This bit is set to 1 after the end of each update cycle. UF is set to 1 regardless of the state of UIE bit. This bit is cleared after CR8E is read. 3-0 Reserved R 0 Reserved 24 V0.20P Fintek 7.47 Reserved – Index 008Fh Bit 7-0 Name Reserved R/W Default R 80 Reserved Feature Integration Technology Inc. F16267 Description 7.48 RAM Data Register –Index 0090h~00CFh (Total 64 Bytes) 7.49 Watchdog Timer Enable Register – Index 00FAh Bit 7 Name Watchdog_EN Reserved 4-0 Watchdog_Status R/W Default R/W R R/W 0 0 0 Set to 1, when watch dog timer count down to 0. Write 1 to clear. Description Set to 1 to enable watch dog timer and start count down. 7.50 Watchdog Timer High Nibble Register – Index 00FBh Bit 7-4 3-0 Name Reserved Time_High_Nibble R/W Default R/W 0 0 Reserved This register sets watch dog time[19:16] Description 7.51 Watchdog Timer Middle Byte Register – Index 00FCh Bit 7-0 Name Time_Middle_Byte R/W Default R/W 0 Description This register sets watch dog time[15:8] 7.52 Watchdog Timer Low Byte Register – Index 00FDh Bit 7-0 Name Time_Low_Byte R/W Default R/W 0 Description This register sets watch dog time[7:0] 25 V0.20P Fintek Feature Integration Technology Inc. F16267 8 Ordering Information Part Number F16267R Package Type 16-SSOP (Green Package) Production Flow Commercial, 0°C to +70°C 9 Package Dimensions (16-SSOP) Figure 4. 16 Pin SSOP Package Diagram 26 V0.20P Fintek Feature Integration Technology Inc. F16267 Feature Integration Technology Inc. Headquarters 3F-7, No 36, Tai Yuan St., Chupei City, Hsinchu, Taiwan 302, R.O.C. TEL : 886-3-5600168 FAX : 886-3-5600166 www: http://www.fintek.com.tw Taipei Office Bldg. K4, 7F, No.700, Chung Cheng Rd., Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 866-2-8227-8027 FAX : 866-2-8227-8037 Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner 27 V0.20P Fintek Feature Integration Technology Inc. F16267 10 Application Circuit Figure 5. F16267R Application Circuit 28 V0.20P