F71805FG

F71805 F71805F/FG Super H/W Monitor + LPC IO Release Date: Dec., 2006 Revision: V0.25P F71805 Dec., 2006 V0.25P F71805 F71805 Datasheet Revision History Version 0.20P 0.21P 0.22P Date 07/07/2004 07/28/2004 10/12/2004 10 22 0.23P 0.24P 04/15/2005 09/05/2006 91 16 0.25P 12/28/2006 4 Page Revision History Preliminary Release Version. Revised PWM frequency range. Added FANCTL Functions. Revised Voltage Fault Enable Register (Index 29h bit 7). Modified Application Circuit. Added “Green Package” ordering information Modified typo. Added PWM Output frequency setting description. Added Patent Note. Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. F71805 Dec., 2006 V0.25P F71805 Table of Contents 1. GENERAL DESCRIPTION .........................................................................................................................................................3 2. FEATURES ....................................................................................................................................................................................3 3. KEY SPECIFICATIONS ..............................................................................................................................................................5 4. PIN CONFIGURATION...............................................................................................................................................................5 5. PIN DESCRIPTION......................................................................................................................................................................6 5.1 5.2 5.3 5.4 5.5 5.6 5.7 POWER PIN .........................................................................................................................................................................6 LPC INTERFACE .................................................................................................................................................................6 FDC ...................................................................................................................................................................................7 UART PORT AND SIR.........................................................................................................................................................7 IEEE 1284 PARALLEL PORT ...............................................................................................................................................9 H/W MONITOR ...................................................................................................................................................................9 FLASH ROM INTERFACE AND GPIO.................................................................................................................................10 6. FUNCTION DESCRIPTION .....................................................................................................................................................11 6.1 6.2 6.3 6.4 6.5 POWER ON STRAPPING OPTIONS.......................................................................................................................................11 HARDWARE MONITOR ......................................................................................................................................................11 FDC .................................................................................................................................................................................18 UART ..............................................................................................................................................................................19 PARALLEL PORT ...............................................................................................................................................................19 7. REGISTER DESCRIPTION ......................................................................................................................................................19 7.1 GLOBAL CONTROL REGISTERS .........................................................................................................................................19 Software Reset Register  Index 02h............................................................................................................................ 20 Logic Device Number Register  Index 07h................................................................................................................. 20 Chip ID Register  Index 20h ....................................................................................................................................... 20 Chip ID Register  Index 21h ....................................................................................................................................... 20 Vendor ID Register  Index 23h ................................................................................................................................... 20 Vendor ID Register  Index 24h ................................................................................................................................... 20 Software Power Down Register  Index 25h ................................................................................................................ 20 UART IRQ Sharing Register  Index 26h .................................................................................................................... 21 Power On Trap Status Register  Index 27h ................................................................................................................. 21 Flash Control Register  Index 28h .............................................................................................................................. 21 Voltage Fault Enable Register  Index 29h................................................................................................................... 22 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 1 Dec., 2006 V0.25P F71805 7.2 FDC REGISTER.................................................................................................................................................................22 Logic Device Number Register........................................................................................................................................ 22 FDC Configuration Registers........................................................................................................................................... 23 Device Registers .............................................................................................................................................................. 25 7.2.1 7.2.2 7.2.3 7.3 UART 1 REGISTER ...........................................................................................................................................................40 Logic Device Number Register........................................................................................................................................ 40 UART 1 Configuration Register....................................................................................................................................... 41 Device Registers .............................................................................................................................................................. 42 7.3.1 7.3.2 7.3.3 7.4 UART 2 REGISTER ...........................................................................................................................................................45 Logic Device Number Register........................................................................................................................................ 45 UART 2 Configuration Registers ..................................................................................................................................... 45 Device Registers .............................................................................................................................................................. 47 7.4.1 7.4.2 7.4.3 7.5 PARALLEL PORT REGISTER ...............................................................................................................................................50 Logic Device Number Register........................................................................................................................................ 50 Parallel Port Configuration Registers............................................................................................................................... 50 Device Registers .............................................................................................................................................................. 51 7.5.1 7.5.2 7.5.3 7.6 HARDWARE MONITOR REGISTER .....................................................................................................................................55 Logic Device Number Registers ...................................................................................................................................... 55 Hardware Monitor Configuration Registers ..................................................................................................................... 55 Device Registers .............................................................................................................................................................. 56 7.6.1 7.6.2 7.6.3 7.7 GPIO REGISTER ...............................................................................................................................................................76 Logic Device Number Register........................................................................................................................................ 76 GPIO Configuration Registers ......................................................................................................................................... 76 7.7.1 7.7.2 7.8 PME REGISTER ................................................................................................................................................................83 Logic Device Number Register........................................................................................................................................ 83 PME Configuration Registers .......................................................................................................................................... 83 7.8.1 7.8.2 8. PCB LAYOUT GUIDE................................................................................................................................................................85 9. ELECTRICAL CHARACTERISTIC........................................................................................................................................86 9.1 9.2 9.3 ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................86 DC CHARACTERISTICS .....................................................................................................................................................86 AC CHARACTERISTICS .....................................................................................................................................................87 10. ORDERING INFORMATION ................................................................................................................................................87 11. PACKAGE DIMENSIONS......................................................................................................................................................88 12. F71805 DEMO CIRCUIT ........................................................................................................................................................89 2 Dec., 2006 V0.25P F71805 1. General Description The F71805 is the featured IO chip specifically for PC system. Equipped with one IEEE 1284 parallel port, two UART port and FDC, F71805 provides SIR and Flash ROM Interface. Integrated with hardware monitor, F71805 supports 9 sets of voltage sensor and 4 voltage fault signal outputs, 3 sets of creative auto-controlling fans and 3 temperature sensor pins for the accurate current type temp. measurement for CPU thermal diode or external transistors 2N3906. The F71805 provides flexible features for multi-directional application. For instance, supports 24 GPIO pins which include pulse/level mode selection, IRQ sharing function also designed in UART feature for particular usage and accurate current mode H/W monitor will be worth in measurement of temperature. The F71805 is powered by 3.3V voltage, with the LPC interface in the package of 128-QFP. 2. Features General Functions Comply with LPC Spec. 1.0 Supports 24 GPIO pins. One set of GPIO supports High/Low Level/Pulse selection. 48 MHz clock input FDC Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and under run conditions Built-in address mark detection circuit to simplify the read electronics Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD, and its Win95/98/2K/XP driver UART Two high-speed 16C550 compatible UART with 16-byte FIFOs Fully programmable serial-interface characteristics 3 Dec., 2006 V0.25P F71805 Baud rate up to 115.2K Infrared Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Flash ROM Interface Up to 4M bits flash ROM supported Parallel Port One PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification Enhanced printer port back-drive current protection Hardware Monitor Functions 3 current type accurate (±3℃) thermal inputs for CPU thermal diode and 2N3906 transistors 9 voltage monitoring inputs (8 external and Vcc power) 4 voltage_fault# hardware signal outputs 3 fan speed monitoring inputs 3 fan speed auto-control --- support 3 wire and 4 wire fans WATCHDOG comparison of all monitored values Issue PME#, OVT# and independent Voltage_fault # Package 128-pin PQFP Noted: Patented TW207103 TW207104 US6788131 B1 TW235231 TW237183 TWI263778 4 Dec., 2006 V0.25P F71805 3. Key Specifications Supply Voltage Operating Supply Current 3.0V to 3.6V 5 mA typ. 4. Pin Configuration F71805 Figure 1 5 Dec., 2006 V0.25P F71805 5. Pin Description I/O12t I/OOD12t I/OOD16t I/OD12ts5V I/O8t I/O8t-u47,5V I/O12ts5V O12 O8 AOUT OD12 OD24 INts INt5V INts5V AIN P - TTL level bi-directional pin with 12 mA source-sink cap ability. - TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA source-sink capability. - TTL level bi-directional pin, can select to OD or OUT by register, with 16 mA source-sink capability. - TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink capability, 5V tolerance. - TTL level bi-directional pin with 8 mA sink capability. - TTL level bi-directional pin with 8 mA sink capability, pull-up 47k ohms, 5V tolerance. - TTL level bi-directional pin and schmitt trigger with 12 mA sink capability, 5V tolerance. - Output pin with 12 mA source-sink capability. - Output pin with 8 A source-sink capability. - Output pin(Analog). - Open-drain output pin with 12 mA sink capability. - Open-drain output pin with 24 mA sink capability. - TTL level input pin and schmitt trigger. - TTL level input, 5V tolerance. - TTL level input pin and schmitt trigger, 5V tolerance. - Input pin(Analog). - Power. 5.1 Power Pin Pin Name VCC AGND(D-) GNDD Type P P P Description Power supply voltage input with 3.3V Analog GND Digital GND Pin No. 4,35,99 86 15,43,67,117 5.2 Pin No. 45 36 37 46 LPC Interface Pin Name LRESET# LDRQ# SERIRQ LFRAM# Type INts O12 I/O12t INts PWR VCC VCC VCC VCC Description Reset signal. It can connect to PCIRST# signal on the host. Encoded DMA Request signal. Serial IRQ input/Output. Indicates start of a new cycle or termination of a broken 6 Dec., 2006 V0.25P F71805 41-38 LAD[3:0] I/O12t VCC cycle. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. PCI clock input. System clock input. According to the input frequency 48MHz. 42 44 PCICLK CLKIN INts INts VCC VCC 5.3 Pin No. 57 FDC Pin Name DENSEL# Type OD24 PWR VCC Description Drive Density Select. Set to 1 - High data rate.(500Kbps, 1Mbps) Set to 0 – Low data rate. (250Kbps, 300Kbps) Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion Step output pulses. This active low open drain output produces a pulse to move the head to another track. Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Write enable. An open drain output. The read data input signal from the FDD. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. Diskette change. This signal is active low at power on and whenever the diskette is removed. 58 60 62 MTRA# DRVA# WDATA# OD24 OD24 OD24 VCC VCC VCC 63 DIR# OD24 VCC 64 65 STEP# HDSEL# OD24 OD24 VCC VCC 66 68 69 WGATE# RDATA# TRK0# OD24 INts5V INts5V VCC VCC VCC 70 INDEX# INts5V VCC 71 72 WPT# DSKCHG# INts5V INts5V VCC VCC 5.4 Pin No. 82 83 118 119 UART Port and SIR Pin Name IRTX IRRX DCD1# RI1# Type O12 INts INt5V INt5V PWR VCC VCC VCC VCC Description Infrared Transmitter Output. Infrared Receiver input. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. 7 Dec., 2006 V0.25P F71805 120 121 CTS1# DTR1#/JP1 INt5V I/O8t-u47,5V VCC VCC Clear To Send is the modem control input. UART 1 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. (Internal 47k pulled high and disable after power on strapping) Power on strapping: Default is high. Flash Rom Interface Address Segment 1 Enable (FFFC0000h-FFFFFFFFh, 000E0000h-000FFFFFh). (000E0000h-000EFFFFh Can be disabled by register change.) 122 RTS1#/JP2 I/O8t-u47,5V VCC UART 1 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data.(Internal 47k pulled high and disable after power on strapping) Power on strapping: Default is high. Flash Rom Interface Address Segment 2 Enable (FFEE0000h-FFEFFFFFh). Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART 1 Serial Output. Used to transmit serial data out to the communication link.( Internal 47k pulled high and disable after power on strapping ) Power on strapping: Default is high. Flash Rom Interface Address Segment 3 Enable (FFF80000h-FFFBFFFFh). Serial Input. Used to receive serial data through the communication link. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. Clear To Send is the modem control input. UART 2 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate.( Internal 47k pulled high and disable after power on strapping ) Power on strapping : 1 PWM Mode (Default) 0 Linear Mode UART 2 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data.(Internal 47k pulled high and disable after power on strapping ) Power on strapping : 1 XBUS Interface (Default) 0 Reserved. 123 DSR1# INt5V VCC 124 SOUT1/JP3 I/O8t-u47,5V VCC 125 126 127 128 1 SIN1 DCD2# RI2# CTS2# DTR2#/JP4 INt5V INt5V INt5V INt5V I/O8t-u47,5V VCC VCC VCC VCC VCC 2 RTS2#/JP6 I/O8t-u47,5V VCC 3 DSR2# INt5V VCC 5 SOUT2/JP5 I/O8t-u47,5V VCC Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART 2 Serial Output. Used to transmit serial data out to the communication link.(Internal 47k pulled high and disable after power on strapping ) Power on strapping : 1 Configuration register:4E (Default) 0 Configuration register:2E Serial Input. Used to receive serial data through the communication link. 6 SIN2 INt5V VCC 8 Dec., 2006 V0.25P F71805 5.5 Pin No. 100 IEEE 1284 Parallel Port Pin Name SLCT Type INts5V PWR VCC Description An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Output line for detection of printer selection. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Output line for the printer initialization. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Parallel port data bus bit 1. Parallel port data bus bit 2. Parallel port data bus bit 3. Parallel port data bus bit 4. Parallel port data bus bit 5. Parallel port data bus bit 6. Parallel port data bus bit 7. 101 PE INts5V VCC 102 BUSY INts5V VCC 103 ACK# INts5V VCC 104 SLIN# I/OD12ts5V VCC 105 INIT# I/OD12ts5V VCC 106 ERR# INts5V VCC 107 AFD# I/OD12ts5V VCC 108 STB# I/OD12ts5V VCC 109 PD0 I/O12ts5V VCC 110 111 112 113 114 115 116 PD1 PD2 PD3 PD4 PD5 PD6 PD7 I/O12ts5V I/O12ts5V I/O12ts5V I/O12ts5V I/O12ts5V I/O12ts5V I/O12ts5V VCC VCC VCC VCC VCC VCC VCC 5.6 Pin No. 91-98 73-75 H/W Monitor Pin Name VIN8~VIN1 FAN_TAC1~ FAN_TAC3 Type AIN INt s PWR VCC VCC Description Voltage input 8 ~ 1. Fan tachometer inputs. 9 Dec., 2006 V0.25P F71805 78-80 87-89 90 81 85 49-52 FAN_CTL1~ FAN_CTL3 D3~ D1 VREF PME# OVT# GP00~ GP03/ Voltage_fault1~4 O12 AIN AOUT OD12 OD12 I/OOD12t VCC VCC VCC VCC VCC VCC Fan control outputs. These pins provide PWM duty-cycle output or a voltage output. CPU thermal diode/transistor temperature sensor input. Voltage sensor output. Generated PME event. Generated over temperature event. General purpose IO. 1. Support Level and Pulse mode output. 2. Open drain and drive select. 3. Without input de-bounce. Voltage fault indication for VIN abnormal event. VIN1 Voltage_fault1 VIN2 Voltage_fault2 VIN3 Voltage_fault3 VIN4 Voltage_fault4 General purpose IO. 1. Support Level and Pulse mode output. 53-55 GP04~ GP06/ VIN7_ID0~2 I/OOD12t VCC 2. Open drain and drive select 3. Without input de-bounce. Voltage fault indication is for VIN7 abnormal event ID. 5.7 Pin No. 7-14 16-23 Flash ROM Interface and GPIO Pin Name FD0~ FD7 FA0~ FA7/ GP10~ GP17 FA8~ FA9 FA10~ FA17/ GP20~ GP27 FRD# FCS# FWE# FA18 GP07/FANCTL Type I/O8t O8 I/O8t O8 O8 I/O8t O8 O8 O8 O8 I/OOD12t PWR VCC VCC Description Flash ROM interface data [0:7]. The first functions of these pins are the Flash ROM interface address [0:7]. The second Functions of these pins are GPIO [10:17]. Flash ROM interface address [8:9]. The first functions of these pins are the Flash ROM interface address [10:17]. The second Functions of these pins are GPIO [20:27]. Flash ROM interface Read Strobe#. Flash ROM interface Chip Select#. Flash ROM interface Write Enable#. Flash ROM interface address18. General purpose IO. 1. Support Level and Pulse mode output. 2. Open drain and drive select 3. Without input de-bounce. Fan 1 control output for Intel 4-pin Fan. All the registers are as same as FANCTL1. 24-25 26-33 VCC VCC 34 47 48 59 56 VCC VCC VCC VCC VCC 10 Dec., 2006 V0.25P F71805 6. Function Description 6.1 Power on Strapping Options The F71805 provides four pins for power on hardware strapping to select functions. There is a form to describe how to set the functions you want. Pin No. 1 2 5 121 Symbol JP4 JP6 JP5 JP1 Value 1 0 1 0 1 0 1 0 1 0 1 0 Description Fan control mode: PWM mode. ( Default) Fan control mode: Linear mode. ISA ROM Interface enable ( Default) Reserved Chip selection in configuration 4E. (Default) Chip selection in configuration 2E. Flash Rom Interface Address Segment 1 Enable (Default) (FFFC0000h-FFFFFFFFh, 000E0000h-000FFFFFh). Disable. Flash Rom Interface Address Segment 2 Enable (Default) (FFEE0000h-FFEFFFFFh). Disable. Flash Rom Interface Address Segment 3 Enable (Default) (FFF80000h-FFFBFFFFh). Disable. 122 JP2 124 JP3 6.2 6.2.1 Hardware Monitor Analog Input The F71805 provides 8 pins (8-bit) ADC voltage inputs. These input voltages should be positive and is limited at range of 0v to 2.048V. The minimum resolution (1-LSB) is 8mV. If the voltage is over this range, the divider resistor must be added and the divided voltage is also in the range of 0V to 2.048V. The maximum input voltage of the analog pin is 2.048V because the 8-bit ADC has a 8mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The voltage range of 0V to 2.048V can be connected to these analog inputs. The 3.3V and VSB5V should be reduced a factor with external resistors so as to obtain the input range.. There are 8 voltage inputs in the F71805 and the voltage divided formula is shown as follows: VIN = V+12V × R2 R1 + R2 For instance, where V+12V is the analog input voltage. If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which is within the 11 Dec., 2006 V0.25P F71805 tolerance. As for application circuit, it can be refer to the figure shown as follows. VIN(Lower than 2.048V) R1 R2 F71805 D1/D2/D3 C 2200pF D1/D2/D3 AGND(D-) 2N3906 VREF R 10K, 1% Typical Thermister Connection 10K, 25 C 6.2.2 Temperature Monitoring and Offset The F71805 can be measured from 0°C to 140°C. The status depends on different situation. As connected to a BJT thermal diode, detected temperature ranges from 0°C to 140°C without considering the OFFSET effect. As connected to a thermistor, detected temperature ranges from 0°C to 127°C without considering the OFFSET effect. The temperature format is as the following table: Temperature ( High Byte ) 0°C 1°C 25°C 50°C 75°C 90°C 100°C 140°C Digital Output 0000 0000 0000 0001 0001 1001 0011 0010 0100 1011 0101 1010 0110 0100 1000 1100 The F71805 provides offset register for each temperature. The offset value is an 7-bit, 2’s complement value. The reading temperature value will be the result of the offset value added to the monitored value. The offset format is as the following table: 12 Dec., 2006 V0.25P F71805 Offset Value 63°C 2°C 1°C 0°C -1°C -2°C -64°C High Byte 0011 1111 0000 0010 0000 0001 0000 0000 0100 0001 0100 0010 0100 0000 The F71805 can provide two external thermal sensors to detect temperature. When monitored temperature exceeds the over-temperature threshold value, OVT# (pin85) will be asserted until the temperature goes below the hysteresis temperature. To T HYST OVT# 6.2.3 Fan speed count Inputs are provided by the signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage cannot be over VCC. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as follows: +12V Pull-up resister 4.7K Ohms +12V Pull-up resister < 1K or totem-pole output +12V FAN Out GND 10K 22K~30K Fan Input +12V FANIN 1 FAN Out GND > 1K Fan Input FANIN 1 F71805 3.3V Zener FAN Connector F71805 Fan with Tach Pull-Up to +12V, or Totern-Pole Output and Register Attenuator Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp 13 Dec., 2006 V0.25P F71805 +5V Pull-up resister 4.7K Ohms Pull-up resister < 1K or totem-pole output +5V FAN Out GND 10K 1K~2.7K Fan Input +5V FANIN1 FAN Out GND > 1K +5V Fan Input FANIN1 F71805 3.3V Zener FAN Connector F71805 Fan with Tach Pull-Up to +5V, or Totern-Pole Output and Register Attenuator Fan with Tach Pull-Up to +5V, or Totem-Pole Putput and Zener Clamp Determine the fan counter according to: 1.5 × 10 6 Count = RPM In other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. As for fan, it would be best to use 2 pulses tachmeter output per round. 1.5 × 10 6 RPM = Count 6.2.4 Fan speed control The F71805 provides 2 fan speed control methods: 1. Linear FAN Control 2. PWM Duty Cycle Linear Fan Control The range of DC output is 0~3.3V, controlled by 8-bit register (CR6Bh for FAN1, CR7Bh for FAN2 and CR8Bh for FAN3). 1 LSB is about 0.013V. The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN OPERATION VOLTAGE, 12V. The output voltage will be given as followed: Output_voltage (V) = 3.3 × Programmed 8 - bit Register Value 255 And the suggested application circuit for linear fac control would be: 14 Dec., 2006 V0.25P F71805 12V 3 DC OUTPUT VOLTAGE 2 8 + 4 1 LM358 PMOS D1 1N4148 R 4.7K JP1 R 10K C 47u 3 2 1 CON3 R 27K FANIN MONITOR C 0.1u R 10K R 3.9K DC FAN Control with OP PWM duty Fan Control The duty cycle of PWM can be programmed by a 8-bit register which are defined in the CR6Bh, CR7Bh and CR8Bh. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Duty_cycle(%) = Programmed 8 - bit Register Value × 100% 255 +5V +12V R1 R2 D G PWM Clock Input NMOS S + C FAN PWM Clock Input G PNP Transistor R1 R2 D NMOS S + C FAN PNP Transistor 6.2.5 Fan speed control mechanism There are 3 modes to control fan speed and they are manual, fan speed mode and temperature mode. For manual mode, it generally acts as PWM fan speed control. As for speed mode and temperature mode, they are more intelligent fan speed control and described as below: Fan Speed mode Fan speed mode is an intelligent method according to expected fan speed pre-setting by BIOS. In the beginning, fan speed will be operated at full speed and the F71805 will get the full speed count value. After that, the fan speed will automatically rotate according to the expected fan speed setting by BIOS. 15 Dec., 2006 V0.25P F71805 For instance, the register CR69h and CR6Ah are used for this mode of FAN1. Temperature mode At this mode, F71805 provides the clever system to automatically control fan speed related to temperature system. The F71805 can provide three temperature boundaries and three intervals for user setting, and each interval has its related fan speed count. All these values should be set by BIOS first. In the F71805 design, the F71805 will auto-generate temperature boundaries (average value) between those boundaries that user setting, and it will auto-produce interval fan speed count (average value) between users setting value. If the temperature value is set to 40, 50 and 90°C, it will auto-generate two temperature boundaries value of 45°C (This value is calculated automatically by hardware design of the F71805. (50+40)/2 =45 ) and 70°C. The same way, the related desired fan speed counts for each interval are 4200RPM, 3600RPM, 3000RPM, 2500RPM, 2000RPM and Stop Counts. When the temperature is within 50~70°C, the fan speed counts will be 3000RPM (Registers CRA4h~CRA9h, CRB4h~CRB9h and CRC4h~CRC9h). The F71805 will auto-adjust PWMOUT (PWM_DUTY) to make fan speed match the expected value. It can be said that the fan will be turned on with a specific speed set by BIOS and automatically controlled with the temperature varying. The F71805 will take charge of all the fan speed control and need no software support. Desired Counts (RPM) 90 Degree C 70 Degree C 3000 50 Degree C 2500 45 Degree C 40 Degree C 2000 Stop Counts 4200 3600 Auto-Generated (Average value) Auto-Generated (Average value) PWMOUT Duty-cycle operating process In both “FAN SPEED” and “TEMPERATURE” modes, F71805 adjust PWMOUT (PWM_DUTY1 (CR6B) of Fan1, PWM_DUTY2 (CR7B) of Fan2, PWM_DUTY3 (CR8B) of Fan3) duty-cycle according to current fan count and expected fan count. It will operate as follows: (1). When expected count is FFFFh, PWMOUT duty-cycle (PWM_DUTY)will be set to 00h to turn off fan. (2). When expected count is 0000h, PWMOUT duty-cycle (PWM_DUTY) will be set to FFh to turn on fan with full speed. 16 Dec., 2006 V0.25P F71805 (3). If both (1) and (2) are not true and KEEP_STOP (see INDEX 60h) is set to 0: (a). When PWMOUT duty-cycle decrease to STOP_DUTY(≠ 00h), obviously the duty-cycle will decrease to 00h next, F71805 will keep duty-cycle at 00h 3 seconds1. After that, F71805 starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. This ensures that if there is any glitch during the 3 seconds1 period, F71805 will ignore it. (b). When PWMOUT duty-cycle increase from 00h to START_DUTY(≠ 00h), F71805 also will keep duty-cycle at START_DUTY 3 seconds1. After that, F71805 starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. This ensures that if there is any glitch during the 3 seconds1 period, F71805 will ignore it. Note 1: The period of HOLD_DUTY_TIME can be programmed at INDEX 67h of FAN1. START STOP START STOP 6.2.6 FAN_FAULT# Fan_Fault will be asserted ( PME# Pin 81) when the fan speed doesn’t meet the expected fan speed within a programmable period (default is 3 seconds) or when PWMOUT duty-cycle is 100%. 17 Dec., 2006 V0.25P F71805 3 sec(default) Current Fan Count Expected Fan Count 100% Duty-cycle Fan_Fault# 6.2.7 VOLT_FAULT# (Voltage Fault Signal) When voltage leaps from the security range setting by BIOS, the warning signal VOLT_FAULT# will be activated. Shown in figure. High limit Low limit VOLT_FAULT# 6.3 FDC The Floppy Disk Controller provides the interface between a host processor and one floppy disk drives. It integrates a controller and a digital data separator with write pre-compensation, data rate selection logic, microprocessor interface, and a set of registers. The FDC supports data transfer rates of 250 Kbps, 300 Kbps, 500 Kbps, and 1 Mbps. It operates in PC/AT mode and supports 3-mode type drives. The FDC configuration is handled by software and a set of Configuration registers. Status, Data, and Control registers facilitate the interface between the host microprocessor and the disk drive, providing information about the condition and/or state of the FDC. These configuration registers can select the data rate, enable interrupts, drives, and DMA modes, and indicate errors in the data or operation of the FDC/FDD. The controller manages data transfers using a set of data transfer and control commands. These commands are handled in three phases: Command, Execution, and Result. Not all commands utilize all these three phases. 18 Dec., 2006 V0.25P F71805 6.4 UART The UARTs are used to convert data between parallel format and serial format. They convert parallel data into serial format on transmission and serial format into parallel data on receiver side. The serial format is formed by one start bit, followed by five to eight data bits, a parity bit if programmed and one ( 1.5 or 2 ) stop bits. The UARTs include complete modem control capability and an interrupt system that may be software trailed to the computing time required to handle the communication link. They have FIFO mode to reduce the number of interrupts presented to the host. Both receiver and transmitter have a 16-byte FIFO. 6.5 Parallel Port The parallel port in F71805 supports an IBM XT/AT compatible parallel port ( SPP ), bi-directional paralle port ( BPP ), Enhanced Parallel Port ( EPP ), Extended Capabilities Parallel Port ( ECP ) mode. Refer to the configuration registers for more information on selecting the mode of operation. 7. Register Description 7.1 Global Control Registers The configuration register is used to control the behavior of the corresponding devices. To configure the register, using the index port to select the index and then writing data port to alter the parameters. The default index port and data port are 0x4E and 0x4F respectively. Pull down the SOUT2/JP5 pin to change the default value to 0x2E/0x2F. To enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0xAA to the index port. Following is a example to enable configuration and disable configuration by using debug. -o 4e 87 -o 4e 87 -o 4e aa ( enable configuration ) ( disable configuration ) 19 Dec., 2006 V0.25P F71805 7.1.1 Software Reset Register  Index 02h Bit Name R/W Default R/W 0 Reserved. Write 1 to reset the register and device powered by VDD ( VCC ). Description 7-1 Reserved 0 SOFT_RST 7.1.2 Logic Device Number Register  Index 07h Bit 7-0 LDN Name R/W Default R/W 00h Description 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 06h: Select GPIO device configuration registers. 0ah: Select PME device configuration registers. Otherwise: reserved. 7.1.3 Chip ID Register  Index 20h Bit Name R/W Default R 04h Chip ID 1 of F71805. Description 7-0 CHIP_ID1 7.1.4 Chip ID Register  Index 21h Bit Name R/W Default R 06h Chip ID2 of F71805. Description 7-0 CHIP_ID2 7.1.5 Vendor ID Register  Index 23h Bit Name R/W Default R 19h Vendor ID 1 of Fintek devices. Description 7-0 VENDOR_ID1 7.1.6 Vendor ID Register  Index 24h Bit Name R/W Default R 34h Vendor ID 2 of Fintek devices. Description 7-0 VENDOR_ID2 7.1.7 Software Power Down Register  Index 25h Bit Name R/W Default Description 20 Dec., 2006 V0.25P F71805 7-6 Reserved 4 3 2 1 0 SOFTPD_HM SOFTPD_PRT SOFTPD_UR2 SOFTPD_UR1 SOFTPD_FDC R/W R/W R/W R/W R/W 0 0 0 0 0 Reserved Power down the Hardware Monitor device. This will stop the Hardware Monitor clock. Power down the Parallel Port device. This will stop the Parallel Port clock. Power down the UART 2 device. This will stop the UART 2 clock. Power down the UART 1 device. This will stop the UART 1 clock. Power down the FDC device. This will stop the FDC clock. 7.1.8 UART IRQ Sharing Register  Index 26h Bit Name R/W Default R/W R/W 0 0 Reserved. 0: PCI IRQ sharing mode (low level). 1: ISA IRQ sharing mode (low pulse). 0 IRQ_SHAR 0: disable IRQ sharing of two UART devices. 1: enable IRQ sharing of two UART devices. Description 7-2 Reserved 1 IRQ_MODE 7.1.9 Power On Trap Status Register  Index 27h Bit Name R/W Default R/W R/W 1 1 Reserved. 0: Configuration Register port is 2E/2F. 1: Configuration Register port is 4E/4F. 4 XBUS_EN 0: disable XBUS. FA17/GP27 ~ FA10/GP20 function as GP2. FA7/GP17 ~ FA0/GP10 function as GP1. 1: enable XBUS. 3 2 1 0 SEG_000E_EN SEG_FFFF_EN SEG_FFEF_EN SEG_FFF8_EN R/W R/W R/W R/W 1 1 1 1 0: disable segment 000E0000h-000EFFFFh. 1: enable segment 000E000h-000EFFFFh. 0: disable segment FFFFFFFFh-FFFC0000h. 1: enable segment FFFFFFFFh-FFFC0000h. 0: disable segment FFEFFFFFh-FFEE0000h. 1: enable segment FFEFFFFFh-FFEE0000h. 0: disable segment FFFBFFFFh-FFF80000h. 1: enable segment FFFBFFFFh-FFF80000h. Description 7-6 Reserved 5 PORT4E_EN 7.1.10 Flash Control Register  Index 28h Bit 7 Name FLASH_WR_EN R/W Default R/W 0 0: disable flash write. 1: enable flash write. 6-5 Reserved Reserved. Description 21 Dec., 2006 V0.25P F71805 4-0 WAIT_TIMES R/W 8h Adjust the cycles of the FCS# to improve the performance of the XBUS. The length of FCS# is from 7 LCLK cycles ( WAIT_TIMES == 00h) to 38 LCLK cycles (WAIT_TIMES == 1fh). 7.1.11 Voltage Fault Enable Register  Index 29h Bit 7 6 5 4 3 2 1 0 Name FANCTL_GPEN VIN7_ID2_EN VIN7_ID1_EN VIN7_ID0_EN VOLT_FAULT4_EN VOLT_FAULT3_EN VOLT_FAULT2_EN VOLT_FAULT1_EN R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0: the function of GP07 is GP07. 1: the function of GP07 is FANCTL. 0: the function of GP06/VIN7_ID2 is GP06. 1: the function of GP06/VIN7_ID2 is VIN7_ID2. 0: the function of GP05/VIN7_ID1 is GP05. 1: the function of GP05/VIN7_ID1 is VIN7_ID1. 0: the function of GP04/VIN7_ID0 is GP04. 1: the function of GP04/VIN7_ID0 is VIN7_ID0. 0: the function of GP03/Voltage_fault4 is GP03. 1: the function of GP03/Voltage_fault4 is Voltage_fault4. 0: the function of GP02/Voltage_fault3 is GP02. 1: the function of GP02/Voltage_fault3 is Voltage_fault3. 0: the function of GP01/Voltage_fault2 is GP01. 1: the function of GP01/Voltage_fault2 is Voltage_fault2. 0: the function of GP00/Voltage_fault1 is GP00. 1: the function of GP00/Voltage_fault1 is Voltage_fault1. Description 7.2 FDC Register 7.2.1 Logic Device Number Register Logic Device Number Register  Index 07h Bit 7-0 LDN Name R/W Default R/W 00h Description 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 06h: Select GPIO device configuration registers. 0ah: Select PME device configuration registers. Otherwise: reserved. 22 Dec., 2006 V0.25P F71805 7.2.2 FDC Configuration Registers FDC Device Enable Register  Index 30h Bit Name R/W Default R/W 1 Reserved 0: disable FDC. 1: enable FDC. Description 7-1 Reserved 0 FDC_EN Base Address High Register  Index 60h Bit Name R/W Default R/W 03h The MSB of FDC base address. Description 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W F0h The LSB of FDC base address. Description 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 06h Reserved. Select the IRQ channel for FDC. Description 7-4 Reserved 3-0 SELFDCIRQ DMA Channel Select Register  Index 74h Bit Name R/W Default R/W 010 Reserved. Select the DAM channel for FDC. Description 7-3 Reserved 2-0 SELFDCDMA FDD Mode Register  Index F0h Bit Name R/W Default Reserved. Description 7-4 Reserved 23 Dec., 2006 V0.25P F71805 3-2 IF_MODE R/W 11 00: Model 30 mode. 01: PS/2 mode. 10: Reserved. 11: AT mode (default). 1 FDMAMODE R/W 1 0: enable burst mode. 1: non-busrt mode (default). 0 EN3MODE R/W 0 0: normal floppy mode (default). 1: enhanced 3-mode FDD. FDD Drive Type Register  Index F2h Bit Name R/W Default R/W 11 Reserved. FDD drive type. Description 7-2 Reserved 1-0 FDD_TYPE FDD Selection Register  Index F4h Bit Name R/W Default R/W 00 Reserved. Data rate table select, refer to table A. 00: select regular drives and 2.88 format. 01: 3-mode drive. 10: 2 mega tape. 11: reserved. 2 Reserved R/W 00 Reserved. Drive type select, refer to table B. Description 7-5 Reserved 4-3 FDD_DRT 1-0 FDD_DT TABLE A Data Rate Table Select FDD_DRT[1] FDD_DRT[0] Data Rate DATARATE1 0 0 0 0 1 1 0 1 0 DATARATE0 0 1 0 1 0 Selected Data Rate MFM 500K 300K 250K 1Meg 500K FM 250K 150K 125K --250K 1 0 0 1 1 DENSEL 24 Dec., 2006 V0.25P F71805 0 1 1 0 1 0 0 1 1 TABLE B Drive Type FDD_DT1 FDD_DT0 0 0 DRVDEN0 DENSEL Remark 4/2/1 MB 3.5” 2/1 MB 5.25” 1/1.6/1 MB 3.5” (3-Mode ) 0 1 1 1 0 1 DATARATE1 DENSEL# DATARATE0 1 0 1 0 1 0 1 500K 250K 1Meg 500K 2Meg 250K 1Meg 250K 125K --250K --125K --0 0 1 1 0 0 1 7.2.3 Device Registers 7.2.3.1 Bit 7 6 5 4 3 Status Register A (PS/2 mode)  Base + 0 Name R/W Default R R R R R 0 0 0 Description This bit indicates the state of the interrupt output. 0: a second drive has been installed. 1: a second drive has not been installed. This bit indicates the complement of STEP# disk interface output. This bit indicates the state of TRK0# disk interface input. This bit indicates the complement of HDSEL# disk interface output. 0: side 0. 1: side 1. This bit indicates the state of INDEX# disk interface input. This bit indicates the state of WPT# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. This bit indicates the complement of DIR# disk interface output. INTPEND DRV2_N STEP TRK0_N HDSEL 2 1 INDEX_N WPT_N R R - 0 DIR R 0 7.2.3.2 Bit Status Register A (Model 30 mode)  Base + 0 Name R/W Default Description 25 Dec., 2006 V0.25P F71805 7 6 5 4 3 INTPEND DRQ STEP_FF TRK0 HDSEL_N R R R R R 0 0 0 1 This bit indicates the state of the interrupt output. This bit indicates the state of the DRQ signal. This bit indicates the complement of latched STEP# disk interface output. This bit indicates the complement of TRK0# disk interface input. This bit indicates the state of HDSEL# disk interface output. 0: side 0. 1: side 1. This bit indicates the complement of INDEX# disk interface input. This bit indicates the complement of WPT# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. This bit indicates the state of DIR# disk interface output. 0: head moves in inward direction. 1: head moves in outward direction. 2 1 INDEX WPT R R - 0 DIR_N R 1 7.2.3.3 Bit Status Register B (PS/2 Mode)  Base + 1 Name R/W Default R R R R R R R 0 0 0 0 0 0 Description Reserved. Return 11b when read. Drive select 0. This bit reflects the bit 0 of Digital Output Register. This bit changes state at every rising edge of WDATA#. This bit changes state at every rising edge of RDATA#. This bit indicates the complement of WGATE# disk interface output. This bit indicates the complement of MOB# disk interface output. Not support in this design. This bit indicates the complement of MOA# disk interface output. 7-6 Reserved 5 4 3 2 1 0 DR0 WDATA RDATA WGATE MOTEN1 MOTEN0 7.2.3.4 Bit 7 6 5 4 3 2 1 0 Status Register B (Model 30 Mode)  Base + 1 Name R/W Default R R R R R R R R 1 1 0 0 0 1 1 Description 0: a second drive has been installed. 1: a second drive has not been installed. This bit indicates the state of DRVB# disk interface output. Not support in this design. This bit indicates the state of DRVA# disk interface output. This bit is latched at the rising edge of WDATA# and is cleared by a read from the Digital Input Register. This bit is latched at the rising edge of RDATA# and is cleared by a read form the Digital Input Register. This bit is latched at the falling edge of WGATE# and is cleared by a read from the Digital Input Register. This bit indicates the complement of DRVD# disk interface output. Not support in this design. This bit indicates the complement of DRVC# disk interface output. Not support in this design. DRV2_N DSB_N DSA_N WDATA_FF RDATA_FF WGATE_FF DSD_N DSC_N 26 Dec., 2006 V0.25P F71805 7.2.3.5 Bit 7 6 5 4 3 Digital Output Register  Base + 2 Name R/W Default R R R/W R/W R/W 0 0 0 0 0 Description Motor enable 3. Not support in this design. Motor enable 2. Not support in this design. Motor enable 1. Used to control MOB#. MOB# is not support in this design. Motor enable 0. Used to control MOA#. DMA enable. This bit has two mode of operation. PC-AT and Model 30 mode: write 1 will enable DMA and IRQ, write 0 will disable DMA and IRQ. PS/2 mode: This bit is reserved. DMA and IRQ are always enabled in PS/2 mode. Write 0 to this bit will reset the controller. I will remain in reset condition until a 1 is written. This bit indicates the complement of DRVD# disk interface output. Not support in this design. This bit indicates the complement of DRVC# disk interface output. Not support in this design. MOTEN3 MOTEN2 MOTEN1 MOTEN0 DAMEN 2 1 0 RESET DSD_N DSC_N R R R 0 1 1 7.2.3.6 Bit Tape Drive Register  Base + 3 Name R/W Default R R R R/W 11 11 00 Description Reserved. Return 00b when read. Reserved in normal function, return 11b when read. If 3 mode FDD function is enabled. These bits indicate the drive type ID. Reserved. Return 11b when read in normal function. Return 00b when read in 3 mode FDD function. These bits assign a logical drive number to be a tape drive. 7-6 Reserved 5-4 TYPEID 3-2 Reserved 1-0 TAPESEL 7.2.3.7 Bit 7 6 RQM DIO Main Status Register  Base + 4 Name R/W Default R R 0 0 Description Request for Master indicates that the controller is ready to send or receive data from the uP through the FIFO. Data I/O (direction): 0: the controller is expecting a byte to be written to the Data Register. 1: the controller is expecting a byte to be read from the Data Register. Non DMA Mode: 0: the controller is in DAM mode. 1: the controller is interrupt or software polling mode. This bit indicate that a read or write command is in process. FDD number 3 is in seek or calibration condition. FDD number 3 is not support in this design. FDD number 2 is in seek or calibration condition. FDD number 2 is not support in this design. 5 NON_DMA R 0 4 3 2 FDC_BUSY DRV3_BUSY DRV2_BUSY R R R 0 0 0 27 Dec., 2006 V0.25P F71805 1 0 DRV1_BUSY DRV0_BUSY R R 0 0 FDD number 1 is in seek or calibration condition. FDD number 1 is not support in this design. FDD number 0 is in seek or calibration condition. 7.2.3.8 Bit 7 6 5 Data Rate Select Register  Base + 4 Name R/W Default W W W 0 0 000 Description A 1 written to this bit will software reset the controller. Auto clear after reset. A 1 to this bit will put the controller into low power mode which will turn off the oscillator and data separator circuits. Return 0 when read. Select the value of write precompensation: 250K-1Mbps 2Mbps 000: default delays default delays 001: 41.67ns 20.8ns 010: 83.34ns 41.17ns 011: 125.00ns 62.5ns 100: 166.67ns 83.3ns 101: 208.33ns 104.2ns 110: 250.00ns 125.00ns 111: 0.00ns (disabled) 0.00ns (disabled) The default value of corresponding data rate: 250Kbps: 125ns 300Kbps: 125ns 500Kbps: 125ns 1Mbps: 41.67ns 2Mbps: 20.8ns SOFTRST PWRDOWN Reserved 4-2 PRECOMP 1-0 DRATE W 10 Data rate select: MFM 00: 500Kbps 01: 300Kbps 10: 250Kbps 11: 1Mbps FM 250Kbps 150Kbps 125Kbps illegal 7.2.3.9 Bit 7-0 DATA Data (FIFO) Register  Base + 5 Name R/W Default R/W 00h Description The FIFO is used to transfer all commands, data and status between controller and the system. The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. The FIFO is default disabled and could be enabled via the CONFIGURE command. Status Registers 0 Bit Name R/W Default Description 28 Dec., 2006 V0.25P F71805 7-6 IC R Interrupt code : 00: Normal termination of command. 01: Abnormal termination of command. 10: Invalid command. 11: Abnormal termination caused by poling. Seek end. Set when a SEEK or RECALIBRATE or a READ or WRITE with implied seek command is completed. Equipment check. 0: No error 1: When a fault signal is received form the FDD or the TRK0# signal fails to occur after 77 step pulses. Not ready. 0: Drive is ready 1: Drive is not ready. Head address. The current head address. Drive select. 00: Drive A selected. 01: Drive B selected. 10: Drive C selected. 11: Drive D selected. 5 SE R - 4 EC R - 3 NR R - 2 HD R R - 1-0 DS Status Registers 1 Bit 7 6 4 EN DE OR Name R/W Default R R R Description End of Track. Set when the FDC tries to access a sector beyond the final sector of a cylinder. Data Error. The FDC detect a CRC error in either the ID field or the data field of a sector. Overrun/Underrun. Set when the FDC is not serviced by the host system within a certain time interval during data transfer. Unused. This bit is always “0” No Data. Set when the following conditions occurred: 1. The specified sector is not found during any read command. 2. The ID field cannot be read without errors during a READ ID command. 3. The proper sector sequence cannot be found during a READ TRACK command. No Writable Set when WPT# is active during execution of write commands. 3 2 Reserved ND R - 1 NW R - 29 Dec., 2006 V0.25P F71805 0 MA R Missing Address Mark. Set when the following conditions occurred: 1. Cannot detect an ID address mark at the specified track after encountering the index pulse form the INDEX# pin twice. 2. Cannot detect a data address mark or a deleted data address mark on the specified track. Status Registers 2 Bit 7 6 Name Reserved CM R/W Default R Unused. This bit is always “0”. Control Mark. Set when following conditions occurred: 1. Encounters a deleted data address mark during a READ DATA command. 2. Encounters a data address mark during a READ DELETED DATA command. Data Error in Data Field. The FDC detects a CRC error in the data field. Wrong Cylinder. Set when the track address from the sector ID field is different from the track address maintained inside the FDC. Scan Equal. Set if the equal condition is satisfied during execution of the SCAN command. Scan Not Satisfied. Set when the FDC cannot find a sector on the track which meets the desired condition during any scan command. Bad Cylinder. The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FFh which indicates a bad track. Missing Data Address Mark. Set when the FDC cannot detect a data address mark or a deleted data address mark. Description 5 4 DD WC R R - 3 2 SE SN R R - 1 BC R - 0 MD R - Status Registers 3 Bit 7 6 5 4 3 2 1 Name Reserved WP Reserved T0 Reserved. HD DS1 R/W Default R R R R R R Unused. This bit is always “0”. Write Protect. Indicates the status of WPT# pin. Unused. This bit is always “1”. Track 0. Indicates the status of the TRK0# pin. Unused. This bit is always “1”. Head Address. Indicates the status of the HDSEL# pin. Drive Select. Description 30 Dec., 2006 V0.25P F71805 0 DS0 R These two bits indicate the DS1, DS0 bits in the command phase. 7.2.3.10 Digital Input Register (PC-AT Mode)  Base + 7 Bit 7 Name DSKCHG R/W Default R Description This bit indicates the complement of DSKCHG# disk interface input. Reserved. 6-0 Reserved 7.2.3.11 Digital Input Register (PS/2 Mode)  Base + 7 Bit 7 Name DSKCHG R/W Default R R R 10 1 Description This bit indicates the complement of DSKCHG# disk interface input. Reserved. These bits indicate the status of the DRATE programmed through the Data Rate Select Register or Configuration Control Register. 0: 1Mbps or 500Kbps data rate is chosen. 1: 300Kbps or 250Kbps data rate is chosen. 6-3 Reserved 2-1 DRATE 0 HIGHDEN_N 7.2.3.12 Digital Input Register (Model 30 Mode)  Base + 7 Bit 7 Name DSKCHG_N R/W Default R R R R 0 0 10 Description This bit indicates the state of DSKCHG# disk interface input. Reserved. This bit reflects the DMA bit in Digital Output Register. This bit reflects the NOPRE bit in Configuration Control Register. These bits indicate the status of DRATE programmed through the Data Rate Select Register or Configuration Control Register. 6-4 Reserved 3 2 DMAEN NOPRE 1-0 DRATE 7.2.3.13 Configuration Control Register (PC-AT and PS/2 Mode)  Base + 7 Bit Name R/W Default W 10 Reserved. These bit determine the data rate of the floppy controller. See DRATE bits in Data Rate Select Register. Description 7-2 Reserved 1-0 DRATE 7.2.3.14 Configuration Control Register (Model 30 Mode)  Base + 7 Bit Name R/W Default Reserved. Description 7-3 Reserved 31 Dec., 2006 V0.25P F71805 2 NOPRE W 0 This bit could be programmed through Configuration Control Register and be read through the bit 2 in Digital Input Register in Model 30 Mode. But it has no functionality. These bit determine the data rate of the floppy controller. See DRATE bits in Data Rate Select Register. 1-0 DRATE W 10 7.2.3.15 C D DIR FDC Commands Cylinder Number 0 -256 Data Pattern Step Direction 0: step out 1: step in Drive Select 0 Drive Select 1 Data Length Enable Count End of Track Enable FIFO 0: FIFO is enabled. 1: FIFO is disabled. Enable Implied Seek FIFO Threshold Alters Gap Length Gap Length Head Address Head Load Time Head Unload Time Lock EFIFO, FIFOTHR, PTRTRK bits. Prevent these bits from being affected by software reset. MFM or FM mode 0: FM 1: MFM Multi-Track Sector Size Code. All values up to 07h are allowable. 00: 128 bytes 01: 256 bytes .. .. 07 16 Kbytes New Cylinder Number Non-DMA Mode Overwritten Present Cylinder Number Polling disable 0: polling is enabled. 1: polling is disabled. Precompensation Start Track Number Sector address Relative Cylinder Number Sector per Cylinder Skip deleted data address mark Step Rate Time Terminology: DS0 DS1 DTL EC EOT EFIFO EIS FIFOTHR GAP GPL H/HDS HLT HUT LOCK MFM MT N NCN ND OW PCN POLL PRETRK R RCN SC SK SRT 32 Dec., 2006 V0.25P F71805 ST0 ST1 ST2 ST3 WGATE Status Register 0 Status Register 1 Status Register 2 Status Register 3 Write Gate alters timing of WE. Read Data Phase Command R/W W W W W W W W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 D3 0 0 D2 1 HDS D1 1 DS1 D0 0 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------- Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution. Read Deleted Data Phase Command R/W W W W W W W D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 D3 1 0 D2 1 HDS D1 0 DS1 D0 0 DS0 Sector ID information prior to command execution Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N --------------------------- 33 Dec., 2006 V0.25P F71805 W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. ---------------------------- EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------Data transfer between the FDD and system Status information after command execution. Read A Track Phase Command R/W W W W W W W W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 0 HDS D1 1 DS1 D0 0 DS0 Sector ID information prior to command execution Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------- Data transfer between the FDD and system. FDD reads contents of all cylinders from index hole to EOT. Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------34 Status information after command execution. Sector ID information after command execution. Dec., 2006 V0.25P F71805 Read ID Phase Command R/W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 1 DS1 D0 0 DS0 The first correct ID information on the cylinder is stored in Data Register. Remark Command code Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------- Status information after command execution. Disk status after the command has been completed. Verify Phase Command R/W W W W W W W W W W Execution Result R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H --------------------------Sector ID information after command execution. D7 MT EC D6 MFM 0 D5 SK 0 D4 1 0 D3 0 0 D2 1 HDS D1 1 DS1 D0 0 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL --------------------------------------------------- DTL/SC ------------------------ Sector ID information prior to command execution No data transfer Status information after command execution. 35 Dec., 2006 V0.25P F71805 R R ----------------------------- R ------------------------------------------------------- N --------------------------- Version Phase Command Result R/W W R D7 0 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 0 Remark Command code Enhanced controller Write Data Phase Command R/W W W W W W W W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. D7 MT 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 1 HDS D1 0 DS1 D0 1 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------- Sector ID information prior to command execution Data transfer between the FDD and system. Status information after command execution. Write Deleted Data Phase Command R/W W W D7 MT 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 0 DS1 D0 1 DS0 Remark Command code 36 Dec., 2006 V0.25P F71805 W W W W W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------- Sector ID information prior to command execution Data transfer between the FDD and system. Status information after command execution. Format A Track Phase Command R/W W W W W W W Execution for each sector ( repeat ) D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 0 DS1 D0 1 DS0 Bytes/Sector Sectors/Cylinder Gap 3 Length Data Pattern Input sector parameter. Remark Command code ------------------------------ N ------------------------------------------------------ SC ----------------------------------------------------- GPL ------------------------------------------------------ D -------------------------------------------------------- C --------------------------- W W W ------------------------------ H -------------------------------------------------------- R ------------------------------------------------------- N ----------------------------------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 -------------------------------------------------- Undefined ---------------------------------------------- Undefined ---------------------- Result R R R R R Status information after command execution. 37 Dec., 2006 V0.25P F71805 R R -------------------------- Undefined ----------------------------------------------- Undefined ---------------------- Recalibrate Phase Command R/W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 0 D1 1 DS1 D0 1 DS0 Head retracted to track 0 Remark Command code Sense Interrupt Status Phase Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0 Remark Command code ---------------------------- ST0 ----------------------------------------------------- PCN -------------------------- Specify Phase Command R/W W W W D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 Remark Command code |------------------ SRT -------------------| |------------------ HUT -------------------| ND |------------------------------------- SRT ---------------------------------------| Seek Phase Command R/W W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 Remark Command code ---------------------------- NCN -------------------------Head positioned over proper cylinder on diskette Configure Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark 38 Dec., 2006 V0.25P F71805 Command W W W W Execution 0 0 0 0 0 EIS 0 0 EFIFO 1 0 POLL 0 0 0 HDS 1 DS1 1 DS0 Command code |---------------- FIFOTHR ---------------| ---------------------------- PRETRK -------------------------Internal registers written Relative Seek Phase Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 Remark Command code ---------------------------- RCN -------------------------- Perpendicular Mode Phase Command R/W W W D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 0 D0 D1 1 GAP D0 0 WGATE Remark Command code Lock Phase Command Result R/W W R D7 LOCK 0 D6 0 0 D5 0 0 D4 1 LOCK D3 0 0 D2 1 0 D1 0 0 D0 0 0 Remark Command code Dumpreg Phase Command Result R/W W R R R R R R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 Remark Command code -------------------------- PCN ( Drive 0 ) ------------------------------------------------- PCN ( Drive 0 ) ------------------------------------------------- PCN ( Drive 0 ) ------------------------------------------------- PCN ( Drive 0 ) -----------------------|------------------ SRT -------------------| |------------------ HUT -------------------| ND |------------------------------------- SRT ---------------------------------------| -------------------------- SC/EOT ------------------------ 39 Dec., 2006 V0.25P F71805 R R R LOCK 0 0 EIS D3 EFIFO D2 POLL D1 D0 GAP WGATE |---------------- FIFOTHR ---------------| ---------------------------- PRETRK -------------------------- Sense Drive Status Phase Command R/W W W Result R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 HDS D1 0 DS1 D0 0 DS0 Status information abut disk drive Remark Command code ---------------------------- ST3 -------------------------- Invalid Phase Command Result R/W W R D7 D6 D5 D4 D3 D2 D1 D0 state. Remark FDC goes to standby ST0 = 80h ---------------------------- Invalid Codes ----------------------------------------------------- ST0 -------------------------- 7.3 UART 1 Register 7.3.1 Logic Device Number Register Logic Device Number Register  Index 07h Bit 7-0 LDN Name R/W Default R/W 00h Description 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 06h: Select GPIO device configuration registers. 0ah: Select PME device configuration registers. Otherwise: reserved. 40 Dec., 2006 V0.25P F71805 7.3.2 UART 1 Configuration Register UART IRQ Sharing Register  Index 26h Bit Name R/W Default R/W R/W 0 0 Reserved. 0: PCI IRQ sharing mode (low level). 1: ISA IRQ sharing mode (low pulse). 0 IRQ_SHAR 0: disable IRQ sharing of two UART devices. 1: enable IRQ sharing of two UART devices. Description 7-2 Reserved 1 IRQ_MODE UART 1 Device Enable Register  Index 30h Bit Name R/W Default R/W 1 Reserved 0: disable UART 1. 1: enable UART 1. Description 7-1 Reserved 0 UR1_EN Base Address High Register  Index 60h Bit Name R/W Default R/W 03h Description The MSB of UART 1 base address. 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W F8h Description The LSB of UART 1 base address. 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 4h Reserved. Select the IRQ channel for UART 1. Description 7-4 Reserved 3-0 SELUR1IRQ RS485 Enable Register  Index F0h Bit Name R/W Default Reserved. Description 7-5 Reserved 41 Dec., 2006 V0.25P F71805 4 RS485_EN R/W 0 0: RS232 driver. 1: RS485 driver. Auto drive RTS# low when transmitting data. 3-0 Reserved Reserved. 7.3.3 Device Registers 7.3.3.1 Bit 7-0 RBR Receiver Buffer Register  Base + 0 Name R/W Default R 00h The data received. Read only when LCR[7] is 0 Description 7.3.3.2 Bit 7-0 THR Transmitter Holding Register  Base + 0 Name R/W Default W 00h Data to be transmitted. Write only when LCR[7] is 0 Description 7.3.3.3 Bit 7-0 DLL Divisor Latch (LSB)  Base + 0 Name R/W Default R/W 01h Baud generator divisor low byte. Access only when LCR[7] is 1. Description 7.3.3.4 Bit 7-0 DLM Divisor Latch (MSB)  Base + 1 Name R/W Default R/W 00h Description Baud generator divisor high byte. Access only when LCR[7] is 1. 7.3.3.5 Bit 3 2 1 0 EDSSI ELSI ETBFI ERBFI Interrupt Enable Register  Base + 1 Name R/W Default R/W R/W R/W R/W 0 0 0 0 Reserved. Enable Modem Status Interrupt. Access only when LCR[7] is 0. Enable Line Status Error Interrupt. Access only when LCR[7] is 0. Enable Transmitter Holding Register Empty Interrupt. Access only when LCR[7] is 0. Enable Received Data Available Interrupt. Access only when LCR[7] is 0. Description 7-4 Reserved 7.3.3.6 Bit 7 Interrupt Identification Register  Base + 2 Name R/W Default R 0 0: FIFO is disabled 1: FIFO is enabled. Description FIFO_EN 42 Dec., 2006 V0.25P F71805 6 FIFO_EN R R 0 000 0: FIFO is disabled 1: FIFO is enabled. Reserved. 000: Interrupt is caused by Modem Status 001: Interrupt is caused by Transmitter Holding Register Empty 010: Interrupt is caused by Received Data Available. 110: Interrupt is caused by Character Timeout 011: Interrupt is caused by Line Status. 1: Interrupt is not pending. 0: Interrupt is pending. 5-4 Reserved 3-1 IRQ_ID 0 IRQ_PENDN R 1 7.3.3.7 Bit FIFO Control Register  Base + 2 Name R/W Default W 00 Description 00: Receiver FIFO trigger level is 1. 01: Receiver FIFO trigger level is 4. 10: Receiver FIFO trigger level is 8. 11: Receiver FIFO trigger level is 14. Reserved. Reset the transmitter FIFO. Reset the receiver FIFO. 0: Disable FIFO. 1: Enable FIFO. 7-6 RCV_TRIG 5-3 Reserved 2 1 0 CLRTX CLRRX FIFO_EN R R R 0 0 0 7.3.3.8 Bit 7 6 5 4 3 2 DLAB Line Control Register  Base + 3 Name R/W Default R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Description 0: Divisor Latch can’t be accessed. 1: Divisor Latch can be accessed via Base and Base+1. 0: Transmitter is in normal condition. 1: Transmit a break condition. XX0: Parity Bit is disable 001: Parity Bit is odd. 011: Parity Bit is even 101: Parity Bit is logic 1 111: Parity Bit is logic 0 0: Stop bit is one bit 1: When word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 00: Word length is 5 bit 01: Word length is 6 bit 10: Word length is 7 bit 11: Word length is 8 bit SETBRK STKPAR EPS PEN STB 1-0 WLS R/W 00 7.3.3.9 Bit 4 LOOP MODEM Control Register  Base + 4 Name R/W Default R/W R/W 0 Reserved. 0: UART in normal condition. 1: UART is internal loop back Description 7-5 Reserved 43 Dec., 2006 V0.25P F71805 3 2 1 0 OUT2 OUT1 RTS DTR R/W R/W R/W R/W 0 0 0 0 0: All interrupt is disabled. 1: Interrupt is enabled(disabled) by IER. Read from MSR[6] is loop back mode 0: RTS# is forced to logic 1 1: RTS# is forced to logic 0 0: DTR# is forced to logic 1 1: DTR# is forced to logic 0 7.3.3.10 Line Status Register  Base + 5 Bit 7 6 5 4 3 2 1 0 Name RCR_ERR TEMT THRE BI FE PE OE DR R/W Default R R R R R R R R 0 1 1 0 0 0 0 0 Description 0: No error in the FIFO when FIFO is enabled 1: Error in the FIFO when FIFO is enabled. 0: Transmitter is in transmitting. 1: Transmitter is empty. 0: Transmitter Holding Register is not empty. 1: Transmitter Holding Register is empty. 0: No break condition detected. 1: A break condition is detected. 0: Data received has no frame error. 1: Data received has frame error. 0: Data received has no parity error. 1: Data received has parity error. 0: No overrun condition occurred. 1: An overrun condition occurred. 0: No data is ready for read. 1: Data is received. 7.3.3.11 MODEM Status Register  Base + 6 Bit 7 6 5 4 3 2 1 0 DCD RI DSR CTS DDCD TERI DDSR DCTS Name R/W Default R R R R R R R R 0 0 0 0 Description Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2 in MCR. Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in MCR Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in MCR Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in MCR 0: No state changed at DCD#. 1: State changed at DCD#. 0: No Trailing edge at RI#. 1: A low to high transition at RI#. 0: No state changed at DSR#. 1: State changed at DSR#. 0: No state changed at CTS#. 1: State changed at CTS#. 7.3.3.12 Scratch Register  Base + 7 Bit 7-0 SCR Name R/W Default R/W 00h Description Scratch register. 44 Dec., 2006 V0.25P F71805 7.4 UART 2 Register 7.4.1 Logic Device Number Register Logic Device Number Register  Index 07h Bit 7-0 LDN Name R/W Default R/W 00h Description 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 06h: Select GPIO device configuration registers. 0ah: Select PME device configuration registers. Otherwise: reserved. 7.4.2 UART 2 Configuration Registers UART IRQ Sharing Register  Index 26h Bit Name R/W Default R/W 0 Reserved. 0: PCI IRQ sharing mode (low level). 1: ISA IRQ sharing mode (low pulse). 0 IRQ_SHAR R/W 0 0: disable IRQ sharing of two UART devices. 1: enable IRQ sharing of two UART devices. Description 7-2 Reserved 1 IRQ_MODE UART 2 Device Enable Register  Index 30h Bit Name R/W Default R/W 1 Reserved 0: disable UART 2. 1: enable UART 2. Description 7-1 Reserved 0 UR2_EN 45 Dec., 2006 V0.25P F71805 Base Address High Register  Index 60h Bit Name R/W Default R/W 02h Description The MSB of UART 2 base address. 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W F8h Description The LSB of UART 2 base address. 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 3h Reserved. Select the IRQ channel for UART 2. Description 7-4 Reserved 3-0 SELUR2IRQ RS485 Enable Register  Index F0h Bit Name R/W Default R/W 0 Reserved. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# low when transmitting data. 3 RXW4C_IR R/W 0 0: No reception delay when SIR is changed form TX to RX. 1: Reception delays 4 characters time when SIR is changed form TX to RX. 2 TXW4C_IR R/W 0 0: No transmission delay when SIR is changed form RX to TX. 1: Transmission delays 4 characters time when SIR is changed form RX to TX. 1-0 Reserved Reserved. Description 7-5 Reserved 4 RS485_EN SIR Mode Control Register  Index F1h Bit 7 6 5 Name Reserved Reserved Reserved R/W Default Reserved. Reserved. Reserved. Description 46 Dec., 2006 V0.25P F71805 4-3 IRMODE R/W 00 00: disable IR function. 01: disable IR function. 10: IrDA function, active pulse is 1.6uS. 11: IrDA function, active pulse is 3/16 bit time. 2 HDUPLX R/W 1 0: SIR is in full duplex mode for loopbak test. TXW4C_IR and RXW4C_IR are of no use. 1: SIR is in half duplex mode. 1 TXINV_IR R/W 0 0: IRTX is in normal condition. 1: inverse the IRTX. 0 RXINV_IR R/W 0 0: IRRX is in normal condition. 1: inverse the IRRX. 7.4.3 Device Registers 7.4.3.1 Bit 7-0 RBR Receiver Buffer Register  Base + 0 Name R/W Default R 00h The data received. Read only when LCR[7] is 0 Description 7.4.3.2 Bit 7-0 THR Transmitter Holding Register  Base + 0 Name R/W Default W 00h Data to be transmitted. Write only when LCR[7] is 0 Description 7.4.3.3 Bit 7-0 DLL Divisor Latch (LSB)  Base + 0 Name R/W Default R/W 01h Baud generator divisor low byte. Access only when LCR[7] is 1. Description 7.4.3.4 Bit 7-0 DLM Divisor Latch (MSB)  Base + 1 Name R/W Default R/W 00h Description Baud generator divisor high byte. Access only when LCR[7] is 1. 7.4.3.5 Bit Interrupt Enable Register  Base + 1 Name R/W Default Description 47 Dec., 2006 V0.25P F71805 7-4 Reserved 3 2 1 0 EDSSI ELSI ETBFI ERBFI R/W R/W R/W R/W 0 0 0 0 Reserved. Enable Modem Status Interrupt. Access only when LCR[7] is 0. Enable Line Status Error Interrupt. Access only when LCR[7] is 0. Enable Transmitter Holding Register Empty Interrupt. Access only when LCR[7] is 0. Enable Received Data Available Interrupt. Access only when LCR[7] is 0. 7.4.3.6 Bit 7 6 Interrupt Identification Register  Base + 2 Name R/W Default R R R 0 0 000 0: FIFO is disabled 1: FIFO is enabled. 0: FIFO is disabled 1: FIFO is enabled. Reserved. 000: Interrupt is caused by Modem Status 001: Interrupt is caused by Transmitter Holding Register Empty 010: Interrupt is caused by Received Data Available. 110: Interrupt is caused by Character Timeout 011: Interrupt is caused by Line Status. 1: Interrupt is not pending. 0: Interrupt is pending. Description FIFO_EN FIFO_EN 5-4 Reserved 3-1 IRQ_ID 0 IRQ_PENDN R 1 7.4.3.7 Bit FIFO Control Register  Base + 2 Name R/W Default W 00 Description 00: Receiver FIFO trigger level is 1. 01: Receiver FIFO trigger level is 4. 10: Receiver FIFO trigger level is 8. 11: Receiver FIFO trigger level is 14. Reserved. Reset the transmitter FIFO. Reset the receiver FIFO. 0: Disable FIFO. 1: Enable FIFO. 7-6 RCV_TRIG 5-3 Reserved 2 1 0 CLRTX CLRRX FIFO_EN R R R 0 0 0 7.4.3.8 Bit 7 6 5 4 3 DLAB Line Control Register  Base + 3 Name R/W Default R/W R/W R/W R/W R/W 0 0 0 0 0 Description 0: Divisor Latch can’t be accessed. 1: Divisor Latch can be accessed via Base and Base+1. 0: Transmitter is in normal condition. 1: Transmit a break condition. XX0: Parity Bit is disable 001: Parity Bit is odd. 011: Parity Bit is even 101: Parity Bit is logic 1 111: Parity Bit is logic 0 SETBRK STKPAR EPS PEN 48 Dec., 2006 V0.25P F71805 2 STB R/W 0 0: Stop bit is one bit 1: When word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 00: Word length is 5 bit 01: Word length is 6 bit 10: Word length is 7 bit 11: Word length is 8 bit 1-0 WLS R/W 00 7.4.3.9 Bit 4 3 2 1 0 LOOP OUT2 OUT1 RTS DTR MODEM Control Register  Base + 4 Name R/W Default R/W R/W R/W R/W R/W R/W 0 0 0 0 0 Reserved. 0: UART in normal condition. 1: UART is internal loop back 0: All interrupt is disabled. 1: Interrupt is enabled(disabled) by IER. Read from MSR[6] is loop back mode 0: RTS# is forced to logic 1 1: RTS# is forced to logic 0 0: DTR# is forced to logic 1 1: DTR# is forced to logic 0 Description 7-5 Reserved 7.4.3.10 Line Status Register  Base + 5 Bit 7 6 5 4 3 2 1 0 Name RCR_ERR TEMT THRE BI FE PE OE DR R/W Default R R R R R R R R 0 1 1 0 0 0 0 0 Description 0: No error in the FIFO when FIFO is enabled 1: Error in the FIFO when FIFO is enabled. 0: Transmitter is in transmitting. 1: Transmitter is empty. 0: Transmitter Holding Register is not empty. 1: Transmitter Holding Register is empty. 0: No break condition detected. 1: A break condition is detected. 0: Data received has no frame error. 1: Data received has frame error. 0: Data received has no parity error. 1: Data received has parity error. 0: No overrun condition occurred. 1: An overrun condition occurred. 0: No data is ready for read. 1: Data is received. 7.4.3.11 MODEM Status Register  Base + 6 Bit 7 6 5 DCD RI DSR Name R/W Default R R R Description Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2 in MCR. Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in MCR Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in MCR 49 Dec., 2006 V0.25P F71805 4 3 2 1 0 CTS DDCD TERI DDSR DCTS R R R R R 0 0 0 0 Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in MCR 0: No state changed at DCD#. 1: State changed at DCD#. 0: No Trailing edge at RI#. 1: A low to high transition at RI#. 0: No state changed at DSR#. 1: State changed at DSR#. 0: No state changed at CTS#. 1: State changed at CTS#. 7.4.3.12 Scratch Register  Base + 7 Bit 7-0 SCR Name R/W Default R/W 00h Description Scratch register. 7.5 Parallel Port Register 7.5.1 Logic Device Number Register Logic Device Number Register  Index 07h Bit 7-0 LDN Name R/W Default R/W 00h Description 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 06h: Select GPIO device configuration registers. 0ah: Select PME device configuration registers. Otherwise: reserved. 7.5.2 Parallel Port Configuration Registers Parallel Port Device Enable Register  Index 30h Bit 0 Name PRT_EN R/W Default R/W 1 Reserved 0: disable Parallel Port. 1: enable Parallel Port. Description 7-1 Reserved 50 Dec., 2006 V0.25P F71805 Base Address High Register  Index 60h Bit Name R/W Default R/W 03h Description The MSB of Parallel Port base address. 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W 78h Description The LSB of Parallel Port base address. 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 7h Reserved. Select the IRQ channel for Parallel Port. Description 7-4 Reserved 3-0 SELPRTIRQ DMA Channel Select Register  Index 74h Bit 4 3 Name ECP_DMA_MODE Reserved R/W Default R/W R/W 0 0 0 011 Reserved. 0: non-burst mode DMA. 1: enable burst mode DMA. Reserved. Select the DMA channel for Parallel Port. Description 7-5 Reserved 2-0 SELPRTDMA PRT Mode Select Register  Index F0h Bit 7 Name Reserved R/W Default R/W R/W 1000 010 Reserved. ECP FIFO threshold. 000: Standard and Bi-direction (SPP) mode. 001: EPP 1.9 and SPP mode. 010: ECP mode (default). 011: ECP and EPP 1.9 mode. 100: Printer mode. 101: EPP 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP1.7 mode. Description 6-3 ECP_FIFO_THR 2-0 PRT_MODE 7.5.3 Device Registers 7.5.3.1 Bit 7-0 DATA Parallel Port Data Register  Base + 0 Name R/W Default R/W 00h Description The output data to drive the parallel port data lines. 51 Dec., 2006 V0.25P F71805 ECP Address FIFO Register  Base + 0 Name R/W Default R/W 00h Description Access only in ECP Parallel Port Mode and the ECP_MODE programmed in the Extended Control Register is 011. The data written to this register is placed in the FIFO and tagged as an Address/RLE. It is auto transmitted by the hardware. The operation is only defined for forward direction. It divide into two parts : Bit 7 : 0: bits 6-0 are run length, indicating how many times the next byte to appear (0 = 1time, 1 = 2times, 2 = 3times and so on). 1: bits 6-0 are a ECP address. Bit 6-0 : Address or RLE depends on bit 7. 7.5.3.2 Bit 7-0 ECP_AFIFO 7.5.3.3 Bit 7 6 5 4 3 Device Status Register  Base + 1 Name R/W Default R R R R R R R 11 Description Inverted version of parallel port signal BUSY. Version of parallel port signal ACK#. Version of parallel port signal PE. Version of parallel port signal SLCT. Version of parallel port signal ERR#. Reserved. Return 11b when read. This bit is valid only in EPP mode. Return 1 when in other modes. It indicates that a 10uS time out has occurred on the EPP bus. 0: no time out error. 1: time out error occurred, write 1 to clear. BUSY_N ACK_N PERROR SELECT ERR_N 2-1 Reserved 0 TMOUT 7.5.3.4 Bit 5 DIR Device Control Register  Base + 2 Name R/W Default R/W 11 0 Description Reserved. Return 11b when read. 0: the parallel port is in output mode. 1: the parallel port is in input mode. It is auto reset to 0 when in SPP mode. Enable an interrupt at the rising edge of ACK#. Inverted and then drives the parallel port signal SLIN#. When read, the status of inverted SLIN# is return. Drives the parallel port signal INIT#. When read, the status of INIT# is return. Inverted and then drives the parallel port signal AFD#. When read, the status of inverted AFD# is return. 7-6 Reserved 4 3 2 1 ACKIRQ_EN SLIN INIT_N AFD R/W R/W R/W R/W 0 0 0 0 52 Dec., 2006 V0.25P F71805 0 STB R/W 0 Inverted and then drives the parallel port signal STB#. When read, the status of inverted STB# is return. 7.5.3.5 Bit 7 EPP Address Register  Base + 3 Name R/W Default R/W 00h Description Write this register will cause the hardware to auto transmit the written data to the device with the EPP Address Write protocol. Read this register will cause the hardware to auto receive data from the device by with the EPP Address Read protocol. EPP_ADDR 7.5.3.6 Bit 7 EPP Data Register  Base + 4 – Base + 7 Name R/W Default R/W 00h Description Write this register will cause the hardware to auto transmit the written data to the device with the EPP Data Write protocol. Read this register will cause the hardware to auto receive data from the device by with the EPP Data Read protocol. EPP_DATA 7.5.3.7 Bit Parallel Port Data FIFO  Base + 400h Name R/W Default R/W 00h Description Data written to this FIFO is auto transmitted by the hardware to the device by using standard parallel port protocol. It is only valid in ECP and the ECP_MODE is 010b.The operation is only for forward direction. 7-0 C_FIFO 7.5.3.8 Bit ECP Data FIFO  Base + 400h Name R/W Default R/W 00h Description Data written to this FIFO when DIR is 0 is auto transmitted by the hardware to the device by using ECP parallel port protocol. Data is auto read from device into the FIFO when DIR is 1 by the hardware by using ECP parallel port protocol. Read the FIFO will return the content to the system. It is only valid in ECP and the ECP_MODE is 011b. 7-0 ECP_DFIFO 7.5.3.9 Bit ECP Test FIFO  Base + 400h Name R/W Default R/W 00h Description Data may be read, written from system to the FIFO in any Direction. But no hardware handshake occurred on the parallel port lines. It could be used to test the empty, full and threshold of the FIFO. It is only valid in ECP and the ECP_MODE is 110b. 7-0 T_FIFO 7.5.3.10 ECP Configuration Register A  Base + 400h Bit Name R/W Default Description 53 Dec., 2006 V0.25P F71805 7 IRQ_MODE R 0 0: interrupt is ISA pulse. 1: interrupt is ISA level. Only valid in ECP and ECP_MODE is 111b. 000: the design is 16-bit implementation. 001: the design is 8-bit implementation (default). 010: the design is 32-bit implementation. 011-111: Reserved. Only valid in ECP and ECP_MODE is 111b. Reserved. 0: when transmitting there is 1 byte waiting in the transceiver that does not affect the FIFO full condition. 1: when transmitting the state of the full bit includes the byte being transmitted. Only valid in ECP and ECP_MODE is 111b. Return 00 when read. Only valid in ECP and ECP_MODE is 111b. 6-4 IMPID R 001 3 2 Reserved BYTETRAN_N R R 1 1-0 Reserved R 00 7.5.3.11 ECP Configuration Register B  Base + 401h Bit 7 COMP Name R/W Default R 0 Description 0: only send uncompressed data. 1: compress data before sending. Only valid in ECP and ECP_MODE is 111b. Reserved. Return 1 when read. Only valid in ECP and ECP_MODE is 111b. 000: the interrupt selected with jumper. 001: select IRQ 7 (default). 010: select IRQ 9. 011: select IRQ 10. 100: select IRQ 11. 101: select IRQ 14. 110: select IRQ 15. 111: select IRQ 5. Only valid in ECP and ECP_MODE is 111b. Return the DMA channel of ECP parallel port. Only valid in ECP and ECP_MODE is 111b. 6 Reserved R R 1 001 5-3 ECP_IRQ_CH 2-0 ECP_DMA_CH R 011 7.5.3.12 Extended Control Register  Base + 402h Bit Name R/W Default R/W 000 Description 000: SPP Mode. 001: PS/2 Parallel Port Mode. 010: Parallel Port Data FIFO Mode. 011: ECP Parallel Port Mode. 100: EPP Mode. 101: Reserved. 110: Test Mode. 111: Configuration Mode. Only valid in ECP. 7-5 ECP_MODE 54 Dec., 2006 V0.25P F71805 4 3 2 ERRINTR_EN DAMEN SERVICEINTR R/W R/W R/W 0 0 1 0: disable the interrupt generated on the falling edge of ERR#. 1: enable the interrupt generated on the falling edge of ERR#. 0: disable DMA. 1: enable DMA. DMA starts when SERVICEINTR is 0. 0: enable the following case of interrupt. DMAEN = 1: DMA mode. DMAEN = 0, DIR = 0: set to 1 whenever there are writeIntrThreshold or more bytes are free in the FIFO. DMAEN = 0, DIR = 0: set to 1 whenever there are readIntrThreshold or more bytes are valid to be read in the FIFO. 0: The FIFO has at least 1 free byte. 1: The FIFO is completely full. 0: The FIFO contains at least 1 byte. 1: The FIFO is completely empty. 1 0 FIFOFULL FIFOEMPTY R R 0 0 7.6 Hardware Monitor Register 7.6.1 Logic Device Number Registers Logic Device Number Register  Index 07h Bit 7-0 LDN Name R/W Default R/W 00h Description 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 06h: Select GPIO device configuration registers. 0ah: Select PME device configuration registers. Otherwise: reserved. 7.6.2 Hardware Monitor Configuration Registers Hardware Monitor Device Enable Register  Index 30h Bit Name R/W Default R/W 0 Reserved 0: disable Hardware Monitor. 1: enable Hardware Monitor. Description 7-1 Reserved 0 HM_EN 55 Dec., 2006 V0.25P F71805 Base Address High Register  Index 60h Bit Name R/W Default R/W 02h Description The MSB of Hardware Monitor base address. 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W 95h Description The LSB of Hardware Monitor base address. 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 0h Reserved. Select the IRQ channel for Hardware Monitor. Description 7-4 Reserved 3-0 SELHMIRQ 7.6.3 Device Registers 7.6.3.1 Bit 7 6 0 INIT SOFT_PWDN START START_STOP Control Register  Index 00h Name R/W Default R/W R/W R R/W 0 0 1 Description Set one restores power on default value to all registers. This bit clears itself since the power on default is zero. Set this bit to 1 will power down A/D converter circuit. Default is 0. Read back will be 0. A one enables startup of monitoring operations; a zero puts the part in standby mode. 5-1 Reserved 7.6.3.2 Bit Temperature Mode Control Register  Index 01h Name R/W Default R/W R R/W 00 1 Description This value stands for how many times of successive temperature fault can be tolerated. 00: 1 times. 01: 2 times. 10: 4 times. 11: 8 times. Read back data will be “0”. Set to 1, enable COMB filter. Set to 0, disable COMB filter. COMB filter is only applied to BJT thermal diode mode. If temperature select thermistor mode, the COMB filter will not work on it. 7-6 Temperature Fault Queue 5-4 Reserved 3 COMB_LEVEL 56 Dec., 2006 V0.25P F71805 2 T3_MODE R/W 0 Set to 1, select T3 as connected to a BJT thermal diode. At this mode, T3 detected temperature ranges from 0°C ~ 140°C, not considering the T3OFFSET(index 92h) effect. Set to 0, select T3 as connected to a thermistor. At this mode, T3 detected temperature ranges from 0°C ~ 127°C, not considering the T3OFFSET(index 92h) effect. Set to 1, select T2 as connected to a BJT thermal diode. At this mode, T2 detected temperature ranges from 0°C ~ 140°C, not considering the T2OFFSET(index 91h) effect. Set to 0, select T2 as connected to a thermistor. At this mode, T2 detected temperature ranges from 0°C ~ 127°C, not considering the T2OFFSET(index 91h) effect. Set to 1, select T1 as connected to a BJT thermal diode. At this mode, T1 detected temperature ranges from 0°C ~ 140°C, not considering the T1OFFSET(index 90h) effect. Set to 0, select T1 as connected to a thermistor. At this mode, T1 detected temperature ranges from 0°C ~ 127°C, not considering the T1OFFSET(index 90h) effect. 1 T2_MODE R/W 0 0 T1_MODE R/W 0 7.6.3.3 Bit ADC_CLK Frequency Control Register  Index 02h Name R/W Default R/W R/W 00 Select ADC clock frequency. 00 : 12.8K(Default) 01 : 6.4K 10 : 3.2K 11 : 1.6K Description 7-2 Reserved 1-0 ADC_CLK_SEL 7.6.3.4 Bit External BJT Offset Register  Index 09h Name R/W Default R/W 37h Description 7-0 Reserved 7.6.3.5 Bit FAN1 Full Speed Count Register 0  Index 0Ah Name R/W Default R 0Fh Description When power on, the FANPWM1 will output full duty cycle (FFh) to enable system FAN. After 10 seconds when detecting FANIN signal, assuming the fan has been fully turned on, the fan speed count detected will be recorded in the register. If there is no signal on FANIN after power on, the PWMOUT1 will keep outputting FFh duty cycle. 7-0 F1_FULL(MSB) 7.6.3.6 Bit FAN1 Full speed Count Register 1 Index 0Bh Name R/W Default Description 57 Dec., 2006 V0.25P F71805 7-0 F1_FULL(LSB) R FFh When power on, the FANPWM1 will output full duty cycle (FFh) to enable system FAN. After 10 seconds when detecting FANIN signal, assuming the fan has been fully turned on, the fan speed count detected will be recorded in the register. If there is no signal on FANIN after power on, the PWMOUT1 will keep outputting FFh duty cycle. 7.6.3.7 Bit FAN2 Full Speed Count Register 0  Index 0Ch Name R/W Default R 0Fh Description When power on, the FANPWM2 will output full duty cycle (FFh) to enable system FAN. After 10 seconds when detecting FANIN signal, assuming the fan has been fully turned on, the fan speed count detected will be recorded in the register. If there is no signal on FANIN2 after power on, the PWMOUT2 will keep outputting FFh duty cycle. 7-0 F2_FULL(MSB) 7.6.3.8 Bit FAN2 Full speed Count Register 1 Index 0Dh Name R/W Default R FFh Description When power on, the FANPWM2 will output full duty cycle (FFh) to enable system FAN. After 10 seconds when detecting FANIN signal, assuming the fan has been fully turned on, the fan speed count detected will be recorded in the register. If there is no signal on FANIN1 after power on, the PWMOUT2 will keep outputting FFh duty cycle. 7-0 F2_FULL(LSB) 7.6.3.9 Bit FAN3 Full Speed Count Register 0  Index 0Eh Name R/W Default R 0Fh Description When power on, the FANPWM3 will output full duty cycle (FFh) to enable system FAN. After 10 seconds when detecting FANIN signal, assuming the fan has been fully turned on, the fan speed count detected will be recorded in the register. If there is no signal on FANIN2 after power on, the PWMOUT3 will keep outputting FFh duty cycle. 7-0 F3_FULL(MSB) 7.6.3.10 FAN3 Full speed Count Register 1 Index 0Fh Bit Name R/W Default R FFh Description When power on, the FANPWM3 will output full duty cycle (FFh) to enable system FAN. After 10 seconds when detecting FANIN signal, assuming the fan has been fully turned on, the fan speed count detected will be recorded in the register. If there is no signal on FANIN3 after power on, the PWMOUT3 will keep outputting FFh duty cycle. 7-0 F3_FULL(LSB) 7.6.3.11 Value RAM  Index 10h - 2Fh, 40h - 59h In the following table, the unit of voltage reading/limit is 8mV. The unit of temperature reading/limit is 1ºC. Address 10-3F 0Ah R/W RO Description FAN1 full speed count reading [11:8] 58 Dec., 2006 V0.25P F71805 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 20h 21h 22h 23h 24h 25h 26h ~ 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h RO RO RO RO RO RO RO RO RO RO RO RO RO RO FAN1 full speed count reading [7:0] FAN2 full speed count reading [11:8] FAN2 full speed count reading [7:0] FAN3 full speed count reading [11:8] FAN3 full speed count reading [7:0] VCC reading. This reading is the divided voltage of VCC inside the chip. VIN1 reading. VIN2 reading. VIN3 reading. VIN4 reading. VIN5 reading. VIN6 reading. VIN7 reading. VIN8 reading. Reserved Reserved T1 temperature reading. T2 temperature reading. T3 temperature reading. Reserved FAN1 count reading (MSB) FAN1 count reading (LSB) FAN2 count reading (MSB) FAN2 count reading (LSB) FAN3 count reading (MSB) FAN3 count reading (LSB) Reserved FAN1 count limit. (MSB) FAN1 count limit. (LSB) FAN2 count limit. (MSB) FAN2 count limit. (LSB). FAN3 count limit. (MSB) FAN3 count limit. (LSB) Reserved Reserved VCC high limit. This limit should correspond to the divided voltage. VCC low limit. This limit should correspond to the divided voltage. VIN1 high limit. VIN1 low limit. VIN2 high limit. VIN2 low limit. VIN3 high limit. VIN3 low limit. VIN4 high limit. VIN4 low limit. VIN5 high limit. VIN5 low limit. VIN6 high limit. VIN6 low limit. VIN7 high limit. VIN7 low limit. VIN8 high limit. RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 59 Dec., 2006 V0.25P F71805 51h 52h 53h 54h 55h 56h 57h 58h 59h R/W VIN8 low limit. Reserved Reserved T1 high limit. T1 low limit. T2 high limit. T2 low limit. T3 high limit. T3 low limit. R/W R/W R/W R/W R/W R/W 7.6.3.12 INTERRUPT ENABLE Control Register 1  Index 30h Bit 7 6 5 4 3 2 1 0 Name EN_VIN7 EN_VIN6 EN_VIN5 EN_VIN4 EN_VIN3 EN_VIN2 EN_VIN1 EN_3VDD R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description Set to 1, enables VIN7 abnormal interrupt. Set to 1, enables VIN6 abnormal interrupt. Set to 1, enables VIN5 abnormal interrupt. Set to 1, enables VIN4 abnormal interrupt. Set to 1, enables VIN3 abnormal interrupt. Set to 1, enables VIN2 abnormal interrupt. Set to 1, enables VIN1 abnormal interrupt. Set to 1, enables 3VDD abnormal interrupt. 7.6.3.13 INTERRUPT ENABLE Control Register 2  Index 31h Bit Name R/W Default R/W R/W R/W R/W 0 0 0 0 Reserved. Set to 1, enables T3 abnormal interrupt. Set to 1, enables T2 abnormal interrupt. Set to 1, enables T1 abnormal interrupt. Reserved. Reserved. Set to 1, enables VIN8 abnormal interrupt. Description 7-6 Reserved 5 4 3 2 1 0 EN_T3 EN_T2 EN_T1 Reserved Reserved EN_VIN8 7.6.3.14 INTERRUPT ENABLE Control Register 3  Index 32h Bit 7 6 5 4 3 2 Name Reserved Reserved EN_FAN3_TAR EN_FAN2_TAR EN_FAN1_TAR EN_FAN3_LMT R/W Default R/W R/W R/W R/W 0 0 0 0 Reserved. Reserved. Set to 1, enables FAN3 target speed mismatched interrupt when FANPWM3 duty-cycle is 100%. Set to 1, enables FAN2 target speed mismatched interrupt when FANPWM2 duty-cycle is 100%. Set to 1, enables FAN1 target speed mismatched interrupt when FANPWM1 duty-cycle is 100%. Set to 1, enables FAN3 abnormal interrupt. Description 60 Dec., 2006 V0.25P F71805 1 0 EN_FAN2_LMT EN_FAN1_LMT R/W R/W 0 0 Set to 1, enables FAN2 abnormal interrupt. Set to 1, enables FAN1 abnormal interrupt. 7.6.3.15 INTERRUPT STATUS Register 1  Index 33h Bit 7 6 5 4 3 2 1 0 Name VIN7_STS VIN6_STS VIN5_STS VIN4_STS VIN3_STS VIN2_STS VIN1_STS 3VDD_STS R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description A one indicates VIN7 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates VIN6 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates VIN5 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates VIN4 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates VIN3 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates VIN2 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates VIN1 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates 3VDD reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. 7.6.3.16 INTERRUPT STATUS Register 2  Index 34h Bit Name R/W Default R/W R/W R/W R/W 0 0 0 0 Reserved. A one indicates T3 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates T2 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates T1 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. Reserved. Reserved. A one indicates VIN8 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. Description 7-6 Reserved 5 4 3 2 1 0 T3_STS T2_STS T1_STS Reserved Reserved VIN8_STS 7.6.3.17 INTERRUPT STATUS Register 3  Index 35h Bit 7 6 5 Name Reserved Reserved FAN3_TAR_STS R/W Default R/W 0 Reserved. Reserved. A one indicates FAN3 can not reach the expect count in time. The time is defined by FAN3 Fault Time registers. Description 61 Dec., 2006 V0.25P F71805 4 3 2 1 0 FAN2_TAR_STS FAN1_TAR_STS FAN3_STS FAN2_STS FAN1_STS R/W R/W R/W R/W R/W 0 0 0 0 0 A one indicates FAN2 can not reach the expect count in time. The time is defined by FAN2 Fault Time registers. A one indicates FAN1 can not reach the expect count in time. The time is defined by FAN1 Fault Time registers. A one indicates FAN3 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates FAN2 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates FAN1 reaches its high or low limit. Write 1 to clear this bit, write 0 will be ignored. 7.6.3.18 REAL_TIME STATUS Register 1  Index 36h Bit 7 6 5 4 3 2 1 0 Name VIN7_RT VIN6_RT VIN5_RT VIN4_RT VIN3_RT VIN2_RT VIN1_RT 3VDD_RT R/W Default R R R R R R R R 0 0 0 0 0 0 0 0 Description A one indicates VIN7 is at abnormal range. A one indicates VIN6 is at abnormal range. A one indicates VIN5 is at abnormal range. A one indicates VIN4 is at abnormal range. A one indicates VIN3 is at abnormal range. A one indicates VIN2 is at abnormal range. A one indicates VIN1 is at abnormal range. A one indicates 3VDD is at abnormal range. 7.6.3.19 REAL_TIME STATUS Register 2  Index 37h Bit Name R/W Default R R R R 0 0 0 0 Reserved. A one indicates T3 exceeds its high limit. A one indicates T2 exceeds its high limit. A one indicates T1 exceeds its high limit. Reserved. Reserved. A one indicates VIN8 exceeds its high limit. Description 7-6 Reserved 5 4 3 2 1 0 T3_RT T2_RT T1_RT Reserved Reserved VIN8_RT 7.6.3.20 REAL_TIME STATUS Register 3  Index 38h Bit 7 6 5 Name Reserved Reserved FAN3_TAR_RT R/W Default R 0 Reserved. Reserved. A one indicates FAN3 can not reach the expect count in time when FANPWM3 duty-cycle is 100%. The time is defined by FAN3 Fault Time registers. After FAN3 reaches the expect count, the bit will be set to 0. A one indicates FAN2 can not reach the expect count in time when FANPWM2 duty-cycle is 100%. The time is defined by FAN2 Fault Time registers. After FAN2 reaches the expect count, the bit will be set to 0. Description 4 FAN2_TAR_RT R 0 62 Dec., 2006 V0.25P F71805 3 FAN1_TAR_RT R 0 A one indicates FAN1 can not reach the expect count in time when FANPWM1 duty-cycle is 100%. The time is defined by FAN1 Fault Time registers. After FAN1 reaches the expect count, the bit will be set to 0. A one indicates FAN3 is at abnormal range. A one indicates FAN2 is at abnormal range. A one indicates FAN1 is at abnormal range. 2 1 0 FAN3_RT FAN2_RT FAN1_RT R R R 0 0 0 7.6.3.21 VIN_FAULT Mode Register 3  Index 39h Bit 7 Name VIN7F_SEL R/W Default R/W 0 Description Set to 1, VIN7_ID value will not change until REG 3Ah Bit7 is cleared if that bit is set. Set to 0, VIN7_ID value changes dynamically according to current voltage which falls on which segments (REGD0h ~ REGD6h). Reserved. Set to 1, once VIN4_FAULT is asserted, it will not be de-asserted when VIN4 is back to normal range. Set to 0, VIN4_FAULT is asserted/de-asserted according to its value whether is out of high/low limit. Set to 1, once VIN3_FAULT is asserted, it will not be de-asserted when VIN4 is back to normal range. Set to 0, VIN3_FAULT is asserted/de-asserted according to its value whether is out of high/low limit. Set to 1, once VIN2_FAULT is asserted, it will not be de-asserted when VIN4 is back to normal range. Set to 0, VIN2_FAULT is asserted/de-asserted according to its value whether is out of high/low limit. Set to 1, once VIN1_FAULT is asserted, it will not be de-asserted when VIN4 is back to normal range. Set to 0, VIN1_FAULT is asserted/de-asserted according to its value whether is out of high/low limit. 6-4 Reserved 3 VIN4F_SEL R 0 2 VIN3F_SEL R 0 1 VIN2F_SEL R 0 0 VIN1F_SEL R 0 7.6.3.22 VIN_FAULT STATUS Register  Index 3Ah Bit 7 3 2 1 0 Name STS_VIN7_CHG STS_VIN4_FAULT STS_VIN3_FAULT STS_VIN2FAULT STS_VIN1_FAULT R/W Default R/W R/W R/W R/W R/W 0 0 0 0 0 Description Read one indicates that the VIN7_ID is changed. Write 1 to clear this status. Reserved. Read one status. Read one status. Read one status. Read one status. indicates that VIN4 is out of its high/low limit. Write 1 to clear this indicates that VIN3 is out of its high/low limit. Write 1 to clear this indicates that VIN2 is out of its high/low limit. Write 1 to clear this indicates that VIN1 is out of its high/low limit. Write 1 to clear this 6-4 Reserved 7.6.3.23 T_FAULT Control Register  Index 3Bh Bit Name R/W Default Reserved. Description 7-3 Reserved 63 Dec., 2006 V0.25P F71805 2 1 0 EN_T3_FAULT EN_T2_FAULT EN_T1_FAULT R/W R/W R/W 0 0 0 Set to 1, enable temperature 3(VT3)fault through pin OVT_N. Set to 1, enable temperature 2(VT2) fault through pin OVT_N. Set to 1, enable temperature 1(VT1) fault through pin OVT_N. 7.6.3.24 Reserved Register  Index 3Ch Bit Name R/W Default Reserved. Description 7-0 Reserved 7.6.3.25 FAN1 OPERATING Control Register -- Index 60h Bit 7 6 5 Name FAN1_SKIP Reserved R/W Default R 0 Description When this bit is set to 1, FAN1 is not monitored. When this bit is set to 0, FAN1 is monitored. Reserved. Set to 1, FAN1 speed is monitored every monitor cycle even the fan is stopped. Set to 0, FAN1 speed will not be monitored at the next monitor cycle if the fan is stopped. Set to 1, FAN1 control is set to DC mode. Set to 0, FAN1 control is set to PWM duty-cycle mode. Set to 1, current FAN1 COUNT will be bypass to FAN1_FULL_SPEED. Set to 1, keep FANPWM1 duty-cycle decrease to STOP DUTY and hold. 00: FAN1 operates in SPEED mode. FANPWM duty-cycle is automatically adjusted according to FAN EXPECT register. 01: FAN1 operates in TEMPERATURE mode. FANPWM duty-cycle is automatically adjusted according to current temperature, 1x: FAN1 operates in MANUAL mode. Software set the FANPWM duty-cycle directly. FAN1_FORCE_MONI R/W TOR FAN1_DC_MODE F1_LATCH_FULL F1_KEEP_STOP R/W R/W R/W R/W 4 3 2 0 0 0 00 1-0 F1_MODE 7.6.3.26 FANPWM1 START UP DUTY-CYCLE  Index 61h Bit 7-0 Name R/W Default 30h Description FANPWM1 will increasing duty-cycle from 0 to this valuedirectly. F1_START_DUTY[9:2] R/W 7.6.3.27 FANPWM1 STOP DUTY-CYCLE  Index 62h Bit Name R/W Default R/W 25h Description FANPWM1 will decreasing duty-cycle to 0 from this value directly or keep duty-cycle in this value when FAN1_KEEP_STOP set to 1. 7-0 F1_STOP_DUTY[9:2] 7.6.3.28 FANPWM1 Output Frequency Control  Index 63h Bit Name R/W Default Description 64 Dec., 2006 V0.25P F71805 7 PWM1_DIV[7] R/W R/W 80h 6-0 PWM1_DIV[6:0] Set to 1, PRECLK(Pre-Clock) = 48M Hz ; Set to 0, PRECLK = 1M Hz . Pre-divisor of PRECLK. Set the value to 0 Pre-divisor =1 Set the value to 1 Pre-divisor =1 Set the value to 2 Pre-divisor =2 Set the value to 3 Pre-divisor =3 ………………. FANPWM1 output frequency = PRECLK (Pr e - divisor ) ∗ 256 So, PWM frequency ranges from 30.5Hz~ 187.5KHz 7.6.3.29 FANPWM1 STEP Control Register -- Index 64h Bit 7-4 3-0 Name F1_UP_STEP F1_DOWN_STEP R/W Default R/W R/W 00h Description This value determines the increasing speed of PWM1_DUTY. This value determines the decreasing speed of PWM1_DUTY. 7.6.3.30 FAN1_FAULT TIME Register  Index 65h Bit Name R/W Default R/W 03h Description This register determines the time for fan to chase to the expect speed. Two conditions cause fan fault event: (1). When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan expect count in the time. (2). When PWM_Duty reaches 00h, if the fan speed count can’t reach the fan expect count in the time. The unit of this register is 1 second. The default value is 3 seconds. 7-0 F1_FAULT_TIME 7.6.3.31 FAN1 Expect count Register---Index 69h Bit Name R/W Default R 00h Description User expect fan1 count value, program this register to control the expect fan1 speed 7-4 Reserved 3-0 F1_EXPECT (MSB) 7.6.3.32 FAN1 Expect count Register-- Index 6Ah PBit Name R/W Default R 00h Description User expect fan1 count value, program this register to control the expect fan1 speed. 7-0 F1_EXPECT (LSB) 7.6.3.33 FAN1 PWM_DUTY -- Index 6Bh Bit Name R/W Default Description 65 Dec., 2006 V0.25P F71805 7-0 PWM_DUTY1 R/W FFh When FAN1 control is at PWM Duty-cycle mode, this value represents the duty-cycle. When FAN1 control is at DC mode, this value represents the DC voltage output. Each step (LSB) is VCC / 256. This register is programmable at Manual mode. At SPEED or TEMPERATURE mode, this register reflects current FANPWM1 duty-cycle. 7.6.3.34 FAN2 OPERATING Control Register -- Index 70h Bit 7 6 5 Name FAN2_SKIP Reserved R/W Default R 0 Description When this bit is set to 1, FAN2 is not monitored. When this bit is set to 0, FAN2 is monitored. Reserved. Set to 1, FAN2 speed is monitored every monitor cycle even the fan is stopped. Set to 0, FAN2 speed will not be monitored at the next monitor cycle if the fan is stopped. Set to 1, FAN2 control is set to DC mode. Set to 0, FAN2 control is set to PWM duty-cycle mode. Set to 1, current FAN2 COUNT will be bypass to F2_FULL_SPEED. Set to 1, keep FANPWM2 duty-cycle decrease to STOP DUTY and hold. 00: FAN2 operates in SPEED mode. FANPWM duty-cycle is automatically adjusted according to FAN EXPECT register. 01: FAN2 operates in TEMPERATURE mode. FANPWM duty-cycle is automatically adjusted according to current temperature, 1x: FAN2 operates in MANUAL mode. Software set the FANPWM duty-cycle directly. FAN2_FORCE_MONI R/W TOR FAN2_DC_MODE R/W R/W R/W R/W 4 0 0 0 00 3 F2_LATCH_FULL 2 F2_KEEP_STOP 1-0 F2_MODE 7.6.3.35 FANPWM2 START UP DUTY-CYCLE  Index 71h Bit Name R/W Default R/W 30h Description FANPWM2 will increase duty-cycle from 0 to this value directly. 7-0 F2_START_DUTY 7.6.3.36 FANPWM2 STOP DUTY-CYCLE  Index 72h Bit Name R/W Default R/W 25h Description FANPWM2 will decreasing duty-cycle to 0 from this value directly or keep duty-cycle in this value when F2_KEEP_STOP set to 1. 7-0 F2_STOP_DUTY 7.6.3.37 FANPWM2 Output Frequency Control  Index 73h Bit 7 Name PWM2_DIV[7] R/W Default R/W 80h Description Set to 1, PRECLK(Pre-Clock) = 48M Hz ; Set to 0, PRECLK = 1M Hz . 66 Dec., 2006 V0.25P F71805 6-0 PWM2_DIV[6:0] R/W Pre-divisor of PRECLK. Set the value to 0 Pre-divisor =1 Set the value to 1 Pre-divisor =1 Set the value to 2 Pre-divisor =2 Set the value to 3 Pre-divisor =3 ………………. FANPWM2 output frequency = PRECLK (Pr e − divisor ) ∗ 256 So, PWM frequency ranges from 30.5Hz~ 187.5KHz 7.6.3.38 FANPWM2 STEP Control Register -- Index 74h Bit Name R/W Default R/W R/W 00h Description This value determines the increasing speed of PWM2_DUTY. This value determines the decreasing speed of PWM2_DUTY 7-4 F2_UP_STEP 3-0 F2_DOWN_STEP 7.6.3.39 FAN2_FAULT TIME Register  Index 75h Bit Name R/W Default R/W 03h Description This register determines the time for fan to chase to the expect speed. Two conditions cause fan fault event: (1). When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan expect count in the time. (2). When PWM_Duty reaches 00h, if the fan speed count can’t reach the fan expect count in the time. The unit of this register is 1 second. The default value is 180 seconds. 7-0 F2_FAULT_TIME 7.6.3.40 FAN2 Expect count Register-- Index 79h Bit Name R/W Default R 00h Description Reserved. User expect fan2 count value, program this register to control the expect fan2 speed 7-4 Reserved 3-0 F2_EXPECT (MSB) 7.6.3.41 FAN2 Expect count Register-- Index 7Ah Bit Name R/W Default R 00h Description User expect fan2 count value, program this register to control the expect fan2 speed. 7-0 F2_EXPECT (LSB) 7.6.3.42 FAN2 PWM_DUTY Bit Name -- Index 7Bh Description R/W Default 67 Dec., 2006 V0.25P F71805 7-0 PWM_DUTY2 R/W FFh When FAN2 control is at PWM Duty-cycle mode, this value represents the duty-cycle. When FAN2 control is at DC mode, this value represents the DC voltage output. Each step (LSB) is VCC / 256. This register is programmable at Manual mode. At SPEED or TEMPERATURE mode, this register reflects current FANPWM1 duty-cycle. 7.6.3.43 FAN3 OPERATING Control Register -- Index 80h Bit 7 6 5 Name FAN3_SKIP Reserved R/W Default R 0 Description When this bit is set to 1, FAN3 is not monitored. When this bit is set to 0, FAN3 is monitored. Reserved. Set to 1, FAN3 speed is monitored every monitor cycle even the fan is stopped. Set to 0, FAN3 speed will not be monitored at the next monitor cycle if the fan is stopped. Set to 1, FAN3 control is set to DC mode. Set to 0, FAN3 control is set to PWM duty-cycle mode. Set to 1, current FAN3 COUNT will be bypass to F3_FULL_SPEED. Set to 1, keep FANPWM3 duty-cycle decrease to STOP DUTY and hold. 00: FAN3 operates in SPEED mode. FANPWM3 duty-cycle is automatically adjusted according to FAN EXPECT register. 01: FAN3 operates in TEMPERATURE mode. FANPWM3 duty-cycle is automatically adjusted according to current temperature, 1x: FAN3 operates in MANUAL mode. Software set the FANPWM3 duty-cycle directly. FAN3_FORCE_MONI R/W TOR FAN3_DC_MODE F3_LATCH_FULL F3_KEEP_STOP F3_MODE R/W R/W R/W R/W 4 3 2 1-0 0 0 0 00 7.6.3.44 FANPWM3 START UP DUTY-CYCLE  Index 81h Bit Name R/W Default R/W 30h Description FANPWM3 will increase duty-cycle from 0 to this value directly. 7-0 F3_START_DUTY 7.6.3.45 FANPWM3 STOP DUTY-CYCLE  Index 82h Bit Name R/W Default R/W 25h Description FANPWM3 will decreasing duty-cycle to 0 from this value directly or keep duty-cycle in this value when F3_KEEP_STOP set to 1. 7-0 F3_STOP_DUTY 7.6.3.46 FANPWM3 Output Frequency Control  Index 83h Bit 7 Name PWM3_DIV[7] R/W Default R/W 80h Description Set to 1, PRECLK(Pre-Clock) = 48M Hz ; Set to 0, PRECLK = 1M Hz . 68 Dec., 2006 V0.25P F71805 6-0 PWM3_DIV[6:0] R/W Pre-divisor of PRECLK. Set the value to 0 Pre-divisor =1 Set the value to 1 Pre-divisor =1 Set the value to 2 Pre-divisor =2 Set the value to 3 Pre-divisor =3 ………………. FANPWM3 output frequency = PRECLK (Pr e − divisor ) ∗ 256 So, PWM frequency ranges from 30.5Hz~ 187.5KHz 7.6.3.47 FANPWM3 STEP Control Register -- Index 84h Bit 7-4 3-0 Name F3_UP_STEP F3_DOWN_STEP R/W Default R/W R/W 00h Description This value determines the increasing speed of PWM3_DUTY. This value determines the decreasing speed of PWM3_DUTY 7.6.3.48 FAN3_FAULT TIME Register  Index 85h Bit Name R/W Default R/W 03h Description This register determines the time for fan to chase to the expect speed. Two conditions cause fan fault event: (1). When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan expect count in the time. (2). When PWM_Duty reaches 00h, if the fan speed count can’t reach the fan expect count in the time. The unit of this register is 1 second. The default value is 180 seconds. 7-0 F3_FAULT_TIME 7.6.3.49 FAN3 Expect count Register-- Index 89h Bit Name R/W Default R 00h Description User expect fan3 count value, program this register to control the expect fan3 speed 7-4 Reserved 3-0 F3_EXPECT (MSB) 7.6.3.50 FAN3 Expect count Register-- Index 8Ah Bit Name R/W Default R 00h Description User expect fan3 count value, program this register to control the expect fan3 speed. 7-0 F3_EXPECT (LSB) 7.6.3.51 FAN3 PWM_DUTY Bit Name -- Index 8Bh Description R/W Default 69 Dec., 2006 V0.25P F71805 7-0 PWM_DUTY3 R/W FFh When FAN3 control is at PWM Duty-cycle mode, this value represents the duty-cycle. When FAN3 control is at DC mode, this value represents the DC voltage output. Each step (LSB) is VCC / 256. This register is programmable at Manual mode. At SPEED or TEMPERATURE mode, this register reflects current FANPWM1 duty-cycle 7.6.3.52 T1 OFFSET Register -- Index 90h Bit Name R/W Default R/W 00h T1 temperature offset register. The real temperature value will be added by this offset and then will be put into temperature reading (Value RAM 1Bh). The offset ranges from -64ºC to 63ºC. 3Fh : +63ºC. 01h : +1ºC. 00h : +0ºC. 7Fh: -1ºC 7Eh: -2ºC 40h: -64ºC Description 7 Reserved 6-0 T1OFFSET 7.6.3.53 T2 OFFSET Register -- Index 91h Bit Name R/W Default R/W 00h T2 temperature offset register. The real temperature value will be added by this offset and then will be put into temperature reading (Value RAM 1Ch). The offset ranges from -64ºC to 63ºC. 3Fh : +63ºC. 01h : +1ºC. 00h : +0ºC. 7Fh: -1ºC 7Eh: -2ºC 40h: -64ºC Description 7 Reserved 6-0 T2OFFSET 7.6.3.54 T3 OFFSET Register -- Index 92h Bit Name R/W Default R/W 00h Description Reserved. T3 temperature offset register. The real temperature value will be added by this offset and then will be put into temperature reading (Value RAM 1Dh). The offset ranges from -64ºC to 63ºC. 3Fh : +63ºC. 01h : +1ºC. 00h : +0ºC. 7Fh: -1ºC 7Eh: -2ºC 40h: -64ºC 7 Reserved 6-0 T3OFFSET 70 Dec., 2006 V0.25P F71805 7.6.3.55 FAN1 CONTROL v.s. TEMPERATURE 1 (INDEX A0 -- AD registers ) T1 BOUNDARY 1 TEMPERATURE – Index A0h Bit Name R/W Default R/W 00h Description The 1st BOUNDARY temperature for T1 in temperature mode. When T1 temperature is exceed this boundary, FAN1 segment 1 speed count registers will be loaded into FAN1 expect count registers. When T1 temperature is below this boundary, FAN1 segment 2 speed count registers will be loaded into FAN1 expect count registers. 7-0 T1_TP_1 T1 BOUNDARY 5 TEMPERATURE – Index A1h Bit Name R/W Default R/W 00h Description The 5th BOUNDARY temperature for T1 in temperature mode. When T1 temperature is exceed this boundary, FAN1 segment 5 speed count registers will be loaded into FAN1 expect count registers. When T1 temperature is below this boundary, FAN1 segment 6 speed count registers will be loaded into FAN1 expect count registers. 7-0 T1_TP_5 T1 BOUNDARY 9 TEMPERATURE – Index A2h Bit Name R/W Default R/W 00h Description The 9th BOUNDARY temperature for T1 in temperature mode. When T1 temperature is exceed this boundary, FAN1 segment 9 speed count registers will be loaded into FAN1 expect count registers. When T1 temperature is below this boundary, FAN1 segment 10 speed count registers will be loaded into FAN1 expect count registers. 7-0 T1_TP_9 FAN1 SEGMENT 1 SPEED COUNT (MSB) – Index A4h Bit Name R/W Default R/W Fh Description The MSB of 1st expected fan speed for FAN1 in temperature mode. 7-4 Reserved 3-0 T1_SP_1_MSB FAN1 SEGMENT 1 SPEED COUNT (LSB) – Index A5h Bit Name R/W Default R/W FFh Description The LSB of 1st expected fan speed for FAN1 in temperature mode. 7-0 T1_SP_1_LSB FAN1 SEGMENT 5 SPEED COUNT (MSB) – Index A6h Bit Name R/W Default R/W Fh Description The MSB of 5th expected fan speed for FAN1 in temperature mode. 7-4 Reserved 3-0 T1_SP_5_MSB 71 Dec., 2006 V0.25P F71805 FAN1 SEGMENT 5 SPEED COUNT (LSB) – Index A7h Bit Name R/W Default R/W FFh Description The LSB of 5th expected fan speed for FAN1 in temperature mode. 7-0 T1_SP_5_LSB FAN1 SEGMENT 9 SPEED COUNT (MSB) – Index A8h Bit Name R/W Default R/W Fh Description The MSB of 9th expected fan speed for FAN1 in temperature mode. 7-4 Reserved 3-0 T1_SP_9_MSB FAN1 SEGMENT 9 SPEED COUNT (LSB) – Index A9h Bit Name R/W Default R/W FFh Description The LSB of 9th expected fan speed for FAN1 in temperature mode. 7-0 T1_SP_9_LSB 7.6.3.56 FAN2 CONTROL v.s. TEMPERATURE 2 (INDEX B0 -- BD registers ) T2 BOUNDARY 1 TEMPERATURE – Index B0h Bit Name R/W Default R/W 00h Description The 1st BOUNDARY temperature for T2 in temperature mode. When T2 temperature is exceed this boundary, FAN2 segment 1 speed count registers will be loaded into FAN2 expect count registers. When T2 temperature is below this boundary, FAN2 segment 2 speed count registers will be loaded into FAN2 expect count registers. 7-0 T2_TP_1 T2 BOUNDARY 5 TEMPERATURE – Index B1h Bit Name R/W Default R/W 00h Description The 5th BOUNDARY temperature for T2 in temperature mode. When T2 temperature is exceed this boundary, FAN2 segment 5 speed count registers will be loaded into FAN2 expect count registers. When T2 temperature is below this boundary, FAN2 segment 6 speed count registers will be loaded into FAN2 expect count registers. 7-0 T2_TP_5 T2 BOUNDARY 9 TEMPERATURE – Index B2h Bit Name R/W Default R/W 00h Description The 9th BOUNDARY temperature for T2 in temperature mode. When T2 temperature is exceed this boundary, FAN2 segment 9 speed count registers will be loaded into FAN2 expect count registers. When T2 temperature is below this boundary, FAN2 segment 10 speed count registers will be loaded into FAN2 expect count registers. 7-0 T2_TP_9 72 Dec., 2006 V0.25P F71805 FAN2 SEGMENT 1 SPEED COUNT (MSB) – Index B4h Bit Name R/W Default R/W Fh Description The MSB of 1st expected fan speed for FAN2 in temperature mode. 7-4 Reserved 3-0 T2_SP_1_MSB FAN2 SEGMENT 1 SPEED COUNT (LSB) – Index B5h Bit Name R/W Default R/W FFh Description The LSB of 1st expected fan speed for FAN2 in temperature mode. 7-0 T2_SP_1_LSB FAN2 SEGMENT 5 SPEED COUNT (MSB) – Index B6h Bit Name R/W Default R/W Fh Description The MSB of 5th expected fan speed for FAN2 in temperature mode. 7-4 Reserved 3-0 T2_SP_5_MSB FAN2 SEGMENT 5 SPEED COUNT (LSB) – Index B7h Bit Name R/W Default R/W FFh Description The LSB of 5th expected fan speed for FAN2 in temperature mode. 7-0 T2_SP_5_LSB FAN2 SEGMENT 9 SPEED COUNT (MSB) – Index B8h Bit Name R/W Default R/W Fh Description The MSB of 9th expected fan speed for FAN2 in temperature mode. 7-4 Reserved 3-0 T2_SP_9_MSB FAN2 SEGMENT 9 SPEED COUNT (LSB) – Index B9h Bit Name R/W Default R/W FFh Description The LSB of 9th expected fan speed for FAN2 in temperature mode. 7-0 T2_SP_9_LSB 7.6.3.57 FAN3 CONTROL v.s. TEMPERATURE 3 ( INDEX C0 -- CD registers ) T3 BOUNDARY 1 TEMPERATURE – Index C0h Bit Name R/W Default R/W 00h Description The 1st BOUNDARY temperature for T3 in temperature mode. When T3 temperature is exceed this boundary, FAN3 segment 1 speed count registers will be loaded into FAN3 expect count registers. When T3 temperature is below this boundary, FAN3 segment 2 speed count registers will be loaded into FAN3 expect count registers. 7-0 T3_TP_1 73 Dec., 2006 V0.25P F71805 T3 BOUNDARY 5 TEMPERATURE – Index C1h Bit Name R/W Default R/W 00h Description The 5th BOUNDARY temperature for T3 in temperature mode. When T3 temperature is exceed this boundary, FAN3 segment 5 speed count registers will be loaded into FAN3 expect count registers. When T3 temperature is below this boundary, FAN3 segment 6 speed count registers will be loaded into FAN3 expect count registers. 7-0 T3_TP_5 T3 BOUNDARY 9 TEMPERATURE – Index C2h Bit Name R/W Default R/W 00h Description The 9th BOUNDARY temperature for T3 in temperature mode. When T3 temperature is exceed this boundary, FAN3 segment 9 speed count registers will be loaded into FAN3 expect count registers. When T3 temperature is below this boundary, FAN3 segment 10 speed count registers will be loaded into FAN3 expect count registers. 7-0 T3_TP_9 FAN3 SEGMENT 1 SPEED COUNT (MSB) – Index C4h Bit Name R/W Default R/W Fh Description The MSB of 1st expected fan speed for FAN3 in temperature mode. 7-4 Reserved 3-0 T3_SP_1_MSB FAN3 SEGMENT 1 SPEED COUNT (LSB) – Index C5h Bit Name R/W Default R/W FFh Description The LSB of 1st expected fan speed for FAN3 in temperature mode. 7-0 T3_SP_1_LSB FAN3 SEGMENT 5 SPEED COUNT (MSB) – Index C6h Bit Name R/W Default R/W Fh Description The MSB of 5th expected fan speed for FAN3 in temperature mode. 7-4 Reserved 3-0 T3_SP_5_MSB FAN3 SEGMENT 5 SPEED COUNT (LSB) – Index C7h Bit Name R/W Default R/W FFh Description The LSB of 5th expected fan speed for FAN1 in temperature mode. 7-0 T3_SP_5_LSB FAN3 SEGMENT 9 SPEED COUNT (MSB) – Index C8h Bit Name R/W Default R/W Fh Description The MSB of 9th expected fan speed for FAN3 in temperature mode. 7-4 Reserved 3-0 T3_SP_9_MSB 74 Dec., 2006 V0.25P F71805 FAN3 SEGMENT 9 SPEED COUNT (LSB) – Index C9h Bit Name R/W Default R/W FFh Description The LSB of 9th expected fan speed for FAN3 in temperature mode. 7-0 T3_SP_9_LSB 7.6.3.58 VIN7 SEGMENT 0 – Index D0h Bit Name R/W Default R/W 00h Description The 1rd mark to denote VIN7’s value. 7-0 VIN7_SEG0 7.6.3.59 VIN7 SEGMENT 1 – Index D1h Bit Name R/W Default R/W 00h Description The 2rd mark to denote VIN7’s value. 7-0 VIN7_SEG1 7.6.3.60 VIN7 SEGMENT 2 – Index D2h Bit Name R/W Default R/W 00h Description The 3rd mark to denote VIN7’s value. 7-0 VIN7_SEG2 7.6.3.61 VIN7 SEGMENT 3 – Index D3h Bit Name R/W Default Description 7-0 VIN7_SEG3 R/W 00h The 4th mark to denote VIN7’s value. 7.6.3.62 VIN7 SEGMENT 4 – Index D4h Bit Name R/W Default Description 7-0 VIN7_SEG4 R/W 00h The 5th mark to denote VIN7’s value. 7.6.3.63 VIN7 SEGMENT 5 – Index D5h Bit Name R/W Default Description 7-0 VIN7_SEG5 R/W 00h The 6th mark to denote VIN7’s value. 7.6.3.64 VIN7 SEGMENT 6 – Index D6h Bit Name R/W Default Description 7-0 VIN7_SEG6 R/W 00h The 7th mark to denote VIN7’s value. 75 Dec., 2006 V0.25P F71805 7.7 GPIO Register 7.7.1 Logic Device Number Register Logic Device Number Register  Index 07h Bit 7-0 LDN Name R/W Default R/W 00h Description 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 06h: Select GPIO device configuration registers. 0ah: Select PME device configuration registers. Otherwise: reserved. 7.7.2 GPIO Configuration Registers 7.7.2.1 Bit IRQ Channel Select Register  Index 70h Name R/W Default R/W 0 0h Reserved. Select the IRQ channel for GP00, GP01, GP02, GP03, GP04, GP05, GP06 and GP07 interrupt. Description 7-4 Reserved 3-0 SELGIOIRQ 7.7.2.2 Bit 7 6 5 4 3 2 1 0 GP0 Output Enable Register  Index E0h Name R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0: GP07 is in input mode. 1: GP07 is in output mode. 0: GP06 is in input mode. 1: GP06 is in output mode. 0: GP05 is in input mode. 1: GP05 is in output mode. 0: GP04 is in input mode. 1: GP04 is in output mode. 0: GP03 is in input mode. 1: GP03 is in output mode. 0: GP02 is in input mode. 1: GP02 is in output mode. 0: GP01 is in input mode. 1: GP01 is in output mode. 0: GP00 is in input mode. 1: GP00 is in output mode. Description GP07_OE GP06_OE GP05_OE GP04_OE GP03_OE GP02_OE GP01_OE GP00_OE 76 Dec., 2006 V0.25P F71805 7.7.2.3 Bit 7 GP0 Output Data Register  Index E1h Name R/W Default R/W 0 Description 0: GP07 outputs 0 when in output mode. 1: GP07 outputs1 when in output mode and GP07_MODE is 0. GP07 outputs a pulse when in output mode and GP07_MODE is 1. Auto clear after the pulse. 0: GP06 outputs 0 when in output mode. 1: GP06 outputs1 when in output mode and GP06_MODE is 0. GP06 outputs a pulse when in output mode and GP06_MODE is 1. Auto clear after the pulse. 0: GP05 outputs 0 when in output mode. 1: GP05 outputs 1 when in output mode and GP05_MODE is 0. GP05 outputs a pulse when in output mode and GP05_MODE is 1. Auto clear after the pulse. 0: GP04 outputs 0 when in output mode. 1: GP04 outputs 1 when in output mode and GP04_MODE is 0. GP04 outputs a pulse when in output mode and GP04_MODE is 1. Auto clear after the pulse. 0: GP03 outputs 0 when in output mode. 1: GP03 outputs 1 when in output mode and GP03_MODE is 0. GP03 outputs a pulse when in output mode and GP03_MODE is 1. Auto clear after the pulse. 0: GP02 outputs 0 when in output mode. 1: GP02 outputs 1 when in output mode and GP02_MODE is 0. GP02 outputs a pulse when in output mode and GP02_MODE is 1. Auto clear after the pulse. 0: GP01 outputs 0 when in output mode. 1: GP01 outputs 1 when in output mode and GP01_MODE is 0. GP01 outputs a pulse when in output mode and GP01_MODE is 1. Auto clear after the pulse. 0: GP00 outputs 0 when in output mode. 1: GP00 outputs 1 when in output mode and GP00_MODE is 0. GP00 outputs a pulse when in output mode and GP00_MODE is 1. Auto clear after the pulse. GP07_VAL 6 GP06_VAL R/W 0 5 GP05_VAL R/W 0 4 GP04_VAL R/W 0 3 GP03_VAL R/W 0 2 GP02_VAL R/W 0 1 GP01_VAL R/W 0 0 GP00_VAL R/W 0 7.7.2.4 Bit 7 6 5 4 3 2 1 0 GP0 Pin Status Register  Index E2h Name R/W Default R R R R R R R R The pin status of GP07. The pin status of GP06/VIN7_ID2. The pin status of GP05/VIN7_ID1. The pin status of GP04/VIN7_ID0. The pin status of GP03/Voltage_fault4. The pin status of GP02/Voltage_fault3. The pin status of GP01/Voltage_fault2. The pin status of GP00/Voltage_fault1. Description GP07_IN GP06_IN GP05_IN GP04_IN GP03_IN GP02_IN GP01_IN GP00_IN 77 Dec., 2006 V0.25P F71805 7.7.2.5 Bit 7 6 5 4 3 2 1 0 GP0 Output Mode Register  Index E3h Name R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: level mode, GP07 output is controlled by GP07_VAL. 1: pulse mode, write GP07_VAL 1 to generate a pulse via GP07. 0: level mode, GP06 output is controlled by GP06_VAL. 1: pulse mode, write GP06_VAL 1 to generate a pulse via GP06. 0: level mode, GP05 output is controlled by GP05_VAL. 1: pulse mode, write GP05_VAL 1 to generate a pulse via GP05. 0: level mode, GP04 output is controlled by GP04_VAL. 1: pulse mode, write GP04_VAL 1 to generate a pulse via GP04. 0: level mode, GP03 output is controlled by GP03_VAL. 1: pulse mode, write GP03_VAL 1 to generate a pulse via GP03. 0: level mode, GP02 output is controlled by GP02_VAL. 1: pulse mode, write GP02_VAL 1 to generate a pulse via GP02. 0: level mode, GP01 output is controlled by GP01_VAL. 1: pulse mode, write GP01_VAL 1 to generate a pulse via GP01. 0: level mode, GP00 output is controlled by GP00_VAL. 1: pulse mode, write GP00_VAL 1 to generate a pulse via GP00. GP07_MODE GP06_MODE GP05_MODE GP04_MODE GP03_MODE GP02_MODE GP01_MODE GP00_MODE 7.7.2.6 Bit GP0 Pulse Width Select 1 Register  Index E4h Name R/W Default R/W 00 GP03 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. GP02 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. GP01 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. GP00 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. Description 7-6 GP03_PW_SEL 5-4 GP02_PW_SEL R/W 00 3-2 GP01_PW_SEL R/W 00 1-0 GP00_PW_SEL R/W 00 7.7.2.7 Bit GP0 Pulse Width Select 2 Register  Index E5h Name R/W Default Description 78 Dec., 2006 V0.25P F71805 7-6 GP07_PW_SEL R/W 00 GP07 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. GP06 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. GP05 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. GP04 pulse width select: 00: 500us (default). 01: 1ms. 10: 20ms. 11: 100ms. 5-4 GP06_PW_SEL R/W 00 3-2 GP05_PW_SEL R/W 00 1-0 GP04_PW_SEL R/W 00 7.7.2.8 Bit 7 GP0 Pulse Mode Register  Index E6h Name R/W Default R/W 0 Description GP07 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. GP06 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. GP05 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. GP04 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. GP03 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. GP02 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. GP01 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. GP07_PUL_MODE 6 GP06_PUL_MODE R/W 0 5 GP05_PUL_MODE R/W 0 4 GP04_PUL_MODE R/W 0 3 GP03_PUL_MODE R/W 0 2 GP02_PUL_MODE R/W 0 1 GP01_PUL_MODE R/W 0 79 Dec., 2006 V0.25P F71805 0 GP00_PUL_MODE R/W 0 GP00 pulse mode: 0: output low pulse when in pulse mode. 1: output high pulse when in pulse mode. 7.7.2.9 Bit 7 GP0 Pad Type Register  Index E7h Name R/W Default R/W 0 GP07 pad type: 0: open drain. 1: push-pull. GP06 pad type: 0: open drain. 1: push-pull. GP05 pad type: 0: open drain. 1: push-pull. GP04 pad type: 0: open drain. 1: push-pull. GP03 pad type: 0: open drain. 1: push-pull. GP02 pad type: 0: open drain. 1: push-pull. GP01 pad type: 0: open drain. 1: push-pull. GP00 pad type: 0: open drain. 1: push-pull. Description GP07_DRV_EN 6 GP06_DRV_EN R/W 0 5 GP05_DRV_EN R/W 0 4 GP04_DRV_EN R/W 0 3 GP03_DRV_EN R/W 0 2 GP02_DRV_EN R/W 0 1 GP01_DRV_EN R/W 0 0 GP00_DRV_EN R/W 0 7.7.2.10 GP0 IRQ Enable Register  Index E8h Bit 7 Name GP07_IRQ_EN R/W Default R/W 0 Description GP07 interrupt enable: 0: disable interrupt. 1: assert an interrupt when GP07 changed in input mode. GP06 interrupt enable: 0: disable interrupt. 1: assert an interrupt when GP06 changed in input mode. GP05 interrupt enable: 0: disable interrupt. 1: assert an interrupt when GP05 changed in input mode. GP04 interrupt enable: 0: disable interrupt. 1: assert an interrupt when GP04 changed in input mode. 6 GP06_IRQ_EN R/W 0 5 GP05_IRQ_EN R/W 0 4 GP04_IRQ_EN R/W 0 80 Dec., 2006 V0.25P F71805 3 GP03_IRQ_EN R/W 0 GP03 interrupt enable: 0: disable interrupt. 1: assert an interrupt when GP03 changed in input mode. GP02 interrupt enable: 0: disable interrupt. 1: assert an interrupt when GP02 changed in input mode. GP01 interrupt enable: 0: disable interrupt. 1: assert an interrupt when GP01 changed in input mode. GP00 interrupt enable: 0: disable interrupt. 1: assert an interrupt when GP00 changed in input mode. 2 GP02_IRQ_EN R/W 0 1 GP01_IRQ_EN R/W 0 0 GP00_IRQ_EN R/W 0 7.7.2.11 GP0 Edge Detect Register  Index E9h Bit 7 Name GP07_EDG R/W Default R/W 0 Description GP07 edge detect: 0: input data does not change. 1: input data changes. Write 1 to clear. GP06 edge detect: 0: input data does not change. 1: input data changes. Write 1 to clear. GP05 edge detect: 0: input data does not change. 1: input data changes. Write 1 to clear. GP04 edge detect: 0: input data does not change. 1: input data changes. Write 1 to clear. GP03 edge detect: 0: input data does not change. 1: input data changes. Write 1 to clear. GP02 edge detect: 0: input data does not change. 1: input data changes. Write 1 to clear. GP01 edge detect: 0: input data does not change. 1: input data changes. Write 1 to clear. GP00 edge detect: 0: input data does not change. 1: input data changes. Write 1 to clear. 6 GP06_EDG R/W 0 5 GP05_EDG R/W 0 4 GP04_EDG R/W 0 3 GP03_EDG R/W 0 2 GP02_EDG R/W 0 1 GP01_EDG R/W 0 0 GP00_EDG R/W 0 7.7.2.12 GP1 Output Enable Register  Index F0h Bit 7 Name GP17_OE R/W Default R/W 0 0: GP17 is in input mode. 1: GP17 is in output mode. Description 81 Dec., 2006 V0.25P F71805 6 5 4 3 2 1 0 GP16_OE GP15_OE GP14_OE GP13_OE GP12_OE GP11_OE GP10_OE R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0: GP16 is in input mode. 1: GP16 is in output mode. 0: GP15 is in input mode. 1: GP15 is in output mode. 0: GP14 is in input mode. 1: GP14 is in output mode. 0: GP13 is in input mode. 1: GP13 is in output mode. 0: GP12 is in input mode. 1: GP12 is in output mode. 0: GP11 is in input mode. 1: GP11 is in output mode. 0: GP10 is in input mode. 1: GP10 is in output mode. 7.7.2.13 GP1 Pin Status Register  Index F1h Bit 7 6 5 4 3 2 1 0 Name GP17_IN GP16_IN GP15_IN GP14_IN GP13_IN GP12_IN GP11_IN GP10_IN R/W Default R R R R R R R R The pin status of FA7/GP17. The pin status of FA6/GP16. The pin status of FA5/GP15. The pin status of FA4/GP14. The pin status of FA3/GP13. The pin status of FA2/GP12. The pin status of FA1/GP11. The pin status of FA0/GP10. Description 7.7.2.14 GP2 Output Enable Register  Index F3h Bit 7 6 5 4 3 2 1 0 Name GP27_OE GP26_OE GP25_OE GP24_OE GP23_OE GP22_OE GP21_OE GP20_OE R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0: GP27 is in input mode. 1: GP27 is in output mode. 0: GP26 is in input mode. 1: GP26 is in output mode. 0: GP25 is in input mode. 1: GP25 is in output mode. 0: GP24 is in input mode. 1: GP24 is in output mode. 0: GP23 is in input mode. 1: GP23 is in output mode. 0: GP22 is in input mode. 1: GP22 is in output mode. 0: GP21 is in input mode. 1: GP21 is in output mode. 0: GP20 is in input mode. 1: GP20 is in output mode. Description 82 Dec., 2006 V0.25P F71805 7.7.2.15 GP2 Pin Status Register  Index F4h Bit 7 6 5 4 3 2 1 0 Name GP27_IN GP26_IN GP25_IN GP24_IN GP23_IN GP22_IN GP21_IN GP20_IN R/W Default R R R R R R R R The pin status of FA17/GP27. The pin status of FA16/GP26. The pin status of FA15/GP25. The pin status of FA14/GP24. The pin status of FA13/GP23. The pin status of FA12/GP22. The pin status of FA11/GP21. The pin status of FA10/GP20. Description 7.8 7.8.1 PME Register Logic Device Number Register Logic Device Number Register  Index 07h Bit 7-0 LDN Name R/W Default R/W 00h Description 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 06h: Select GPIO device configuration registers. 0ah: Select PME device configuration registers. Otherwise: reserved. 7.8.2 PME Configuration Registers Device Enable Register  Index 30h Bit 0 Name PME_EN R/W Default R/W 0 Reserved 0: disable PME. 1: enable PME. Description 7-1 Reserved PME Event Enable Register  Index F0h Bit Name R/W Default Reserved Description 7-5 Reserved 83 Dec., 2006 V0.25P F71805 4 HM_PME_EN R/W 0 Hardware monitor PME event enable. 0: disable hardware monitor PME event. 1: enable hardware monitor PME event. Parallel port PME event enable. 0: disable parallel port PME event. 1: enable parallel port PME event. UART 2 PME event enable. 0: disable UART 2 PME event. 1: enable UART 2 PME event. UART 1 PME event enable. 0: disable UART 1 PME event. 1: enable UART 1 PME event. FDC PME event enable. 0: disable FDC PME event. 1: enable FDC PME event. 3 PRT_PME_EN R/W 0 2 UR2_PME_EN R/W 0 1 UR1_PME_EN R/W 0 0 FDC_PME_EN R/W 0 PME Event Status Register  Index F1h Bit 4 Name HM_PME_ST R/W Default R/W 0 Reserved Hardware monitor PME event status. 0: Hardware monitor has no PME event. 1: Hardware monitor has a PME event to assert. Write 1 to clear to be ready for next PME event. Parallel port PME event status. 0: Parallel port has no PME event. 1: Parallel port has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 2 PME event status. 0: UART 2 has no PME event. 1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 1 PME event status. 0: UART 1 has no PME event. 1: UART 1 has a PME event to assert. Write 1 to clear to be ready for next PME event. FDC PME event status. 0: FDC has no PME event. 1: FDC has a PME event to assert. Write 1 to clear to be ready for next PME event. Description 7-5 Reserved 3 PRT_PME_ST R/W 0 2 UR2_PME_ST R/W 0 1 UR1_PME_ST R/W 0 0 FDC_PME_ST R/W 0 84 Dec., 2006 V0.25P F71805 8. PCB Layout Guide F71805 adopts Current Mode measure method to do temperature detected. The measure data will not be affected by different process of CPU due to use current mode technology. This technology measures mini-voltage from the remote sensor so a good PCB layout must be cared about noise minimizing. The noises often come from circuit trace which is a track from remote sensor (CPU side) to detect circuit input (F71805 side). The signal on this track will be inducted mini-noises when it passes through a high electromagnetic area. Those effects will result in the mini-noises and show in the detected side. It will be reported a wrong data which you want to measure. Please pay attention and follow up the check list below in order to get an actual and real temperature inside the chip. 1. The D1+/D2+/D3+ and AGND (D-) tracks Must Not pass through/by PWM POWER-MOS. Keep as far as possible from POWER MOS. 2. Place a 0.1µF bypass capacitor close to the VCC pin (Pin# 99). Place an external 2200pF input filter capacitors across D+, D- and close to the F71805. Near the pin AGND (D-) Must Be placed a through hole into the GND Plane before connect to the external 2200pF capacitor. 99 VCC VCC F71805F D1+ 89 AGND(D-) 86 0.1uF THERMDA THERMDC From thermal diode 2200pF 3. Place the F71805 as close as practical to the remote sensor diode. In noisy environments, such as a computer main-board, the distance can be 4 to 8 inches. (typ). This length can be increased if the worst noise sources are avoided. Noise sources generally include clock generators, CRTs, memory buses and PCI/ISA bus etc. 4. Separated route the D1+, D2+ or D3+ with AGND (D-) tracks close together and in parallel after adding external 2200pF capacitor. For more reliable, it had better with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. Do not route D+ & D- lines next to the deflection coil of the CRT. And also don’t route the trace across fast digital signals which can easily induce bigger error. GND 10MILS THERMDA(DXP) MINIMUM THERMDC(DXN) 10MILS GND 10MILS 10MILS 85 Dec., 2006 V0.25P F71805 5. Use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended. 6. Try to minimize the number of component/solder joints, called through hole, which can cause thermocouple effects. Where through holes are used, make sure that they are in both the D+ and D- path and at the same temperature. Thermocouple effects should not be a major problem as 1℃ corresponds to about 200µV. It means that a copper-solder thermocouple exhibits 3µV/℃, and takes about 200µV of the voltage error at D+ & D- to cause a 1℃ measurement error. Adding a few thermocouples causes a negligible error. 7. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. It will work up to around 6 to 12 feet. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance will affect the measurement accuracy. When using long cables, the filter capacitor should be reduced or removed. Cable resistance can also induce errors. For example: 1 Ω series resistance introduces about 0.5℃ error. 9. Electrical characteristic 9.1 Absolute Maximum Ratings RATING -0.5 to 5.5 -0.5 to VDD+0.5 0 to +70 -55 to 150 UNIT V V °C °C PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature affect the life and reliability of the device Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely 9.2 DC Characteristics (Ta = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V) (Note) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/OD16ts - TTL level bi-directional pin, can select to OD by register, with 16 mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage VtVt+ 86 V V VDD = 3.3 V VDD = 3.3 V Dec., 2006 V0.25P F71805 Output Low Current Input High Leakage Input Low Leakage IOL ILIH ILIL mA µA µA VOL = 0.4 V VIN = VDD VIN = 0V I/OD12ts - TTL level bi-directional pin, can select to OD by register, with 12 mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Output Low Current Input High Leakage Input Low Leakage VtVt+ IOL ILIH ILIL V V mA µA µA VDD = 3.3 V VDD = 3.3 V VOL = 0.4 V VIN = VDD VIN = 0V 9.3 AC Characteristics Serial Bus Timing PARAMETER SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time SYMBOL t SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF - MIN. MAX. UNIT uS uS uS nS nS uS nS 10. Ordering Information Part Number F71805F F71805FG Package Type 128-QFP (Normal) 128-QFP (Green Package) Production Flow Commercial, 0°C to +70°C Commercial, 0°C to +70°C 87 Dec., 2006 V0.25P F71805 11. Package Dimensions Feature Integration Technology Inc. Headquaters 7F, No 31, Shintai Rd., Jubei City, Hsinchu 302, Taiwan, R.O.C. TEL : 886-3-6562727 FAX : 886-3-6560537 www: http://www.fintek.com.tw Taipei Office Bldg K4, 7F, No. 700, Chung Cheng Rd., Chungho City, Taipei 235, Taiwan, R.O.C. TEL : 886-2-8227-8027 FAX : 886-2-8227-8037 Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner 88 Dec., 2006 V0.25P 12. F71805 Demo Circuit VCC3V No need the Filter OVT# DD3+ D2+ D1+ VREF VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 SLCT PE BUSY + C1 0.1U (GND close to IC) IRRX IRTX PME# FAN_CTL3 FAN_CTL2 FAN_CTL1 FANIN3 FANIN2 FANIN1 VCC_ROM 32 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 22 24 1 31 16 U1 VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE OE VPP PGM GND FLASH ROM 4.7k 0 O0 O1 O2 O3 O4 O5 O6 O7 13 14 15 17 18 19 20 21 FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 FD0 FD1 FD2 FD3 8 6 4 2 VCC_ROM RN1 7 5 3 1 4.7K-8P4R RN2 FD7 FD6 FD5 FD4 8 6 4 2 7 5 3 1 4.7K-8P4R VCC5V VCC_ROM JP1 VCC3V DSKCHG# WPT# INDEX# TRK0# RDATA# WGATE# HDSEL# U2 102 101 100 099 098 097 096 095 094 093 092 091 090 089 088 087 086 085 084 083 082 081 080 079 078 077 076 075 074 073 072 071 070 069 068 067 066 065 3V ROM 5V 1 2 3 HEADER 3 BUSY PE SLCT VCC VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VREF D1+ D2+ D3+ GND/DOVT# N.C4 IRRX IRTX PME# FAN_CTL3 FAN_CTL2 FAN_CTL1 N.C3 N.C2 FAN_TAC3 FAN_TAC2 FAN_TAC1 DSKCHG# WPT# INDEX# TRK0# RDATA# GND WGATE# HDSEL# FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FA8 FA9 FA10 FA11 FA12 FA13 FA14 FA15 FA16 FA17 ACK# SLIN# INIT# ERR# AFD# STB# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD[7..0] DTR2# RTS2# DSR2# VCC SOUT2 SIN2 FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 GND FA0/GP10 FA1/GP11 FA2/GP12 FA3/GP13 FA4/GP14 FA5/GP15 FA6/GP16 FA7/GP17 FA8 FA9 FA10/GP20 FA11/GP21 FA12/GP22 FA13/GP23 FA14/GP24 FA15/GP25 FA16/GP26 FA17/GP27 FRD# VCC LDRQ# SERIRQ LAD0 DCD1# RI1# CTS1# DTR1# RTS1# DSR1# SOUT1 SIN1 DCD2# RI2# CTS2# DTR1# RTS1# SOUT1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 ACK# SLIN# INIT# ERR# AFD# STB# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 GND DCD1# RI1# CTS1# DTR1# RTS1# DSR1# SOUT1 SIN1 DCD2# RI2# CTS2# F71805F F71805 STEP# DIR# WDATA# N.C1 DRVA# FA18 MTRA# DENSEL# GP07 GP06/VIN7_ID2 GP05/VIN7_ID1 GP04/VIN7_ID0 GP03/Voltage_f ault4 GP02/Voltage_f ault3 GP01/Voltage_f ault2 GP00/Voltage_f ault1 FWE# FCS# LFRAME# LRESET# CLKIN GND PCICLK LAD3 LAD2 LAD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 STEP# DIR# WDATA# DRVA# FA18 MTRA# DENSEL# GP06 GP05 GP04 GP03 GP02 GP01 GP00 FWE# FCS# LFRAME# LRESET# CLKIN PCICLK FANCTL GP06 GP05 GP04 GP03 GP02 GP01 GP00 VCC_ROM R4 FA18 R7 FCS# FRD# FWE# VCC5V R1 R2 R3 R5 R6 1K 1K 1K 1K 1K 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 WPT# INDEX# TRK0# RDATA# DSKCHG# J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 ISA INTERFACE ROM 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 DENSEL# INDEX# MTRA# DRVA# DIR# STEP# WDATA# WGATE# TRK0# WPT# RDATA# HDSEL# DSKCHG# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 F71805F DTR2# RTS2# VCC3V DTR2# RTS2# DSR2# SOUT2 SIN2 LAD3 LAD2 LAD1 LAD0 SERIRQ LDRQ# FRD# C2 0.1U VCC3V HEADER 17X2 FLOPPY CONN. FDC SOUT2 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FA8 FA9 FA10 FA11 FA12 FA13 FA14 FA15 FA16 FA17 FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 + FLASH_SEG1_EN FLASH_SEG2_EN FLASH_SEG3_EN PWM XBUS 4E DTR1# RTS1# SOUT1 DTR2# RTS2# SOUT2 + C3 0.1U R8 R9 R10 R11 R12 R13 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K FLASH_SEG1_DIS FLASH_SEG2_DIS FLASH_SEG3_DIS LINEAR RESERVED 2E Title Size B Feature Integration Technology Inc. Document Number F71805F Monday , August 09, 2004 Sheet 1 of 4 Rev 0.11 POWER_ON TRAP PINS Date: 89 Dec., 2006 V0.25P 12V +12V R14 R15 4.7K 8 1K Q2 PNP 4 HEADER 4 3 2 1 JP2 R25 FANCTL VCC5V R26 R27 0 0 10K 4FANCTL D1 1N4148 4FANCTL 3 R16 4.7K R18 27K R21 10K C7 0.1U R24 3.9K FANCTL1 2 U3A + 4 LM358 JP3 R22 10K C5 47u 3 2 1 CON3 C6 NDS0605/SOT Q1 D2 1N4148 R17 4.7K R19 27K 0.1u R23 10K FANIN1 1 FANCTL1 R20 330 C4 Q3 + MOSFET N 2N7002 10U FANIN1 DC FAN Control with OP 1 PWM FAN 1 SPEED CONTROL +12V R28 R29 4.7K 1K Q5 PNP 5 D4 1N4148 JP5 3 2 1 HEADER 3 R31 4.7K R33 27K R37 10K C11 0.1U R38 3.9K FANCTL2 6 8 U3B 12V The C10 is reserved for FAN noise dis-bounce. NDS0605/SOT Q4 D3 1N4148 R30 4.7K JP4 + 4 7 LM358 R35 10K C9 47u 3 2 1 FANCTL2 R34 330 Q6 + MOSFET N 2N7002 10U C8 R32 27K C10 0.1u R36 10K FANIN2 FANIN2 CON3 PWM FAN 2 SPEED CONTROL +12V DC FAN Control with OP 2 12V The C13 is reserved for FAN noise dis-bounce. R39 R40 4.7K 8 1K Q8 PNP D5 1N4148 JP6 3 2 1 HEADER 3 3 R41 4.7K R43 27K R46 10K C15 0.1U R49 3.9K FANCTL3 2 U4A + 4 NDS0605/SOT Q7 D6 1N4148 R42 4.7K JP7 1 LM358 R47 10K C13 47u 3 2 1 FANCTL3 R45 330 Q9 + MOSFET N 2N7002 10U C12 FANIN3 R44 27K C14 0.1u R48 10K FANIN3 CON3 PWM FAN 3 SPEED CONTROL DC FAN Control with OP 3 The C17 is reserved for FAN noise dis-bounce. FAN CONTROL FOR PWM OR DC Title Size B Date: Feature Integration Technology Inc. Document Number FAN Control Monday , August 09, 2004 Sheet 2 of 4 Rev 0.11 90 Dec., 2006 V0.25P R50 VTT1.2V R51 VRAM 10K 100K VIN1 VIN2 VIN1 VIN2 D1+ DD2+ D1+ C16 3300P D+ from CPU D- D2+ C17 3300P Q10 PNP 3906 for SYSTEM R53 VCHIPSET 47K R52 100K VIN3 VIN3 DD3+ D3+ C18 D3300P Q11 PNP 3906 for SYSTEM R55 VCC5V 200K R54 100K VIN4 VIN4 +12V R57 200K R56 R58 47K 20K VIN5 VIN5 DIODE SENSING CIRCUIT RT1 10K 1% (for system) VCC1.5V VCORE R62 R61 200K 10K VIN7 VIN8 VREF VIN7 VIN8 D1+ VREF D2+ R64 47K VREF R60 10K 1% THERMISTOR R63 10K 1% RT2 VSB5V T T T R59 10K VIN6 VIN6 10K 1% (for system) THERMISTOR R65 10K 1% RT3 10K 1% (for system) VOLTAGE SENSING. The best voltage input level is about 1V. D3+ THERMISTOR THERMISTOR SENSING CIRCUIT Temperature Sensing Title Size B Date: Feature Integration Technology Inc Document Number Hardware Monitor Monday , August 09, 2004 Sheet 3 of 4 Rev 0.1 91 Dec., 2006 V0.25P 2 D7 1 VCC5V U5 VCC RY 1 RY 2 RY 3 DA1 DA2 RY 4 DA3 RY 5 GND +12V RA1 RA2 RA3 DY 1 DY 2 RA4 DY 3 RA9 -12V 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 1N5819 FOR LEKAGE TO POWER VCC5V RI1# CTS1# DSR1# RTS1# DTR1# SIN1 SOUT1 DCD1# 20 19 18 17 16 15 14 13 12 11 RN3 RN4 RN5 RN6 1 2 3 4 5 6 7 8 9 10 +12V RIN1 CTSN1 DSRN1 RTSN1 DTRN1 SINN1 SOUTN1 DCDN1 -12V 2.7K-8P4R 2.7K-8P4R 2.7K-8P4R 2.7K-8P4R 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 R66 2.7K RN7 STB# AFD# INIT# SLIN# 1 3 5 7 33-8P4R RN8 PD0 PD1 PD2 PD3 1 3 5 7 33-8P4R RN9 PD4 PD5 PD6 PD7 1 3 5 7 33-8P4R ERR# ACK# BUSY PE SLCT 2 4 6 8 2 4 6 8 2 4 6 8 GND RIN1 DTRN1 CTSN1 SOUTN1 RTSN1 SINN1 DSRN1 DCDN1 5 9 4 8 3 7 2 6 1 P1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 J2 UART DB9 UART VCC5V RI2# CTS2# DSR2# RTS2# DTR2# SIN2 SOUT2 DCD2# 20 19 18 17 16 15 14 13 12 11 U6 VCC RY 1 RY 2 RY 3 DA1 DA2 RY 4 DA3 RY 5 GND +12V RA1 RA2 RA3 DY 1 DY 2 RA4 DY 3 RA9 -12V 1 PORT INTERFACE 1 2 3 4 5 6 7 8 9 10 +12V RIN2 CTSN2 DSRN2 RTSN2 DTRN2 SINN2 SOUTN2 DCDN2 -12V P2 GND RIN2 DTRN2 CTSN2 SOUTN2 RTSN2 SINN2 DSRN2 DCDN2 5 9 4 8 3 7 2 6 1 UART DB9 DB25 (FEMALE) C26 180pC28 180p C19 180p C29 180p C20 180p C30 180p C21 180p C31 180p C22 180p C32 180p C23 180p C33 180p C24 180p C34 180p C25 180p C27 C35 180p 180p UART 2 PORT INTERFACE PARALLEL PORT INTERFACE VCC5V/3V JP8 1 2 3 4 5 C36 0.1U HEADER 5 IRTX IRRX IR INTERFACE Title Size B Date: Feature Integration Technology Inc. Document Number Printer &UART Monday , August 09, 2004 Sheet 4 of 4 Rev 0.1 92 Dec., 2006 V0.25P