F71862FG

F71862 F71862 Super Hardware Monitor + LPC I/O Release Date: July, 2008 Version: V0.28P July, 2008 V0.28P F71862 F71862 Datasheet Revision History Version 0.10P 0.20P 0.21P 0.22P 0.23P 0.24P 0.25P 0.26P 0.27P 0.28P Date 2006/04/21 2006/06/14 2006/11/23 2007/7/6 2007/9/21 2008/1/30 2008/5/2 2008/5/26 2008/7/14 2008/7/21 Page 62 97 104 74 Revision History Preliminary Version Release Version Modified the description of Wakeup Control Register 2Dh bit 7(SPI_CS1_EN) Company readdress Modify typesetting Modify operating temperature Modify power type of pin PWROK description Add register description of ACPI register F4h/F5h bit7 Update application circuit (V0.11P) Add Register of New Function (Index 29h bit4-6) Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. July, 2008 V0.28P F71862 Table of Content 1. 2. 3. 4. 5. 6. 7. 8. General Description ........................................................................................................................5 Feature List .....................................................................................................................................5 Key Specification............................................................................................................................8 Block Diagram ................................................................................................................................8 Pin Configuration............................................................................................................................9 Pin Description................................................................................................................................9 6.1 Power Pin ..................................................................................................................................10 6.2 LPC Interface ............................................................................................................................10 6.3 FDC...........................................................................................................................................10 6.4 UART and SIR ..........................................................................................................................11 6.5 Parallel Port...............................................................................................................................13 6.6 Hardware Monitor.....................................................................................................................14 6.7 ACPI Function Pins ..................................................................................................................15 6.8 VID Controller and Others........................................................................................................16 6.9 KBC Function ...........................................................................................................................16 Function Description.....................................................................................................................18 7.1 Power on Strapping Option.......................................................................................................18 7.2 FDC...........................................................................................................................................18 7.3 UART........................................................................................................................................32 7.4 Parallel Port...............................................................................................................................35 7.5 Keyboard Contoller...................................................................................................................39 7.6 Hardware Monitor.....................................................................................................................41 Configuration Registers ..............................................................................................................49 Voltage Setting ............................................................................................................................51 Temperature Setting ....................................................................................................................52 Fan Control Setting .....................................................................................................................55 Fan1 Index A0h- AFh..................................................................................................................58 Fan2 Index B0h- BFh..................................................................................................................60 Fan3 Index C0h- CFh..................................................................................................................61 7.7 SPI Interface..............................................................................................................................63 7.8 ACPI Function ..........................................................................................................................63 7.9 AMDSI and Intel PECI Function..............................................................................................66 Register Description......................................................................................................................68 July, 2008 V0.28P F71862 8.1 Global Control Registers...........................................................................................................72 8.2 FDC Registers (CR00)..............................................................................................................77 8.3 UART1 Registers (CR01) .........................................................................................................79 8.4 UART 2 Registers (CR02) ........................................................................................................80 8.5 Parallel Port Registers (CR03)..................................................................................................82 8.6 Hardware Monitor Registers (CR04)........................................................................................84 8.7 KBC Registers (CR05) .............................................................................................................85 8.8 GPIO Registers (CR06) ............................................................................................................86 8.9 VID Registers (CR07)...............................................................................................................93 8.10 SPI Registers (CR08)................................................................................................................95 8.11 PME and ACPI Registers (CR0A)............................................................................................98 9. Electron Characteristic................................................................................................................101 9.1 Absolute Maximum Ratings ...................................................................................................101 9.2 DC Characteristics ..................................................................................................................101 9.3 DC Characteristics Continued.................................................................................................101 10. Ordering Information ..................................................................................................................102 11. Package Dimensions ...................................................................................................................103 12. Application Circuit......................................................................................................................104 July, 2008 V0.28P F71862 1. General Description The F71862 is the featured IO chip for PC system. Equipped with one IEEE 1284 Parallel Port, two UART Ports, Hardware Keyboard Controller, Serial Peripheral Interface (SPI), SIR and one FDC. The F71862 integrated with hardware monitor, 9 sets of voltage sensor, 3 sets of creative auto-controlling fans and 3 temperature sensor pins for the accurate dual current type temp. measurement for CPU thermal diode or external transistors 2N3906. Others, the F71862 supports newest AMDSI and Intel PECI interfaces for temperature sensing. The F71862 provides flexible features for multi-directional application. For instance, supports 4-In and 4-Out pins CPU VID controlling with offset implement., provides 30 GPIO pins (multi-pin), IRQ sharing function also designed in UART feature for particular usage and accurate current mode H/W monitor will be worth in measurement of temperature, provides 3 modes fan speed control mechanism included Manual Mode/Stage Auto Mode/Linear Auto Mode for users’ selection. The F71862 also integrated SPI interface. The SPI interface is for BIOS usage including bridge function and back up function. User can implement BIOS data in second flash to boot system when primary BIOS error. These features as above description will help you more and improve product value. Finally, the F71862 is powered by 3.3V voltage, with the LPC interface in the green package of 128-PQFP. 2. Feature List General Functions Comply with LPC Spec. 1.0 Support DPM (Device Power Management), ACPI 4-VIDIN and 4-VIDOUT for Vcore use. Provides one FDC, two UARTs, Hardware KBC and Parallel Port H/W monitor functions SPI interface for BIOS usage Support AMD SID/SIC interface and Intel PECI interface 30 GPIO Pins for flexible application 24/48 MHz clock input Packaged in 128-PQFP and powered by 3.3VCC 5 July, 2008 V.28P F71862 FDC Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and under run conditions Built-in address mark detection circuit to simplify the read electronics Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate UART Two high-speed 16C550 compatible UART with 16-byte FIFOs Fully programmable serial-interface characteristics Baud rate up to 115.2K Support IRQ sharing Infrared Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Parallel Port One PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification Enhanced printer port back-drive current protection Keyboard Controller LPC interface support serial interrupt channel 1, 12. Two 16bit Programmable Address fully decoder, default 0x60 and 0x64. Support two PS/2 interface, one for PS/2 mouse and the other for keyboard. Keyboard’s scan code support set1, set2. Programmable compatibility with the 8042. Support both interrupt and polling modes. Fast Gate A20 and Hardware Keyboard Reset. Hardware Monitor Functions 3 dual current type (±3℃) thermal inputs for CPU thermal diode and 2N3906 transistors 6 July, 2008 V.28P F71862 Temperature range -40℃~127℃ 9 sets voltage monitoring (6 external and 3 internal powers) High limit signal (PME#) for Vcore level 3 fan speed monitoring inputs 3 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans) Stage auto mode ( 2-Limit and 3-Stage)/Linear auto mode/Manual mode Issue PME# and OVT# hardware signals output Case intrusion detection circuit WATCHDOG comparison of all monitored values Serial Peripheral Interface Compatible Support SPI Bridge Function for BIOS use Support Back Up BIOS function Integrate AMD SI Interface Integrate Intel PECI Interface Package 128-pin PQFP Green Package Noted: Patented TW207103 TW207104 TW220442 US6788131 B1 TWI235231 TW237183 TW235553 7 July, 2008 V.28P F71862 3. Key Specification Supply Voltage Operating Supply Current 3.0V to 3.6V 10 mA typ. 4. Block Diagram CPU Chipset (NB+SB) Super H/W Monitor + F71862 IDE USB AC’97 Temperature Voltage Fan AMDSI PECI A KBC IrDA Parallel ACPI SPI I/O LED(GPIO) COM Floppy VID Controller 8 July, 2008 V.28P F71862 5. Pin Configuration 6. Pin Description I/O12t I/OOD12t I/OD16t5v OD16-u10-5v I/OD12ts5v ILv/OD8-S1 ILv/OD12 - TTL level bi-directional pin with 12 mA source-sink cap ability. - TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA source-sink capability. - TTL level bi-directional pin,Open-drain output with 16 mA source-sink capability, 5V tolerance. - Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance. - TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink capability, 5V tolerance. - Low level bi-directional pin (VIH 0.9V, VIL 0.6V.). Output with 8mA drive and 1mA sink capability. - Low level bi-directional pin (VIH 0.9V, VIL 0.6V.). Output with 12mA sink capability. 9 July, 2008 V.28P O8-u47-5v O8 O12 O30 AOUT OD12 OD12-5v OD24 INt5v INts INts5v AIN P - Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance. - Output pin with 8 mA source-sink capability. - Output pin with 12 mA source-sink capability. - Output pin with 30 mA source-sink capability. - Output pin(Analog). - Open-drain output pin with 12 mA sink capability. - Open-drain output pin with 12 mA sink capability, 5V tolerance. - Open-drain output pin with 24 mA sink capability. - TTL level input pin,5V tolerance. - TTL level input pin and schmitt trigger. - TTL level input pin and schmitt trigger, 5V tolerance. - Input pin(Analog). - Power. F71862 6.1 Power Pin Pin Name VCC VSB VBAT AGND(D-) GND Type P P P P P Description Power supply voltage input with 3.3V Stand-by power supply voltage input 3.3V Battery voltage input Analog GND Digital GND Pin No. 4,37,99 68 86 88 20, 48, 73, 117 6.2 Pin No. 29 30 31 32 36-33 LPC Interface Pin Name LRESET# LDRQ# SERIRQ LFRAM# LAD[3:0] Type INts5v O12 I/O12t INts I/O12t PWR VCC VCC VCC VCC VCC Description Reset signal. It can connect to PCIRST# signal on the host. Encoded DMA Request signal. Serial IRQ input/Output. Indicates start of a new cycle or termination of a broken cycle. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. 33MHz PCI clock input. System clock input. According to the input frequency 24/48MHz. 38 39 PCICLK CLKIN INts INts VCC VCC 6.3 Pin No. 7 FDC Pin Name DENSEL# Type OD24 PWR VCC Description Drive Density Select. Set to 1 - High data rate.(500Kbps, 1Mbps) Set to 0 – Low data rate. (250Kbps, 300Kbps) Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. 8 9 MOA# DRVA# OD24 OD24 VCC VCC 10 July, 2008 V.28P F71862 10 WDATA# OD24 VCC 11 DIR# OD24 VCC Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion Step output pulses. This active low open drain output produces a pulse to move the head to another track. Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Write enable. An open drain output. The read data input signal from the FDD. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. Diskette change. This signal is active low at power on and whenever the diskette is removed. 12 13 STEP# HDSEL# OD24 OD24 VCC VCC 14 15 16 WGATE# RDATA# TRK0# OD24 INts5v INts5v VCC VCC VCC 17 INDEX# INts5v VCC 18 19 WPT# DSKCHG# INts5v INts5v VCC VCC 6.4 Pin No. 27 28 118 119 120 121 UART and SIR Pin Name IRTX GPIO42 IRRX GPIO43 DCD1# RI1# CTS1# DTR1# Type O12 I/OOD12t INts I/OOD12t INt5v INt5v INt5v O8-u47,5v PWR VCC VSB VCC VCC VCC VCC Description Infrared Transmitter Output.(Default function) General Purpose IO Infrared Receiver input. (Default function) General Purpose IO. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. Clear To Send is the modem control input. UART 1 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping pin: 1(Default): (Internal pull high) Power on fan speed default duty is 60%.(PWM) 0: (External pull down) Power on fan speed default duty is 100%.(PWM) FAN60_100 INt5v 11 July, 2008 V.28P F71862 122 RTS1# O8-u47,5v VCC UART 1 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Internal 47k ohms pulled high and disable after power on strapping. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART 1 Serial Output. Used to transmit serial data out to the communication link. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping: 1(Default)Configuration register:4E 0 Configuration register:2E Serial Input. Used to receive serial data through the communication link. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. Clear To Send is the modem control input. UART 2 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping : 1(Default): SPI as a backup BIOS 0 : SPI as a primary BIOS UART 2 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping : 1 (Default): Fan control method will be PWM Mode 0 Drive :Fan control method will be DAC Mode Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART 2 Serial Output. Used to transmit serial data out to the communication link. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping: 1(Default) : SPI function disable 6 66 SIN2 GPIO17 INt5v I/OOD12t VCC VSB 0 : SPI function enable Serial Input. Used to receive serial data through the communication link. General Purpose IO 123 DSR1# INt5v VCC 124 SOUT1 O8-u47,5v VCC Config4E_2E 125 126 127 128 1 SIN1 DCD2# RI2# CTS2# DTR2# INt5v INt5v INt5v INt5v INt5v O8-u47,5v VCC VCC VCC VCC VCC FWH_TRAP INt5v 2 RTS2# O8-u47,5v VCC HPWM_DC INt5v 3 DSR2# INt5v VCC 5 SOUT2 O8-u47,5v VCC SPI_TRAP INt5v 12 July, 2008 V.28P F71862 6.5 Pin No. 100 Parallel Port Pin Name SLCT Type INts5v PWR VCC Description An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Output line for detection of printer selection. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Output line for the printer initialization. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Parallel port data bus bit 1. Parallel port data bus bit 2. Parallel port data bus bit 3. Parallel port data bus bit 4. Parallel port data bus bit 5. Parallel port data bus bit 6. Parallel port data bus bit 7. 101 PE INts5v VCC 102 BUSY INts5v VCC 103 ACK# INts5v VCC 104 SLIN# OD12-5v VCC 105 INIT# OD12-5v VCC 106 ERR# INts5v VCC 107 AFD# OD12-5v VCC 108 STB# OD12-5v VCC 109 PD0 I/O12ts5v VCC 110 111 112 113 114 115 116 PD1 PD2 PD3 PD4 PD5 PD6 PD7 I/O12ts5v I/O12ts5v I/O12ts5v I/O12ts5v I/O12ts5v I/O12ts5v I/O12ts5v VCC VCC VCC VCC VCC VCC VCC 13 July, 2008 V.28P F71862 6.6 Pin No. 93-97 98 21 22 23 24 25 26 Hardware Monitor Pin Name VIN6~VIN2 Vcore(VIN1) FANIN1 FAN_CTL1 FANIN2 FAN_CTL2 FANIN3 GPIO40 FAN_CTL3* Type AIN AIN INt s 5 v OD12-5v AOUT INt s 5 v OD12-5v AOUT INt s 5 v I/OOD12t OD12-5V AOUT PWR VCC VCC VCC VCC VCC VCC VCC VCC Description Voltage Input 2 ~ 6. Voltage Input for Vcore. Fan 1 tachometer input. Fan 1 control output. This pin provides PWM duty-cycle output or a voltage output. Fan 2 tachometer input. Fan 2 control output. This pin provides PWM duty-cycle output or a voltage output. Fan 3 speed input. (Default function) General purpose IO. Fan 3 control output. This pin provides PWM duty-cycle output or a voltage output. (Default function) *This pin default function is FANCTL (PWM signal output), please take care the application if user want to implement GPIO function. General purpose IO. Thermal diode/transistor temperature sensor input for system use. Thermal diode/transistor temperature sensor input. CPU thermal diode/transistor temperature sensor input. This pin is for CPU use. Voltage sensor output. Generated PME event. It supports the PCI PME# interface. This signal allows the peripheral to request the system to wake up from the S3 state. (Default function) General Purpose IO. General purpose IO. Serial clock output pin for SPI device. General purpose IO. (Default function) Function A: When using firmware hub BIOS for primary BIOS and SPI BIOS for second BIOS, please connect this pin to SPI BIOS chip select pin. Function B: When using two SPI Flashes for primary and back up BIOS, please connect this pin to primary BIOS chip select pin. General purpose IO.(Default function) SPI master in/slave out pin. Fan 1 control output. This pin provides PWM duty-cycle open drain output for Intel 4-pin Fan. VSB General purpose IO.(Default function) SPI master out/slave in pin. Beep pin. GPIO41 89 90 91 92 79 D3+(System) D2+ D1+(CPU) VREF PME# I/OOD12t AIN AIN AIN AOUT OD12-5v VCC VCC VCC VCC VSB 59 60 GPIO25 GPIO10 SPI_SLK GPIO11 SPI_CS0# I/OOD12t I/OOD12t O12 I/OOD12t O12 VSB VSB 61 GPIO12 SPI_MISO FANCTL1_1 I/OOD12t INt 5 v OD12-5v I/OOD12t O12 OD24 VSB 62 GPIO13 SPI_MOSI BEEP 14 July, 2008 V.28P F71862 63 GPIO14 FWH_DIS WDTRST# SPI_CS1# I/OOD12t O12 OD12-5v O12 VSB General purpose IO. (Default function) Firmware hub disable Watch dog timer signal output. When using two SPI Flashes for primary and back up BIOS, please connect this pin to back up BIOS chip select pin. Over temperature signal output. 67 OVT# OD12-5v VSB 6.7 Pin No. 64 ACPI Function Pins Pin Name GPIO15 LED_VSB ALERT# GPIO16 LED_VCC PCIRST1# GPIO20 PCIRST2# GPIO21 PCIRST3# GPIO22 S5# GPIO23 RSTCON# Type I/OOD12t OD12 OD12 I/OOD12t OD12 OD12 I/OOD12 O12 I/OOD12 O12 I/OOD12 INts5v I/OOD12 OD12 PWR VSB Description General purpose IO. (Default function) Power LED for VSB. Alert a signal when temperature over limit setting. General purpose IO. Power LED for VCC. It is a output buffer of RSTCON# and LRESET#. (Default function) General purpose IO. It is a output buffer of RSTCON# and LRESET#. (Default function) General purpose IO. It is a output buffer of RSTCON# and LRESET#. (Default function) General purpose IO. S5# signal input. General purpose IO. (Default function) RESET Connect# with 50ms debouce function, it connects to reset button, and also other reset source on the motherboard. ATX Power Good input. ( Default function) General purpose IO. PWROK function, It is power good signal of VCC, which is delayed 400ms (default) as VCC arrives at 2.8V. General purpose IO. Main power switch button input. (Default function) General purpose IO. Panel Switch Output. This pin is low active and pulse output. It is power on request output#. (Default function) General purpose IO. S3# Input is Main power on-off switch input. (Default function) General purpose IO. Power supply on-off control output. Connect to ATX 65 74 VSB VSB 75 VSB 76 VSB 77 VSB 78 84 ATXPG_IN GPIO24 PWROK AIN I/OOD12t OD12 VSB VBAT 80 81 GPIO32 PWSIN# GPIO26 PWSOUT# I/OOD12t INts5v I/OOD12t OD12 VSB VSB 82 GPIO27 S3# GPIO30 PSON# I/OOD12t INts5v I/OOD12t OD12-5v VSB 83 VSB 15 July, 2008 V.28P F71862 85 GPIO31 RSMRST# I/OOD12t OD12 VBAT power supply PS_ON# signal. (Default function) General purpose IO. Resume Reset# function, It is power good signal of VSB, which is delayed 66ms as VSB arrives at 2.3V. (Default function) General purpose IO. Case Open Detection #. This pin is connected to a specially designed low power CMOS flip-flop backed by the battery for case open state preservation during power loss. 87 GPIO33 COPEN# I/OOD12t INts5v VBAT 6.8 Pin No. 45-42 52-49 46 47 53 54 55 VID Controller and Others Pin Name VIDIN[D:A] VIDOUT[D:A] GPIO44 GPIO45 GPIO00 GPIO01 ST2 Type INts5v OD12 I/OOD12t I/OOD12t I/OOD12t I/OOD12t OD12 PWR VCC VSB VCC VCC VSB VSB VSB Description CPU VID input pins. Special level input VIH CPU VID output pins. 0.9, VIL 0.6 SLOTOCC# 56 GPIO02 ST1 INts5v I/OOD12t OD12 VSB General purpose IO. General purpose IO. General purpose pin. General purpose pin. Status Pin2 for S0#/S3#/S5# states application. (Default function) In S0# ST2 pin status is Tri-state. In S3# ST2 pin status is Low level. In S5# ST2 pin status is Low level, and can be programmed to Tri-state. CPU SLOTOCC# input. General purpose pin. Status Pin1 for S0#/S3#/S5# states application. (Default function) In S0# ST1 pin status is Tri-state. In S3# ST1 pin status is Low level. In S5# ST1 pin status is Tri-state. General purpose pin. Watch dog timer signal output. AMDSI interface clock output. Intel PECI hardware monitor interface. (Default by register setting) AMDSI interface data input. (Default by register setting) GPIO03 WDTRST# 57 58 SIC PECI SID I/OOD12t OD12-5v OD12 VSB ILv/OD8-S1 VSB ILv/OD12 6.9 Pin No. 40 KBC Function Pin Name KBRST# Type OD16-u10,5V PWR VCC Description Keyboard reset. This pin is high after system reset. 16 July, 2008 V.28P Internal pull high 3.3V with 10k ohms. (KBC P20) 41 69 70 71 72 GA20 KDATA KCLK MDAT MCLK OD16-u10,5V I/OD16t,5V I/OD16t,5V I/OD16t,5V I/OD16t,5V VCC VSB VSB VSB VSB F71862 Gate A20 output. This pin is high after system reset. Internal pull high 3.3V with 10k ohms. (KBC P21) Keyboard Data. Keyboard Clock. PS2 Mouse Data. PS2 Mouse Clock. 17 July, 2008 V.28P F71862 7. Function Description 7.1 Power on Strapping Option The F71862 provides four pins for power on hardware strapping to select functions. There is a form to describe how to set the functions you want. Pin No. 1 2 5 121 124 Symbol FWH_TRAP PWM_DC SPI_TRAP FAN60_100 Config4E_2E Value 1 0 1 0 1 0 1 0 1 0 Description SPI as a backup BIOS (Default) SPI as a primary BIOS Fan control mode: PWM mode. ( Default) Fan control mode: Linear mode. SPI function disable (Default) SPI function enable Power on Fan speed default duty is 60%(PWM)(Default) Power on Fan speed default duty is 100%(PWM) Configuration Register I/O port is 4E/4F. (Default) Configuration Register I/O port is 2E/2F. 7.2 FDC The Floppy Disk Controller provides the interface between a host processor and one floppy disk drives. It integrates a controller and a digital data separator with write pre-compensation, data rate selection logic, microprocessor interface, and a set of registers. The FDC supports data transfer rates of 250 Kbps, 300 Kbps, 500 Kbps, and 1 Mbps. It operates in PC/AT mode and supports 3-mode type drives. The FDC configuration is handled by software and a set of Configuration registers. Status, Data, and Control registers facilitate the interface between the host microprocessor and the disk drive, providing information about the condition and/or state of the FDC. These configuration registers can select the data rate, enable interrupts, drives, and DMA modes, and indicate errors in the data or operation of the FDC/FDD. The controller manages data transfers using a set of data transfer and control commands. These commands are handled in three phases: Command, Execution, and Result. Not all commands utilize all these three phases. The below content is about the FDC device register descriptions. All the registers are for software porting reference. Status Register A (PS/2 mode)  Base + 0 Bit Name R/W Default Description 18 July, 2008 V.28P F71862 7 6 5 4 3 INTPEND DRV2_N STEP TRK0_N HDSEL R R R R R 0 0 0 This bit indicates the state of the interrupt output. 0: a second drive has been installed. 1: a second drive has not been installed. This bit indicates the complement of STEP# disk interface output. This bit indicates the state of TRK0# disk interface input. This bit indicates the complement of HDSEL# disk interface output. 0: side 0. 1: side 1. This bit indicates the state of INDEX# disk interface input. This bit indicates the state of WPT# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. This bit indicates the complement of DIR# disk interface output. 2 1 INDEX_N WPT_N R R - 0 DIR R 0 Status Register A (Model 30 mode)  Base + 0 Bit 7 6 5 4 3 Name INTPEND DRQ STEP_FF TRK0 HDSEL_N R/W Default R R R R R 0 0 0 1 Description This bit indicates the state of the interrupt output. This bit indicates the state of the DRQ signal. This bit indicates the complement of latched STEP# disk interface output. This bit indicates the complement of TRK0# disk interface input. This bit indicates the state of HDSEL# disk interface output. 0: side 0. 1: side 1. This bit indicates the complement of INDEX# disk interface input. This bit indicates the complement of WPT# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. This bit indicates the state of DIR# disk interface output. 0: head moves in inward direction. 1: head moves in outward direction. 2 1 INDEX WPT R R - 0 DIR_N R 1 Status Register B (PS/2 Mode)  Base + 1 Bit Name R/W Default R R R R R R R 11 0 0 0 0 0 0 Description Reserved. Return 11b when read. Drive select 0. This bit reflects the bit 0 of Digital Output Register. This bit changes state at every rising edge of WDATA#. This bit changes state at every rising edge of RDATA#. This bit indicates the complement of WGATE# disk interface output. This bit indicates the complement of MOB# disk interface output. Not support in this design. This bit indicates the complement of MOA# disk interface output. 7-6 Reserved 5 4 3 2 1 0 DR0 WDATA RDATA WGATE MOTEN1 MOTEN0 19 July, 2008 V.28P F71862 Status Register B (Model 30 Mode)  Base + 1 Bit 7 6 5 4 3 2 1 0 Name DRV2_N DSB_N DSA_N WDATA_FF RDATA_FF WGATE_FF DSD_N DSC_N R/W Default R R R R R R R R 1 1 0 0 0 1 1 Description 0: a second drive has been installed. 1: a second drive has not been installed. This bit indicates the state of DRVB# disk interface output. Not support in this design. This bit indicates the state of DRVA# disk interface output. This bit is latched at the rising edge of WDATA# and is cleared by a read from the Digital Input Register. This bit is latched at the rising edge of RDATA# and is cleared by a read form the Digital Input Register. This bit is latched at the falling edge of WGATE# and is cleared by a read from the Digital Input Register. This bit indicates the complement of DRVD# disk interface output. Not support in this design. This bit indicates the complement of DRVC# disk interface output. Not support in this design. Digital Output Register  Base + 2 Bit 7 6 5 4 3 Name MOTEN3 MOTEN2 MOTEN1 MOTEN0 DAMEN R/W Default R R R/W R/W R/W 0 0 0 0 0 Description Motor enable 3. Not support in this design. Motor enable 2. Not support in this design. Motor enable 1. Used to control MOB#. MOB# is not support in this design. Motor enable 0. Used to control MOA#. DMA enable. This bit has two mode of operation. PC-AT and Model 30 mode: write 1 will enable DMA and IRQ, write 0 will disable DMA and IRQ. PS/2 mode: This bit is reserved. DMA and IRQ are always enabled in PS/2 mode. Write 0 to this bit will reset the controller. I will remain in reset condition until a 1 is written. This bit indicates the complement of DRVD# disk interface output. Not support in this design. This bit indicates the complement of DRVC# disk interface output. Not support in this design. 2 1 0 RESET DSD_N DSC_N R R R 0 1 1 Tape Drive Register  Base + 3 Bit Name R/W Default R R R R/W 00 11 11 0 Description Reserved. Return 00b when read. Reserved in normal function, return 11b when read. If 3 mode FDD function is enabled. These bits indicate the drive type ID. Reserved. Return 11b when read in normal function. Return 00b when read in 3 mode FDD function. These bits assign a logical drive number to be a tape drive. 7-6 Reserved 5-4 TYPEID 3-2 Reserved 1-0 TAPESEL 20 July, 2008 V.28P F71862 Main Status Register  Base + 4 Bit 7 6 RQM DIO Name R/W Default R R 0 0 Description Request for Master indicates that the controller is ready to send or receive data from the uP through the FIFO. Data I/O (direction): 0: the controller is expecting a byte to be written to the Data Register. 1: the controller is expecting a byte to be read from the Data Register. Non DMA Mode: 0: the controller is in DAM mode. 1: the controller is interrupt or software polling mode. This bit indicate that a read or write command is in process. FDD number 3 is in seek or calibration condition. FDD number 3 is not support in this design. FDD number 2 is in seek or calibration condition. FDD number 2 is not support in this design. FDD number 1 is in seek or calibration condition. FDD number 1 is not support in this design. FDD number 0 is in seek or calibration condition. 5 NON_DMA R 0 4 3 2 1 0 FDC_BUSY DRV3_BUSY DRV2_BUSY DRV1_BUSY DRV0_BUSY R R R R R 0 0 0 0 0 Data Rate Select Register  Base + 4 Bit 7 6 Name SOFTRST PWRDOWN R/W Default W W W 0 0 000 Description A 1 written to this bit will software reset the controller. Auto clear after reset. A 1 to this bit will put the controller into low power mode which will turn off the oscillator and data separator circuits. Return 0 when read. Select the value of write precompensation: 250K-1Mbps 2Mbps 000: default delays default delays 001: 41.67ns 20.8ns 010: 83.34ns 41.17ns 011: 125.00ns 62.5ns 100: 166.67ns 83.3ns 101: 208.33ns 104.2ns 110: 250.00ns 125.00ns 111: 0.00ns (disabled) 0.00ns (disabled) The default value of corresponding data rate: 250Kbps: 125ns 300Kbps: 125ns 500Kbps: 125ns 1Mbps: 41.67ns 2Mbps: 20.8ns Data rate select: MFM FM 00: 500Kbps 250Kbps 01: 300Kbps 150Kbps 10: 250Kbps 125Kbps 11: 1Mbps illegal 5 Reserved 4-2 PRECOMP 1-0 DRATE W 10 Data (FIFO) Register  Base + 5 Bit Name R/W Default Description 21 July, 2008 V.28P F71862 7-0 DATA R/W 00h The FIFO is used to transfer all commands, data and status between controller and the system. The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. The FIFO is default disabled and could be enabled via the CONFIGURE command. Status Registers 0 Bit 7-6 IC Name R/W Default R Description Interrupt code : 00: Normal termination of command. 01: Abnormal termination of command. 10: Invalid command. 11: Abnormal termination caused by poling. Seek end. Set when a SEEK or RECALIBRATE or a READ or WRITE with implied seek command is completed. Equipment check. 0: No error 1: When a fault signal is received form the FDD or the TRK0# signal fails to occur after 77 step pulses. Not ready. 0: Drive is ready 1: Drive is not ready. Head address. The current head address. Drive select. 00: Drive A selected. 01: Drive B selected. 10: Drive C selected. 11: Drive D selected. 5 SE R - 4 EC R - 3 NR R - 2 HD R R - 1-0 DS Status Registers 1 Bit 7 6 4 EN DE OR Name R/W Default R R R Description End of Track. Set when the FDC tries to access a sector beyond the final sector of a cylinder. Data Error. The FDC detect a CRC error in either the ID field or the data field of a sector. Overrun/Underrun. Set when the FDC is not serviced by the host system within a certain time interval during data transfer. Unused. This bit is always “0” No Data. Set when the following conditions occurred: 1. The specified sector is not found during any read command. 2. The ID field cannot be read without errors during a READ ID command. 3. The proper sector sequence cannot be found during a READ TRACK command. 3 2 Reserved ND R - 22 July, 2008 V.28P F71862 1 0 NW MA R R No Writable Set when WPT# is active during execution of write commands. Missing Address Mark. Set when the following conditions occurred: 1. Cannot detect an ID address mark at the specified track after encountering the index pulse form the INDEX# pin twice. 2. Cannot detect a data address mark or a deleted data address mark on the specified track. Status Registers 2 Bit 7 6 Name Reserved CM R/W Default R Unused. This bit is always “0”. Control Mark. Set when following conditions occurred: 1. Encounters a deleted data address mark during a READ DATA command. 2. Encounters a data address mark during a READ DELETED DATA command. Data Error in Data Field. The FDC detects a CRC error in the data field. Wrong Cylinder. Set when the track address from the sector ID field is different from the track address maintained inside the FDC. Scan Equal. Set if the equal condition is satisfied during execution of the SCAN command. Scan Not Satisfied. Set when the FDC cannot find a sector on the track which meets the desired condition during any scan command. Bad Cylinder. The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FFh which indicates a bad track. Missing Data Address Mark. Set when the FDC cannot detect a data address mark or a deleted data address mark. Description 5 4 DD WC R R - 3 2 SE SN R R - 1 BC R - 0 MD R - Status Registers 3 Bit 7 6 5 4 3 2 1 Name Reserved WP Reserved T0 Reserved. HD DS1 R/W Default R R R R R R Unused. This bit is always “0”. Write Protect. Indicates the status of WPT# pin. Unused. This bit is always “1”. Track 0. Indicates the status of the TRK0# pin. Unused. This bit is always “1”. Head Address. Indicates the status of the HDSEL# pin. Drive Select. Description 23 July, 2008 V.28P 0 DS0 R - These two bits indicate the DS1, DS0 bits in the command phase. F71862 Digital Input Register (PC-AT Mode)  Base + 7 Bit 7 Name DSKCHG R/W Default R R Description This bit indicates the complement of DSKCHG# disk interface input. Reserved. 6-0 Reserved Digital Input Register (PS/2 Mode)  Base + 7 Bit 7 Name DSKCHG R/W Default R R R 10 1 Description This bit indicates the complement of DSKCHG# disk interface input. Reserved. These bits indicate the status of the DRATE programmed through the Data Rate Select Register or Configuration Control Register. 0: 1Mbps or 500Kbps data rate is chosen. 1: 300Kbps or 250Kbps data rate is chosen. 6-3 Reserved 2-1 DRATE 0 HIGHDEN_N Digital Input Register (Model 30 Mode)  Base + 7 Bit 7 Name DSKCHG_N R/W Default R R R R 0 0 10 Description This bit indicates the state of DSKCHG# disk interface input. Reserved. This bit reflects the DMA bit in Digital Output Register. This bit reflects the NOPRE bit in Configuration Control Register. These bits indicate the status of DRATE programmed through the Data Rate Select Register or Configuration Control Register. 6-4 Reserved 3 2 DMAEN NOPRE 1-0 DRATE Configuration Control Register (PC-AT and PS/2 Mode)  Base + 7 Bit Name R/W Default W 10 Reserved. These bit determine the data rate of the floppy controller. See DRATE bits in Data Rate Select Register. Description 7-2 Reserved 1-0 DRATE Configuration Control Register (Model 30 Mode)  Base + 7 Bit Name R/W Default W 0 Reserved. This bit could be programmed through Configuration Control Register and be read through the bit 2 in Digital Input Register in Model 30 Mode. But it has no functionality. Description 7-3 Reserved 2 NOPRE 24 July, 2008 V.28P F71862 1-0 DRATE W 10 These bit determine the data rate of the floppy controller. See DRATE bits in Data Rate Select Register. FDC Commands Terminology: C D DIR Cylinder Number 0 -256 Data Pattern Step Direction 0: step out 1: step in DS0 Drive Select 0 DS1 Drive Select 1 DTL Data Length EC Enable Count EOT End of Track EFIFO Enable FIFO 0: FIFO is enabled. 1: FIFO is disabled. EIS Enable Implied Seek FIFOTHR FIFO Threshold GAP Alters Gap Length GPL Gap Length H/HDS Head Address HLT Head Load Time HUT Head Unload Time LOCK Lock EFIFO, FIFOTHR, PTRTRK bits. Prevent these bits from being affected by software reset. MFM MFM or FM mode 0: FM 1: MFM MT Multi-Track N Sector Size Code. All values up to 07h are allowable. 00: 128 bytes 01: 256 bytes .. .. 07 16 Kbytes NCN New Cylinder Number ND Non-DMA Mode OW Overwritten PCN Present Cylinder Number POLL Polling disable 0: polling is enabled. 1: polling is disabled. PRETRK Precompensation Start Track Number R Sector address RCN Relative Cylinder Number SC Sector per Cylinder SK Skip deleted data address mark SRT Step Rate Time ST0 Status Register 0 ST1 Status Register 1 ST2 Status Register 2 ST3 Status Register 3 WGATE Write Gate alters timing of WE. 25 July, 2008 V.28P F71862 Read Data Phase Command R/W W W W W W W W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 D3 0 0 D2 1 HDS D1 1 DS1 D0 0 DS0 Sector ID information prior to command execution Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------- Data transfer between the FDD and system Status information after command execution. Read Deleted Data Phase R/W Command W W W W W W W W W Execution Result R R D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 D3 1 0 D2 1 HDS D1 0 DS1 D0 0 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------- Sector ID information prior to command execution ---------------------------- ST0 ------------------------------------------------------ ST1 -------------------------- Data transfer between the FDD and system Status information after command execution. 26 July, 2008 V.28P F71862 R R R R R ---------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. Read A Track Phase R/W Command W W W W W W W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 0 HDS D1 1 DS1 D0 0 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------- Sector ID information prior to command execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------- Data transfer between the FDD and system. FDD reads contents of all cylinders from index hole to EOT. Status information after command execution. Sector ID information after command execution. Read ID Phase Command R/W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 1 DS1 D0 0 DS0 The first correct ID information on the cylinder is stored in Data Register. R R ---------------------------- ST0 ------------------------------------------------------ ST1 -------------------------Status information after command Remark Command code Result 27 July, 2008 V.28P R R R R R ---------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------- execution. F71862 Disk status after the command has been completed. Verify Phase Command R/W W W W W W W W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. D7 MT EC D6 MFM 0 D5 SK 0 D4 1 0 D3 0 0 D2 1 HDS D1 1 DS1 D0 0 DS0 Sector ID information prior to command execution Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL --------------------------------------------------- DTL/SC ------------------------ No data transfer Status information after command execution. Version Phase Command Result R/W W R D7 0 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 0 Remark Command code Enhanced controller Write Data Phase Command R/W W W W D7 MT 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 1 HDS D1 0 DS1 D0 1 DS0 Sector ID Remark Command code ----------------------------- C --------------------------- 28 July, 2008 V.28P W W W W W W Execution ----------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------- information prior to command execution F71862 Data transfer between the FDD and system. R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. Status information after command execution. Result Write Deleted Data Phase Command R/W W W W W W W W W W Execution D7 MT 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 0 DS1 D0 1 DS0 Sector ID information prior to command execution Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------- Data transfer between the FDD and system. R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. Status information after command execution. Result 29 July, 2008 V.28P F71862 Format A Track Phase Command R/W W W W W W W Execution for each sector ( repeat ) D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 0 DS1 D0 1 DS0 Bytes/Sector Sectors/Cylinder Gap 3 Length Data Pattern Input sector parameter. Remark Command code ------------------------------ N ------------------------------------------------------ SC ----------------------------------------------------- GPL ------------------------------------------------------ D -------------------------------------------------------- C --------------------------- W W W ------------------------------ H -------------------------------------------------------- R ------------------------------------------------------- N ----------------------------------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 -------------------------------------------------- Undefined ---------------------------------------------- Undefined ----------------------------------------------- Undefined ----------------------------------------------- Undefined ---------------------- Result R R R R R R R Status information after command execution. Recalibrate Phase Command R/W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 0 D1 1 DS1 D0 1 DS0 Head retracted to track 0 Remark Command code Sense Interrupt Status Phase Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0 Remark Command code ---------------------------- ST0 ----------------------------------------------------- PCN -------------------------- Specify Phase Command R/W W W D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 Remark Command code |------------------ SRT -------------------| |------------------ HUT -------------------| 30 July, 2008 V.28P F71862 W |------------------------------------- SRT ---------------------------------------| ND Seek Phase Command R/W W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 Remark Command code ---------------------------- NCN -------------------------Head positioned over proper cylinder on diskette Configure Phase Command R/W W W W W Execution D7 0 0 0 D6 0 0 EIS D5 0 0 EFIFO D4 1 0 POLL D3 0 0 D2 0 HDS D1 1 DS1 D0 1 DS0 Remark Command code |---------------- FIFOTHR ---------------| ---------------------------- PRETRK -------------------------Internal registers written Relative Seek Phase Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 Remark Command code ---------------------------- RCN -------------------------- Perpendicular Mode Phase Command R/W W W D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 0 D0 D1 1 GAP D0 0 WGATE Remark Command code Lock Phase Command Result R/W W R D7 LOCK 0 D6 0 0 D5 0 0 D4 1 LOCK D3 0 0 D2 1 0 D1 0 0 D0 0 0 Remark Command code Dumpreg Phase Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 Remark Command code -------------------------- PCN ( Drive 0 ) ------------------------------------------------- PCN ( Drive 0 ) ------------------------ 31 July, 2008 V.28P F71862 R R R R R R R R LOCK 0 0 EIS -------------------------- PCN ( Drive 0 ) ------------------------------------------------- PCN ( Drive 0 ) -----------------------|------------------ SRT -------------------| |------------------ HUT -------------------| ND |------------------------------------- SRT ---------------------------------------| -------------------------- SC/EOT -----------------------D3 EFIFO D2 POLL D1 D0 GAP WGATE |---------------- FIFOTHR ---------------| ---------------------------- PRETRK -------------------------- Sense Drive Status Phase Command R/W W W Result R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 HDS D1 0 DS1 D0 0 DS0 Status information abut disk drive Remark Command code ---------------------------- ST3 -------------------------- Invalid Phase Command Result R/W W R D7 D6 D5 D4 D3 D2 D1 D0 Remark FDC goes to standby state. ST0 = 80h ---------------------------- Invalid Codes ----------------------------------------------------- ST0 -------------------------- 7.3 UART The F71862 provides two UART ports and supports IRQ sharing for system application. The UARTs are used to convert data between parallel format and serial format. They convert parallel data into serial format on transmission and serial format into parallel data on receiver side. The serial format is formed by one start bit, followed by five to eight data bits, a parity bit if programmed and one ( 1.5 or 2 ) stop bits. The UARTs include complete modem control capability and an interrupt system that may be software trailed to the computing time required to handle the communication link. They have FIFO mode to reduce the number of interrupts presented to the host. Both receiver and transmitter have a 16-byte FIFO. The below content is about the UART1 and UART2 device register descriptions. All the registers are for software porting reference. 32 July, 2008 V.28P F71862 Receiver Buffer Register  Base + 0 Bit 7-0 RBR Name R/W Default R 00h The data received. Read only when LCR[7] is 0 Description Transmitter Holding Register  Base + 0 Bit 7-0 THR Name R/W Default W 00h Data to be transmitted. Write only when LCR[7] is 0 Description Divisor Latch (LSB)  Base + 0 Bit 7-0 DLL Name R/W Default R/W 01h Baud generator divisor low byte. Access only when LCR[7] is 1. Description Divisor Latch (MSB)  Base + 1 Bit 7-0 DLM Name R/W Default R/W 00h Description Baud generator divisor high byte. Access only when LCR[7] is 1. Interrupt Enable Register  Base + 1 Bit 3 2 1 0 EDSSI ELSI ETBFI ERBFI Name R/W Default R/W R/W R/W R/W 0 0 0 0 Reserved. Enable Modem Status Interrupt. Access only when LCR[7] is 0. Enable Line Status Error Interrupt. Access only when LCR[7] is 0. Enable Transmitter Holding Register Empty Interrupt. Access only when LCR[7] is 0. Enable Received Data Available Interrupt. Access only when LCR[7] is 0. Description 7-4 Reserved Interrupt Identification Register  Base + 2 Bit 7 6 Name FIFO_EN FIFO_EN R/W Default R R R 0 0 000 0: FIFO is disabled 1: FIFO is enabled. 0: FIFO is disabled 1: FIFO is enabled. Reserved. 000: Interrupt is caused by Modem Status 001: Interrupt is caused by Transmitter Holding Register Empty 010: Interrupt is caused by Received Data Available. 110: Interrupt is caused by Character Timeout 011: Interrupt is caused by Line Status. 1: Interrupt is not pending. 0: Interrupt is pending. Description 5-4 Reserved 3-1 IRQ_ID 0 IRQ_PENDN R 1 33 July, 2008 V.28P F71862 FIFO Control Register  Base + 2 Bit Name R/W Default W 00 Description 00: Receiver FIFO trigger level is 1. 01: Receiver FIFO trigger level is 4. 10: Receiver FIFO trigger level is 8. 11: Receiver FIFO trigger level is 14. Reserved. Reset the transmitter FIFO. Reset the receiver FIFO. 0: Disable FIFO. 1: Enable FIFO. 7-6 RCV_TRIG 5-3 Reserved 2 1 0 CLRTX CLRRX FIFO_EN R R R 0 0 0 Line Control Register  Base + 3 Bit 7 6 5 4 3 2 DLAB SETBRK STKPAR EPS PEN STB Name R/W Default R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Description 0: Divisor Latch can’t be accessed. 1: Divisor Latch can be accessed via Base and Base+1. 0: Transmitter is in normal condition. 1: Transmit a break condition. XX0: Parity Bit is disable 001: Parity Bit is odd. 011: Parity Bit is even 101: Parity Bit is logic 1 111: Parity Bit is logic 0 0: Stop bit is one bit 1: When word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 00: Word length is 5 bit 01: Word length is 6 bit 10: Word length is 7 bit 11: Word length is 8 bit 1-0 WLS R/W 00 MODEM Control Register  Base + 4 Bit 4 3 2 1 0 LOOP OUT2 OUT1 RTS DTR Name R/W Default R/W R/W R/W R/W R/W 0 0 0 0 0 Reserved. 0: UART in normal condition. 1: UART is internal loop back 0: All interrupt is disabled. 1: Interrupt is enabled (disabled) by IER. Read from MSR[6] is loop back mode 0: RTS# is forced to logic 1 1: RTS# is forced to logic 0 0: DTR# is forced to logic 1 1: DTR# is forced to logic 0 Description 7-5 Reserved Line Status Register  Base + 5 Bit 7 6 Name RCR_ERR TEMT R/W Default R R 0 1 Description 0: No error in the FIFO when FIFO is enabled 1: Error in the FIFO when FIFO is enabled. 0: Transmitter is in transmitting. 1: Transmitter is empty. 34 July, 2008 V.28P F71862 5 4 3 2 1 0 THRE BI FE PE OE DR R R R R R R 1 0 0 0 0 0 0: Transmitter Holding Register is not empty. 1: Transmitter Holding Register is empty. 0: No break condition detected. 1: A break condition is detected. 0: Data received has no frame error. 1: Data received has frame error. 0: Data received has no parity error. 1: Data received has parity error. 0: No overrun condition occurred. 1: An overrun condition occurred. 0: No data is ready for read. 1: Data is received. MODEM Status Register  Base + 6 Bit 7 6 5 4 3 2 1 0 DCD RI DSR CTS DDCD TERI DDSR DCTS Name R/W Default R R R R R R R R 0 0 0 0 Description Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2 in MCR. Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in MCR Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in MCR Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in MCR 0: No state changed at DCD#. 1: State changed at DCD#. 0: No Trailing edge at RI#. 1: A low to high transition at RI#. 0: No state changed at DSR#. 1: State changed at DSR#. 0: No state changed at CTS#. 1: State changed at CTS#. Scratch Register  Base + 7 Bit 7-0 SCR Name R/W Default R/W 00h Scratch register. Description 7.4 Parallel Port The parallel port in F71862 supports an IBM XT/AT compatible parallel port ( SPP ), bi-directional paralle port ( BPP ), Enhanced Parallel Port ( EPP ), Extended Capabilities Parallel Port ( ECP ) mode. Refer to the configuration registers for more information on selecting the mode of operation. The below content is about the Parallel Port device register descriptions. All the registers are for software porting reference. 35 July, 2008 V.28P F71862 Parallel Port Data Register  Base + 0 Bit 7-0 DATA Name R/W Default R/W 00h Description The output data to drive the parallel port data lines. ECP Address FIFO Register  Base + 0 Bit Name R/W Default R/W 00h Description Access only in ECP Parallel Port Mode and the ECP_MODE programmed in the Extended Control Register is 011. The data written to this register is placed in the FIFO and tagged as an Address/RLE. It is auto transmitted by the hardware. The operation is only defined for forward direction. It divide into two parts : Bit 7 : 0: bits 6-0 are run length, indicating how many times the next byte to appear (0 = 1time, 1 = 2times, 2 = 3times and so on). 1: bits 6-0 are a ECP address. Bit 6-0 : Address or RLE depends on bit 7. 7-0 ECP_AFIFO Device Status Register  Base + 1 Bit 7 6 5 4 3 Name BUSY_N ACK_N PERROR SELECT ERR_N R/W Default R R R R R R R 11 Description Inverted version of parallel port signal BUSY. Version of parallel port signal ACK#. Version of parallel port signal PE. Version of parallel port signal SLCT. Version of parallel port signal ERR#. Reserved. Return 11b when read. This bit is valid only in EPP mode. Return 1 when in other modes. It indicates that a 10uS time out has occurred on the EPP bus. 0: no time out error. 1: time out error occurred, write 1 to clear. 2-1 Reserved 0 TMOUT Device Control Register  Base + 2 Bit Name R/W Default R/W 11 0 Description Reserved. Return 11b when read. 0: the parallel port is in output mode. 1: the parallel port is in input mode. It is auto reset to 0 when in SPP mode. Enable an interrupt at the rising edge of ACK#. Inverted and then drives the parallel port signal SLIN#. When read, the status of inverted SLIN# is return. 7-6 Reserved 5 DIR 4 3 ACKIRQ_EN SLIN R/W R/W 0 0 36 July, 2008 V.28P F71862 2 1 0 INIT_N AFD STB R/W R/W R/W 0 0 0 Drives the parallel port signal INIT#. When read, the status of INIT# is return. Inverted and then drives the parallel port signal AFD#. When read, the status of inverted AFD# is return. Inverted and then drives the parallel port signal STB#. When read, the status of inverted STB# is return. EPP Address Register  Base + 3 Bit Name R/W Default R/W 00h Description Write this register will cause the hardware to auto transmit the written data to the device with the EPP Address Write protocol. Read this register will cause the hardware to auto receive data from the device by with the EPP Address Read protocol. 7-0 EPP_ADDR EPP Data Register  Base + 4 – Base + 7 Bit Name R/W Default R/W 00h Description Write this register will cause the hardware to auto transmit the written data to the device with the EPP Data Write protocol. Read this register will cause the hardware to auto receive data from the device by with the EPP Data Read protocol. 7-0 EPP_DATA Parallel Port Data FIFO  Base + 400h Bit Name R/W Default R/W 00h Description Data written to this FIFO is auto transmitted by the hardware to the device by using standard parallel port protocol. It is only valid in ECP and the ECP_MODE is 010b.The operation is only for forward direction. 7-0 C_FIFO ECP Data FIFO  Base + 400h Bit Name R/W Default R/W 00h Description Data written to this FIFO when DIR is 0 is auto transmitted by the hardware to the device by using ECP parallel port protocol. Data is auto read from device into the FIFO when DIR is 1 by the hardware by using ECP parallel port protocol. Read the FIFO will return the content to the system. It is only valid in ECP and the ECP_MODE is 011b. 7-0 ECP_DFIFO ECP Test FIFO  Base + 400h Bit 7-0 T_FIFO Name R/W Default R/W 00h Description Data may be read, written from system to the FIFO in any Direction. But no hardware handshake occurred on the parallel port lines. It could be used to test the empty, full and threshold of the FIFO. It is only valid in ECP and the ECP_MODE is 110b. 37 July, 2008 V.28P F71862 ECP Configuration Register A  Base + 400h Bit 7 Name IRQ_MODE R/W Default R 0 Description 0: interrupt is ISA pulse. 1: interrupt is ISA level. Only valid in ECP and ECP_MODE is 111b. 000: the design is 16-bit implementation. 001: the design is 8-bit implementation (default). 010: the design is 32-bit implementation. 011-111: Reserved. Only valid in ECP and ECP_MODE is 111b. Reserved. 0: when transmitting there is 1 byte waiting in the transceiver that does not affect the FIFO full condition. 1: when transmitting the state of the full bit includes the byte being transmitted. Only valid in ECP and ECP_MODE is 111b. Return 00 when read. Only valid in ECP and ECP_MODE is 111b. 6-4 IMPID R 001 3 2 Reserved BYTETRAN_N R 1 1-0 Reserved R 00 ECP Configuration Register B  Base + 401h Bit 7 COMP Name R/W Default R 0 Description 0: only send uncompressed data. 1: compress data before sending. Only valid in ECP and ECP_MODE is 111b. Reserved. Return 1 when read. Only valid in ECP and ECP_MODE is 111b. 000: the interrupt selected with jumper. 001: select IRQ 7 (default). 010: select IRQ 9. 011: select IRQ 10. 100: select IRQ 11. 101: select IRQ 14. 110: select IRQ 15. 111: select IRQ 5. Only valid in ECP and ECP_MODE is 111b. Return the DMA channel of ECP parallel port. Only valid in ECP and ECP_MODE is 111b. 6 Reserved R R 1 001 5-3 ECP_IRQ_CH 2-0 ECP_DMA_CH R 011 Extended Control Register  Base + 402h Bit Name R/W Default Description 38 July, 2008 V.28P F71862 7-5 ECP_MODE R/W 000 000: SPP Mode. 001: PS/2 Parallel Port Mode. 010: Parallel Port Data FIFO Mode. 011: ECP Parallel Port Mode. 100: EPP Mode. 101: Reserved. 110: Test Mode. 111: Configuration Mode. Only valid in ECP. 0: disable the interrupt generated on the falling edge of ERR#. 1: enable the interrupt generated on the falling edge of ERR#. 0: disable DMA. 1: enable DMA. DMA starts when SERVICEINTR is 0. 0: enable the following case of interrupt. DMAEN = 1: DMA mode. DMAEN = 0, DIR = 0: set to 1 whenever there are writeIntrThreshold or more bytes are free in the FIFO. DMAEN = 0, DIR = 0: set to 1 whenever there are readIntrThreshold or more bytes are valid to be read in the FIFO. 0: The FIFO has at least 1 free byte. 1: The FIFO is completely full. 0: The FIFO contains at least 1 byte. 1: The FIFO is completely empty. 4 3 2 ERRINTR_EN DAMEN SERVICEINTR R/W R/W R/W 0 0 1 1 0 FIFOFULL FIFOEMPTY R R 0 0 7.5 Keyboard Contoller The KBC circuit provides the functions included a keyboard and/or a PS/2 mouse, and can be used with IBM-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The controller will assert an interrupt to the system when data are placed in its output buffer. Output Buffer The output buffer is an 8-bit read-only register at I/O address 60H. bytes required by commands to the system. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data Input Buffer The input buffer is an 8-bit write-only register at I/O address 60H or 64H. Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard through the 39 July, 2008 V.28P F71862 controller's input buffer only if the input buffer full bit in the status register is “0”. Status Register The status register is an 8-bit read-only register at I/O address 64H, that holds information about the status of the keyboard controller and interface. time. BIT 0 1 2 BIT FUNCTION Output Buffer Full Input Buffer Full System Flag 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller (KCCB). It defaults to 0 after a power-on reset. 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Muse output buffer empty 1: Mouse output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) DESCRIPTION It may be read at any 3 4 5 6 7 Command/Data Inhibit Switch Mouse Output Buffer General Purpose Time-out Parity Error Commands COMMAND 20h 60h FUNCTION Read Command Byte Write Command Byte BIT 0 1 2 3 4 5 6 7 A7h A8h DESCRIPTION Enable Keyboard Interrupt Enable Mouse Interrupt System flag Reserve Disable Keyboard Interface Disable Mouse interface IBM keyboard Translate Mode Reserve Disable Auxiliary Device Interface Enable Auxiliary Device Interface 40 July, 2008 V.28P F71862 A9h Auxiliary Interface Test 8’h00: indicate Auxiliary interface is ok. 8’h01: indicate Auxiliary clock is low. 8’h02: indicate Auxiliary clock is high 8’h03: indicate Auxiliary data is low 8’h04: indicate Auxiliary data is high Self-test Returns 055h if self test succeeds keyboard Interface Test 8’h00: indicate keyboard 8’h01: indicate keyboard 8’h02: indicate keyboard 8’h03: indicate keyboard 8’h04: indicate keyboard interface is ok. clock is low. clock is high data is low data is high AAh ABh ADh AEh C0h C1h C2h D0h D1h D2h D3h D4h FEh Disable Keyboard Interface Enable Keyboard Interface Read Input Port(P1) and send data to the system Continuously puts the lower four bits of Port1 into STATUS register Continuously puts the upper four bits of Port1 into STATUS register Send Port2 value to the system Only set/reset GateA20 line based on the system data bit 1 Send data back to the system as if it came from Keyboard Send data back to the system as if it came from Muse Output next received byte of data from system to Mouse Pulse only RC(the reset line) low for 6µS if Command byte is even KBC Command Description PS2 wakeup function The KBC supports keyboard and mouse wakeup function, keyboard wakeup function has 4 kinds of conditions, when key is pressed combinational key (1) CTRL +ESC (2) CTRL+F1 (3) CTRL+SPACE (4) ANY KEY (5) windows 98 wakeup up key, KBC will assert PME signal. Mouse wakeup function has 2 kinds of conditions, when mouse (1) BUTTON CLICK or (2) BUTTON CLICK AND MOVEMENT, KBC will assert PME signal. Those wakeup conditions are controlled by configuration register. 7.6 Hardware Monitor For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is 2.048V. Therefore the voltage under 2.048V (ex:1.5V) can be directly connected to these analog inputs. The voltage higher than 2.048V should be reduced by a factor with external 41 July, 2008 V.28P F71862 resistors so as to obtain the input range. Only 3VCC/VSB/VBAT is an exception for it is main power of the F71862. Therefore 3VCC/VSB/VBAT can directly connect to this chip’s power pin and need no external resistors. There are two functions in this pin with 3.3V. The first function is to supply internal analog power of the F71862 and the second function is that voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The internal serial resistors are two 150K ohm, so that the internal reduced voltage is half of +3.3V. There are four voltage inputs in the F71862 and the voltage divided formula is shown as follows: VIN = V+12V × R2 R1 + R2 where V+12V is the analog input voltage, for example. If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which is within the tolerance. As for application circuit, it can be refer to the figure shown as follows. 3VCC/VSB Voltage Inputs VIN (Lower than 2.048V) VIN(Higher than 2.048V) (directly connect to the chip) (directly connect to the chip) VIN1(Max2.048V) R1 R2 150K VIN3.3 150K VREF R 10K, 1% D+ Typical BJT Connection 2N3906 Typical Thermister Connection RTHM 10K, 25 C D- 8-bit ADC with 8 mV LSB Fig 7-1 The F71862 monitors three remote temperature sensors.These sensors can be measured from -40°C to 127°C. More detail please refer register description. Remote-sensor transistor manufacturers Manufacturer Panasonic Philips Model Number 2SB0709 2N3906 PMBT3906 42 July, 2008 V.28P F71862 Monitor Temperature from “thermistor” The F71862 can connect three thermistor to measure environment temperature or remote temperature. The specification of thermistor should be considered to (1) β value is 3435K (2) resistor value is 10K ohm at 25°C. In the Figure 7-1, the thermistor is connected by a serial resistor with 10K ohm, then connected to VREF. Monitor Temperature from “thermal diode” Also, if the CPU, GPU or external circuits provide thermal diode for temperature measurement, the F71862 is capable to these situations. The build-in reference table is for PNP 2N3906 transistor. In the Figure 7-1, the transistor is directly connected into temperature pins. ADC Noise Filtering The ADC is integrating type with inherently good noise rejection. Micro-power operation places constraints on high-frequency noise rejection; therefore, careful PCB board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environment. High frequency EMI is best filtered at D+ and D- with an external 2200pF capacitor. Too high capacitance may introduce errors due to the rise time of the switched current source. Nearly all noise sources tested cause the ADC measurement to be higher than the actual temperature, depending on the frequency and amplitude. Over Temperature Signal (OVT#) OVT# alert for temperature is shown as figure 7-2. When monitored temperature exceeds the over-temperature threshold value, OVT# will be asserted until the temperature goes below the hysteresis temperature. 43 July, 2008 V.28P F71862 To T HYST OVT# Fig 7-2 Temperature PME# PME# interrupt for temperature is shown as figure 7-3. Temperature exceeding high limit or going below hysteresis will cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register. To T HYST SMI# (pulse mode) (level mode active low) * * * * *Interrupt Reset when Interrupt Status Registers are written 1 Fig 7-3 Fan speed count Inputs are provided by the signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage cannot be over 5V. If the input signals from the tachometer outputs are over the 5V, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as follows: 44 July, 2008 V.28P F71862 +12V Pull-up resister 4.7K Ohms Pull-up resister < 1K or totem-pole output +12V FAN Out GND 10K 22K~30K Fan Input +12V FANIN 1 FAN Out GND > 1K +12V Fan Input FANIN 1 F71862 3.3V Zener FAN Connector F71862 Fan with Tach Pull-Up to +12V, or Totern-Pole Output and Register Attenuator Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp Fig 7-4 / 7-5 +5V Pull-up resister 4.7K Ohms Pull-up resister < 1K or totem-pole output +5V FAN Out GND 10K 1K~2.7K Fan Input +5V FANIN1 FAN Out GND > 1K +5V Fan Input FANIN1 F71862 3.3V Zener FAN Connector F71862 Fan with Tach Pull-Up to +5V, or Totern-Pole Output and Register Attenuator Fan with Tach Pull-Up to +5V, or Totem-Pole Putput and Zener Clamp Fig 7-6 / 7-7 Determine the fan counter according to: Count = 1.5 × 10 6 RPM In other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. As for fan, it would be best to use 2 pulses tachometer output per round. RPM = 1.5 × 10 6 Count Fan speed control The F71862 provides 2 fan speed control methods: 1. DAC FAN CONTROL 2. PWM DUTY CYCLE DAC Fan Control 45 July, 2008 V.28P F71862 The range of DC output is 0~3.3V, controlled by 8-bit register. 1 LSB is about 0.013V. The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN OPERATION VOLTAGE, 12V. The output voltage will be given as followed: Programmed 8bit Register Value 255 Output_voltage (V) = 3.3 × And the suggested application circuit for linear fan control would be: 12V 3 D C OUTPUT VOLTAGE 2 8 + 4 1 LM358 PMOS D1 1N4148 R 4.7K JP1 R 10K C 47u 3 2 1 CON3 R 27K FANIN MONITOR C 0.1u R 10K R 3.9K DC FAN Control with OP Fig 7-8 PWM duty Fan Control The duty cycle of PWM can be programmed by a 8-bit register. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Duty_cycle(%) = +12V Programmed 8bit Register Value × 100% 255 +5V R1 R2 D G PWM Clock Input NMOS S + C FAN PWM Clock Input G PNP Transistor R1 R2 D NMOS S + C FAN PNP Transistor Fig 7-9 Fan speed control mechanism 46 July, 2008 V.28P F71862 There are some modes to control fan speed and they are 1.Manual mode, 2.Stage auto mode, 3. Linear auto mode. More detail, please refer the description of registers. Manual mode For manual mode, it generally acts as software fan speed control. Stage auto mode At this mode, the F71862 provides automatic fan speed control related to temperature variation of CPU/GPU or the system. The F71862 can provide two temperature boundaries and three intervals, and each interval has its related fan speed PWM duty. All these values should be set by BIOS first. Take figure 7-10 as example. When temperature boundaries are set as 45 and 75°C and there are three intervals. The related desired fan speed for each interval are 40%, 80% and 100% (fixed). When the temperature is within 45~75’C, the fan speed will follow 80% PWM duty and that define in registers. It can be said that the fan will be turned on with a specific speed set by BIOS and automatically controlled with the temperature variation. The F71862 will take charge of all the fan speed control and need no software support. Temperature PWM Duty 100% 75 Degree C 80% 45 Degree C 40% Temperature Fan Speed Figure 7-10 Below is a sample for Stage auto mode: Set temperature as 60°C, 40°C and Duty as 100%, 70%, 50% PWM duty 100% 60 Degree C hysteresis 57 Degree C 40 Degree C 50% 70% Temp. Fan Speed a b c d 47 July, 2008 V.28P F71862 a. Once temp. is under 40°C, the lowest fan speed keeps 50% PWM duty b. Once temp. is over 40°C,60°C, the fan speed will vary from 70% to 100% PWM duty and increase with temp. level. c. Once temp. keeps in 55°C, fan speed keeps in 70% PWM duty reduces to 70% PWM duty and stays there. d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 57°C, fan speed Linear auto mode Otherwise, F71862 supports linear auto mode. Below has a example to describe this mode. More detail, please refer the register description. A. Linear auto mode (PWM Duty I) Set temperature as 70°C, 40°C and Duty as 100%, 70%, 40% PWM duty 70 Degree C hysteresis 65 Degree C 100% 70% 40 Degree C Temp. Fan Speed 40% a b c d a. Once temp. is under 40°C, the lowest fan speed keeps 40% PWM duty b. Once temp. is over 40°C and under 70°C, the fan speed will vary from 40% to 70% PWM duty and linearly increase with temp. variation. and flash interval is 1sec. c. Once temp. goes over 70°C, fan speed will directly increase to 100% PWM duty (full speed) d. If set the hysteresis as 5°C(default is 4°C), once temp reduces under 65°C (not 70°C), fan speed reduces from 100% PWM duty and decrease linearly with temp.. The temp.-fan speed monitoring FAN_FAULT# Fan_Fault# will be asserted when the fan speed doesn’t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to PWM duty-cycle which should be able to turn on the fan. There are two conditions may 48 July, 2008 V.28P F71862 cause the FAN_FAULT# event. (1). When PWM_Duty reaches 0xFF, the fan speed count can’t reach the fan expected count in time. (Figure 7-11) 11 sec(default) Current Fan Count Expected Fan Count 100% Duty-cycle Fan_Fault# Fig 7-11 (2). After the period of detecting fan full speed, when PWM_Duty > Min. Duty, and fan count still in 0xFFF. Before the device registers, the following is a register map order which shows a summary of all registers. Please refer each one register if you want more detail information. Register CR01 ~ CR03 Register CR10 ~ CR4F Register CR60 ~ CR8E Register CR90 ~ CRDF Configuration Registers Voltage Setting Register Temperature Setting Register Fan Control Setting Register Fan1 Detail Setting CRA0 ~ CRAF Fan2 Detail Setting CRB0 ~ CRBF Fan3 Detail Setting CRC0 ~ CRCF Configuration Registers Configuration Register  Index 01h Bit 7-3 2 1 0 Name Reserved POWER_DOWN FAN_START V_T_START R/W Default 0h R/W R/W R/W 0 0 1 1 Reserved Hardware monitor function power down. Set one to enable startup of fan monitoring operations; a zero puts the part in standby mode. Set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. Description Configuration Register  Index 02h Bit 7 6 Name Reserved CASE_BEEP_EN R/W Default R/W R/W 0 0 Dummy register. 0: Disable case open event output via BEEP. 1: Enable case open event output via BEEP. Description 49 July, 2008 V.28P 0 5-4 3 2 OVT_MODE Reserved CASE_SMI_EN R/W R/W R/W 0 0 0 1-0 ALERT_MODE R/W 00: The OVT# will be low active level mode. 01: The OVT# will be high active level mode. 10: The OVT# will indicate by 1Hz LED function. 11: The OVT# will indicate by (400/800HZ) BEEP output. Dummy register. 0: Disable case open event output via PME. 1: Enable case open event output via PME. 00: The ALERT# will be low active level mode. 01: The ALERT# will be high active level mode. 10: The ALERT# will indicate by 1Hz LED function. 11: The ALERT# will indicate by (400/800HZ) BEEP output. F71862 Configuration Register  Index 03h Bit 7-1 0 Name Reserved CASE_STS R/W Default R/W R/W 0 0 Return 0 when read. Case open event status, write 1 to clear if case open event cleared. Description Configuration Register  Index 0Ah Bit 7-6 5 4 Name Reserved T1_IIR_EN Reserved R/W Default R/W R/W 00 0 0 0 3-2 VTT_SEL R/W Reserved. Set 1 to enable IIR for AMDSI/PECI reading. The reading will be more stable. Reserved. PECI (Vtt) voltage select. 00: Vtt is 1.23V 01: Vtt is 1.13V 10: Vtt is 1.00V 11: Vtt is 1.00V CPU Temperature Measurement method. 00: with external diode. 01: with PECI interface. 10: with AMDSI interface. 11: reserved. Description 00 1-0 MEAS_TYPE R/W Configuration Register  Index 0Bh Bit Name 0 (MEAS_TYPE == 2’b01) Description Select the Intel CPU socket number. 0000: no CPU presented. PECI host will use Ping() command to find CPU address. 0001: CPU is in socket 0, i.e. PECI address is 0x30. 0010: CPU is in socket 0, i.e. PECI address is 0x31. 0100: CPU is in socket 0, i.e. PECI address is 0x32. 1000: CPU is in socket 0, i.e. PECI address is 0x33. Otherwise are reserved. Reserved. If the CPU selected is dual core. Set this register 1 to read the temperature of domain1. R/W Default 7-4 CPU_SEL R/W 3-1 0 Reserved DOMAIN1_EN R/W 0 0 Configuration Register  Index 0Bh Bit Name (MEAS_TYPE ==2’b10) Description R/W Default 50 July, 2008 V.28P F71862 7-0 AMDSI_VER R Return the AMDSI version. Configuration Register  Index 0Ch Bit 7-0 Name TCC_TEMP (MEAS_TYPE == 2’b01) Description R/W Default R/W 8’h55 TCC Activation Temperature. The absolute value of CPU temperature is calculated by the equation: CPU_TEMP = TCC_TEMP + PECI Reading. The range of this register is 0 ~ 255. Configuration Register  Index 0Ch Bit 7-0 Name NODE_ID (MEAS_TYPE ==2’b10) Description Return the AMDSI node id. R/W Default R - Configuration Register  Index 0Dh Bit 7-0 Name Reserved R/W Default Reserved. Description Configuration Register  Index 0Eh Bit 7-4 Name Reserved R/W Default R/W 0 0 3 PECI_SCALE_ADD R/W Reserved. This register is used to indicate how to calculate the PECI reading with PECI_SCALE register. 0: The real value is the reading adds the value calculated by PECI_SCALE. 1: The real value is the reading adds the value calculated by PECI_SCALE. This register is used to control the PECI reading slope. See also PECI_SCALE_ADD register. 000: The real value is the PECI reading. 001: The real value is (1 ± 1/2) PECI reading. 010: The real value is (1 ± 1/4) PECI reading. 011: The real value is (1 ± 1/8) PECI reading. 100: The real value is (1 ± 1/16) PECI reading. 101: The real value is (1 ± 1/32) PECI reading. 110: The real value is (1 ± 1/64) PECI reading. 111: The real value is (1 ± 1/128) PECI reading. Description 0 2-0 PECI_SCALE R/W Configuration Register  Index 0Fh Bit 7-0 Name Reserved. R/W Default Reserved Description Voltage Setting Voltage1 Voltage reading and limit Index 20h- 4Fh Address 20h 21h Attribute RO RO Default Value --Description VCC3V reading. The unit of reading is 8mV. V1 (Vcore) reading. The unit of reading is 8mV. 51 July, 2008 V.28P F71862 22h 23h 24h 25h 26h 27h 28h 29~2Fh 30~4Fh RO RO RO RO RO RO RO RO RO -------FF FF V2 reading. The unit of reading is 8mV. V3 reading. The unit of reading is 8mV. V4 reading. The unit of reading is 8mV. V5 reading. The unit of reading is 8mV. V6 reading. The unit of reading is 8mV. VSB3V reading. The unit of reading is 8mV. VBAT reading. The unit of reading is 8mV. Reserved Reserved Temperature Setting Temperature PME# Enable Register  Index 60h Bit 7 6 5 4 3 2 1 0 Name EN_ T3_OVT_PME EN_ T2_ OVT_PME EN_ T1_ OVT_PME Reserved EN_ T3_EXC_PME EN_ T2_EXC_PME EN_ T1_EXC_PME Reserved R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description If set this bit to 1, PME# signal will be issued when TEMP3 exceeds OVT limit setting. If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT setting. If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT setting. Reserved If set this bit to 1, PME# signal will be issued when TEMP3 exceeds high limit setting. If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high limit setting. If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high limit setting. Reserved Temperature Interrupt Status Register  Index 61h Bit 7 Name T3_OVT_STS R/W Default 0 R/W 0 6 T2_OVT _STS R/W 0 5 4 3 T1_OVT _STS Reserved T3_EXC _STS R/W R/W R/W 0 2 T2_EXC _STS R/W 0 1 0 T1_EXC _STS Reserved R/W R/W 0 0 0 Description A one indicates TEMP3 temperature sensor has exceeded OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be ignored. A one indicates TEMP2 temperature sensor has exceeded OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be ignored. A one indicates TEMP1 temperature sensor has exceeded OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be ignored. Reserved A one indicates TEMP3 temperature sensor has exceeded high limit or below the “high limit –hysteresis”. Write 1 to clear this bit, write 0 will be ignored. A one indicates TEMP2 temperature sensor has exceeded high limit or below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates TEMP1 temperature sensor has exceeded high limit or below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will be ignored. Reserved 52 July, 2008 V.28P F71862 Temperature Real Time Status Register  Index 62h Bit 7 6 5 4 3 2 1 0 Name T3_OVT T2_OVT T1_OVT Reserved T3_EXC T2_EXC T1_EXC Reserved R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description Set when the TEMP3 exceeds the OVT limit. Clear when the TEMP3 is below the “OVT limit –hysteresis” temperature. Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is below the “OVT limit –hysteresis” temperature. Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is below the “OVT limit –hysteresis” temperature. Reserved Set when the TEMP3 exceeds the high limit. Clear when the TEMP3 is below the “high limit –hysteresis” temperature. Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is below the “high limit –hysteresis” temperature. Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is below the “high limit –hysteresis” temperature. Reserved Temperature BEEP Enable Register  Index 63h Bit 7 6 5 4 3 2 1 0 Name EN_ T3_OVT_BEEP EN_ T2_ OVT_BEEP EN_ T1_ OVT_BEEP Reserved EN_ T3_EXC_BEEP EN_ T2_EXC_BEEP EN_ T1_EXC_BEEP Reserved R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds OVT limit setting. If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT limit setting. If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT limit setting. Reserved If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds high limit setting. If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high limit setting. If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high limit setting. Reserved OVT Output Enable Register 1  Index 66h Bit 7 6 5 4 3 2 1 0 Name EN_T3_ALERT EN_T2_ALERT EN_T1_ALERT Reserved EN_T3_OVT EN_T2_OVT EN_T1_OVT Reserved R/W Default R R R R R/W R/W R/W R 0 0 0 0 0 0 1 0h Description Enable temperature 3 alert event (asserted when temperature over high limit) Enable temperature 2 alert event (asserted when temperature over high limit) Enable temperature 1 alert event (asserted when temperature over high limit) Reserved for temp4 Enable over temperature (OVT) mechanism of temperature3. Enable over temperature (OVT) mechanism of temperature2. Enable over temperature (OVT) mechanism of temperature1. Reserved. 53 July, 2008 V.28P Temperature Sensor Type Register  Index 6Bh Bit 7-4 3 2 1 0 Name Reserved T3_MODE T2_MODE T1_MODE Reserved R/W Default RO R/W R/W R/W R 0 1 1 1 0h -0: TEMP3 is connected to a thermistor 1: TEMP3 is connected to a BJT.(default) 0: TEMP2 is connected to a thermistor. 1: TEMP2 is connected to a BJT. (default) 0: TEMP1 is connected to a thermistor 1: TEMP1 is connected to a BJT.(default) -Description F71862 TEMP1 Limit Hystersis Select Register -- Index 6Ch Bit 7-4 3-0 Name TEMP1_HYS Reserved R/W Default R/W R 4h 0h Description Limit hysteresis. (0~15 degree C) Temperature and below the ( boundary – hysteresis ). -- TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh Bit 7-4 3-0 Name TEMP3_HYS TEMP2_HYS R/W Default R/W R/W 2h 4h Description Limit hysteresis. (0~15 degree C) Temperature and below the ( boundary – hysteresis ). Limit hysteresis. (0~15 degree C) Temperature and below the ( boundary – hysteresis ). DIODE OPEN Status Register -- Index 6Fh Bit 7-4 3 2 1 Name Reserved T3_DIODE_OPEN T2_DIODE_OPEN T1_DIODE_OPEN R/W Default RO RO RO RO 0h 0h 0h 0h Reserved External diode 3 is open External diode 2 is open This register indicates the abnormality of temperature 1 measurement. When AMDSI interface is enabled, it indicates the error of not receiving ACK bit when read TCON command is asserted. When PECI interface is enabled, it indicates a error code is received from PECI slave. When external diode is used, it indicates the BJT is open or short. -Description 0 Reserved R 0h Temperature  Index 70h- 8Fh Address 70h 71h 72h 73h 74h 75h Attribute Reserved Reserved RO RO RO RO Default Value FFh FFh ----Reserved Reserved Temperature 1 reading. The unit of reading is 1ºC.At the moment of reading this register. Reserved Temperature 2 reading. The unit of reading is 1ºC.At the moment of reading this register. Reserved Description 54 July, 2008 V.28P 76h 77-7Bh 7C-7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88-8Bh 8C~8Dh RO RO RO Reserved Reserved R/W R/W R/W R/W R/W R/W RO RO --FFh FFh FFh 64h 55h 64h 55h 55h 46h -FFH Temperature 3 reading. The unit of reading is 1 C.At the moment of reading this register. Reserved Reserved Reserved Reserved Temperature sensor 1 OVT limit. The unit is 1ºC. Temperature sensor 1 high limit. The unit is 1ºC. Temperature sensor 2 OVT limit. The unit is 1ºC. Temperature sensor 2 high limit. The unit is 1ºC. Temperature sensor 3 OVT limit. The unit is 1ºC. Temperature sensor 3 high limit. The unit is 1ºC. Reserved Reserved º F71862 Temperature Filter Select Register -- Index 8Eh Bit Name R/W Default Description The queue time for second filter to quickly update values. 00: disable. 01: 16 times. 10: 32 times. (default) 11: 48 times. The queue time for second filter to quickly update values. 00: disable. 01: 16 times. 10: 32 times. (default) 11: 48 times. The queue time for second filter to quickly update values. 00: disable. 01: 16 times. 10: 32 times. (default) 11: 48 times. -- 7-6 IIR-QUEUR3 R/W 0h 5-4 IIR-QUEUR2 R/W 0h 3-2 IIR-QUEUR1 R/W 0h 0 Reserved R 0h Fan Control Setting FAN PME# Enable Register  Index 90h Bit Name EN_FAN3_PME EN_FAN2_PME EN_FAN1_PME R/W Default RO R/W R/W R/W 0h 0h 0h 0h Reserved A one enables the corresponding interrupt status bit for PME# interrupt.. Set this bit 1 to enable PME# function for Fan3. A one enables the corresponding interrupt status bit for PME# interrupt. Set this bit 1 to enable PME# function for Fan2. A one enables the corresponding interrupt status bit for PME# interrupt. Set this bit 1 to enable PME# function for Fan1. Description 7-3 Reserved 2 1 0 FAN Interrupt Status Register  Index 91h Bit 7-3 Name Reserved R/W Default RO 0 Reserved Description 55 July, 2008 V.28P F71862 2 1 0 FAN3_STS FAN2_STS FAN1_STS R/W R/W R/W ---This bit is set when the fan3 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. This bit is set when the fan2 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. This bit is set when the fan1 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. FAN Real Time Status Register  Index 92h Bit 7-3 2 1 0 Name Reserved FAN3_EXC FAN2_EXC FAN1_EXC R/W Default -RO RO RO 0 ---Reserved This bit set to high mean that fan3 count can’t meet expect count over than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. This bit set to high mean that fan2 count can’t meet expect count over than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. This bit set to high mean that fan1 count can’t meet expect count over than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. Description FAN BEEP# Enable Register  Index 93h Bit 7 6 5 4 3 2 1 0 Name R/W Default 0 0 0 0 0 0 0 0 Description Set one will enable FAN to force full speed when T3 over high limit. Set one will enable FAN to force full speed when T2 over high limit. Set one will enable FAN to force full speed when T1 over high limit. Reserved for local temperature. Reserved. A one enables the corresponding interrupt status bit for BEEP. A one enables the corresponding interrupt status bit for BEEP. A one enables the corresponding interrupt status bit for BEEP. FULL_WITH_T3_EN R/W FULL_WITH_T2_EN R/W FULL_WITH_T1_EN R/W Reserved Reserved EN_FAN3_ BEEP EN_FAN2_ BEEP EN_FAN1_ BEEP R/W R R/W R/W R/W Fan Type Select Register -- Index 94h Bit Name R/W Default R 0 Reserved. Description 7-6 Reserved 5-4 FAN3_TYPE R/W 3-2 FAN2_TYPE R/W 1-0 FAN1_TYPE R/W 00: Output PWM mode (pushpull) to control fans. 01: Use linear fan application circuit to control fan speed by fan’s power 2’b 0S terminal . 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. 00: Output PWM mode (pushpull) to control fans. 01: Use linear fan application circuit to control fan speed by fan’s power 2’b 0S terminal . 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. 00: Output PWM mode (push pull) to control fans. 01: Use linear fan application circuit to control fan speed by fan’s power 2’b 0S terminal . 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. S: Register default values are decided by trapping. 56 July, 2008 V.28P F71862 Fan mode Select Register -- Index 96h Bit Name R/W Default R 0 Reserved. 00: Reserved 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle (voltage) that define in 0xB6-0xBE. 10: Reserved 11: Manual mode fan control, user can write expect duty cycle (PWM fan type) or voltage(linear fan type) to 0xC3, and F71883FG will output this value duty or voltage to control fan speed. 00: Reserved. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle (voltage) that define in 0xB6-0xBE. 10: Reserved. 11: Manual mode fan control, user can write expect duty cycle (PWM fan type) or voltage (linear fan type) to 0xB3, and F71883FG will output this value duty or voltage to control fan speed. 00: Reserved. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle that define in 0xA6-0xAE. 10: Reserved. 11: Manual mode fan control, user can write expect duty cycle (PWM fan type) or voltage(linear fan type) to 0xA3, and F71883FG will output this value duty or voltage to control fan speed. Description 7-6 Reserved 5-4 FAN3_MODE R/W 1h 3-2 FAN2_MODE R/W 1h 1-0 FAN1_MODE R/W 1h Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h Bit 7-4 Name FAN2_HYS R/W Default 4h R/W 4h 3-0 FAN1_HYS R/W Description 0000: Boundary hysteresis. (0~15 degree C) Segment will change when the temperature over the boundary temperature and below the ( boundary – hysteresis ). 0000: Boundary hysteresis. (0~15 degree C) Segment will change when the temperature over the boundary temperature and below the ( boundary – hysteresis ). Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 99h Bit Name R/W Default R R/W 0 2h 3-0 FAN3_HYS Reserved. 0000: Boundary hysteresis. (0~15 degree C) Segment will change when the temperature over the boundary temperature and below the ( boundary – hysteresis ). Description 7-4 Reserved Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 9Bh Bit Name R/W Default R 0 1h 5-4 FAN3_RATE_SEL R/W Reserved. Fan3 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Description 7-6 Reserved 57 July, 2008 V.28P F71862 1h 3-2 FAN2_RATE_SEL R/W Fan2 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan1 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz 1h 1-0 FAN1_RATE_SEL R/W FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE  Index 9Ch Bit 7-4 Name FAN2_STOP_DUTY R/W Default 5h R/W 5h 3-0 FAN1_STOP_DUTY R/W Description When fan start, the FAN_CTRL2 will increase duty-cycle from 0 to this (value x 8) directly. And if fan speed is down, the FAN_CTRL 2 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 to this (value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). FAN3 START UP DUTY-CYCLE/VOLTAGE  Index 9Dh Bit Name R/W Default R R/W 0 5h 3-0 FAN3_STOP_DUTY Reserved. When fan start, the FAN_CTRL 3 will increase duty-cycle from 0 to this (value x 8 directly. And if fan speed is down, the FAN_CTRL 3 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). Description 7-4 Reserved Fan Fault Time Register -- Index 9Fh Bit 7-5 4 Name Reserved FULL_DUTY_SEL R/W Default -R/W R 0 --Reservd 0: the full duty is 100%. 1: the full duty is 60% (default). This register is power on trap by DTR1#. Reserved. Description 3-0 Reserved Fan1 Index A0h- AFh Address Attribute Default Value Description FAN1 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 count reading (LSB). A0h RO 8’h0f A1h RO 8’hff 58 July, 2008 V.28P F71862 A2h A3h R/W 8’h01 Reserved The Value programming in this byte is duty value. In auto fan mode(CR96 bit5 0) this register is updated by hardware. Ex: 5 5*100/255 % 255 100% FAN1 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 full speed count reading (LSB). A4h A5h R/W R/W 8’h03 8’hff VT1 BOUNDARY 1 TEMPERATURE – Index A6h Bit 7 Name Reserved R/W RO Default 0 Return 0 when read. Description 6-0 BOUND1TMP1 R/W st 3Ch The 1 BOUNDARY temperature for VT1 in temperature mode. (60oC) When VT1 temperature is exceed this boundary, FAN1 expect value will load full speed duty 8’hFF. When VT1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 1 register (index ABh). VT1 BOUNDARY 2 TEMPERATURE – Index A9 Bit 7 Name Reserved R/W Default RO 0 Return 0 when read. Description 6-0 BOUND4TMP1 R/W st 1Eh The 2 BOUNDARY temperature for VT1 in temperature mode. o (30 C) When VT1 temperature is exceed this boundary, FAN1 expect value will load from segment 1 register (index ABh). When VT1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 2 register (index AEh). FAN1 SEGMENT 1 SPEED COUNT Bit 7-0 Name SEC1SPEED1 – Index ABh Description R/W Default R/W D9h The value that set in this byte is mean the expect PWM duty-cycle in this (85%) temperature section. FAN1 SEGMENT 2 SPEED COUNT Bit 7-0 Name SEC2SPEED1 – Index AEh Description R/W Default R/W 80h The value that set in this byte is mean the expect PWM duty-cycle in this (50%) temperature section. FAN1 Temperature Mapping Select Bit 7-6 5 4 Name Reserved FAN1_UP_T_EN – Index AFh Description Reserved Set 1 to force FAN1 to full speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. This register controls the FAN1 duty movement when temperature over highest boundary. 0: The FAN1 duty will increases with the slope selected by FAN1_RATE_SEL register (Index 9Bh). 1: The FAN1 duty will directly jumps to full speed. R/W Default -R/W 0 0 0 1 FAN1_INTERPOLATION_ R/W EN 3 FAN1_JUMP_HIGH_EN R/W 59 July, 2008 V.28P 1 2 FAN1_JUMP_LOW_EN R/W 1-0 Fan1_temp_sel R/W 1h This register controls the FAN1 duty movement when temperature under (highest boundary – hysteresis). 0: The FAN1 duty will decreases with the slope selected by FAN1_RATE_SEL register (Index 9Bh). 1: The FAN1 duty will directly jumps to the value of SEC1SPEED1 register. 0: reserved. 1: fan1 follow temperature 1. 2: fan1 follow temperature 2. 3: fan1 follow temperature 3. F71862 Fan2 Index B0h- BFh Address Attribute Default Value Description FAN1 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 count reading (LSB). Reserved The Value programming in this byte is duty value. In auto fan mode(CR96 bit5 0) this register is updated by hardware. Ex: 5 5*100/255 % 255 100% FAN1 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 full speed count reading (LSB). B0h RO 8’h0f B1h B2h B3h RO R/W R/W 8’hff 8’h00 8’h01 B4h B5h R/W R/W 8’h03 8’hff VT2 BOUNDARY 1 TEMPERATURE – Index B6h Bit 7 Name Reserved R/W Default RO 0 Return 0 when read. Description 6-0 BOUND1TMP2 R/W st 3Ch The 1 BOUNDARY temperature for VT2 in temperature mode. (60oC) When VT2 temperature is exceed this boundary, FAN2 expect value will load full speed duty 8’hFF. When VT2 temperature is below this boundary – hysteresis, FAN2 expect value will load from segment 1 register (index BBh). VT2 BOUNDARY 2 TEMPERATURE – Index B9 Bit 7 Name Reserved R/W Default RO 0 Return 0 when read. Description 6-0 BOUND2TMP1 R/W st 1Eh The 2 BOUNDARY temperature for VT1 in temperature mode. o (30 C) When VT1 temperature is exceed this boundary, FAN1 expect value will load from segment 1 register (index BBh). When VT1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 2 register (index BEh). 60 July, 2008 V.28P F71862 FAN2 SEGMENT 1 SPEED COUNT Bit 7-0 Name SEC1SPEED2 – Index BBh Description R/W Default R/W D9h The value that set in this byte is mean the expect PWM duty-cycle in this (85%) temperature section. FAN2 SEGMENT 2 SPEED COUNT Bit 7-0 Name SEC2SPEED2 – Index BEh Description R/W Default R/W 80h The value that set in this byte is mean the expect PWM duty-cycle in this (50%) temperature section. FAN2 Temperature Mapping Select Bit 7-6 5 4 Name Reserved FAN2_UP_T_EN – Index BFh Description Reserved Set 1 to force FAN2 to full speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. This register controls the FAN2 duty movement when temperature over highest boundary. 0: The FAN2 duty will increases with the slope selected by FAN2_RATE_SEL register (Index 9Bh). 1: The FAN2 duty will directly jumps to full speed. This register controls the FAN2 duty movement when temperature under (highest boundary – hysteresis). 0: The FAN2 duty will decreases with the slope selected by FAN2_RATE_SEL register (Index 9Bh). 1: The FAN2 duty will directly jumps to the value of SEC1SPEED2 register. 0: reserved. 1: fan2 follow temperature 1. 2: fan2 follow temperature 2. 3: fan2 follow temperature 3. R/W Default -R/W 0 0 0 1 FAN2_INTERPOLATION_ R/W EN 3 FAN2_JUMP_HIGH_EN R/W 1 2 FAN2_JUMP_LOW_EN R/W 1-0 Fan2_temp_sel R/W 2h Fan3 Index C0h- CFh Address Attribute Default Value Description FAN3 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN3 count reading (LSB). Reserved. The Value programming in this byte is duty value. In auto fan mode(CR96 bit5 0) this register is updated by hardware. Ex: 5 5*100/255 % 255 100% FAN3 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. C0h RO 8’h0F C1h C2h C3h RO R/W 8’hff 8’h01 C4h R/W 8’h03 61 July, 2008 V.28P F71862 C5h R/W 8’hff FAN3 full speed count reading (LSB). VT3 BOUNDARY 1 TEMPERATURE – Index C6h Bit 7 Name Reserved R/W Default RO 0 Return 0 when read. Description 6-0 BOUND1TMP3 R/W st 3Ch The 1 BOUNDARY temperature for VT3 in temperature mode. (60oC) When VT3 temperature is exceed this boundary, FAN3 expect value will load the full speed duty 8’hFF. When VT3 temperature is below this boundary – hysteresis, FAN3 expect value will load from segment 1 register (index CBh). VT3 BOUNDARY 2 TEMPERATURE – Index C9 Bit 7 Name Reserved R/W Default RO 0 Return 0 when read. Description 6-0 BOUND2TMP3 R/W st 1Eh The 2 BOUNDARY temperature for VT3 in temperature mode. (30oC) When VT3 temperature is exceed this boundary, FAN3 expect value will load from segment 1 register (index CBh). When VT3 temperature is below this boundary – hysteresis, FAN3 expect value will load from segment 2 register (index CEh). FAN3 SEGMENT 1 SPEED COUNT Bit 7-0 Name SEC1SPEED3 – Index CBh Description R/W Default R/W D9h The value that set in this byte is mean the expect PWM duty-cycle in this (85%) temperature section. FAN3 SEGMENT 2 SPEED COUNT Bit 7-0 Name SEC2SPEED3 – Index CEh Description R/W Default R/W 80h The value that set in this byte is mean the expect PWM duty-cycle in this (50%) temperature section. FAN3 Temperature Mapping Select Bit 7-6 5 4 Name Reserved FAN3_UP_T_EN – Index CFh Description Reserved Set 1 to force FAN3 to full speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. This register controls the FAN3 duty movement when temperature over highest boundary. 0: The FAN3 duty will increases with the slope selected by FAN3_RATE_SEL register (Index 9Bh). 1: The FAN3 duty will directly jumps to full speed. This register controls the FAN3 duty movement when temperature under (highest boundary – hysteresis). 0: The FAN3 duty will decreases with the slope selected by FAN3_RATE_SEL register (Index 9Bh). 1: The FAN3 duty will directly jumps to the value of SEC1SPEED3 register. R/W Default -R/W 0 0 0 1 FAN3_INTERPOLATION_ R/W EN 3 FAN3_JUMP_HIGH_EN R/W 1 2 FAN3_JUMP_LOW_EN R/W 62 July, 2008 V.28P 1-0 Fan3_temp_sel R/W 3h 0: reserved. 1: fan3 follow temperature 1. 2: fan3 follow temperature 2. 3: fan3 follow temperature 3. F71862 7.7 SPI Interface Communication between the two devices is handling the serial peripheral interface (SPI). Every SPI system consist of one master and one or more slaves, where a master provides the SPI clock and slave receives clock from the master. This design is only master function, for basic signal, master-out/slave-in (MOSI), master-in/slave-out (MISO), serial clock (SCK), and 4 slaves select (SS), are needed for SPI interface. Each of slave select supports from 512kbits to 4096kbits flash is decided by configuration register. Serial clock (SCK) signal frequency is varied from 24MHz to 187.5 KHz. The serial data (MOSI) for SPI interface translates to depend on SCK rising edge or falling edge is decided by configuration register. 7.8 ACPI Function The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of power in a computer. It lets computer manufacturer and user to determine the computer’s power usage dynamically. There are three ACPI states that are of primary concern to the system designer and they are designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this state. The other two are called sleep states and reflect different power consumption when power-down. S3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. S5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. Take S3 and S5 as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3. It is anticipated that only the following state transitions may happen: S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5. Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is necessary to enter S0 first in order to get to S5 from S3. As for transition S5→S3 will occur only as an immediate state during state transition from S5→S0. It isn’t allowed in the normal state transition. The below diagram described the timing, the always on and always off, keep last state could be set in control register. In keep last state mode, one register will keep the status of before power loss. If it is power on before power loss, it will remain power on when power is resumed, otherwise, if it is power off before power loss, it will remain power off when power is July, 2008 V.28P 63 F71862 resumed. VBAT VSB RSMRST# S3# PS_ON# PSIN# PSOUT# VCC3V DEFAULT TIMING Always off VBAT VSB RSMRST# S3# PS_ON# PSIN# PSOUT# VCC3V ALways ON TIMING PCI Reset and PWROK Signals The F71862 supports 3 output buffers for 3 reset signals. If the register RSTCON_EN is set to 1, the pin RSTCON# will infect PCIRST1# ~ PCIRST3# outcome. Then, the result of PCIRST# outcome will be affected by conditions as below: PCIRST1# Output buffer of RSTCON# and LRESET#. PCIRST2# Output buffer of RSTCON# and LRESET#. PCIRST3# Output buffer of RSTCON# and LRESET#. 64 July, 2008 V.28P F71862 +3.3V ATXPG RSTCON# Delay PWROK RSTCON# LRESET# PCIRST1~3# So far as the PWROK issue is as the figure above. PWROK is delayed 400ms (default) as VCC arrives 2.8V, and the delay timing can be programmed by register. (100ms ~ 400ms) In the figure, the RSTCON# will be implemented by register RSTCON_EN. If RSTCON_EN be set to 0, the RSTCON# pin will affect PWROK outputs(Default). If RSTCON_EN be set to 1, the RSTCON# pin will affect PCIRST outputs. VCC3 CPU 1 3 2 1K-8P4R 4 1K-8P4R NORTH BRIDGE IDE ATA 133 PCIRST3# PCIRST3# PCIRST2# VSB3 FRONT PANEL VSB3 SATA*2 SOUTH BRIDGE 1 2 R85 4.7K R88 1 33 Front Panel 2 7 RESET PSW8 R87 12 2 C47 0.1UF 5 RSTGND PSW+ 6 -PWR_BTN 1 2 R86 4.7K 1 R STCON# PCIRST2# LRESET# F71862 PCI S3# PWSOUT# RSMRST# PCIRST1# VSB5 1 R90 4.7K -12V 2 ATX1 3V3 3V3 -12V 3V3 GND GND PS-ON 5V GND GND GND 5V GND GND -5V PW-OK 5V 5VSB 5V 12V 1 3 1 1K 2 4.7K 4 4.7K 2 VSB3 VCC3 PCLK_1,2,3(33MHz) PWSIN# ATXPG_IN PSON# VCC5 1 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 VCC3 VCC5 VSB5 1 VSB5 2 R91 4.7K +12V Title Size A Date: ATX CONNECTOR ATX CONNECTOR 2 TC1 22uF Feature Integration Technology Inc. Document Number Example_ACPI Tuesday , May 16, 2006 Sheet 7 of 7 Rev 0.10 ACPI Reference Circuit Status Pins Application The F71862 provides two status pins (ST1/ST2) and S5 signal for user application. The state 65 July, 2008 V.28P F71862 and timing sequence of each signal is as below: 7.9 AMDSI and Intel PECI Function The F71862 provides Intel PECI/AMDSI interfaces for new generational CPU temperature sensing. In AMDSI interface, there are SIC and SID signals for temperature information reading from AMD CPU. The SIC signal is for clocking use, the other is for data transferring. More detail please refer register description. VDDIO 300 300 SIC SID AMD CPU SIC SID F71862 In Intel PECI interface, the F71862 can connect to CPU directly. The F71862 can read the temperature data from CPU, than the fan control machine of F71862 can implement the Fan to cool down CPU temperature. The application circuit is as below. More detail please refer the register description. 66 July, 2008 V.28P F71862 Intel CPU PECI 100K avoid pre-BIOS floating F71862 PECI 67 July, 2008 V.28P F71862 8. Register Description The configuration register is used to control the behavior of the corresponding devices. To configure the register, using the index port to select the index and then writing data port to alter the parameters. The default index port and data port are 0x4E and 0x4F respectively. Pull down the SOUT1 pin to change the default value to 0x2E/0x2F. To enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0xAA to the index port. Following is a example to enable configuration and disable configuration by using debug. -o 4e 87 -o 4e 87 -o 4e aa ( enable configuration ) ( disable configuration ) The Following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of all registers and their default value. Please refer each device chapter if you want more detail information. Global Control Registers “-“ Reserved or Tri-State Global Control Registers Register 0x[HEX] 02 07 20 21 23 24 25 26 27 28 29 2A 2B 2C 2D Register Name MSB Software Reset Register Logic Device Number Register (LDN) Chip ID Register Chip ID Register Vender ID Register Vender ID Register Software Power Down Register UART IRQ Sharing Register ROM Address Select Register Power LED Function Select Register Multi Function Select 1 Register Multi Function Select 2 Register Multi Function Select 3 Register Multi Function Select 4 Register Wakeup Control Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 1 0 1/0 0 0 0 0 0 0 0 1 1 0 1/0 0 0 0 0 0 0 0 1 0 0 0/1 0 0 0 0 1 0 1 0 0 1 0 0/1 0 0 0 0 0 0 0 1 0 0 0 0 0 0/1 0 0 0 0 0 0 Default Value LSB 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 68 July, 2008 V.28P F71862 Device Configuration Registers “-“ Reserved or Tri-State FDC Device Configuration Registers (LDN CR00) Register 0x[HEX] 30 60 61 70 74 F0 F2 F4 Register Name MSB FDC Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register DMA Channel Select Register FDD Mode Register FDD Drive Type Register FDD Selection Register 0 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1 1 1 0 Default Value LSB 1 1 0 0 0 0 1 0 UART1 Device Configuration Registers (LDN CR01) Register 0x[HEX] 30 60 61 70 F0 Register Name MSB UART1 Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register RS485 Enable Register 0 1 0 1 0 1 0 1 0 0 1 0 0 0 1 1 0 0 Default Value LSB 1 1 0 0 - UART2 Device Configuration Registers (LDN CR02) Register 0x[HEX] 30 60 61 70 F0 F1 Register Name MSB UART2 Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register RS485 Enable Register SIR Mode Control Register 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 Default Value LSB 1 0 0 1 0 Parallel Port Device Configuration Registers (LDN CR03) Register 0x[HEX] 30 60 61 70 74 Register Name MSB Parallel Port Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register DMA Channel Select Register 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 1 Default Value LSB 1 1 0 1 1 69 July, 2008 V.28P F71862 F0 PRT Mode Select Register 0 1 0 0 0 0 1 0 Hardware Monitor Device Configuration Registers (LDN CR04) Register 0x[HEX] 30 60 61 70 Register Name MSB H/W Monitor Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 Default Value LSB 1 0 1 0 KBC Device Configuration Registers (LDN CR05) Register 0x[HEX] 30 60 61 70 72 Register Name MSB KBC Device Enable Register Base Address High Register Base Address Low Register KB IRQ Channel Select Register Mouse IRQ Channel Select Register 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default Value LSB 1 0 0 0 0 GPIO Device Configuration Registers (LDN CR06) Register 0x[HEX] F0 F1 F2 F3 E0 E1 E2 E3 D0 D1 D2 D3 C0 C1 C2 C3 B0 B1 B2 B3 Register Name MSB GPIO Output Enable Register GPIO Output Data Register GPIO Pin Status Register GPIO Drive Enable Register GPIO1 Output Enable Register GPIO1 Output Data Register GPIO1 Pin Status Register GPIO1 Drive Enable Register GPIO2 Output Enable Register GPIO2 Output Data Register GPIO2 Pin Status Register GPIO2 Drive Enable Register GPIO3 Output Enable Register GPIO3 Output Data Register GPIO3 Pin Status Register GPIO3 Drive Enable Register GPIO4 Output Enable Register GPIO4 Output Data Register GPIO4 Pin Status Register GPIO4 Drive Enable Register 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 Default Value LSB 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 70 July, 2008 V.28P F71862 VID Device Configuration Registers (LDN CR07) Register 0x[HEX] 30 60 61 Register Name MSB VID Device Enable Register Base Address High Register Base Address Low Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default Value LSB 0 0 0 SPI Device Configuration Registers (LDN CR08) Register 0x[HEX] F0 F1 F2 F3 F4 F5 F6 F7 F8 FA FB FC FD FE FF Register Name MSB SPI Control Register SPI Timeout Value Register SPI Baud Rate Divisor Register SPI Status Register SPI High Byte Data Register SPI Command Data Register SPI Chip Select Register SPI Memory Mapping Register SPI Operate Register SPI Low Byte Data Register SPI Address High Byte Register SPI Address Medium Byte Register SPI Address Low Byte Register SPI Program Byte Register SPI Write Data Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default Value LSB 0 0 1 0 0 0 0 0 0 0 0 0 0 PME and ACPI Device Configuration Registers (LDN CR0A) Register 0x[HEX] 30 F0 F1 F4 F5 Register Name MSB PME Device Enable Register PME Event Enable Register PME Event Status Register ACPI Control Register ACPI Control Register 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 0 Default Value LSB 0 0 0 0 71 July, 2008 V.28P 8.1 Global Control Registers 8.1.1 Bit Software Reset Register  Index 02h Name R/W Default R/W 0 Reserved Description F71862 7-1 Reserved 0 8.1.2 Bit 7-0 LDN SOFT_RST Write 1 to reset the register and device powered by VDD ( VCC ). Logic Device Number Register (LDN)  Index 07h Name R/W Default R/W 00h Description 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 05h: Select KBC device configuration registers. 06h: Select GPIO device configuration registers. 07h: Select VID device configuration registers. 08h: Select SPI device configuration registers. 0ah: Select PME & ACPI device configuration registers. 8.1.3 Bit Chip ID Register  Index 20h Name R/W Default R 06h Chip ID 1 of F71862FG. Description 7-0 CHIP_ID1 8.1.4 Bit Chip ID Register  Index 21h Name R/W Default R 01h Chip ID2 of F71862FG. Description 7-0 CHIP_ID2 8.1.5 Bit Vendor ID Register  Index 23h Name R/W Default R 19h Vendor ID 1 of Fintek devices. Description 7-0 VENDOR_ID1 8.1.6 Bit Vendor ID Register  Index 24h Name R/W Default R 34h Vendor ID 2 of Fintek devices. Description 7-0 VENDOR_ID2 8.1.7 Bit Software Power Down Register  Index 25h Name R/W Default R/W 0 Reserved Dummy register. Description 7-6 Reserved 5 Reserved 72 July, 2008 V.28P F71862 4 3 2 1 0 8.1.8 Bit 7 SOFTPD_HM SOFTPD_PRT SOFTPD_UR2 SOFTPD_UR1 SOFTPD_FDC R/W R/W R/W R/W R/W 0 0 0 0 0 Power down the Hardware Monitor device. This will stop the Hardware Monitor clock. Power down the Parallel Port device. This will stop the Parallel Port clock. Power down the UART 2 device. This will stop the UART 2 clock. Power down the UART 1 device. This will stop the UART 1 clock. Power down the FDC device. This will stop the FDC clock. UART IRQ Sharing Register  Index 26h Name CLK24M_SEL R/W Default R/W R/W R/W 0 0 0 0: CLKIN is 48MHz 1: CLKIN is 24MHz Reserved. 0: PCI IRQ sharing mode (low level). 1: ISA IRQ sharing mode (low pulse). 0: disable IRQ sharing of two UART devices. 1: enable IRQ sharing of two UART devices. Description 6-2 Reserved 1 o IRQ_MODE IRQ_SHAR 8.1.9 Bit 7 6 ROM Address Select Register  Index 27h Name ROM_WR_EN SPI_EN R/W Default R/W R/W 0 0: disable ROM writing 1: enable ROM writing 0: SPI disable 1: SPI enable This register is power on trapped by SOUT2/SPI_TRAP. Pull down to enable SPI. Description 5 SPI_BIOS_EN R/W - 0: use SPI bridge for BIOS 1: Reserved This register is power on trapped by DTR2#/FWH_TRAP. Pull down to enable SPI bridge for BIOS. 4 PORT_4E_EN R/W - 0: The configuration register port is 2E/2F. 1: The configuration register port is 4E/4F. This register is power on trapped by SOUT1/ Config4E_2E. Pull down to select port 2E/2F. 3 SEG_000E_EN R/W - 0: disable address 0x000E0000 – 0x000EFFFF decode 1: enable address 0x000E0000 – 0x000EFFFF decode This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable. 2 SEG_FFF8_EN R/W - 0: disable address 0xFFF80000 – 0xFFFFFFFF and 0x000F0000 – 0x000FFFFF decode 1: enable address 0xFFF80000 – 0xFFFFFFFF and 0x000F0000 – 0x000FFFFF decode This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable. 73 July, 2008 V.28P F71862 1 SEG_FFEF_EN R/W 0: disable address 0xFFEE – 0xFFEFFFFF decode 1: enable address 0xFFEE0000 – 0xFFEFFFFF decode This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable. 0 SEG_FFF0_EN R/W 0 0: disable address 0xFFF00000 – 0xFFF7FFFF decode 1: enable address 0xFFF00000 – 0xFFF7FFFF decode 8.1.10 Bit Power LED Function Select Register  Index 28h Name R/W Default R/W R/W R/W R/W 0 0 0 0 Reserved. 0: IRRX/GPIO43 functions as IRRX. 1: IRRX/GPIO43 functions as GPIO43. 0: IRTX/GPIO42 functions as IRTX. 1: IRTX/GPIO42 functions as GPIO42. 0: FANCTRL3/GPIO41 functions as FANCTRL3. 1: FANCTRL3/GPIO41 functions as GPIO41. 0: FANIN3/GPIO40 functions as FANIN3. 1: FANIN3/GPIO40 functions as GPIO40. Description 7-4 Reserved 3 2 1 0 GPIO43_SEL GPIO42_SEL GPIO41_SEL GPIO40_SEL 8.1.11 Bit 7 6 5 4 3 2 1 0 Multi Function Select 1 Register  Index 29h (Powered by VSB3V) Name R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Reserved 0: FDD write-protect status depends on PIN18(WPT#) 1: FDD is write-protected 0: LED_VCC (PIN65) is tri-state if VCC power loss 1: LED_VCC (PIN65) is still programmable while VCC power loss 0: KB/MOUSE signal as default. 1: KB/MOUSE signal swapped. Reserved 0: SLOTOCC#/GPIO02 will functions as SLOTOCC#. 1: SLOTOCC#/GPIO02 will functions as GPIO02. 0: GPIO03/WDTRST# will function as GPIO03 1: GPIO03/WDTRST# will function as WDTRST#. 0: GPIO15/LED_VSB/ALERT# will function as GPIO15/LED_VSB controlled by GPIO15_SEL register. 1: GPIO15/LED_VSB/ALERT# will function as ALERT#. Description Reserved FDD_PROT_STS LEC_VCC_PRO KB_MO_SWP Reserved GPIO02_SEL WDT_GP03_EN ALERT_GP_EN 8.1.12 Bit Multi Function Select 2 Register  Index 2Ah (Powered by VSB3V) Name R/W Default Description 74 July, 2008 V.28P F71862 7-6 VSBLED_SEL R/W 2’b00 VSBLED function select, powered by VSB. 00: VSBLED always output low. 01: VSBLED tri-state 10: VSBLED output 0.5Hz clock. 11: VSBLED output 1Hz clock. ( clock output is inverse with VDDLED clock output ) 5-4 VDDLED_SEL R/W 2’b00 VDDLED function select, powered by VDD. 00: VDDLED always output low. 01: VDDLED tri-state 10: VDDLED output 0.5Hz clock. 11: VDDLED output 1Hz clock. ( clock output is inverse with VSBLED clock output ) 3 2 1 0 GPIO33_SEL GPIO32_SEL GPIO31_SEL GPIO30_SEL R/W R/W R/W R/W 0 0 0 0 0: RSMRST#/GPIO33 functions as RSMRST#. 1: RSMRST#/GPIO33 functions as GPIO33. 0: PWROK/GPIO32 functions as PWROK. 1: PWROK/GPIO32 functions as GPIO32. 0: PS_ON#/GPIO31 functions as PS_ON#. 1: PS_ON#/GPIO31 functions as GPIO31. 0: S3#/GPIO30 functions as S3#. 1: S3#/GPIO30 functions as GPIO30. 8.1.13 Bit 7 6 5 Multi Function Select 3 Register  Index 2Bh (Powered by VSB3V) Name Reserved GPIO16_SEL GPIO15_SEL R/W Default R/W R/W R/W 0 0 0 Dummy register. 0: GPIO16/LED_VCC functions as GPIO16. 1: GPIO16/LED_VCC functions as LED_VCC. When register ALERT_GP_EN is 0, the register functions as: 0: GPIO15/LED_VSB/ALERT# functions as GPIO15. 1: GPIO15/LED_VSB/ALERT# functions as LED_VSB. 4 GPIO14_SEL R/W 0 0: GPIO14/FWH_DIS/WDTRST# functions as GPIO14 when SPI is disabled. 1: GPIO14/FWH_DIS/WDTRST# functions as WDTRST# when SPI is disabled. 3 2 GPIO13_SEL GPIO12_SEL R/W R/W 0 0 0: GPIO13/SPI_MOSI/BEEP functions as GPIO13 when SPI is disabled. 1: GPIO13/SPI_MOSI/BEEP functions as BEEP when SPI is disabled. 0: GPIO12/SPI_MISO/FANCTRL1_1 functions as GPIO12 when SPI is disabled. 1: GPIO12/SPI_NISO/FANCTRL1_1 functions as FANCTRL1_1 when SPI is disabled. 1-0 Reserved R/W 0 Reserved Description 8.1.14 Bit Multi Function Select 4 Register  Index 2Ch (Powered by VSB3V) Name R/W Default Description 75 July, 2008 V.28P F71862 7 6 5 4 3 2 1 0 GPIO27_SEL GPIO26_SEL GPIO25_SEL GPIO24_SEL GPIO23_SEL GPIO22_SEL GPIO21_SEL GPIO20_SEL R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0: PWSOUT#/GPIO27 functions as PWSOUT#. 1: PWSOUT#/GPIO27 functions as GPIO27. 0: PWSIN#/GPIO26 functions as PWSIN#. 1: PWSIN#/GPIO26 functions as GPIO26. 0: PME#/GPIO25 functions as PME#. 1: PME#/GPIO25 functions as GPIO25. 0: ATXPG_IN/GPIO24 functions as ATXPG_IN. 1: ATXPG_IN/GPIO24 functions as GPIO24. 0: RSTCON#/GPIO23 functions as RSTCON#. 1: RSTCON#/GPIO23 functions as GPIO23. 0: PCIRST3#/GPIO22 functions as PCIRST3#. 1: PCIRST3#/GPIO22 functions as GPIO22. 0: PCIRST2#/GPIO21 functions as PCIRST2#. 1: PCIRST2#/GPIO21 functions as GPIO21. 0: PCIRST1#/GPIO20 functions as PCIRST1#. 1: PCIRST1#/GPIO20 functions as GPIO20. 8.1.15 Bit 7 Wakeup Control Register  Index 2Dh (Powered by VBAT) Name SPI_CS1_EN R/W Default R/W 0 Description This register decides the architecture of SPI when used as primary BIOS. 1: use two 4Mbits. (FWH_DIS will multi-functions as SPI_CS1#) 0: use one 8Mbits. (Divided into two 4Mbits. Originally use the higher part. If the higher part is booting fail, the memory address will be auto mapped to lower part.) 6-4 Reserved 3 WAKEUP_EN R/W R/W R/W 0 1 00 Dummy register. 0: disable keyboard/mouse wake up. 1: enable keyboard/mouse wake up. 2-1 KEY_SEL This registers select the keyboard wake up key. When KEY_SEL_ADD is low, the register indicates 00: Wake up key is Ctrl + Esc. 01: Wake up key is Ctrl + F1. 10: Wake up key is Ctrl + Space. 11: Wake up key is any key. Otherwise, wake up key is win98 wakeup key. 0 MO_SEL R/W 0 This register selects the mouse wake up key. 0: Wake up by click. 1: Wake up by click and movement. 76 July, 2008 V.28P 8.2 FDC Registers (CR00) 8.2.1 Bit FDC Configuration Registers Name R/W Default R/W 1 Reserved 0: disable FDC. 1: enable FDC. Description FDC Device Enable Register  Index 30h F71862 7-1 Reserved 0 FDC_EN Base Address High Register  Index 60h Bit Name R/W Default R/W 03h The MSB of FDC base address. Description 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W F0h The LSB of FDC base address. Description 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 06h Reserved. Select the IRQ channel for FDC. Description 7-4 Reserved 3-0 SELFDCIRQ DMA Channel Select Register  Index 74h Bit Name R/W Default R/W 010 Reserved. Select the DMA channel for FDC. Description 7-3 Reserved 2-0 SELFDCDMA FDD Mode Register  Index F0h Bit Name R/W Default R/W 11 Reserved. 00: Model 30 mode. 01: PS/2 mode. 10: Reserved. 11: AT mode (default). 0: enable burst mode. 1: non-busrt mode (default). 0: normal floppy mode (default). 1: enhanced 3-mode FDD. Description 7-4 Reserved 3-2 IF_MODE 1 0 FDMAMODE EN3MODE R/W R/W 1 0 FDD Drive Type Register  Index F2h Bit Name R/W Default Reserved. Description 7-2 Reserved 77 July, 2008 V.28P F71862 1-0 FDD_TYPE R/W 11 FDD drive type. FDD Selection Register  Index F4h Bit Name R/W Default R/W 00 Reserved. Data rate table select, refer to table A. 00: select regular drives and 2.88 format. 01: 3-mode drive. 10: 2 mega tape. 11: reserved. Reserved. Drive type select, refer to table B. Description 7-5 Reserved 4-3 FDD_DRT 2 Reserved R/W 00 1-0 FDD_DT TABLE A Data Rate Table Select FDD_DRT[1] Data Rate DATARATE1 0 0 DATARATE0 0 1 0 1 0 1 0 1 0 1 0 1 Selected Data Rate MFM 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K 1Meg FM 250K 150K 125K --250K 250K 125K --250K --125K --- DENSEL FDD_DRT[0] 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 TABLE B Drive Type FDD_DT1 0 0 1 1 1 0 1 DATARATE1 DENSEL# DATARATE0 FDD_DT0 0 DRVDEN0 DENSEL Remark 4/2/1 MB 3.5” 2/1 MB 5.25” 1/1.6/1 MB 3.5” (3-Mode ) 78 July, 2008 V.28P 8.3 UART1 Registers (CR01) 8.3.1 Bit UART 1 Configuration Registers Name R/W Default R/W 1 Reserved 0: disable UART 1. 1: enable UART 1. Description UART 1 Device Enable Register  Index 30h F71862 7-1 Reserved 0 UR1_EN Base Address High Register  Index 60h Bit Name R/W Default R/W 03h Description The MSB of UART 1 base address. 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W F8h Description The LSB of UART 1 base address. 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 4h Reserved. Select the IRQ channel for UART 1. Description 7-4 Reserved 3-0 SELUR1IRQ RS485 Enable Register  Index F0h Bit Name R/W Default R/W 0 Reserved. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# low when transmitting data. Reserved. Description 7-5 Reserved 4 RS485_EN 3-0 Reserved 79 July, 2008 V.28P 8.4 UART 2 Registers (CR02) 8.4.1 Bit UART 2 Configuration Registers Name R/W Default R/W 1 Reserved 0: disable UART 2. 1: enable UART 2. Description UART 2 Device Enable Register  Index 30h F71862 7-1 Reserved 0 UR2_EN Base Address High Register  Index 60h Bit Name R/W Default R/W 02h Description The MSB of UART 2 base address. 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W F8h Description The LSB of UART 2 base address. 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 3h Reserved. Select the IRQ channel for UART 2. Description 7-4 Reserved 3-0 SELUR2IRQ RS485 Enable Register  Index F0h Bit Name R/W Default R/W R/W R/W 0 0 0 Reserved. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# low when transmitting data. 0: No reception delay when SIR is changed form TX to RX. 1: Reception delays 4 characters time when SIR is changed form TX to RX. 0: No transmission delay when SIR is changed form RX to TX. 1: Transmission delays 4 characters time when SIR is changed form RX to TX. Reserved. Description 7-5 Reserved 4 3 2 RS485_EN RXW4C_IR TXW4C_IR 1-0 Reserved SIR Mode Control Register  Index F1h Bit 7 6 5 Name Reserved Reserved Reserved R/W Default R/W 00 Reserved. Reserved. Reserved. 00: disable IR function. 01: disable IR function. 10: IrDA function, active pulse is 1.6uS. 11: IrDA function, active pulse is 3/16 bit time. Description 4-3 IRMODE 80 July, 2008 V.28P F71862 2 HDUPLX R/W 1 0: SIR is in full duplex mode for loopbak test. TXW4C_IR and RXW4C_IR are of no use. 1: SIR is in half duplex mode. 0: IRTX is in normal condition. 1: inverse the IRTX. 0: IRRX is in normal condition. 1: inverse the IRRX. 1 0 TXINV_IR RXINV_IR R/W R/W 0 0 81 July, 2008 V.28P 8.5 Parallel Port Registers (CR03) 8.5.1 Bit Parallel Port Configuration Registers Name R/W Default R/W 1 Reserved 0: disable Parallel Port. 1: enable Parallel Port. Description Parallel Port Device Enable Register  Index 30h F71862 7-1 Reserved 0 PRT_EN Base Address High Register  Index 60h Bit Name R/W Default R/W 03h Description The MSB of Parallel Port base address. 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W 78h Description The LSB of Parallel Port base address. 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 7h Reserved. Select the IRQ channel for Parallel Port. Description 7-5 Reserved 3-0 SELPRTIRQ DMA Channel Select Register  Index 74h Bit Name R/W Default R/W R/W 0 011 Reserved. 0: non-burst mode DMA. 1: enable burst mode DMA. Reserved. Select the DMA channel for Parallel Port. Description 7-5 Reserved 4 3 ECP_DMA_MODE Reserved 2-0 SELPRTDMA PRT Mode Select Register  Index F0h Bit 7 Name SPP_IRQ_MODE R/W Default R/W 0 Description Interrupt mode in non-ECP mode. 0: Level mode. 1: Pulse mode. ECP FIFO threshold. 6-3 ECP_FIFO_THR R/W 1000 82 July, 2008 V.28P F71862 2-0 PRT_MODE R/W 010 000: Standard and Bi-direction (SPP) mode. 001: EPP 1.9 and SPP mode. 010: ECP mode (default). 011: ECP and EPP 1.9 mode. 100: Printer mode. 101: EPP 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP1.7 mode. 83 July, 2008 V.28P 8.6 Hardware Monitor Registers (CR04) 8.6.1 Bit Hardware Monitor Configuration Registers Name R/W Default R/W 1 Reserved 0: disable Hardware Monitor. 1: enable Hardware Monitor. Description Hardware Monitor Device Enable Register  Index 30h F71862 7-1 Reserved 0 HM_EN Base Address High Register  Index 60h Bit Name R/W Default R/W 02h Description The MSB of Hardware Monitor base address. 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W 95h Description The LSB of Hardware Monitor base address. 7-0 BASE_ADDR_LO IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 0000 Reserved. Select the IRQ channel for Hardware Monitor. Description 7-4 Reserved 3-0 SELHMIRQ 84 July, 2008 V.28P 8.7 KBC Registers (CR05) 8.7.1 Bit KBC Configuration Registers Name R/W Default R/W 1 Reserved 0: disable KBC. 1: enable KBC. Description KBC Device Enable Register  Index 30h F71862 7-1 Reserved 0 KBC_EN Base Address High Register  Index 60h Bit Name R/W Default R/W 00h Description The MSB of KBC command port address. The address of data port is command port address + 4; 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W 60h Description The LSB of KBC command port address. The address of data port is command port address + 4. 7-0 BASE_ADDR_LO KB IRQ Channel Select Register  Index 70h Bit Name R/W Default R/W 0h Reserved. Select the IRQ channel for keyboard interrupt. Description 7-4 Reserved 3-0 SELKIRQ Mouse IRQ Channel Select Register  Index 72h Bit Name R/W Default R/W 0h Reserved. Select the IRQ channel for PS/2 mouse interrupt. Description 7-4 Reserved 3-0 SELMIRQ 85 July, 2008 V.28P 8.8 GPIO Registers (CR06) 8.8.1 GPIO0 Registers F71862 GPIO0 Output Enable Register  Index F0h Bit 3 2 1 0 Name GPIO03_OE GPIO02_OE GPIO01_OE GPIO00_OE R/W Default R/W R/W R/W R/W 0 0 0 0 0 Reserved 0: GPIO03 is in input mode. 1: GPIO03 is in output mode. 0: GPIO02 is in input mode. 1: GPIO02 is in output mode. 0: GPIO01 is in input mode. 1: GPIO01 is in output mode. 0: GPIO00 is in input mode. 1: GPIO00 is in output mode. Description 7-4 Reserved GPIO0 Output Data Register  Index F1h Bit 3 2 1 0 Name GPIO03_VAL GPIO02_VAL GPIO01_VAL GPIO00_VAL R/W Default R/W R/W R/W R/W 0 1 1 1 1 Reserved 0: GPIO03 outputs 0 when in output mode. 1: GPIO03 outputs 1 when in output mode. 0: GPIO02 outputs 0 when in output mode. 1: GPIO02 outputs 1 when in output mode. 0: GPIO01 outputs 0 when in output mode. 1: GPIO01 outputs 1 when in output mode. 0: GPIO00 outputs 0 when in output mode. 1: GPIO00 outputs 1 when in output mode. Description 7-4 Reserved GPIO0 Pin Status Register  Index F2h Bit 3 2 1 0 Name GPIO03_IN GPIO02_IN GPIO01_IN GPIO00_IN R/W Default R R R R 0 Reserved The pin status of GPIO03/WDTRST#. The pin status of SLOTOCC#/GPIO02. The pin status of GPIO01. The pin status of GPIO00. Description 7-4 Reserved GPIO0 Drive Enable Register  Index F3h Bit 3 2 1 Name GPIO03_DRV_EN GPIO02_DRV_EN GPIO01_DRV_EN R/W Default R/W R/W R/W 0 0 0 0 Reserved 0: GPIO03 is open drain in output mode. 1: GPIO03 is push pull in output mode. 0: GPIO02 is open drain in output mode. 1: GPIO02 is push pull in output mode. 0: GPIO01 is open drain in output mode. 1: GPIO01 is push pull in output mode. Description 7-4 Reserved 86 July, 2008 V.28P F71862 0 GPIO00_DRV_EN R/W 0 0: GPIO00 is open drain in output mode. 1: GPIO00 is push pull in output mode. 8.8.2 GPIO1 Registers GPIO1 Output Enable Register  Index E0h Bit 7 6 5 4 3 2 1 0 Name GPIO17_OE GPIO16_OE GPIO15_OE GPIO14_OE GPIO13_OE GPIO12_OE GPIO11_OE GPIO10_OE R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0: GPIO16 is in input mode. 1: GPIO16 is in output mode. 0: GPIO16 is in input mode. 1: GPIO16 is in output mode. 0: GPIO15 is in input mode. 1: GPIO15 is in output mode. 0: GPIO14 is in input mode. 1: GPIO14 is in output mode. 0: GPIO13 is in input mode. 1: GPIO13 is in output mode. 0: GPIO12 is in input mode. 1: GPIO12 is in output mode. 0: GPIO11 is in input mode. 1: GPIO11 is in output mode. 0: GPIO10 is in input mode. 1: GPIO10 is in output mode. Description GPIO1 Output Data Register  Index E1h Bit 7 6 5 4 3 2 1 0 Name GPIO17_VAL GPIO16_VAL GPIO15_VAL GPIO14_VAL GPIO13_VAL GPIO12_VAL GPIO11_VAL GPIO10_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description 0: GPIO16 outputs 0 when in output mode. 1: GPIO16 outputs1 when in output mode. 0: GPIO16 outputs 0 when in output mode. 1: GPIO16 outputs1 when in output mode. 0: GPIO15 outputs 0 when in output mode. 1: GPIO15 outputs 1 when in output mode. 0: GPIO14 outputs 0 when in output mode. 1: GPIO14 outputs 1 when in output mode. 0: GPIO13 outputs 0 when in output mode. 1: GPIO13 outputs 1 when in output mode. 0: GPIO12 outputs 0 when in output mode. 1: GPIO12 outputs 1 when in output mode. 0: GPIO11 outputs 0 when in output mode. 1: GPIO11 outputs 1 when in output mode. 0: GPIO10 outputs 0 when in output mode. 1: GPIO10 outputs 1 when in output mode. GPIO1 Pin Status Register  Index E2h Bit Name R/W Default Description 87 July, 2008 V.28P F71862 7 6 5 4 3 2 1 0 GPIO17_IN GPIO16_IN GPIO15_IN GPIO14_IN GPIO13_IN GPIO12_IN GPIO11_IN GPIO10_IN R R R R R R R R The pin status of GPIO17. The pin status of GPIO16/LED_VCC The pin status of GPIO15/LED_VSB/ALERT#. The pin status of GPIO14/FWH_DIS/WDTRST#/SPI_CS1#. The pin status of GPIO13/SPI_MOSI/BEEP. The pin status of GPIO12/SPI_MISO/FANCTRL1_1. The pin status of GPIO11/SPI_CS. The pin status of GPIO10/SPI_CLK. GPIO1 Drive Enable Register  Index E3h Bit 7 6 5 4 3 2 1 0 Name GPIO17_DRV_EN GPIO16_DRV_EN GPIO15_DRV_EN GPIO14_DRV_EN GPIO13_DRV_EN GPIO12_DRV_EN GPIO11_DRV_EN GPIO10_DRV_EN R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: GPIO17 is open drain in output mode. 1: GPIO17 is push pull in output mode. 0: GPIO16 is open drain in output mode. 1: GPIO16 is push pull in output mode. 0: GPIO15 is open drain in output mode. 1: GPIO15 is push pull in output mode. 0: GPIO14 is open drain in output mode. 1: GPIO14 is push pull in output mode. 0: GPIO13 is open drain in output mode. 1: GPIO13 is push pull in output mode. 0: GPIO12 is open drain in output mode. 1: GPIO12 is push pull in output mode. 0: GPIO11 is open drain in output mode. 1: GPIO11 is push pull in output mode. 0: GPIO10 is open drain in output mode. 1: GPIO10 is push pull in output mode. 8.8.3 GPIO2 Registers GPIO2 Output Enable Register  Index D0h Bit 7 6 5 4 3 2 Name GPIO27_OE GPIO26_OE GPIO25_OE GPIO24_OE GPIO23_OE GPIO22_OE R/W Default R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0: GPIO27 is in input mode. 1: GPIO27 is in output mode. 0: GPIO26 is in input mode. 1: GPIO26 is in output mode. 0: GPIO25 is in input mode. 1: GPIO25 is in output mode. 0: GPIO24 is in input mode. 1: GPIO24 is in output mode. 0: GPIO23 is in input mode. 1: GPIO23 is in output mode. 0: GPIO22 is in input mode. 1: GPIO22 is in output mode. Description 88 July, 2008 V.28P F71862 1 0 GPIO21_OE GPIO20_OE R/W R/W 0 0 0: GPIO21 is in input mode. 1: GPIO21 is in output mode. 0: GPIO20 is in input mode. 1: GPIO20 is in output mode. GPIO2 Output Data Register  Index D1h Bit 7 6 5 4 3 2 1 0 Name GPIO27_VAL GPIO26_VAL GPIO25_VAL GPIO24_VAL GPIO23_VAL GPIO22_VAL GPIO21_VAL GPIO20_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description 0: GPIO27 outputs 0 when in output mode. 1: GPIO27 outputs1 when in output mode. 0: GPIO26 outputs 0 when in output mode. 1: GPIO26 outputs1 when in output mode. 0: GPIO25 outputs 0 when in output mode. 1: GPIO25 outputs 1 when in output mode. 0: GPIO24 outputs 0 when in output mode. 1: GPIO24 outputs 1 when in output mode. 0: GPIO23 outputs 0 when in output mode. 1: GPIO23 outputs 1 when in output mode. 0: GPIO22 outputs 0 when in output mode. 1: GPIO22 outputs 1 when in output mode. 0: GPIO21 outputs 0 when in output mode. 1: GPIO21 outputs 1 when in output mode. 0: GPIO20 outputs 0 when in output mode. 1: GPIO20 outputs 1 when in output mode. GPIO2 Pin Status Register  Index D2h Bit 7 6 5 4 3 2 1 0 Name GPIO27_IN GPIO26_IN GPIO25_IN GPIO24_IN GPIO23_IN GPIO22_IN GPIO21_IN GPIO20_IN R/W Default R R R R R R R R Description The pin status of PWSOUT#/GPIO27. The pin status of PWSIN#/GPIO26. The pin status of PME#/GPIO25. The pin status of ATXPG_IN/GPIO24. The pin status of GPIO23/RSTCON#. The pin status of PCIRST3#/GPIO22. The pin status of PCIRST2#/GPIO21. The pin status of PCIRST1#/GPIO20. GPIO2 Drive Enable Register  Index D3h Bit 7 6 5 4 Name GPIO27_DRV_EN GPIO26_DRV_EN GPIO25_DRV_EN GPIO24_DRV_EN R/W Default R/W R/W R/W R/W 0 0 0 0 Description 0: GPIO27 is open drain in output mode. 1: GPIO27 is push pull in output mode. 0: GPIO26 is open drain in output mode. 1: GPIO26 is push pull in output mode. 0: GPIO25 is open drain in output mode. 1: GPIO25 is push pull in output mode. 0: GPIO24 is open drain in output mode. 1: GPIO24 is push pull in output mode. 89 July, 2008 V.28P F71862 3 2 1 0 GPIO23_DRV_EN GPIO22_DRV_EN GPIO21_DRV_EN GPIO20_DRV_EN R/W R/W R/W R/W 0 0 0 0 0: GPIO23 is open drain in output mode. 1: GPIO23 is push pull in output mode. 0: GPIO22 is open drain in output mode. 1: GPIO22 is push pull in output mode. 0: GPIO21 is open drain in output mode. 1: GPIO21 is push pull in output mode. 0: GPIO20 is open drain in output mode. 1: GPIO20 is push pull in output mode. 8.8.4 GPIO3 Registers GPIO3 Output Enable Register  Index C0h Bit 3 2 1 0 Name GPIO33_OE GPIO32_OE GPIO31_OE GPIO30_OE R/W Default R/W R/W R/W R/W 0 0 0 0 Reserved. 0: GPIO33 is in input mode. 1: GPIO33 is in output mode. 0: GPIO32 is in input mode. 1: GPIO32 is in output mode. 0: GPIO31 is in input mode. 1: GPIO31 is in output mode. 0: GPIO30 is in input mode. 1: GPIO30 is in output mode. Description 7-4 Reserved GPIO3 Output Data Register  Index C1h Bit 3 2 1 0 Name GPIO33_VAL GPIO32_VAL GPIO31_VAL GPIO30_VAL R/W Default R/W R/W R/W R/W 1 1 1 1 Reserved. 0: GPIO33 outputs 0 when in output mode. 1: GPIO33 outputs 1 when in output mode. 0: GPIO32 outputs 0 when in output mode. 1: GPIO32 outputs 1 when in output mode. 0: GPIO31 outputs 0 when in output mode. 1: GPIO31 outputs 1 when in output mode. 0: GPIO30 outputs 0 when in output mode. 1: GPIO30 outputs 1 when in output mode. Description 7-4 Reserved GPIO3 Pin Status Register  Index C2h Bit 3 2 1 0 Name GPIO33_IN GPIO32_IN GPIO31_IN GPIO30_IN R/W Default R R R R Reserved. The pin status of RSMRST#/GPIO33. The pin status of PWROK/GPIO32. The pin status of PS_ON#/GPIO31. The pin status of S3#/GPIO30. Description 7-4 Reserved 90 July, 2008 V.28P GPIO3 Drive Enable Register  Index C3h Bit 3 2 1 0 Name GPIO33_DRV_EN GPIO32_DRV_EN GPIO31_DRV_EN GPIO30_DRV_EN R/W Default R/W R/W R/W R/W 0 0 0 0 Reserved. 0: GPIO33 is open drain in output mode. 1: GPIO33 is push pull in output mode. 0: GPIO32 is open drain in output mode. 1: GPIO32 is push pull in output mode. 0: GPIO31 is open drain in output mode. 1: GPIO31 is push pull in output mode. 0: GPIO30 is open drain in output mode. 1: GPIO30 is push pull in output mode. Description F71862 7-4 Reserved 8.8.5 GPIO4 Registers GPIO4 Output Enable Register  Index B0h Bit 5 4 3 2 1 0 Name GPIO45_OE GPIO44_OE GPIO43_OE GPIO42_OE GPIO41_OE GPIO40_OE R/W Default R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Reserved. 0: GPIO45 is in input mode. 1: GPIO45 is in output mode. 0: GPIO44 is in input mode. 1: GPIO44 is in output mode. 0: GPIO43 is in input mode. 1: GPIO43 is in output mode. 0: GPIO42 is in input mode. 1: GPIO42 is in output mode. 0: GPIO41 is in input mode. 1: GPIO41 is in output mode. 0: GPIO40 is in input mode. 1: GPIO40 is in output mode. Description 7-6 Reserved GPIO4 Output Data Register  Index B1h Bit 5 4 3 2 1 0 Name GPIO45_VAL GPIO44_VAL GPIO43_VAL GPIO42_VAL GPIO41_VAL GPIO40_VAL R/W Default R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 Reserved. 0: GPIO45 outputs 0 when in output mode. 1: GPIO45 outputs 1 when in output mode. 0: GPIO44 outputs 0 when in output mode. 1: GPIO44 outputs 1 when in output mode. 0: GPIO43 outputs 0 when in output mode. 1: GPIO43 outputs 1 when in output mode. 0: GPIO42 outputs 0 when in output mode. 1: GPIO42 outputs 1 when in output mode. 0: GPIO41 outputs 0 when in output mode. 1: GPIO41 outputs 1 when in output mode. 0: GPIO40 outputs 0 when in output mode. 1: GPIO40 outputs 1 when in output mode. Description 7-6 Reserved 91 July, 2008 V.28P GPIO4 Pin Status Register  Index B2h Bit 5 4 3 2 1 0 Name GPIO45_IN GPIO44_IN GPIO43_IN GPIO42_IN GPIO41_IN GPIO40_IN R/W Default R R R R R R Reserved. The pin status of GPIO45 The pin status of GPIO44. The pin status of IRRX/GPIO43 The pin status of IRTX/GPIO42. The pin status of FANCTRL3/GPIO41. The pin status of FANIN3/GPIO40. Description F71862 7-6 Reserved GPIO4 Drive Enable Register  Index B3h Bit 5 4 3 2 1 0 Name GPIO45_DRV_EN GPIO44_DRV_EN GPIO43_DRV_EN GPIO42_DRV_EN GPIO41_DRV_EN GPIO40_DRV_EN R/W Default R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Reserved. 0: GPIO45 is open drain in output mode. 1: GPIO45 is push-pull in output mode. 0: GPIO44 is open drain in output mode. 1: GPIO44 is push-pull in output mode. 0: GPIO43 is open drain in output mode. 1: GPIO43 is push-pull in output mode. 0: GPIO42 is open drain in output mode. 1: GPIO42 is push-pull in output mode. 0: GPIO41 is open drain in output mode. 1: GPIO41 is push-pull in output mode. 0: GPIO40 is open drain in output mode. 1: GPIO40 is push-pull in output mode. Description 7-6 Reserved 92 July, 2008 V.28P 8.9 VID Registers (CR07) 8.9.1 Bit VID Configuration Registers Name R/W Default R/W 0 0 Reserved 0: disable VID. 1: enable VID. Description VID Device Enable Register  Index 30h F71862 7-1 Reserved 0 VID_EN Base Address High Register  Index 60h Bit Name R/W Default R/W 00h The MSB of VID base address. Description 7-0 BASE_ADDR_HI Base Address Low Register  Index 61h Bit Name R/W Default R/W 00h The LSB of VID base address. Description 7-0 BASE_ADDR_LO 8.9.2 Bit 7 6-3 2* 1:0 Configuration Register  Index F0h (00h) ( * cleared by slotocc_n and watch dog timeout) Name WDOUT_EN Reserved OTF_EN Dummy Reg R/W Default R/W R/W R/W 0 0 0 0 Description If this bit is set to 1 and watchdog timeout event occurs, WDTRST# output is enabled. Return 0 when read. This bit is used to enable vid on-the-fly function. Dummy register. 8.9.3 Bit 7:4 3-0 VID Offset Register 0  Index F1h (01h) Name Reserved VID_OFFSET R/W Default R R/W 0 Reserved VID offset. VID_OFFSET[3] is sign bit. Description 8.9.4 Bit 7* 6 5-4 3-0 VID Manual Register  Index F2h (02h) Name MANUAL_MODE KEY_OK Reserved VID_MANUAL R/W Default R/W R R R/W 0 0 Description If this bit is set to 1 and OTF_EN is 0, VIDOUT will be VID_MANUAL This bit is 1 represents that the serial key is entered correctly. Return 0 when read. Manually assigned VIDOUT value 8.9.5 Bit Serial Key Data Register  Index F3h (03h) Name R/W Default Description 93 July, 2008 V.28P 0 7-0 KEY_DATA R/W Write serial data to this register correctly, the KEY_OK bit will be set to 1. Hence, users are able to write key protected registers. The sequence to enable KEY_OK is 0x32, 0x5D, 0x42, 0xAC. When KEY_OK is set, write this register 0x35 will clear KEY_OK. F71862 8.9.6 Bit 7-4 3-0 VIDIN Register  Index F4h (04h) ( * cleared by slotocc_n and watch dog timeout) Name Reserved VID_IN R/W Default R R 0 Reserved Return the VID_IN status. Description 8.9.7 Bit 7 6 5 4 3 2 1:0 Watchdog Timer Configuration Register 1 Index F5h (05h) Name Reserved WDTMOUT_STS WD_EN WD_PULSE WD_UNIT WD_HACTIVE WD_PSWIDTH R/W Default R R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Reserved If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to this bit will clear it to 0. If this bit is set to 1, the counting of watchdog time is enabled. Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit. Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. Select output polarity of RSTOUT# (1: high active, 0: low active) by setting this bit. Select output pulse width of RSTOUT# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec Description 8.9.8 Bit 7:0 Watchdog Timer Configuration Register 2  Index F6h (06h) Name WD_TIME R/W Default R/W 0 Time of watchdog timer Description 8.9.9 Bit 7-6 5 4 3-0 Output Voltage Control Register 1  Index F7h (07h) ( * cleared by slotocc_n and watch dog timeout) Name Dummy Reg REG_RST_SEL Reserved Dummy Reg R/W Default R/W R/W R/W R/W 0 0 0 0 Dummy register. 0: The VID registers is reseted when VDD power lose and watch dog timeout. 1: The VID registers is reseted by slotcc_n and watch dog timeout. Reserved Dummy registers. Description 94 July, 2008 V.28P 8.10 SPI Registers (CR08) 8.10.1 Configuration Register SPI Control Register  Index F0h Bit Name R/W Default R/W R/W R/W 0 1 0 Reserved. Description F71862 7-6 Reserved 5 4 3 SPTIE MSTR CPOL SPI interrupt enable. Set to 1, SPIE interrupt enabled, set to 0 spie interrupt disabled. Master mode select. Set to 1, SPI function is master mode; set to 0 is disable SPI function Clock polarity this bit selects inverted or non-inverted SPI clock. Set to 1, active low clock selected; SCK idles high. Set to 0, active high clock selected; SCK idles low. Clock phase. This bit is used to shift the SCK serial clock. Set to 1, the first SCK edge is issued at the beginning of the transfer operation. Set to 0, the first SCK edge is issued one-half cycle into the transfer operation. Reserved This bit control data shift from lsb or msb. Set to 1, data is transferred from lsb to msb. Set to 0, data is transferred from msb to lsb. 2 CPHA R/W 0 1 0 Reserved LSBFE R/W 0 0 SPI Timeout Register  Index F1h Bit Name R/W Default R/W Description 7-0 TIMER_VAL 8’h04 The time in second to assert FWH_DIS signal when SPI in used as backup BIOS. SPI Baud Rate Divisor Register  Index F2h Bit Name R/W Default R/W 0 1 Reserved This register decides to SCK frequency. Baud rate divisor equation is 33MHz/2*(BAUD_VAL). 00: 33MHz. 01: 16.7MHz. Description 7-3 Reserved 2-0 BAUD_VAL SPI Status Register  Index F3h Bit 7 6 SPIE FWH_DIS Name R/W Default R/W R/W 0 Description SPI interrupt status. When SPI is transferred or received data from device finish, this bit will be set. Write 1 to clear this bit. When SPI is used as backup BIOS, this bit will set when time in second reaches the value programmed in TIMER_VAL (CRF1). Write one to clear this register. When SPI is used as primary BIOS, this register will always be 1. This bit reflects the SPI_EN register. (which will be 1 when SPI is enabled.) 5 SPE R - 95 July, 2008 V.28P F71862 4 SPI0_TIMER_DIS R/W When SPI is used as primary BIOS, it will also have backup function as used in backup BIOS. The bit will set to 1 when the time in second reaches the value programmed in TIMER_VAL (CRF1). That is the first SPI could not function well. Then a reset signal will asserted and reboot the system with the second SPI. (I could be another SPI with chip-selected by FWH_DIS or another 4Mbits of an 8Mbits SPI. The SPI_CS1_EN (CR2D[4]) determines the method). Write one to clear this bit. SPI operation status. When SPI is transferred or received data from device, this bit will be set 1, Clear by SPI operation finish. Reserved 3 SPTEF R - 0 - 2-0 Reserved SPI High Byte Data Register  Index F4h Bit Name R/W Default R 0 Description When SPI is received 16 bits data from device. This register saves high byte data. 7-0 H_DATA SPI command data Register  Index F5h Bit Name R/W Default R/W 0 Description This register provides command value for flash command. 7-0 CMD_DATA SPI chip select Register  Index F6h Bit Name R/W Default R/W R/W R/W R/W 0 0 0 0 Reserved Dummy register. Dummy register. Dummy register. Chip select 0. To select device 0 Description 7-4 Reserved 3 2 1 0 Dummy_Reg Dummy_Reg Dummy_Reg CS0 SPI memory mapping Register  Index F7h Bit Name R/W Default R/W 0 Reserved This register decides memory size. 3’b000: one of the memory sizes is 512k bytes. 3’b001: one of the memory sizes is 1024k bytes. 3’b100: one of the memory sizes is 2048k bytes. 3’b011: one of the memory sizes is 4096k bytes. 3’b100: one of the memory sizes if 8092k bytes. Description 7-3 Reserved 2-0 Mem_map SPI operate Register  Index F8h Bit 7 TYPE Name R/W Default R/W 0 Description This bit decide flash continuous programming mode. Set to 1, if programming continuous mode is same as the SST flash. Set to 0 if programming continuous mode is same as the ATMEL flash This bit control SPI function transfer 8 bit command to device. Clear 0 by operation finish. 6 IO_SPI R/W 0 96 July, 2008 V.28P F71862 5 4 3 2 1 0 RDSR WRSR SECTOR_ERASE READ_ID PROG READ R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 This bit control SPI function read status from to device. Clear 0 by operation finish. This bit control SPI function write status to device. Clear 0 by operation finish. This bit control SPI function sector erase device. Clear 0 by operation finish. This bit control SPI function read id from device. Clear 0 by operation finish. This bit control SPI function program data to device or set to 1 when memory cycle for LPC interface program flash. Clear 0 by operation finish. This bit control SPI function read data from device or set to 1 when memory cycle for LPC interface read flash. Clear 0 by operation finish. SPI Low Byte Data Register  Index FAh Bit Name R/W Default R 0 Description When SPI is received 16 bits or 8 bits data from device. This register saves low byte data. 7-0 L_DATA SPI address high byte Register  Index FBh Bit Name R/W Default R/W 0 Description This register provides high byte address for sector erase, program, read operation. 7-0 Addr_H_byte SPI address medium byte Register  Index FCh Bit Name R/W Default R/W 0 Description This register provides medium byte address for sector erase, program, read operation. 7-0 Addr_M_byte SPI address low byte Register  Index FDh Bit Name R/W Default R/W 0 Description This register provides low byte address for sector erase, program, read operation. 7-0 Addr_L_byte SPI program byte Register  Index FEh Bit Name R/W Default R/W 0 Description This register provides number to program flash for continuous mode. 7-0 PORG_BYTE SPI write data Register  Index FFh Bit Name R/W Default R/W 0 Description This register provides data to write flash for program, write status function. 7-0 WR_dat 97 July, 2008 V.28P 8.11 PME and ACPI Registers (CR0A) 8.11.1 Configuration Register Device Enable Register  Index 30h Bit 0 Name PME_EN R/W Default R/W 0 Reserved 0: disable PME. 1: enable PME. Description 7-1 Reserved F71862 PME Event Enable Register  Index F0h Bit 7 6 Name Reserved MO_PME_EN R/W Default R/W 0 Reserved Mouse PME event enable. 0: disable mouse PME event. 1: enable mouse PME event. Keyboard PME event enable. 0: disable keyboard PME event. 1: enable keyboard PME event. Hardware monitor PME event enable. 0: disable hardware monitor PME event. 1: enable hardware monitor PME event. Parallel port PME event enable. 0: disable parallel port PME event. 1: enable parallel port PME event. UART 2 PME event enable. 0: disable UART 2 PME event. 1: enable UART 2 PME event. UART 1 PME event enable. 0: disable UART 1 PME event. 1: enable UART 1 PME event. FDC PME event enable. 0: disable FDC PME event. 1: enable FDC PME event. Description 5 KB_PME_EN R/W 0 4 HM_PME_EN R/W 0 3 PRT_PME_EN R/W 0 2 UR2_PME_EN R/W 0 1 UR1_PME_EN R/W 0 0 FDC_PME_EN R/W 0 PME Event Status Register  Index F1h Bit 7 6 Name Reserved MO_PME_ST R/W Default R/W Reserved Mouse PME event status. 0: Mouse has no PME event. 1: Mouse has a PME event to assert. Write 1 to clear to be ready for next PME event. Keyboard PME event status. 0: Keyboard has no PME event. 1: Keyboard has a PME event to assert. Write 1 to clear to be ready for next PME event. Hardware monitor PME event status. 0: Hardware monitor has no PME event. 1: Hardware monitor has a PME event to assert. Write 1 to clear to be ready for next PME event. Description 5 KB_PME_ST R/W - 4 HM_PME_ST R/W - 98 July, 2008 V.28P F71862 3 PRT_PME_ST R/W Parallel port PME event status. 0: Parallel port has no PME event. 1: Parallel port has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 2 PME event status. 0: UART 2 has no PME event. 1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 1 PME event status. 0: UART 1 has no PME event. 1: UART 1 has a PME event to assert. Write 1 to clear to be ready for next PME event. FDC PME event status. 0: FDC has no PME event. 1: FDC has a PME event to assert. Write 1 to clear to be ready for next PME event. 2 UR2_PME_ST R/W - 1 UR1_PME_ST R/W - 0 FDC_PME_ST R/W - ACPI Control Register  Index F4h Bit 7 TS3 Name R/W Default R/W 0 Description Set to 1 into S1 state. Two wake up methods: 1. PME wake up event Must write this bit to 0. 2. PS_OUT# wake up event Auto clear this bit. Set one to enable the reset signal from SPI via the PWROK or PCIRST#. (SPI as backup BIOS will assert a reset signal when FWH doesn’t response in 4 seconds) Set this bit one and KEY_SEL (CR2D[2:1]) 2’b00 will select windows 98 wakeup key as keyboard wakeup key. Set one to enable keyboard wakeup event asserted via PWSOUT#. Set one to enable mouse wakeup event asserted via PWSOUT#. The ACPI Control the PSON_N to always on or always off or keep last state 00 : keep last state 10 : Always on 01 : Reserved (always on) 11: Always off When VSB 3V comes, it will set to 1, and write 1 to clear it 6 SPI_RST_EN R/W 0 5 4 3 KEY_SEL_ADD EN_KBWAKEUP EN_MOWAKEUP R/W R/W R/W R/W 0 0 0 11 2-1 PWRCTRL 0 VSB_PWR_LOSS R/W 0 ACPI Control Register  Index F5h Bit 7 Name SEL_S3 R/W Default R/W 0 Description 1:selected by TS3 TS3 0: chip decided into S3 state from S3 pin 1 : chip direct into S3 state 0: chip decided into S3 state from VDD (VCC) power detect ok., which chip detects voltage circuit Dummy register 0: Enable RSTCON# output via PWROK. 1: Enable RSTCON# output via PCIRST#. 6 5 Reserved RSTCON_EN R/W R/W 0 0 99 July, 2008 V.28P F71862 4-3 DELAY R/W 11 The PWROK delay timing from VDD3VOK by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms 2 1 0 VINDB_EN PCIRST_DB_EN Reserved R/W R/W R/W 1 0 0 Enable the PCIRSTIN_N and ATXPWGD de-bounce. Enable the LRESET_N de-bounce. Dummy register. ACPI Control Register  Index F7h Bit Name R/W Default R/W R/W R/W R/W 0 0 0 1 Reserved. Dummy registers. Set this bit to one will cuase Pin55 be tri-state Status in S5 state. Enable power status pins. Pin77 will be S5# function. P56 will be ST1 function. P55 will be ST2 function. Description 7-4 Reserved 3-2 Reserved 1 0 PWR_STS2_TRI PWR_STS_EN 100 July, 2008 V.28P F71862 9. Electron Characteristic 9.1 Absolute Maximum Ratings RATING -0.5 to 5.5 -0.5 to VDD+0.5 0 to 70 -55 to 150 UNIT V V °C °C PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device 9.2 DC Characteristics MIN TYP ±1 ±1 3.3 10 5 1 2.2 95 10 MAX ±3 ±3 3.6 Unit o C V mA uA o C V uA uA (TA = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V ) Parameter Conditions Temperature Error, Remote 60 oC < TD < 145 oC, VCC = 3.0V to 3.6V Diode 0 oC