F75122RG

F75122R/F75122RG F75122R/F75122RG Dynamic VID Control + 8 GPIO Datasheet Release Date: July, 2007 Revision: V0.28P F75122 V0.28P July, 2007 F75122R/F75122RG F75122 Datasheet Revision History Version 0.20P 0.21P 0.22P 0.23P 0.24P 0.25P 0.26P 0.27P 0.28P Date Jan/2004 Feb/2004 Feb/2004 May/2004 June/2004 Sep/2004 Jan/2005 Jan/2005 July/2007 41 5-7 40-41 13-17 18 31 Page Revision History Preliminary Version Add DC spec description for low level input pin(INlv) Revise pin10 ~ 12 configuration and description Update DC spec about Input High/Low Leakage Current Delete redundant register description Add VID Offset table on index30h Add Green Package support (F75122RG) Update application circuit Add company address Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. F75122 V0.28P July, 2007 Table of Contents 1. GENERAL DESCRIPTION .......................................................................................................................................- 3 2. FEATURES................................................................................................................................................................- 3 3. KEY SPECIFICATIONS ............................................................................................................................................- 4 4. PIN CONFIGURATION .............................................................................................................................................- 4 5. PIN DESCRIPTION ...................................................................................................................................................- 5 5.1 POWER PIN ........................................................................................................................................................ - 5 5.2 VID CONTROL AND GPIO PINS ............................................................................................................................ - 5 6. FUNCTIONAL DESCRIPTION..................................................................................................................................- 6 6.1 GENERAL DESCRIPTION ...................................................................................................................................... - 6 6.2 ACCESS INTERFACE ............................................................................................................................................ - 7 6.3 THE SMBUS ACCESS TIMING ARE SHOWN AS FOLLOW: .......................................................................................... - 7 6.4 VID FUNCTION ................................................................................................................................................... - 8 6.5 GPIO FUNCTION ................................................................................................................................................ - 8 6.5.1 General GPIO Function................................................................................................................................. - 8 6.5.3 Reset Out (RSTOUT) Function ..................................................................................................................... - 9 6..4 Watchdog Function ......................................................................................................................................... - 9 7. REGISTERS DESCRIPTION ....................................................................................................................................- 9 7.1 CONFIGURATION AND CONTROL REGISTER – INDEX 01H ....................................................................................... - 9 7.2 STATUS REGISTER – INDEX 02H ........................................................................................................................ - 10 7.3 CONFIGURATION AND FUNCTION SELECT REGISTER – INDEX 03H ......................................................................... - 10 7.6 LED FREQ CONTROL REGISTER – INDEX 06H .................................................................................................... - 11 7.10 GPIO1X OUTPUT CONTROL REGISTER – INDEX 10H ........................................................................................ - 12 7.11 GPIO1X OUTPUT DATA REGISTER – INDEX 11H ................................................................................................ - 12 7.12 GPIO1X INPUT STATUS REGISTER – INDEX 12H ............................................................................................... - 12 7.13 GPIO1X LEVEL/PULSE CONTROL REGISTER – INDEX 13H ................................................................................ - 13 7.14 GPIO1X PULSE WIDTH CONTROL REGISTER – INDEX 14H ................................................................................ - 13 7.15 GPIO1X PULL-UP RESISTOR CONTROL REGISTER – INDEX 15H ........................................................................ - 13 7.16 GPIO1X INPUT DE-BOUNCE REGISTER – INDEX 16H ........................................................................................ - 14 7.17 GPIO1X PULSE INVERSE REGISTER – INDEX 17H ............................................................................................ - 14 7.18 EDGE DETECTOR ENABLE REGISTER – INDEX 0X18 ......................................................................................... - 15 7.19 EDGE DETECTOR STATUS REGISTER – INDEX 0X19 .......................................................................................... - 15 7.20 IRQ OR SMI# ENABLE REGISTER – INDEX 0X1A .............................................................................................. - 15 - -1- July, 2007 V0.28P 7.21 OUTPUT DRIVING ENABLE – INDEX 0X1B ......................................................................................................... - 16 7.22 OUTPUT DRIVING ENABLE – INDEX 0X1C ......................................................................................................... - 16 7.36 VID ON THE FLY OFFSET REGISTER – INDEX 30H .............................................................................................. - 17 7.37 VID OUTPUT DATA REGISTER – INDEX 31H ...................................................................................................... - 18 7.38 VIDKEY PROTECTION REGISTER – INDEX 32H ................................................................................................ - 18 7.39 VID INPUT LATCH REGISTER – INDEX 33H ........................................................................................................ - 19 7.40 RSTOUT CONTROL REGISTER – INDEX 34H .................................................................................................... - 19 7.41 RSTOUT CONTROL REGISTER – INDEX 35H .................................................................................................... - 19 7.42 WATCHDOG TIMER CONTROL REGISTER – INDEX 36H ....................................................................................... - 20 7.43 WATCHDOG TIMER RANGE REGISTER – INDEX 37H........................................................................................... - 21 7.44 GPIO3X OUTPUT CONTROL REGISTER – INDEX 40H ........................................................................................ - 21 7.45 GPIO3X OUTPUT DATA REGISTER – INDEX 41H ............................................................................................... - 21 7.46 GPIO3X INPUT STATUS REGISTER – INDEX 42H ............................................................................................... - 22 7.47 GPIO3X LEVEL/PULSE CONTROL REGISTER – INDEX 43H ................................................................................ - 22 7.48 GPIO3X PULSE WIDTH CONTROL REGISTER – INDEX 44H ................................................................................ - 22 7.49 GPIO3X INPUT DE-BOUNCE REGISTER – INDEX 46H ........................................................................................ - 23 7.50 GPIO3X PULSE INVERSE REGISTER – INDEX 47H ............................................................................................ - 23 7.51 GP3X EDGE DETECTOR ENABLE REGISTER – INDEX 0X48 ............................................................................... - 24 7.52 EDGE DETECTOR STATUS REGISTER – INDEX 0X49 .......................................................................................... - 24 7.53 IRQ OR SMI# ENABLE REGISTER – INDEX 0X4A .............................................................................................. - 25 7.54 OUTPUT DRIVING ENABLE – INDEX 0X4C ......................................................................................................... - 25 7.55 CHIPID(1) REGISTER – INDEX 5AH ................................................................................................................. - 26 7.56 CHIPID(2) REGISTER – INDEX 5BH ................................................................................................................. - 26 7.57 VENDOR ID(1) REGISTER – INDEX 5DH ......................................................................................................... - 26 7.58 VENDOR ID(2) REGISTER – INDEX 5EH ......................................................................................................... - 26 7.59 REGISTER – INDEX F1H................................................................................................................................... - 26 8. ELECTRON CHARACTERISTIC............................................................................................................................- 27 8.1 ABSOLUTE MAXIMUM RATINGS........................................................................................................................... - 27 8.2 DC CHARACTERISTICS ...................................................................................................................................... - 27 8.3 AC CHARACTERISTICS ...................................................................................................................................... - 30 9. ORDERING INFORMATION ...................................................................................................................................- 31 10. PACKAGE DIMENSIONS ....................................................................................................................................- 31 - -2- July, 2007 V0.28P 1. General Description The F75122 is the dynamic voltage ID controller chip to provide the advanced CPU voltage programming when over clocking. F75122 supports the dynamic VID spec. for new generation Auto sensing CPU Besides of VID controlling Intel Prescott CPU and also compatible to VRM10.0/VRM9.X spec.. replacement and setting watch dog timer for OS idling protection. function, F75122 also supports pure 8 GPIO pins. by registers. Level or pulse modes can be programmed With 2 sets of watchdog timer, F75122 provides more flexible control for PC system, and there are four kinds of pulse width of the time out alert output pin can be selected. 2. Features Supporting new generation Intel dynamic Processor VID input /output Supporting Intel Prescott CPU low level input (VIH > 0.9V, VIL