F75125

F75125 Serial VID, Parallel VID Translator for AMD AM2 and AM2+ Release Date: Mar, 2008 Version: 0.16P Fintek Feature Integration Technology Inc. F75125 F75125 Datasheet Revision History Version 0.10P 0.11P 0.12P Date Jun, 2007 Page Preliminary version 17 Add register description Company address Revision History Jul, 2007 22 Jul, 2007 8 1 Add Electrical Characteristics Correct over voltage max a\value:2.325V Add VSI/VSO illustration Revise register description Remove “G” from ordering information Add SVI output and PSI description in General Description Add SVI output in Features 5 6 7 8 Add PSI in Features Revise Pin Configuration Add SVI output related pin descriptions in NB related pins Set VID_OUT[2] and VID_OUT[3] to multi-function pins with SVC_OUT and SVD_OUT 17 25 26 27 32 25 26 Add NB OFF code and power saving mode description Add VDD and VDD_NB follow mode register Add VDD0,1 and VDD_NB SVID value monitor function register Add VDD timeout set register Add Serial VID output application circuit Register 0x08 renamed to VSI/VSO 1 Register 0x09 renamed to VSI/VSO 2 Add register 0x10 description Add register 0x11 description Add register 0x12 description 0.13P Sep, 2007 16 19 0.14P Oct, 2007 27 4 0.15P Feb, 2008 0.16P Mar, 2008 27 27 28 1 V0.16P Fintek Feature Integration Technology Inc. F75125 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. 2 V0.16P Fintek Feature Integration Technology Inc. F75125 Table of Contents 1 2 3 4 GENERAL DESCRIPTION ........................................................................................................................................................ 5 FEATURE ..................................................................................................................................................................................... 5 PIN CONFIGURATION .............................................................................................................................................................. 7 PIN DESCRIPTION..................................................................................................................................................................... 8 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 5 POWER PIN ........................................................................................................................................................................... 8 NORTH BRIDGE VOLTAGE PIN/ VOLTAGE REGULATOR SET TRAP PIN ................................................................................... 8 VID PIN ................................................................................................................................................................................ 9 POWER GOOD PIN ................................................................................................................................................................. 9 VOLTAGE SENSE INPUT/VOLTAGE SENSE OUTPUT PIN ........................................................................................................ 10 I2C INTERFACE PIN ............................................................................................................................................................. 10 MISCELLANEOUS PIN .......................................................................................................................................................... 10 ELECTRICAL CHARACTERISTIC........................................................................................................................................11 5.1 5.2 ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................... 11 DC CHARACTERISTICS ........................................................................................................................................................ 11 6 FUNCTIONAL DESCRIPTION ............................................................................................................................................... 14 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 LINEAR CON PARALLEL VID INTERFACE ............................................................................................................................ 14 SERIAL VID INTERFACE ...................................................................................................................................................... 16 2-BIT BOOT CODE AND VFIXEN MODE ............................................................................................................................. 18 NORTH BRIDGE REFERENCE VOLTAGE AND ENABLE .......................................................................................................... 18 POWER SAVING MODE ........................................................................................................................................................ 19 CORE_TYPE..................................................................................................................................................................... 20 VOLTAGE SENSE INPUT/ VOLTAGE SENSE OUTPUT ............................................................................................................. 20 I2C INTERFACE ................................................................................................................................................................... 21 7 REGISTER DESCRIPTION (I2C ADDRESS = 0X5C).......................................................................................................... 22 7.1 7.2 7.3 7.4 7.5 7.6 7.7 VDDNB VOLTAGE VALUE REGISTER ⎯ INDEX 00H ............................................................................................................ 22 VDD0 VOLTAGE VALUE REGISTER ⎯ INDEX 01H ............................................................................................................... 23 VDD1 VOLTAGE VALUE REGISTER ⎯ INDEX 02H ............................................................................................................... 23 VID KEY PROTECT REGISTER ⎯ INDEX 03H ..................................................................................................................... 24 VDDNB VOLTAGE OFFSET VALUE REGISTER ⎯ INDEX 04H................................................................................................ 24 VDD0 VOLTAGE OFFSET VALUE REGISTER ⎯ INDEX 05H ................................................................................................... 24 VDD1 VOLTAGE OFFSET VALUE REGISTER ⎯ INDEX 06H ................................................................................................... 25 3 V0.16P Fintek Feature Integration Technology Inc. F75125 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 8 9 VDDNB STEP TIME REGISTER ⎯ INDEX 07H ................................................................................................................ 25 VSI/VSO 1 OVER VOLTAGE SELECT READING REGISTER ⎯ INDEX 08H ............................................................................ 25 VSI/VSO 2 OVER VOLTAGE SELECT READING REGISTER ⎯ INDEX 09H ............................................................................ 26 VDD0, VDD1 AND VDDNB MANUAL ENABLE REGISTER ⎯ INDEX 0AH .......................................................................... 26 NB_VREF VOLTAGE READING REGISTER (LSB) ⎯ INDEX 0BH ...................................................................................... 26 VDDNB SVI OUTPUT READING REGISTER (LSB) ⎯ INDEX 0CH .................................................................................... 27 VDD0 SVI OUTPUT READING REGISTER (LSB) ⎯ INDEX 0DH........................................................................................ 27 VDD1 SVI OUTPUT READING REGISTER (LSB) ⎯ INDEX 0EH ........................................................................................ 27 SLOTOCC CONTROL ENABLE READING REGISTER ⎯ INDEX 0FH................................................................................... 27 VDD_NB VOLTAGE VALUE REGISTER ⎯ INDEX 10H ....................................................................................................... 27 VDD0 VOLTAGE VALUE REGISTER ⎯ INDEX 11H ............................................................................................................. 27 VDD1 VOLTAGE VALUE REGISTER ⎯ INDEX 12H............................................................................................................. 28 VID TIMEOUT VALUE SELECT REGISTER ⎯ INDEX 13H.................................................................................................... 28 CHIP ID1 REGISTER ⎯ INDEX 5AH ................................................................................................................................... 28 CHIP ID2 REGISTER ⎯ INDEX 5BH .................................................................................................................................... 28 VERSION ID REGISTER ⎯ INDEX 5CH ................................................................................................................................ 28 VENDOR ID1 REGISTER ⎯ INDEX 5DH............................................................................................................................... 28 VENDOR ID2 REGISTER ⎯ INDEX 5EH ............................................................................................................................... 28 ORDERING INFORMATION .................................................................................................................................................. 29 PACKAGE DIMENSIONS (28-SSOP) ..................................................................................................................................... 29 10 APPLICATION CIRCUIT ........................................................................................................................................................ 32 4 V0.16P Fintek Feature Integration Technology Inc. F75125 1 General Description The Serial VID interface (SVI)/ Parallel VID interface (PVI) translator,F75125, which can translate PVI to PVI and SVI to PVI for AMD AM2 or AM2+ platform and output a programmable reference voltage of North Bridge voltage (VNB) to an external single phase PWM by decoding serial VID. Or, it can translate SVI to SVI and PVI to SVI for AMD AM2 or AM2+ platform. In the PVI output application, the F75125 can replace the hybrid (PVI+SVI) or SVI voltage regulator by the original PVI voltage regulator controller to save the extra cost. The F75125 supports VDDIO, VDDA, and CPU power good input, CPU_PG_IN, such as from the south bridge, SB600, to control the signal, VR_EN to enable the VR controller. F75125 supports all AM2+ new features including CORE_TYPE and VFIXEN. The CORE_TYPE is used to indicate AM2 or AM2+ placed, and the VFIXEN paired with SVC and SVD let voltage regulator output a fixed voltage. In this application of the F75125, VID[5] is recommended to pull low ,so the VID output [4:0] is corresponding to output from 0.775 to 1.550V. In concern of mapping SVI to PVI, VID table on-the-fly tuning is constrained in 0.800V to 1.550V. The Voltage Sense Input (VSI)/Voltage Sense Output (VSO) also provide the similar function, but the tuning range up to 2.325V. In the SVI output application, the F75125 will issue SVI OFF code to VDD_NB to avoid VDD_NB mis-action when AM2 is implemented. In SVI output mode, the F75125 also supports PSI (bit7 of SVI command). The F75125 is SSOP-28 package and powered by 3.3VSB. 2 Feature Serial VID Input to Parallel VID Output or Parallel VID Input to Parallel VID Output Translation for Parallel VID Interface Voltage Regulator Controller Serial VID Input to Serial VID Output or Parallel VID Input to Serial VID Output Translation for Hybrid/Serial VID Interface Voltage Regulator Controller Serial or Parallel VID Mapping Table Is Adjustable to Tune Voltage Regulator Controller Output. Programmable Reference Voltage Output for North Bridge Voltage for Over or Under Voltage in PVI Output Mode VFIXEN, SVC, SCD Translation to PVI Voltage Regulator Realizes AM2+ Fixed Voltage Output to CPU Function Support CORE_TYPE Input to Indicate AMD Processor Family 0Fh,AM2 or 10h,AM2+ Support VDDIO, VDDA, CPU Power Good, CPU_PG_IN, Input to Generate Voltage Regulator Controller Enable Signal, VR_EN, and CPU Power Good Output, CPU_PG_OUT, to CPU and Voltage Regulator. 5 V0.16P Fintek Feature Integration Technology Inc. F75125 2 Sets of Voltage Sense Input (VSI) and Voltage Sense Output (VSO) for Over Voltage Vcore and VNB beyond Maximum of VID Table, 1.55V. I2C Interface Is Built-in to Fine Tune Vcore and VNB output. Power Saving Mode Supported in Both AM2+ Platform Powered by 3.3VSB and SSOP-28 Package 6 V0.16P Fintek Feature Integration Technology Inc. F75125 3 Pin Configuration Figure1. F75125 pin configuration 7 V0.16P Fintek Feature Integration Technology Inc. F75125 4 Pin Description P INst INLV Power pins - TTL level input pin with schmitt trigger - Low level input, transient point at 0.9V I/OD12st5V - TTL level bi-directional pin with schmitt trigger, Open-drain output with 12 mA sink capability, 5V tolerance I/OD12st - TTL level bi-directional pin with schmitt trigger, Open-drain output with 12 mA sink capability. I/OD12LV O12 OD12 AIN AOUT - Low level input, transient point at 0.9V , Open-drain output with 12 mA sink capability - Output pin with 12mA sink/driving capability. - Open-Drain output pin with 12mA sink capability. - Input pin (Analog). - Output pin (Analog). 4.1. Power Pin Pin No. 4 6 8 26 Pin Name VSB3V VDDA VDDIO VSS Type P P P P Description 3.3V stand by power VDDA input VDDIO power Ground 4.2. North Bridge Voltage Pin/ Voltage Regulator Set Trap Pin Pin No. 3 Pin Name VREF_NB Type AOUT PWR VSB3V Description In PVI output mode, reference voltage output to external single phase PWM to supply VNB. Pull high to 3,3VSB before POK, the F75125 will enter SVI 5 NB_EN#/VR_TRAP O12 VSB3V output mode, or the F75125 is set to PVI output mode. In PVI output mode, NB_EN# is an external single phase PWM enable signal. 8 V0.16P Fintek Feature Integration Technology Inc. F75125 4.3. VID Pin Pin No. 10 Pin Name VID_IN[4] Type INLV PWR VSB3V CPU VID input pin. Special level input VIH CPU VID input pin. VID_IN[3] 11 SVC_IN VID_IN[2] 12 SVD_IN I/OD12LV VSB3V INLV VSB3V SVC (Serial VID Clock)-open drain output of the processor. Connect to this pin to the processor. CPU VID input pin. Special level input VIH 0.9, VIL 0.6 SVD (Serial VID Data)-bidirectional signal that is an input and open drain output for both master and slave devices. Connect to this pin to the processor. 13 14 15 16 VID_IN[1] VID_IN[0] VID_OUT[0] VID_OUT[1] INLV INLV OD12 VSB3V VSB3V VSB3V VSB3V CPU VID input pin. Special level input VIH CPU VID input pin. Special level input VIH CPU VID output pin. Special level input VIH CPU VID output pin. Special level input VIH 0.6 SVC(Serial VID Clock)-open drain output of the F75125. Connect to this pin to the voltage regulator. CPU VID output pin. Special level input VIH 0.6 I/OD12 SVD_OUT VSB3V SVD (Serial VID Data)-bidirectional signal that is an input and open drain output for both master and slave devices. Connect to this pin to the voltage regulator. 19 VID_OUT[4] OD12 VSB3V CPU VID output pin. Special level input VIH 0.9, VIL 0.6 0.9, VIL 0.9, VIL 0.6 0.9, VIL CPU VID output pin. Special level input VIH OD12 SVC_OUT VID_OUT[3] 18 VSB3V 0.9, VIL 0.6 0.9, VIL 0.6 0.9, VIL 0.6 Special level input VIH 0.9, VIL 0.6 0.9, VIL 0.6 Description OD12 VID_OUT[2] 17 4.4. Power Good Pin Pin No. Pin Name Type PWR Description VR disable signal input. The source is NOR S3# and 21 VR_DIS_IN INLV VSB3V VLDT. VR_DIS_IN < 0.6V, VR_EN goes high. VR_DIS_IN > 0.9V, VR_REN goes low. 9 V0.16P Fintek Feature Integration Technology Inc. F75125 22 CPU_PG_IN INst VSB3V CPU power good signal input, usually from the south bridge 4.5. Voltage Sense Input/Voltage Sense Output Pin Pin No. 1 Pin Name VSI_1 Type AIN PWR VSB3V Description Voltage sensor channel 1 input for Vcore or VNB change use. Voltage sensor channel 1 output for Vcore or VNB change use. VSB3V Voltage sensor channel 2 output for Vcore or VNB change use. VSB3V Voltage sensor channel 2 input for Vcore or VNB change use. 2 VSO_1 AOUT VSB3V 27 VSO_2 AOUT 28 VSO_1 AIN 4.6. I2C Interface Pin Pin No. 24 25 Pin Name SCL SDA Type INst I/OD12st PWR VSB3V VSB3V Description I2C interface, serial clock input pin. I2C interface, serial data pin. 4.7. Miscellaneous Pin Pin No. Pin Name Type PWR Description Hardware jumper input that selects normal operation 7 VFIXEN INLV VSB3V mode or VFIX mode. When VFIXEN inserts, the voltage regulator will enter VFIX mode. Processor CORE_TYPE input. 9 CORE_TYPE INLV VSB3V In AMD NPT Family 0Fh, CORE_TYPE is floating In AMD NPT Family 10h, CORE_TYPE is tied to VSS at package. 20 23 VR_EN SLOTOCC# OD12 INst VSB3V VSB3V Active-high signal enables the VID VR CPU SLOTOCC# input. 10 V0.16P Fintek Feature Integration Technology Inc. F75125 5 Electrical Characteristic 5.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature RATING -0.5 to 5.5 -0.5 to VDD+0.5 0 to +70 -55 to 150 UNIT V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device 5.2 DC Characteristics (Ta = 0° C to 70° C, VCC = 3.3V ± 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS OD12- Open-drain output with12 mA sink capability. Output Low Current IOL +12 mA VOL = 0.4V Input High Leakage ILIH +1 μA VIN = VCC Input Low Leakage ILIL -1 μA VIN = 0V I/OD12st-TTL level bi-directional pin with schmitt trigger, Output pin with 12mA sink capability. Input Low Threshold Voltage Vt0.8 V VCC = 3.3 V Input High Threshold Voltage Vt+ 2.0 V VCC = 3.3 V Output Low Current IOL -12 -9 mA VOL = 0.4 V Input High Leakage ILIH +1 μA VIN = VCC Input Low Leakage ILIL -1 μA VIN = 0V I/OD12lv-Low voltage bi-directional pin, Open drain output pin with 12mA sink capability. Input Low Threshold Voltage Vt0.6 V VCC = 3.3 V Input High Threshold Voltage Vt+ 0.9 V VCC = 3.3 V Output Low Current IOL -12 -9 mA VOL = 0.4 V Output High Current IOH +9 +12 mA VOH = 2.4V Input High Leakage ILIH +1 μA VIN = 1.2V Input Low Leakage ILIL -1 μA VIN = 0V INlv - Low level input pin Input Low Voltage VIL 0.6 V Input High Voltage VIH 0.9 V Input High Leakage ILIH +1 μA VIN = 1.2V 11 V0.16P Fintek Input Low Leakage ILIL -1 O12- Output pin with 12mA source-sink capability. Output Low Current IOL -12 Output High Current IOH +9 +12 Input High Leakage ILIH Input Low Leakage ILIL -1 Feature Integration Technology Inc. F75125 μA -9 +1 mA mA μA μA VIN = 0 V VOL = 0.4 V VOH = 2.4V VIN = VCC VIN = 0V 5.3 AC Characteristics t SCL t t R R SCL t HD;STA t HD;DAT t t SU;DAT SU;STO SDA IN VALID DATA t DEL;DAT SDA OUT Serial Bus Timing Diagram Figure2. SMBus timing diagram Serial Bus Timing PARAMETER SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time DATA OUT to SCL delay time SCL and SDA rise time SCL and SDA fall time SYMBOL t-SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tDEL:DATA tR tF MIN 3 50 50 50 5 200 200 200 MAX UNIT uS nS nS nS nS ns nS nS 12 V0.16P Fintek t SVC Feature Integration Technology Inc. F75125 tR tR SVC t HD;STA t HD;DAT t SU;DAT t SU;STO SVD IN VALID DATA t DEL;DAT SVD OUT Serial Bus Timing Diagram Figure3. Serial VID timing diagram Serial VID interface Timing PARAMETER SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time DATA OUT to SCL delay time SCL and SDA rise time SCL and SDA fall time SYMBOL t-SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tDEL:DATA tR tF MIN. 2 50 50 50 5 200 200 200 MAX. UNIT uS nS nS nS nS ns nS nS 13 V0.16P Fintek Feature Integration Technology Inc. F75125 6 Functional Description 6.1 Linear Con Parallel VID Interface The F75125 supports 6-bit Parallel VID Interface (PVI). The 6-bit parallel VID codes and the corresponding reference voltage are shown in Table 1. It is recommended to connect VID[0:4] output of AM2 or AM2+ and VID[0:4] input of voltage regulator (VR) controller with F75125 due to the pin-out constraint and tied VID[5] input of the VR controller to VSS. The connection can correspond to reference voltage from 1.55V to 0.775V. The corresponding reference voltage is from 0.800V to 1.550V in concerns of the translation between Serial VID Interface (SVI) and PVI. The VID output is adjustable according to the Parallel VID table on-the-fly or by VSI/VSO function through I2C interface. Table 1. 6-bit Parallel VID Codes VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VREF 1.5500 1.5250 1.5000 1.4750 1.4500 1.4250 1.4000 1.3750 1.3500 1.3250 1.3000 1.2750 1.2500 1.2250 1.2000 1.1750 1.1500 1.1250 1.1000 1.0750 1.0500 14 V0.16P Fintek 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Feature Integration Technology Inc. F75125 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.0250 1.0000 0.9750 0.9500 0.9250 0.9000 0.8750 0.8500 0.8250 0.8000 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 15 V0.16P Fintek 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 Feature Integration Technology Inc. F75125 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 6.2 Serial VID Interface The Serial VID Interface (SVI) circuitry allows AM2+ to directly drive the core voltage and Northbridge voltage reference level with the SVI VR controller. The SVC and SVD states are decoded with direction from the PWROK and VFIXEN inputs as described in the following sections. The F75125 is built-in SVI client to translate SVI to PVI. It can help the PVI VR controller keep supporting AM2+ in SVI mode to reduce extra cost to adapt the hybrid VR controller (SVI+PVI) or the SVI VR controller. The VID codes output translated form SVI is also adjustable from 0.800V to 1.550V according to the VID table on-the-fly by I2C interface. If the output is beyond the VID table, it can be tuned by VSI/VSO function, too. 16 V0.16P Fintek Feature Integration Technology Inc. F75125 Table 2. Serial VID Codes SVID[6:0] 000_0000 000_0001 000_0010 000_0011 000_0100 000_0101 000_0110 000_0111 000_1000 000_1001 000_1010 000_1011 000_1100 000_1101 000_1110 000_1111 001_0000 001_0001 001_0010 001_0011 001_0100 001_0101 001_0110 001_0111 001_1000 001_1001 001_1010 001_1011 001_1100 001_1101 001_1110 001_1111 VREF 1.5500 1.5375 1.5250 1.5125 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 SVID[6:0] 010_0000 010_0001 010_0010 010_0011 010_0100 010_0101 010_0110 010_0111 010_1000 010_1001 010_1010 010_1011 010_1100 010_1101 010_1110 010_1111 011_0000 011_0001 011_0010 011_0011 011_0100 011_0101 011_0110 011_0111 011_1000 011_1001 011_1010 011_1011 011_1100 011_1101 011_1110 011_1111 VREF 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 SVID[6:0] 100_0000 100_0001 100_0010 100_0011 100_0100 100_0101 100_0110 100_0111 100_1000 100_1001 100_1010 100_1011 100_1100 100_1101 100_1110 100_1111 101_0000 101_0001 101_0010 101_0011 101_0100 101_0101 101_0110 101_0111 101_1000 101_1001 101_1010 101_1011 101_1100 101_1101 101_1110 101_1111 VREF 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 * * * * * * * * * * * SVID[6:0] 110_0000 110_0001 110_0010 110_0011 110_0100 110_0101 110_0110 110_0111 110_1000 110_1001 110_1010 110_1011 110_1100 110_1101 110_1110 110_1111 111_0000 111_0001 111_0010 111_0011 111_0100 111_0101 111_0110 111_0111 111_1000 111_1001 111_1010 111_1011 111_1100 111_1101 111_1110 111_1111 VREF 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 OFF OFF OFF OFF * * * * * * * * * * * * * * * * * * * * * * * * * * * * Note: * Indicates a VID not required for AMD Family 10h processors (AM2+). 17 V0.16P Fintek Feature Integration Technology Inc. F75125 6.3 2-Bit Boot Code and VFIXEN Mode VFIXEN is an input signal used to indicate the VR controller in the VFIX mode. If anytime VFIXEN is asserted, the VR controller must enter VFIX mode. When in VFIX mode, all of the VR controller’s output voltage will be governed by the information shown in Table 4. However, the PVI VR controller doesn’t integrate the VFIXEN input pin, the F75125 can translate the VFIXEN, SVC, and SVD to PVI codes to indicate the PVI VR controller in the VFIX mode. Pre-PWROK METAL VID, 2-Bit Boot Code Typical motherboard start-up occurs with the VFIXEN input low. The F75125 decodes the SVC and SVD inputs to determine the Pre-PWROK metal VID setting. After PWROK is asserted, the processor initializes the SVI, and the serial VID codes are used. Table 3. Pre-PWROK Metal VID Codes SVC 0 0 1 1 SVD 0 1 0 1 Output Voltage (V) 1.1 1.0 0.9 0.8 VFIX MODE In VFIX mode, the SVC, SVD, and VFIXEN inputs are fixed external to controller through jumpers to either GND or VDDIO. If VFIXEN is high, the F75125 decodes the SVC and SVD states per Table 4 regardless of the state of PWROK. Once enable, the VR controller and the external single phase PWM begin to soft-start both VDD and VDDNB planes. Table 4. VFIX Mode VID Codes SVC 0 0 1 1 SVD 0 1 0 1 Output Voltage (V) 1.4 1.2 1.0 0.8 6.4 North Bridge Reference Voltage and Enable The PVI VR controller which is designed for AM2 or prior processor doesn’t integrate the second precision voltage regulation system for the North Bridge portion of AM2+. In order to forward compatible to AM2+, the F75125 18 V0.16P Fintek Feature Integration Technology Inc. F75125 provides the North Bridge reference voltage output, NB_VREF, and North Bridge voltage enable signal, NB_EN#, to the external single phase PWM which provides the North Bridge voltage. The F75125 successfully decodes the information North Bridge voltage determines as the processor in the SVI mode, and then the NB_VREF is in the soft-start process. The NB_EN# will be asserted high to low when the NB_VREF is over 0.3V. Both NB_VREF and NB_EN# will be disabled as the processor in PVI mode. The NB_VREF output is adjustable from 0.3V to 2.04V by I2C interface. Per Step is 12.5mV. Another application of the F75125 is to support SVI output. Pull high NB_EN# to 3,3VSB before POK, and then the F75125 will switch the output mode to SVI output. In SVI output mode, the F75125 will translate PVID to the corresponding SVID and issue VDD_NB an OFF command (111_1111 in SVID table) to disable VDD_NB output of voltage regulator as AM2 implemented*1. Note: *1 The chosen voltage regulator must support SVID OFF command, or VDD_NB keeps outputting as AMD implemented. 6.5 Power Saving Mode The power saving mode is supported in SVI mode. Serial VID codes are transmitted as part of an 8-bit data phase over the SVI. The bits are allocated as defined in Table 5. Table 5. Serial VID 8-Bit Data Field Encoding Bits PSI_L: 7 =0, means the processor is at an optimal load for the regulator(s) to enter power saving mode =1, means the processor is not at an optimal load for the regulator(s) to enter power saving mode 6:0 SVID[6:0] as defined in Table 2. Description In AM2+ platform, the truth table of PSI# and SVID_IN[7] is defined in Table 6. Table 6. SVID_IN[7], SVID_OUT[7] Relationship SVID_IN[7]*1 0 SVID_OUT[7]*2 0 Remark AM2+ is at a light load condition for the regulator(s) to enter power saving mode AM2+ is not at a light load condition for the regulator(s) to enter power saving mode 1 1 19 V0.16P Fintek Note: *1 SVID_IN[7] is output by the processor to the F75125 Feature Integration Technology Inc. F75125 *2 SVID_OUT[7] is output by the F75125 to the Vcore voltage regulator 6.6 CORE_TYPE The CORE_TYPE is used to indicate which kind of processor placed and which kind of VID codes should be issued by the processor. According to AMD’s reference circuit, the VID[1] is recommended tied with CORE_TYPE. In AM2, CORE_TYPE is floating, and VID[1] is driven to VDDIO by the processor. The processor will issue the parallel VID codes. In AM2+, CORE_TYPE is tied to VSS at the package, and VID[1] is driven low via strap to ground. The processor will issue the serial VID codes. CORE_TYPE is also connected to the F75125 to indicate which kind of VID codes will be decoded. 6.7 Voltage Sense Input/ Voltage Sense Output The Voltage Sense Input (VSI) and Voltage Sense Output (VSO) are designed for another option of over voltage, especially beyond the VID table, 1.55V. Every step of over voltage is 1.5% more of the current voltage. Total tuning steps are 32 steps, so the maximum tuning range up is to 2.325V. F72815 VREF Multi-phase PWM VI Vout VREF + _ + _ Vout VSO VSI VSO VSI F75125 Vout=VREF*(1+n*0.01613) F75125 n=0,1,2……31 Figure 4 VSI/VSO function illustration 20 V0.16P Fintek Feature Integration Technology Inc. F75125 6.8 I2C Interface The F75125 can be connected to a compatible 2-wire serial system Management Bus (SMBus) as a slave device under the control of the master device, using two device terminals SCL and SDA. The controller can provide a clock signal to the device SCL pin and read/write data from/to the device through the device SDA pin. The address default is 0x5C(0101_1100) and the operation of device to the bus is described with details in the following sections. (a) SMBus write to internal address register followed by the data byte 0 SCLK SDA Start By Master 7 8 0 7 8 0 1 0 1 1 1 1 R/W Ack by 125 D7 D6 D5 D4 D3 D2 D1 D0 Ack by 125 Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte 7 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 8 Frame 3 Data Byte Stop by Master Figure 5. Serial Bus Write to Internal Address Register followed by the Data Byte (b) Serial bus write to internal address register only 0 SCL SDA Start By Master 7 8 0 7 8 0 1 0 1 1 1 1 R/W Ack by 125 D7 D6 D5 D4 D3 D2 D1 D0 Ack by 125 Stop by Master Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte Figure 6. Serial Bus Write to Internal Address Register Only (c) Serial bus read from a register with the internal address register prefer to desired location 0 SCL SDA Start By Master 7 8 0 7 8 0 1 0 1 1 1 1 R/W Ack by 125 D7 D6 D5 D4 D3 D2 D1 D0 Ack by Master Stop by Master Frame 1 Serial Bus Address Byte 1 Frame 2 Internal Index Register Byte Figure 7. Serial Bus Read from Internal Address Register 21 V0.16P Fintek Feature Integration Technology Inc. F75125 7 Register Description (I2C Address = 0x5C) 7.1 Bit VDDNB voltage value Register ⎯ Index 00h Name R/W Default Description VDDNB value, The default value is latch from SVC and SVD VFIXEN=1 SVC,SVD=0, The VDDNB default is 0x0C (1.4V) SVC,SVD=1, The VDDNB default is 0x1C (1.2V) SVC,SVD=2, The VDDNB default is 0x2C (1.0V) SVC,SVD=3, The VDDNB default is 0x3C (0.8V) VFIXEN=0 7-0 VDDNB R/W xx SVC,SVD=0, The VDDNB default is 0x24 (1.1V) SVC,SVD=1, The VDDNB default is 0x2C (1.0V) SVC,SVD=2, The VDDNB default is 0x34 (0.9V) SVC,SVD=3, The VDDNB default is 0x3C (0.8V) Manual disable(CR0A bit0 “0”) This register can program by SVI interface by ID 8’b110x_xx10. Manual enable(CR0A bit0 “1”) Programming by I2C interface and protect by key CR03 . 22 V0.16P Fintek 7.2 Bit Feature Integration Technology Inc. F75125 VDD0 voltage value Register ⎯ Index 01h Name R/W Default Description VDD0 value, The default value is latch from SVC and SVD VFIXEN=1 SVC,SVD=0, The VDD0 default is 0x0C (1.4V) SVC,SVD=1, The VDD0 default is 0x1C (1.2V) SVC,SVD=2, The VDD0 default is 0x2C (1.0V) SVC,SVD=3, The VDD0 default is 0x3C (0.8V) VFIXEN=0 7-0 VDD0 R/W xx SVC,SVD=0, The VDD0 default is 0x24 (1.1V) SVC,SVD=1, The VDD0 default is 0x2C (1.0V) SVC,SVD=2, The VDD0 default is 0x34 (0.9V) SVC,SVD=3, The VDD0 default is 0x3C (0.8V) Manual disable(CR0A bit0 “0”) This register can program by SVI interface by ID 8’b110x_x1x0 Manual enable(CR0A bit0 “1”) Programming by I2C interface and protect by key CR03. 7.3 Bit VDD1 voltage value Register ⎯ Index 02h Name R/W Default Description VDD1 value, The default value is latch from SVC and SVD VFIXEN=1 SVC,SVD=0, The VDD0 default is 0x0C (1.4V) SVC,SVD=1, The VDD0 default is 0x1C (1.2V) SVC,SVD=2, The VDD0 default is 0x2C (1.0V) SVC,SVD=3, The VDD0 default is 0x3C (0.8V) VFIXEN=0 7-0 VDD1 R/W xx SVC,SVD=0, The VDD0 default is 0x24 (1.1V) SVC,SVD=1, The VDD0 default is 0x2C (1.0V) SVC,SVD=2, The VDD0 default is 0x34 (0.9V) SVC,SVD=3, The VDD0 default is 0x3C (0.8V) Manual disable(CR0A bit0 “0”) This register can program by SVI interface by ID 8’b110x_1xx0 Manual enable(CR0A bit0 “1”) Programming by I2C interface and protect by key CR03. 23 V0.16P Fintek Feature Integration Technology Inc. F75125 7.4 Bit VID Key protect Register ⎯ Index 03h Name R/W Default Description Enter key by 0x32 0x5d 0x42 0xac When into key the reading value in this register will be 0xff. 7-0 VID_KEY R/W 0 Exit key by 0x35 It can be reset by watchdog timeout. If CR0F[0] is set to 1, it can be reset by SLOTOCC# pin, too (Default is disabled). 7.5 Bit VDDNB voltage offset value Register ⎯ Index 04h Name R/W Default Description 0x00: VDDNB voltage = VDDNB value(CR00) 0x01: VDDNB voltage = VDDNB value(CR00) + 1 voltage step(12.5mv) 0x7f: VDDNB voltage = VDDNB value(CR00) + 127 voltage step(12.5mv) but maximum value is 1.55V 0xff: VDDNB voltage = VDDNB value(CR00) - 1 voltage step(12.5mv) 7-0 NB_OFFSET R/W 0 0x80: VDDNB voltage = VDDNB value(CR00) - 128 voltage step(12.5mv) but minimum value is 0.0125V This register is write protect by Enter key CR03 It can be reset by watchdog timeout. If CR0F[0] is set to 1, it can be reset by SLOTOCC# pin, too (Default is disabled). 7.6 Bit VDD0 voltage offset value Register ⎯ Index 05h Name R/W Default Description 0x00:VDD0 voltage = VDD0 value(CR01) 0x01:VDD0 voltage = VDD0 value(CR01) + 1 step(12.5mv) 0x7F:VDD0 voltage = VDD0 value(CR01) + 127 step(12.5mv) but maximum value is 1.55V 0xFF:VDD0 voltage = VDD0 value(CR01) - 1 step(12.5mv) 7-0 VDD0_OFFSET R/W 0 0x80:VDD0 voltage = VDD0 value(CR01) - 128 step(12.5mv) but minimum value is 0.0125 ( in serial to parallel mode minimum value is 0.7875V) This register is write protect by Enter key CR03 It can be reset by watchdog timeout. If CR0F[0] is set to 1, it can be reset by SLOTOCC# pin, too (Default is disabled). 24 V0.16P Fintek Feature Integration Technology Inc. F75125 7.7 Bit VDD1 voltage offset value Register ⎯ Index 06h Name R/W Default Description 0x00:VDD1 voltage = VDD1 value(CR02) 0x01:VDD1 voltage = VDD1 value(CR02) + 1 step (12.5mv) 0x7f:VDD1 voltage = VDD1 value(CR02) + 127 step (12.5mv) but maximum value is 1.55V 0xff:VDD1 voltage = VDD1 value(CR02) - 1 step(12.5mv) 7-0 VDD1_OFFSET R/W 0 0x80:VDD1 voltage = VDD1 value(CR02) - 128 step (12.5mv) but minimum value is 0.0125V This register is write protect by Enter key CR03 It can be reset by watchdog timeout. If CR0F[0] is set to 1, it can be reset by SLOTOCC# pin, too (Default is disabled). 7.8 Bit 7-4 VDDNB STEP TIME Register ⎯ Index 07h Name Reserved R/W Default R 0 0: Direct load expect voltage (CR00+CR04) to NB_VREF pin 1: NB_VREF change voltage by step(8mV), each step is 100us 2: NB_VREF change voltage by step(8mV), each step is 200us Description 3_0 STEP_TIME_SEL R/W 2 But in power on NB_VREF soft start the rise time is 8mv per 100us This register is write protect by Enter key CR03 It can be reset by watchdog timeout. If CR0F[0] is set to 1, it can be reset by SLOTOCC# pin, too (Default is disabled). 7.9 Bit 7-5 VSI/VSO 1 Over Voltage select Reading Register ⎯ Index 08h Name Reserved R/W Default R 0 Vout = VREF *( 1 + (SWITCH_SEL_0*0.01613) ) Please refer Figure 4,P16 Description 4-0 SWITCH_SEL_1 R/W 0 This register is write protect by Enter key CR03 It can be reset by watchdog timeout. If CR0F[0] is set to 1, it can be reset by SLOTOCC# pin, too (Default is disabled). 25 V0.16P Fintek Feature Integration Technology Inc. F75125 7.10 VSI/VSO 2 Over Voltage select Reading Register ⎯ Index 09h Bit 7-5 Name Reserved R/W Default R 0 Vout = VREF *( 1 + (SWITCH_SEL_0*0.01613) ) Please refer Figure 4,P16 4-0 SWITCH_SEL_2 R/W 0 This register is write protect by Enter key CR03 It can be reset by watchdog timeout. If CR0F[0] is set to 1, it can be reset by SLOTOCC# pin, too (Default is disabled). Description 7.11 VDD0, VDD1 and VDDNB manual enable Register ⎯ Index 0Ah Bit 7-6 5 Name Reserved VDD0_MIRROR_EN R/W Default R R/W 0 0 of VDDNB. In serial VID output mode, if this bit is set to 1, VDDNB will follow VID 4 3-1 NB_MIRROR_EN Reserved R/W R 0 value of VDD0. 0 Reserved, 00: Manual mode is disabled. 01: Serial to parallel manual mode is enabled, but parallel to parallel keep in bypass mode. 10: Reserved. 11: Serial to parallel and parallel to parallel manual mode enabled. When F75125 manual mode enable, user can program CR00 , CR01 and 0 MANUAL_EN R/W 0 CR02 by i2c interface, and CR00 value will direct to control NB_VREF voltage (each step is 12.5mv) CR01 value + CR05 offset value will output to VID out. This register is write protect by Enter key CR03 It can be reset by watchdog timeout. If CR0F[0] is set to 1, it can be reset by SLOTOCC# pin, too (Default is disabled). Reserved, In serial VID output mode, if this bit is set to 1, VDD0 will follow VID value Description 7.12 NB_VREF Voltage Reading Register (LSB) ⎯ Index 0Bh Bit 7-0 Name NB_VID_OUT R/W Default R 0 {1’b0,VID_OUT_NB} * 8mv Description 26 V0.16P Fintek Feature Integration Technology Inc. F75125 7.13 VDDNB SVI Output Reading Register (LSB) ⎯ Index 0Ch Bit 7-0 Name NB _OUT R/W Default R 0 SVID_OUT_NB (CR00+CR04) Description 7.14 VDD0 SVI Output Reading Register (LSB) ⎯ Index 0Dh Bit 7-0 Name VDD0_OUT R/W Default R 0 Description SVID_OUT_VDD0 (CR01+CR05) 7.15 VDD1 SVI Output Reading Register (LSB) ⎯ Index 0Eh Bit 7-0 Name VDD1_OUT R/W Default R 0 Description SVID_OUT_VDD1(CR02+CR06) 7.16 SLOTOCC Control Enable Reading Register ⎯ Index 0Fh Bit 7 6-1 0 Name Reserved DUMMY_REG R/W Default R R/W 1 0 0 Reserved Dummy registers. Description SLOTOCC_CLR_EN R/W Enable SLOTOCC# pin to clear register 7.17 VDD_NB Voltage Value Register ⎯ Index 10h Bit 7-0 Name VDDNB R/W Default R xx presents all the SVID code including bit 7, PSI_L. Description This register can read VID value that input from SVI interface. This register 7.18 VDD0 Voltage Value Register ⎯ Index 11h Bit Name R/W Default Description This register can read VID value that input from PVI/SVI interface. In PVI input mode, MSB and LSB will be inserted “0” to complement 8 bit register. 7-0 VDD0 R xx For example, PVID code “111_111” will be read as 0x7E. In SVI mode, this register presents all the SVID code including bit 7, PSI_L. 27 V0.16P Fintek Feature Integration Technology Inc. F75125 7.19 VDD1 Voltage Value Register ⎯ Index 12h Bit 7-0 Name VDD1 R/W Default R xx presents all the SVID code including bit 7, PSI_L. Description This register can read VID value that input from SVI interface. This register 7.20 VID Timeout Value Select Register ⎯ Index 13h Bit 7 Name TIMER_EN R/W Default R/W 0 Description Set to 1 to enable VID watchdog timer.. When TIMER_EN is set to 1 and counter value down count to zero, it will 6-0 COUNT_VALUE R/W 7’h0 generate one reset pulse to clear internal registers and TIMER_EN bit will auto clear to 0. 7.21 CHIP ID1 Register ⎯ Index 5Ah Bit 7-0 Name CHIP_ID1 R/W Default R 07h Chip ID1 Description 7.22 Bit 7-6 CHIP ID2 Register ⎯ Index 5Bh Name CHIP_ID2 R/W Default R 03h Chip ID2 Description 7.23 Bit 7-0 Version ID Register ⎯ Index 5Ch Name VER_ID R/W Default R 30h Version ID Description 7.24 Bit 7-0 Vendor ID1 Register ⎯ Index 5Dh Name VENDOR_ID1 R/W Default R 19h Vendor ID1 Description 7.25 Vendor ID2 Register ⎯ Index 5Eh Bit 7-0 Name VENDOR_ID2 R/W Default R 34h Vendor ID2 Description 28 V0.16P Fintek Feature Integration Technology Inc. F75125 8 Ordering Information Part Number F75125R Package Type 28-SSOP (Green Package) Production Flow Commercial, 0°C to +70°C 9 Package Dimensions (28-SSOP) Figure 8. 28 Pin SSOP Package Diagram 29 V0.16P Fintek Feature Integration Technology Inc. F75125 Feature Integration Technology Inc. Headquarters 3F-7, No 36, Tai Yuan St., Chupei City, Hsinchu, Taiwan 302, R.O.C. TEL : 886-3-5600168 FAX : 886-3-5600166 www: http://www.fintek.com.tw Taipei Office Bldg. K4, 7F, No.700, Chung Cheng Rd., Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 866-2-8227-8027 FAX : 866-2-8227-8037 30 V0.16P Fintek Feature Integration Technology Inc. F75125 Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner 31 V0.16P Fintek 10 Application Circuit Feature Integration Technology Inc. F75125 Figure 9. F75125R Parallel VID Output Application Circuit 32 V0.16P Fintek Feature Integration Technology Inc. F75125 Figure 10. F75125R Serial VID Output Application Circuit 33 V0.16P