F81865

F81865 F81865 Super IO with 6 UARTs Release Date: May, 2010 Version: V0.28P May, 2010 V0.28P F81865 F81865 Datasheet Revision History Version V0.20P V0.21P V0.22P Date 2008/10/9 2008/10/23 2008/10/30 Page 92 130 Revision History Release Version Add GPIO Base Address Register Update Application Circuit 1. Pin 82 PWR Type Update to VBAT 2. Update UART Clock Register 3. Revise UART Name From UART0~5 to UART1~6 4. Add IR & Part of UART 6 Function at Pin 9, 10, 11 5. Add Bypass Mode at ACPI control register. 6. Add Electrical Characteristics 7. Checking Typing Made Correction & Clarification Made Correction & Clarification Revise index 96h bit 3-0 Update Application Circuit Made Correction & Clarification Modify Electrical Characteristics Made Correction & Clarification Modify Application Circuit (sheet 4) Made Correction & Clarification Add OVT# SMI mode to index 2h bit 5-4 & figure 7.3 Enhanced Fan Description & Count (Section 7.6.1 fan) Modify RS485 Enable Register for COM 1~6—Index F0h, bit 4 V0.23P 2008/12/17 - V0.24P V0.25P V0.26P V0.27P 2008/12/25 2009/6/17 2009/9/17 2009/12/07 V0.28P 2010/5/24 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. May, 2010 V0.28P F81865 Table of Content 1. 2. 3. 4. 5. 6. 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7. General Description ..................................................................................................................................... 5 Feature List .................................................................................................................................................. 5 Key Specification ......................................................................................................................................... 7 Block Diagram.............................................................................................................................................. 8 Pin Configuration ......................................................................................................................................... 9 Pin Description........................................................................................................................................... 10 Power Pin .............................................................................................................................................. 10 LPC Interface..........................................................................................................................................11 FDC ........................................................................................................................................................11 UART ..................................................................................................................................................... 13 Parallel Port ........................................................................................................................................... 16 Hardware Monitor .................................................................................................................................. 17 SPI, GPIO, SIR...................................................................................................................................... 17 ACPI Function Pins ............................................................................................................................... 18 KBC Function ........................................................................................................................................ 19 Function Description .................................................................................................................................. 20 7.1. 7.2. 7.3. 7.4. 7.5. 7.6. 7.7. 7.8. 7.9. 8. 8.1 8.2 8.3 8.4 8.5 8.6 Power on Strapping Option ................................................................................................................... 20 FDC ....................................................................................................................................................... 20 UART ..................................................................................................................................................... 34 Parallel Port ........................................................................................................................................... 37 Keyboard Controller............................................................................................................................... 41 Hardware Monitor .................................................................................................................................. 43 SPI Interface.......................................................................................................................................... 64 ACPI Function ....................................................................................................................................... 65 Watchdog Timer Function...................................................................................................................... 65 6.10 RTC Function ........................................................................................................................................ 19 7.10. RTC Function ........................................................................................................................................ 66 Register Description .................................................................................................................................. 69 Global Control Registers ....................................................................................................................... 75 FDC Registers (CR00) .......................................................................................................................... 83 Parallel Port Registers (CR03) .............................................................................................................. 85 Hardware Monitor Registers (CR04) ..................................................................................................... 86 KBC Registers (CR05) .......................................................................................................................... 86 GPIO Registers (CR06)......................................................................................................................... 87 May, 2010 V0.28P F81865 8.7 8.8 8.9 WDT Registers (CR07)........................................................................................................................ 102 SPI Registers (CR08) .......................................................................................................................... 102 PME and ACPI Registers (CR0A) ....................................................................................................... 105 8.10 RTC Registers (CR0B) ........................................................................................................................ 108 8.11 UART1 Registers (CR10) .................................................................................................................... 108 8.12 UART2 Registers (CR11) .....................................................................................................................110 8.13 UART3 Registers (CR12) .....................................................................................................................112 8.14 UART4 Registers (CR13) .....................................................................................................................113 8.15 UART5 Registers (CR14) .....................................................................................................................115 8.16 UART6 Registers (CR15) .....................................................................................................................117 9. 10. 11. 12. Electrical Characteristics ..........................................................................................................................119 Ordering Information................................................................................................................................ 122 Package Dimensions ............................................................................................................................... 123 Application Circuit .................................................................................................................................... 124 May, 2010 V0.28P F81865 1. General Description The F81865 is the featured IO chip for Industrial PC system. Equipped with one IEEE 1284 parallel port, 6 UART ports with 9-bit protocol, KBC, Serial Peripheral Interface (SPI), SIR and one FDC. The F81865 integrated with hardware monitor, 7 sets of voltage sensor, 2 sets of creative auto-controlling fans and 2 temperature sensor pins for the accurate dual current type temperature measurement for CPU thermal diode or external transistors 2N3906. The F81865 provides flexible features for multi-directional application. For instance, supports 53 GPIO pins, IRQ sharing function designed in UART feature for particular usage and accurate current mode H/W monitor will be worth in measurement of temperature, the F81865 also integrated SPI interface. The SPI interface is for BIOS usage including bridge function. Others, the F81865 supports newest Intel PECI interfaces for new generational CPU temperature use. Furthermore, F81865 provides independent RTC function. These features as above description will help you more and improve product value. Finally, the F81865 is powered by 3.3V voltage, with the LPC interface in the package of 128-PQFP. 2. Feature List General Functions Comply with LPC 1.1 Support ACPI 3.0 Provides one FDC, KBC and Parallel Port Provide 6 fully functional UART and 1 SIR 9-bit Protocol for UARTs Support IRQ Sharing function. H/W monitor functions SPI interface for BIOS RTC function Support PECI 1.0 interface 53 GPIO Pins for flexible application 24/48 MHz clock input Packaged in 128-PQFP and powered by 3.3VCC 5 May, 2010 V0.28P F81865 FDC Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and under run conditions Built-in address mark detection circuit to simplify the read electronics Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate UART Provide 6 fully functional UART 6 high-speed 16C550 compatible UART with 16-byte FIFOs Fully programmable serial-interface characteristics Baud rate supports 115.2K, max. up to 1.5M Support IRQ 3,4,5,6,7,8,9,10,11 sharing Provide 9-bits Function for Gaming Machine Support IrDA version 1.0 SIR protocol Parallel Port One PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 Enhanced printer port back-drive current protection Keyboard Controller compatibility with the 8042 Support PS/2 mouse Support both interrupt and polling modes Hardware Gate A20 and Hardware Keyboard Reset Hardware Monitor Functions 2 dual current type (±3℃) thermal inputs for CPU thermal diode and 2N3906 transistors Temperature range -40℃~127℃ 7 sets voltage monitoring (4 external and 3 internal powers) High limit signal (PME#) for Vcore level 6 May, 2010 V0.28P F81865 2 fan speed monitoring inputs 2 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans) Issue PME# and OVT# hardware signals output Case intrusion detection circuit WATCHDOG# comparison of all monitored values Integrate Intel PECI 1.0 Interface Serial Peripheral Interface Compatible Support SPI bridge function for BIOS use RTC function RTC for time synchronizing. Provide 256 bytes RAM for CMOS setting save. 32.768K Crystal input Stand alone VBAT power input requirement GPIO Function Total 53 pins GPIO Interrupt status support All GPIO can be programmed. All GPIO pins default mode are OD level input. Supports High/Low Level/Pulse, Open Drain/Push Pull function selection Package 128-pin PQFP Green Package Noted: Patented TW207103 TW207104 TW220442 US6788131 B1 TWI235231 TW237183 TWI263778 3. Key Specification Supply Voltage Operating Supply Current 3.0V to 3.6V 10 mA typ. 7 May, 2010 V0.28P F81865 4. Block Diagram CPU Chipset (NB+SB) Super H/W Monitor + F81865 IDE USB AC’97 Temperature Voltage Fan PECI KBC IrDA Parallel ACPI I/O LED (GPIO) COM Floppy SPI RTC 8 May, 2010 V0.28P F81865 5. Pin Configuration 9 May, 2010 V0.28P F81865 I/O12st,5V I/OOD12t I/OOD14 I/OOD8 I/OD16t,5v OD16,u10,5v I/OD12st,5v O8,u47,5v O8 O12 AOUT OD12,5v OD14 OD24 I/O24t I/O8t INt,5v INst INst,5v AIN P - TTL level bi-directional pin and schmitt trigger, 12 mA sink capability, 5V tolerance. - TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA source-sink capability. - TTL level bi-directional pin, can select to OD or OUT by register, with 14 mA source-sink capability. - TTL level bi-directional pin, can select to OD or OUT by register, with 8 mA source-sink capability. - TTL level bi-directional pin,Open-drain output with 16 mA source-sink capability, 5V tolerance. - Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance. - TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink capability, 5V tolerance. - Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance. - Output pin with 8 mA source-sink capability. - Output pin with 12 mA source-sink capability. - Output pin(Analog). - Open-drain output pin with 12 mA sink capability, 5V tolerance. - Open-drain output pin with 14 mA sink capability. - Open-drain output pin with 24 mA sink capability. - TTL level bi-directional pin, 24mA sink capability. - TTL level bi-directional pin, 8 mA sink capability. - TTL level input pin,5V tolerance. - TTL level input pin and schmitt trigger. - TTL level input pin and schmitt trigger, 5V tolerance. - Input pin(Analog). - Power. 6. Pin Description 6.1 Power Pin Pin Name VCC VSB VBAT RTC_VBAT AVCC AGND(D-) GND Type P P P P P P P Description Power supply voltage input with 3.3V Stand-by power supply voltage input 3.3V Battery voltage input Battery voltage input for RTC Analog Power with 3.3V Analog GND Digital GND Pin No. 31, 119 60 84 88 97 89 22, 73, 128 10 May, 2010 V0.28P F81865 6.2 23 24 25 26 27-30 32 33 LPC Interface Pin Name LRESET# LDRQ# SERIRQ LFRAME# LAD[0:3] PCICLK CLKIN Type INst,5v O12 I/O24t INst I/O24t INst INst PWR VCC VCC VCC VCC VCC VCC VCC Description Reset signal. It can connect to PCIRST# signal on the host. Encoded DMA Request signal. Serial IRQ input/Output. Indicates start of a new cycle or termination of a broken cycle. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. 33MHz PCI clock input. System clock input. According to the input frequency 24/48MHz. Pin No. 6.3 FDC Pin Name DENSEL# Type OD14 I/OOD14 O14 Pin No. PWR Description Drive Density Select. Set to 1 – High data rate.(500Kbps, 1Mbps) Set to 0 – Low data rate. (250Kbps, 300Kbps) General Purpose IO. UART Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. General Purpose IO. UART Serial Input. Used to receive serial data through the communication link. Infrared Receiver input. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. General Purpose IO. UART Serial Output. Used to transmit serial data out to the communication link. Infrared Transmitter Output. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. General Purpose IO. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. 9 GPIO50 RTS6_2# MOA# VCC OD14 I/OOD14 INt,5v INt,5v OD14 I/OOD14 O14 O14 OD14 I/OOD14 INt,5v 10 GPIO51 SIN6_2 IRRX_2 DRVA# VCC 11 GPIO52 SOUT6_2 IRTX_2 WDATA# VCC 12 GPIO53 DCD6# VCC 11 May, 2010 V0.28P F81865 DIR# 13 GPIO54 RI6# STEP# 14 GPIO55 CTS6# OD14 I/OOD14 INt,5v Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion VCC General Purpose IO. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. Step output pulses. This active low open drain output produces a pulse to move the head to another track. General Purpose IO. Clear To Send is the modem control input. Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 General Purpose IO. UART Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Write enable. An open drain output. General Purpose IO. VCC Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. The read data input signal from the FDD. General Purpose IO. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. General Purpose IO. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. General Purpose IO. Clear To Send is the modem control input. Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. VCC General Purpose IO. UART Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. OD14 I/OOD14 INt,5v VCC HDSEL# 15 OD14 GPIO56 DTR6# WGATE# GPIO57 I/OOD14 O14 OD14 I/OOD14 INt,5v INts5v I/OOD12 INt,5v VCC 16 DSR6# RDATA# GPIO60 DCD5# TRK0# 18 GPIO61 RI5# 17 VCC INt,5v I/OOD12 INt,5v VCC INDEX# 19 GPIO62 CTS5# WPT# 20 GPIO63 DTR5# INst,5v VCC I/OOD12 INt,5v INst,5v I/OOD12 O12 12 May, 2010 V0.28P F81865 DSKCHG# 21 GPIO64 DSR5# INt,s5v I/OOD12 INt,5v Diskette change. This signal is active low at power on and whenever the diskette is removed. VCC General Purpose IO. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. 6.4 120 121 122 UART Pin Name DCD1# RI1# CTS1# Type INt,5v INt,5v INt,5v Pin No. PWR VCC VCC VCC Description Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. Clear To Send is the modem control input. UART Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping pin: 1(Default): (Internal pull high) Power on fan speed default duty is 60%.(PWM) 0: (External pull down) Power on fan speed default duty is 100%.(PWM) UART Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping pin: 1: (internal pull high, default) Power on I2C slave address is 8’h5C. 0: (external pull down) Power on I2C slave address is 8’h5A. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART Serial Output. Used to transmit serial data out to the communication link. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping: 1(Default)Configuration register:4E/4F 0 Configuration register:2E/2F UART Serial Input. Used to receive serial data through the communication link. DTR1# 123 PWM_DUTY_T RAP O8,u47,5v VCC INt,5v VCC RTS1# 124 I2C_ADDR_TR AP O8,u47,5v VCC INt,5v VCC 125 DSR1# INt,5v VCC SOUT1 126 Config4E_2E O8,u47,5v VCC INt,5v 127 SIN1 INt,5v VCC 13 May, 2010 V0.28P F81865 1 2 3 DCD2# RI2# CTS2# INt,5v INt5v INt5v VCC VCC VCC Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. Clear To Send is the modem control input. UART Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping pin: 1(Default): (Internal pull high) FWH is enabled. 0: (External pull down) FWH is disabled. UART Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping pin: 1: (internal pull high, default) Fan control is PWM mode. 0: (external pull down) Fan control is linear mode (DAC output). Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART Serial Output. Used to transmit serial data out to the communication link. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping: 1(Default internal pull high) SPI is disabled. 0 (external pull down) SPI is enabled. UART Serial Input. Used to receive serial data through the communication link. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. General Purpose IO. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. General Purpose IO. Clear To Send is the modem control input. General Purpose IO. UART Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to DTR2# 4 FWH_TRAP O8,u47,5v VCC INt,5v VCC RTS2# 5 PWM_DC O8,u47,5v VCC INt5v VCC 6 DSR2# INt,5v VCC SOUT2 O8,u47,5v 7 SPI_TRAP INt,5v VCC 8 SIN2 DCD3# GPIO30 INt,5v INt,5v I/OOD8 INt5v I/OOD8 INt,5v I/OOD8 O8 VCC VCC 36 37 RI3# GPIO31 CTS3# GPIO32 DTR3# VCC 38 39 VCC VCC 14 May, 2010 V0.28P F81865 GPIO33 RTS3# GPIO34 DSR3# GPIO35 42 SOUT3 GPIO36 43 SIN3 GPIO37 44 DCD4# GPIO40 45 RI4# GPIO41 CTS4# GPIO42 DTR4# GPIO43 RTS4# I/OOD8 O8 I/OOD8 INt,5v I/OOD8 O8 I/OOD8 INt,5v I/OOD8 INt,5v I/OOD8 INt,5v I/OOD8 INt,5v I/OOD8 O8 I/OOD8 40 VCC communicate. General Purpose IO. UART Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. General Purpose IO. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General Purpose IO. UART Serial Output. Used to transmit serial data out to the communication link. General Purpose IO. 41 VCC VCC VCC UART Serial Input. Used to receive serial data through the communication link. General Purpose IO. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. General Purpose IO. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. General Purpose IO. Clear To Send is the modem control input. General Purpose IO. UART Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. General Purpose IO. UART Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Internal 47k ohms pulled high and disable after power on strapping. General Purpose IO. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General Purpose IO. UART Serial Output. Used to transmit serial data out to the communication link. General Purpose IO. UART Serial Input. Used to receive serial data through the communication link. General Purpose IO. VCC VCC 46 VCC 47 VCC 48 O8,u47,5v VCC GPIO44 DSR4# GPIO45 50 SOUT4 GPIO46 51 SIN4 GPIO47 I/OOD8 INt,5v I/OOD8 O8 I/OOD8 INt,5v I/OOD8 49 VCC VCC VCC 15 May, 2010 V0.28P F81865 6.5 Pin No. 102 Parallel Port Pin Name SLCT Type INst,5v PWR VCC Description An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Output line for detection of printer selection. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Output line for the printer initialization. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Parallel port data bus bit 1. Parallel port data bus bit 2. Parallel port data bus bit 3. Parallel port data bus bit 4. Parallel port data bus bit 5. Parallel port data bus bit 6. Parallel port data bus bit 7. 103 PE INst,5v VCC 104 BUSY INst,5v VCC 105 ACK# INst,5v VCC 106 SLIN# OD12,5v VCC 107 INIT# OD12,5v VCC 108 ERR# INst,5v VCC 109 AFD# OD12,5v VCC 110 STB# OD12,5v VCC 111 112 113 114 115 116 117 118 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 I/O12st,5v I/O12st,5v I/O12st,5v I/O12st,5v I/O12st,5v I/O12st,5v I/O12st,5v I/O12st,5v VCC VCC VCC VCC VCC VCC VCC VCC 16 May, 2010 V0.28P F81865 6.6 Pin No. 93 94 95 96 98 99 100 101 90 91 92 71 72 75 85 Hardware Monitor Pin Name VIN3 VIN2 VIN1 VIN0 (Vcore) FANIN1 FANCTL1 FANIN2 FANCTL2 D2+ D1+(CPU) VREF BEEP GPIO16 PECI GPIO17 OVT# COPEN# Type AIN AIN AIN AIN INs t , 5 v OD12,5v AOUT INs t , 5 v OD12,5v AOUT AIN AIN AOUT OD24 I/OOD12t I/O8t I/OOD12t OD12,5v INst,5v PWR AVCC AVCC AVCC AVCC VCC VCC VCC VCC AVCC AVCC AVCC VSB VSB VSB VBAT Description Voltage Input 3. Voltage Input 2. Voltage Input 1. Voltage Input for Vcore. Fan 1 tachometer input. Fan 1 control output. This pin provides PWM duty-cycle output or a voltage output. Fan 2 tachometer input. Fan 2 control output. This pin provides PWM duty-cycle output or a voltage output. Thermal diode/transistor temperature sensor input. CPU thermal diode/transistor temperature sensor input. This pin is for CPU use. Voltage reference output. Beep pin. General purpose IO. PECI interface pin. General purpose IO. Over temperature signal output. Case Open Detection #. This pin is connected to a specially designed low power CMOS flip-flop backed by the battery for case open state preservation during power loss. 6.7 Pin No. 52 53 54 55 56 57 SPI, GPIO, SIR Pin Name GPIO00 SPI_CLK GPIO01 SPI_CS0# GPIO02 SPI_MISO GPIO03 SPI_MOSI GPIO04 FWH_DIS GPIO05 SOUT6_1 Type I/OOD12t O12 I/OOD12t OD12 I/OOD12t INt , 5 v I/OOD12t O12 I/OOD12t O12 I/OOD12t O12 PWR VSB VSB VSB VSB VSB VSB Description General purpose IO. Serial clock output pin for SPI device. General purpose IO. Connect this pin to primary BIOS chip select pin. General purpose IO. SPI master in/slave out pin. General purpose IO. SPI master out/slave in pin. General purpose IO. Firmware hub disable General purpose IO. UART Serial Output. Used to transmit serial data out to the communication link. 17 May, 2010 V0.28P F81865 IRTX_1 GPIO06 58 SIN6_1 IRRX_1 GPIO07 59 RTS6_1# GPIO10 LED_VSB GPIO11 LED_VCC GPIO12 67 SCL SOUT5 GPIO13 68 SDA SIN5 GPIO14 69 RTS5# O12 Infrared Transmitter Output. I/OOD12t INt,5v INt,5v I/OOD12t O12 I/OOD12t OD12 I/OOD12t OD12 I/OOD12t I/OOD12t O12 I/OOD12t I/OOD12t INt,5v I/OOD12t O12 VSB VSB VSB VSB VSB General purpose IO. UART Serial Input. Used to receive serial data through the communication link. Infrared Receiver input. General purpose IO. UART Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. General purpose IO. Power LED for VSB. General purpose IO. Power LED for VCC. General purpose IO. SMBus Clock. UART Serial Output. Used to transmit serial data out to the communication link. General purpose IO. SMBus Data. UART Serial Output. Used to transmit serial data out to the communication link. General purpose IO. UART Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. 65 66 VSB VSB 6.8 Pin No. 70 76 ACPI Function Pins Pin Name WDTRST# GPIO15 ALERT# GPIO20 PME# ATXPG_IN GPIO21 PWSIN# GPIO22 PWSOUT# GPIO23 S3# GPIO24 Type OD12,5v I/OOD12t OD12 I/OOD12t OD12,5v INst,5v I/OOD12t INst,5v I/OOD12t OD12 I/OOD12t INst,5v I/OOD12t PWR VSB VSB Description Watch dog timer signal output. General purpose IO. Alert a signal when temperature over limit setting. General purpose IO. Generated PME event. It supports the PCI PME# interface. This signal allows the peripheral to request the system to wake up. ATX Power Good input. General purpose IO. Main power switch button input. General purpose IO. Panel Switch Output. This pin is low active and pulse output. It is power on request output#. General purpose IO. S3# Input is Main power on-off switch input. General purpose IO. 74 77 78 VSB VSB VSB 79 VSB 80 VSB 18 May, 2010 V0.28P F81865 81 PS_ON# GPIO25 82 PWROK GPIO26 83 RSMRST# GPIO27 OD12-5v I/OOD12t OD12 I/OOD12t OD12 I/OOD12t VBAT VBAT VSB Power supply on-off control output. Connect to ATX power supply PS_ON# signal. General purpose IO. PWROK function, It is power good signal of VCC, which is delayed 400ms (default) as VCC arrives at 2.8V. General purpose IO. Resume Reset# function, It is power good signal of VSB, which is delayed 66ms as VSB arrives at 2.8V. General purpose IO. 6.9 Pin No. 34 35 63 64 61 62 KBC Function Pin Name KBRST# GA20 KDATA KCLK MDATA MCLK Type OD16,u10,5V OD16,u10,5V I/OD16t,5V I/OD16t,5V I/OD16t,5V I/OD16t,5V PWR VCC VCC VSB VSB VSB VSB Description Keyboard reset. This pin is high after system reset. Internal pull high 3.3V with 10k ohms. Gate A20 output. This pin is high after system reset. Internal pull high 3.3V with 10k ohms. PS/2 Keyboard Data. PS/2 Keyboard Clock. PS/2 Mouse Data. PS/2 Mouse Clock. 6.10 RTC Function Pin No. 86 87 Pin Name RTC_X1 RTC_X2 Type AIN AOUT PWR RTC_ VBAT RTC_ VBAT Description RTC 32.768KHz crystal input. RTC 32.768KHz crystal output. 19 May, 2010 V0.28P F81865 7. Function Description 7.1. Power on Strapping Option The F81865 provides six pins for power on hardware strapping to select required functions. See below table for the detail: Pin No. 4 123 7 124 126 5 Symbol FWH_TRAP PWM_Duty SPI_TRAP I2C_ADDR Config4E_2E PWM_DC Value 1 0 1 0 1 0 1 0 1 0 1 0 Description FWH as a primary BIOS SPI as a primary BIOS Power on fan speed default duty is 60%. ( Default) Power on fan speed default duty is 100%. SPI function disable(Default) SPI function enable The I2C slave address is 8’h5C (Default) The I2C slave address is 8’h5A Configuration Register I/O port is 4E/4F. (Default) Configuration Register I/O port is 2E/2F. Fan control mode: PWM mode. ( Default) Fan control mode: DAC mode. 7.2. FDC The Floppy Disk Controller provides the interface between a host processor and one floppy disk drive. It integrates a controller and a digital data separator with write pre-compensation, data rate selection logic, microprocessor interface, and a set of registers. The FDC supports data transfer rates of 250 Kbps, 300 Kbps, 500 Kbps, 1 Mbps and 2 Mbps. It operates in PC/AT mode. The FDC configuration is handled by software and a set of Configuration registers. Status, Data, and Control registers facilitate the interface between the host microprocessor and the disk drive, providing information about the condition and/or state of the FDC. These configuration registers can select the data rate, enable interrupts, drives, and DMA modes, and indicate errors in the data or operation of the FDC/FDD. The controller manages data transfers using a set of data transfer and control commands. These commands are handled in three phases: Command, Execution, and Result. Not all commands utilize all these three phases. The below content is about the FDC device register descriptions. All the registers are for software porting reference. Status Register A (PS/2 mode) ⎯ Base + 0 Bit 7 6 Name INTPEND DRV2_N R/W Default R R 0 Description This bit indicates the state of the interrupt output. 0: a second drive has been installed. 1: a second drive has not been installed. 20 May, 2010 V0.28P F81865 5 4 3 2 1 0 STEP TRK0_N HDSEL INDEX_N WPT_N DIR R R R R R R 0 0 0 This bit indicates the complement of STEP# disk interface output. This bit indicates the state of TRK0# disk interface input. This bit indicates the complement of HDSEL# disk interface output. 0: side 0. 1: side 1. This bit indicates the state of INDEX# disk interface input. This bit indicates the state of WPT# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. This bit indicates the complement of DIR# disk interface output. Status Register A (Model 30 mode) ⎯ Base + 0 Bit 7 6 5 4 3 2 1 Name INTPEND DRQ STEP_FF TRK0 HDSEL_N INDEX WPT R/W Default R R R R R R R 0 0 0 1 Description This bit indicates the state of the interrupt output. This bit indicates the state of the DRQ signal. This bit indicates the complement of latched STEP# disk interface output. This bit indicates the complement of TRK0# disk interface input. This bit indicates the state of HDSEL# disk interface output. 0: side 0. 1: side 1. This bit indicates the complement of INDEX# disk interface input. This bit indicates the complement of WPT# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. This bit indicates the state of DIR# disk interface output. 0: head moves in inward direction. 1: head moves in outward direction. 0 DIR_N R 1 Status Register B (PS/2 Mode) ⎯ Base + 1 Bit 7-6 5 4 3 2 1 0 Name Reserved DR0 WDATA RDATA WGATE MOTEN1 MOTEN0 R/W Default R R R R R R R 11 0 0 0 0 0 0 Description Reserved. Return 11b when read. Drive select 0. This bit reflects the bit0 of Digital Output Register. This bit changes state at every rising edge of WDATA#. This bit changes state at every rising edge of RDATA#. This bit indicates the complement of WGATE# disk interface output. This bit indicates the complement of MOB# disk interface output. Not support in this design. This bit indicates the complement of MOA# disk interface output. Status Register B (Model 30 Mode) ⎯ Base + 1 Bit 7 Name DRV2_N R/W Default R Description 0: a second drive has been installed. 1: a second drive has not been installed. 21 May, 2010 V0.28P F81865 6 5 4 3 2 1 0 DSB_N DSA_N WDATA_FF RDATA_FF WGATE_FF DSD_N DSC_N R R R R R R R 1 1 0 0 0 1 1 This bit indicates the state of DRVB# disk interface output. Not support in this design. This bit indicates the state of DRVA# disk interface output. This bit is latched at the rising edge of WDATA# and is cleared by a read from the Digital Input Register. This bit is latched at the rising edge of RDATA# and is cleared by a read form the Digital Input Register. This bit is latched at the falling edge of WGATE# and is cleared by a read from the Digital Input Register. This bit indicates the complement of DRVD# disk interface output. Not support in this design. This bit indicates the complement of DRVC# disk interface output. Not support in this design. Digital Output Register ⎯ Base + 2 Bit 7 6 5 4 Name MOTEN3 MOTEN2 MOTEN1 MOTEN0 R/W Default R R R/W R/W 0 0 0 0 Description Motor enable 3. Not support in this design. Motor enable 2. Not support in this design. Motor enable 1. Used to control MOB#. MOB# is not support in this design. Motor enable 0. Used to control MOA#. DMA enable. This bit has two mode of operation. PC-AT and Model 30 mode: write 1 will enable DMA and IRQ, write 0 will disable DMA and IRQ. PS/2 mode: This bit is reserved. DMA and IRQ are always enabled in PS/2 mode. Write 0 to this bit will reset the controller. I will remain in reset condition until a 1 is written. This bit indicates the complement of DRVD# disk interface output. Not support in this design. This bit indicates the complement of DRVC# disk interface output. Not support in this design. 3 DAMEN R/W 0 2 1 0 RESET DSD_N DSC_N R R R 0 1 1 Tape Drive Register ⎯ Base + 3 Bit 7-6 5-4 3-2 1-0 Name Reserved TYPEID Reserved TAPESEL R/W Default R R R R/W 00 11 11 0 Description Reserved. Return 00b when read. Reserved in normal function, return 11b when read. If 3 mode FDD function is enabled. These bits indicate the drive type ID. Reserved. Return 11b when read in normal function. Return 00b when read in 3 mode FDD function. These bits assign a logical drive number to be a tape drive. Main Status Register ⎯ Base + 4 Bit 7 Name RQM R/W Default R 0 Description Request for Master indicates that the controller is ready to send or receive data from the uP through the FIFO. 22 May, 2010 V0.28P F81865 6 DIO R 0 Data I/O (direction): 0: the controller is expecting a byte to be written to the Data Register. 1: the controller is expecting a byte to be read from the Data Register. Non DMA Mode: 0: the controller is in DAM mode. 1: the controller is interrupt or software polling mode. This bit indicate that a read or write command is in process. FDD number 3 is in seek or calibration condition. FDD number 3 is not support in this design. FDD number 2 is in seek or calibration condition. FDD number 2 is not support in this design. FDD number 1 is in seek or calibration condition. FDD number 1 is not support in this design. FDD number 0 is in seek or calibration condition. 5 4 3 2 1 0 NON_DMA FDC_BUSY DRV3_BUSY DRV2_BUSY DRV1_BUSY DRV0_BUSY R R R R R R 0 0 0 0 0 0 Data Rate Select Register ⎯ Base + 4 Bit 7 6 5 Name SOFTRST PWRDOWN Reserved R/W Default Description W 0 A 1 written to this bit will software reset the controller. Auto clear after reset. A 1 to this bit will put the controller into low power mode which will turn off the W 0 oscillator and data separator circuits. Return 0 when read. Select the value of write precompensation: 250K-1Mbps 2Mbps 000: default delays default delays 001: 41.67ns 20.8ns 010: 83.34ns 41.17ns 011: 125.00ns 62.5ns 100: 166.67ns 83.3ns 101: 208.33ns 104.2ns W 000 110: 250.00ns 125.00ns 111: 0.00ns (disabled) 0.00ns (disabled) The default value of corresponding data rate: 250Kbps: 125ns 300Kbps: 125ns 500Kbps: 125ns 1Mbps: 41.67ns 2Mbps: 20.8ns Data rate select: MFM FM 00: 500Kbps 250Kbps 01: 300Kbps 150Kbps 10: 250Kbps 125Kbps 11: 1Mbps illegal 4-2 PRECOMP 1-0 DRATE W 10 Data (FIFO) Register ⎯ Base + 5 Bit Name R/W Default Description The FIFO is used to transfer all commands, data and status between controller and the system. The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. The FIFO is default disabled and could be enabled via the CONFIGURE command. 7-0 DATA R/W 00h 23 May, 2010 V0.28P F81865 Status Registers 0 Bit Name R/W Default Description Interrupt code : 00: Normal termination of command. 01: Abnormal termination of command. 10: Invalid command. 11: Abnormal termination caused by poling. Seek end. Set when a SEEK or RECALIBRATE or a READ or WRITE with implied seek command is completed. Equipment check. 0: No error 1: When a fault signal is received form the FDD or the TRK0# signal fails to occur after 77 step pulses. Not ready. 0: Drive is ready 1: Drive is not ready. Head address. The current head address. Drive select. 00: Drive A selected. 01: Drive B selected. 10: Drive C selected. 11: Drive D selected. 7-6 IC R - 5 SE R - 4 EC R - 3 NR R - 2 HD R - 1-0 DS R - Status Registers 1 Bit 7 6 Name EN DE R/W Default R R Description End of Track. Set when the FDC tries to access a sector beyond the final sector of a cylinder. Data Error. The FDC detect a CRC error in either the ID field or the data field of a sector. Overrun/Underrun. Set when the FDC is not serviced by the host system within a certain time interval during data transfer. Unused. This bit is always “0” No Data. Set when the following conditions occurred: 1. The specified sector is not found during any read command. 2. The ID field cannot be read without errors during a READ ID command. 3. The proper sector sequence cannot be found during a READ TRACK command. No Writable Set when WPT# is active during execution of write commands. 4 3 OR Reserved R - - 2 ND R - 1 NW R - 24 May, 2010 V0.28P F81865 0 MA R Missing Address Mark. Set when the following conditions occurred: 1. Cannot detect an ID address mark at the specified track after encountering the index pulse form the INDEX# pin twice. 2. Cannot detect a data address mark or a deleted data address mark on the specified track. Status Registers 2 Bit 7 Name Reserved R/W Default Unused. This bit is always “0”. Control Mark. Set when following conditions occurred: 1. Encounters a deleted data address mark during a READ DATA command. 2. Encounters a data address mark during a READ DELETED DATA command. Data Error in Data Field. The FDC detects a CRC error in the data field. Wrong Cylinder. Set when the track address from the sector ID field is different from the track address maintained inside the FDC. Scan Equal. Set if the equal condition is satisfied during execution of the SCAN command. Scan Not Satisfied. Set when the FDC cannot find a sector on the track which meets the desired condition during any scan command. Bad Cylinder. The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FFh which indicates a bad track. Missing Data Address Mark. Set when the FDC cannot detect a data address mark or a deleted data address mark. Description 6 CM R - 5 DD R - 4 WC R - 3 SE R - 2 SN R - 1 BC R - 0 MD R - Status Registers 3 Bit 7 6 5 4 3 2 1 0 Name Reserved WP Reserved T0 Reserved. HD DS1 DS0 R/W Default R R R R R R R Unused. This bit is always “0”. Write Protect. Indicates the status of WPT# pin. Unused. This bit is always “1”. Track 0. Indicates the status of the TRK0# pin. Unused. This bit is always “1”. Head Address. Indicates the status of the HDSEL# pin. Drive Select. These two bits indicate the DS1, DS0 bits in the command phase. Description 25 May, 2010 V0.28P F81865 Digital Input Register (PC-AT Mode) ⎯ Base + 7 Bit 7 6-0 Name DSKCHG Reserved R/W Default R R Reserved. Description This bit indicates the complement of DSKCHG# disk interface input. Digital Input Register (PS/2 Mode) ⎯ Base + 7 Bit 7 6-3 2-1 0 Name DSKCHG Reserved DRATE HIGHDEN_N R/W Default R R R 10 1 Reserved. These bits indicate the status of the DRATE programmed through the Data Rate Select Register or Configuration Control Register. 0: 1Mbps or 500Kbps data rate is chosen. 1: 300Kbps or 250Kbps data rate is chosen. Description This bit indicates the complement of DSKCHG# disk interface input. Digital Input Register (Model 30 Mode) ⎯ Base + 7 Bit 7 6-4 3 2 1-0 Name DSKCHG_N Reserved DMAEN NOPRE DRATE R/W Default R R R R 0 0 10 Description This bit indicates the state of DSKCHG# disk interface input. Reserved. This bit reflects the DMA bit in Digital Output Register. This bit reflects the NOPRE bit in Configuration Control Register. These bits indicate the status of DRATE programmed through the Data Rate Select Register or Configuration Control Register. Configuration Control Register (PC-AT and PS/2 Mode) ⎯ Base + 7 Bit 7-2 1-0 Name Reserved DRATE R/W Default W 10 Reserved. These bit determine the data rate of the floppy controller. See DRATE bits in Data Rate Select Register. Description Configuration Control Register (Model 30 Mode) ⎯ Base + 7 Bit 7-3 2 Name Reserved NOPRE R/W Default W 0 Reserved. This bit could be programmed through Configuration Control Register and be read through the bit 2 in Digital Input Register in Model 30 Mode. But it has no functionality. These bits determine the data rate of the floppy controller. See DRATE bits in Data Rate Select Register. Description 1-0 DRATE W 10 26 May, 2010 V0.28P F81865 FDC Commands Terminology: C D DIR Cylinder Number 0 -256 Data Pattern Step Direction 0: step out 1: step in DS0 Drive Select 0 DS1 Drive Select 1 DTL Data Length EC Enable Count EOT End of Track EFIFO Enable FIFO 0: FIFO is enabled. 1: FIFO is disabled. EIS Enable Implied Seek FIFOTHR FIFO Threshold GAP Alters Gap Length GPL Gap Length H/HDS Head Address HLT Head Load Time HUT Head Unload Time LOCK Lock EFIFO, FIFOTHR, PTRTRK bits. Prevent these bits from being affected by software reset. MFM MFM or FM mode 0: FM 1: MFM MT Multi-Track N Sector Size Code. All values up to 07h are allowable. 00: 128 bytes 01: 256 bytes .. .. 07 16 Kbytes NCN New Cylinder Number ND Non-DMA Mode OW Overwritten PCN Present Cylinder Number POLL Polling disable 0: polling is enabled. 1: polling is disabled. PRETRK Precompensation Start Track Number R Sector address RCN Relative Cylinder Number SC Sector per Cylinder SK Skip deleted data address mark SRT Step Rate Time ST0 Status Register 0 ST1 Status Register 1 ST2 Status Register 2 ST3 Status Register 3 WGATE Write Gate alters timing of WE. 27 May, 2010 V0.28P F81865 Read Data Phase Command R/W W W W W W W W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. Status information after command execution. D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 D3 0 0 D2 1 HDS D1 1 DS1 D0 0 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------Data transfer between the FDD and system Sector ID information prior to command execution Read Deleted Data Phase R/W Command W W W W W W W W W Execution Result R R R D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 D3 1 0 D2 1 HDS D1 0 DS1 D0 0 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------Data transfer between the FDD and system ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 -------------------------Status information after command execution. Sector ID information prior to command execution 28 May, 2010 V0.28P F81865 R R R R ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. Read A Track Phase R/W Command W W W W W W W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 0 HDS D1 1 DS1 D0 0 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------Data transfer between the FDD and system. FDD reads contents of all cylinders from index hole to EOT. Sector ID information prior to command execution Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. Status information after command execution. Read ID Phase Command R/W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 1 DS1 D0 0 DS0 The first correct ID information on the cylinder is stored in Data Register. R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 -------------------------Status information after command execution. Remark Command code Execution Result 29 May, 2010 V0.28P F81865 R R R R ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Disk status after the command has been completed. Verify Phase Command R/W W W W W W W W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------Sector ID information after command execution. D7 MT EC D6 MFM 0 D5 SK 0 D4 1 0 D3 0 0 D2 1 HDS D1 1 DS1 D0 0 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL --------------------------------------------------- DTL/SC -----------------------No data transfer Status information after command execution. Sector ID information prior to command execution Version Phase Command Result R/W W R D7 0 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 0 Remark Command code Enhanced controller Write Data Phase Command R/W W W W W D7 MT 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 1 HDS D1 0 DS1 D0 1 DS0 Sector ID information prior to command Remark Command code ----------------------------- C ------------------------------------------------------- H --------------------------- 30 May, 2010 V0.28P F81865 W W W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------Data transfer between the FDD and system. Status information after command execution. execution Sector ID information after command execution. Write Deleted Data Phase Command R/W W W W W W W W W W Execution Result R R R R R R R ---------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 ------------------------------------------------------ C ------------------------------------------------------- H ------------------------------------------------------- R ------------------------------------------------------- N --------------------------D7 MT 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 0 DS1 D0 1 DS0 Remark Command code ----------------------------- C ------------------------------------------------------- H ------------------------------------------------------- R -------------------------------------------------------- N ------------------------------------------------------ EOT ----------------------------------------------------- GPL ----------------------------------------------------- DTL -------------------------Data transfer between the FDD and system. Status information after command execution. Sector ID information prior to command execution Sector ID information after command execution. 31 May, 2010 V0.28P F81865 Format A Track Phase Command R/W W W W W W W Execution for each sector ( repeat ) Result D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 0 DS1 D0 1 DS0 Bytes/Sector Sectors/Cylinder Gap 3 Length Data Pattern Remark Command code ------------------------------ N ------------------------------------------------------ SC ----------------------------------------------------- GPL ------------------------------------------------------ D -------------------------------------------------------- C --------------------------- W W W R R R R R R R ------------------------------ H -------------------------------------------------------- R ------------------------------------------------------- N ----------------------------------------------------- ST0 ------------------------------------------------------ ST1 ----------------------------------------------------- ST2 -------------------------------------------------- Undefined ---------------------------------------------- Undefined ----------------------------------------------- Undefined ----------------------------------------------- Undefined ---------------------- Input sector parameter. Status information after command execution. Recalibrate Phase Command R/W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 0 D1 1 DS1 D0 1 DS0 Head retracted to track 0 Remark Command code Sense Interrupt Status Phase Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0 Remark Command code ---------------------------- ST0 ----------------------------------------------------- PCN -------------------------- Specify Phase Command R/W W W W D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 Remark Command code |------------------ SRT -------------------| |------------------ HUT -------------------| ND |------------------------------------- SRT ---------------------------------------| 32 May, 2010 V0.28P F81865 Seek Phase Command R/W W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 Remark Command code ---------------------------- NCN -------------------------Head positioned over proper cylinder on diskette Configure Phase Command R/W W W W W Execution D7 0 0 0 D6 0 0 EIS D5 0 0 EFIFO D4 1 0 POLL D3 0 0 D2 0 HDS D1 1 DS1 D0 1 DS0 Remark Command code |---------------- FIFOTHR ---------------| ---------------------------- PRETRK -------------------------Internal registers written Relative Seek Phase Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 Remark Command code ---------------------------- RCN -------------------------- Perpendicular Mode Phase Command R/W W W D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 0 D0 D1 1 GAP D0 0 WGATE Remark Command code Lock Phase Command Result R/W W R D7 LOCK 0 D6 0 0 D5 0 0 D4 1 LOCK D3 0 0 D2 1 0 D1 0 0 D0 0 0 Remark Command code Dumpreg Phase Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 Remark Command code -------------------------- PCN ( Drive 0 ) ------------------------------------------------- PCN ( Drive 0 ) ------------------------ 33 May, 2010 V0.28P F81865 R R R R R R R R LOCK 0 0 EIS -------------------------- PCN ( Drive 0 ) ------------------------------------------------- PCN ( Drive 0 ) -----------------------|------------------ SRT -------------------| |------------------ HUT -------------------| ND |------------------------------------- SRT ---------------------------------------| -------------------------- SC/EOT -----------------------D3 EFIFO D2 POLL D1 D0 GAP WGATE |---------------- FIFOTHR ---------------| ---------------------------- PRETRK -------------------------- Sense Drive Status Phase Command R/W W W Result R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 HDS D1 0 DS1 D0 0 DS0 Status information abut disk drive Remark Command code ---------------------------- ST3 -------------------------- Invalid Phase Command Result R/W W R D7 D6 D5 D4 D3 D2 D1 D0 Remark FDC goes to standby state. ST0 = 80h ---------------------------- Invalid Codes ----------------------------------------------------- ST0-------------------------- 7.3. UART The F81865 provides up to 6 UART ports and supports IRQ sharing for system application. The UARTs are used to convert data between parallel format and serial format. They convert parallel data into serial format on transmission and serial format into parallel data on receiver side. The serial format is formed by one start bit, followed by five to eight data bits, a parity bit if programmed and one ( 1.5 or 2 ) stop bits. The UARTs include complete modem control capability and an interrupt system that may be software trailed to the computing time required to handle the communication link. They have FIFO mode to reduce the number of interrupts presented to the host. Both receiver and transmitter have a 16-byte FIFO. The below content is about the UARTs device register descriptions. All the registers are for software porting reference. Receiver Buffer Register ⎯ Base + 0 Bit 7-0 Name RBR R/W Default R 00h The data received. Read only when LCR[7] is 0 Description 34 May, 2010 V0.28P F81865 Transmitter Holding Register ⎯ Base + 0 Bit 7-0 Name THR R/W Default W 00h Data to be transmitted. Write only when LCR[7] is 0 Description Divisor Latch (LSB) ⎯ Base + 0 Bit 7-0 Name DLL R/W Default R/W 01h Baud generator divisor low byte. Access only when LCR[7] is 1. Description Divisor Latch (MSB) ⎯ Base + 1 Bit 7-0 Name DLM R/W Default R/W 00h Description Baud generator divisor high byte. Access only when LCR[7] is 1. Interrupt Enable Register (IER) ⎯ Base + 1 Bit 7-5 Name Reserved R/W Default Reserved. This bit is used only in 9-bit mode and always returns “0” when 9-bit mode is disabled. 0: The receiver could receive data byte. 1: The receiver could only receive address byte and issue an interrupt when the address is received. Enable Modem Status Interrupt. Access only when LCR[7] is 0. Enable Line Status Error Interrupt. Access only when LCR[7] is 0. Enable Transmitter Holding Register Empty Interrupt. Access only when LCR[7] is 0. Enable Received Data Available Interrupt. Access only when LCR[7] is 0. Description 4 SM2 R/WC 0 3 2 1 0 EDSSI ELSI ETBFI ERBFI R/W R/W R/W R/W 0 0 0 0 Interrupt Identification Register (IIR) ⎯ Base + 2 Bit 7 6 5-4 Name FIFO_EN FIFO_EN Reserved R/W Default R R 0 0 0: FIFO is disabled 1: FIFO is enabled. 0: FIFO is disabled 1: FIFO is enabled. Reserved. 000: Interrupt is caused by Modem Status 001: Interrupt is caused by Transmitter Holding Register Empty 010: Interrupt is caused by Received Data Available. 110: Interrupt is caused by Character Timeout 011: Interrupt is caused by Line Status. 1: Interrupt is not pending. 0: Interrupt is pending. Description 3-1 IRQ_ID R 00 0 IRQ_PENDN R 1 35 May, 2010 V0.28P F81865 FIFO Control Register ⎯ Base + 2 Bit Name R/W Default Description 00: Receiver FIFO trigger level is 1. 01: Receiver FIFO trigger level is 4. 10: Receiver FIFO trigger level is 8. 11: Receiver FIFO trigger level is 14. Reserved. Reset the transmitter FIFO. Reset the receiver FIFO. 0: Disable FIFO. 1: Enable FIFO. 7-6 RCV_TRIG W 00 5-3 2 1 0 Reserved CLRTX CLRRX FIFO_EN R R R 0 0 0 Line Control Register (LCR) ⎯ Base + 3 Bit 7 6 5 4 3 Name DLAB SETBRK STKPAR EPS PEN R/W Default R/W R/W R/W R/W R/W 0 0 0 0 0 Description 0: Divisor Latch can’t be accessed. 1: Divisor Latch can be accessed via Base and Base+1. 0: Transmitter is in normal condition. 1: Transmit a break condition. XX0: Parity Bit is disable 001: Parity Bit is odd. 011: Parity Bit is even 101: Parity Bit is logic 1 111: Parity Bit is logic 0 0: Stop bit is one bit 1: When word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 00: Word length is 5 bit 01: Word length is 6 bit 10: Word length is 7 bit 11: Word length is 8 bit 2 STB R/W 0 1-0 WLS R/W 00 MODEM Control Register (MCR) ⎯ Base + 4 Bit 7-5 4 3 2 1 0 Name Reserved LOOP OUT2 OUT1 RTS DTR R/W Default R/W R/W R/W R/W R/W 0 0 0 0 0 Reserved. 0: UART in normal condition. 1: UART is internal loop back 0: All interrupt is disabled. 1: Interrupt is enabled (disabled) by IER. Read from MSR[6] while in loop back mode 0: RTS# is forced to logic 1 1: RTS# is forced to logic 0 0: DTR# is forced to logic 1 1: DTR# is forced to logic 0 Description Line Status Register (LSR) ⎯ Base + 5 Bit 7 Name RCR_ERR R/W Default R 0 Description 0: No error in the FIFO when FIFO is enabled 1: Error in the FIFO when FIFO is enabled. 36 May, 2010 V0.28P F81865 6 5 4 3 2 1 0 TEMT THRE BI FE PE OE DR R R R R R R R 1 1 0 0 0 0 0 0: Transmitter is in transmitting. 1: Transmitter is empty. 0: Transmitter Holding Register is not empty. 1: Transmitter Holding Register is empty. 0: No break condition detected. 1: A break condition is detected. 0: Data received has no frame error. 1: Data received has frame error. 0: Data received has no parity error. 1: Data received has parity error. 0: No overrun condition occurred. 1: An overrun condition occurred. 0: No data is ready for read. 1: Data is received. MODEM Status Register (MSR) ⎯ Base + 6 Bit 7 6 5 4 3 2 1 0 Name DCD RI DSR CTS DDCD TERI DDSR DCTS R/W Default R R R R R R R R 0 0 1 1 Description Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2 in MCR. Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in MCR Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in MCR Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in MCR 0: No state changed at DCD#. 1: State changed at DCD#. 0: No Trailing edge at RI#. 1: A low to high transition at RI#. 0: No state changed at DSR#. 1: State changed at DSR#. 0: No state changed at CTS#. 1: State changed at CTS#. Scratch Register ⎯ Base + 7 Bit 7-0 Name SCR R/W Default R/W 00h Scratch register. Description 7.4. Parallel Port The parallel port in F81865 supports an IBM XT/AT compatible parallel port ( SPP ), bi-directional parallel port ( BPP ), Enhanced Parallel Port ( EPP ), Extended Capabilities Parallel Port ( ECP ) mode. Refer to the configuration registers for more information on selecting the mode of operation. The below content is about the Parallel Port device register descriptions. All the registers are for software porting reference. 37 May, 2010 V0.28P F81865 Parallel Port Data Register ⎯ Base + 0 Bit 7-0 Name DATA R/W Default R/W 00h Description The output data to drive the parallel port data lines. ECP Address FIFO Register ⎯ Base + 0 Bit Name R/W Default Description Access only in ECP Parallel Port Mode and the ECP_MODE programmed in the Extended Control Register is 011. The data written to this register is placed in the FIFO and tagged as an Address/RLE. It is auto transmitted by the hardware. The operation is only defined for forward direction. It divide into two parts : Bit 7 : 0: bits 6-0 are run length, indicating how many times the next byte to appear (0 = 1time, 1 = 2times, 2 = 3times and so on). 1: bits 6-0 are ECP address. Bit 6-0 : Address or RLE depends on bit 7. Device Status Register ⎯ Base + 1 Bit 7 6 5 4 3 2-1 Name BUSY_N ACK_N PERROR SELECT ERR_N Reserved R/W Default R R R R R R 11 Description Inverted version of parallel port signal BUSY. Version of parallel port signal ACK#. Version of parallel port signal PE. Version of parallel port signal SLCT. Version of parallel port signal ERR#. Reserved. Return 11b when read. This bit is valid only in EPP mode. Return 1 when in other modes. It indicates that a 10uS time out has occurred on the EPP bus. 0: no time out error. 1: time out error occurred, write 1 to clear. 7-0 ECP_AFIFO R/W 00h 0 TMOUT R - Device Control Register ⎯ Base + 2 Bit 7-6 5 4 3 2 1 Name Reserved DIR ACKIRQ_EN SLIN INIT_N AFD R/W Default R/W R/W R/W R/W R/W 11 0 0 0 0 0 Description Reserved. Return 11b when read. 0: the parallel port is in output mode. 1: the parallel port is in input mode. It is auto reset to 1 when in SPP mode. Enable an interrupt at the rising edge of ACK#. Inverted and then drives the parallel port signal SLIN#. When read, the status of inverted SLIN# is return. Drives the parallel port signal INIT#. When read, the status of INIT# is return. Inverted and then drives the parallel port signal AFD#. When read, the status of inverted AFD# is return. 38 May, 2010 V0.28P F81865 0 STB R/W 0 Inverted and then drives the parallel port signal STB#. When read, the status of inverted STB# is return. EPP Address Register ⎯ Base + 3 Bit Name R/W Default Description Write this register will cause the hardware to auto transmit the written data to the device with the EPP Address Write protocol. Read this register will cause the hardware to auto receive data from the device by with the EPP Address Read protocol. 7-0 EPP_ADDR R/W 00h EPP Data Register ⎯ Base + 4 – Base + 7 Bit Name R/W Default Description Write this register will cause the hardware to auto transmit the written data to the device with the EPP Data Write protocol. Read this register will cause the hardware to auto receive data from the device by with the EPP Data Read protocol. 7-0 EPP_DATA R/W 00h Parallel Port Data FIFO ⎯ Base + 400h Bit Name R/W Default Description Data written to this FIFO is auto transmitted by the hardware to the device by using standard parallel port protocol. It is only valid in ECP and the ECP_MODE is 010b.The operation is only for forward direction. 7-0 C_FIFO R/W 00h ECP Data FIFO ⎯ Base + 400h Bit Name R/W Default Description Data written to this FIFO when DIR is 0 is auto transmitted by the hardware to the device by using ECP parallel port protocol. Data is auto read from device into the FIFO when DIR is 1 by the hardware by using ECP parallel port protocol. Read the FIFO will return the content to the system. It is only valid in ECP and the ECP_MODE is 011b. 7-0 ECP_DFIFO R/W 00h ECP Test FIFO ⎯ Base + 400h Bit Name R/W Default Description Data may be read, written from system to the FIFO in any Direction. But no hardware handshake occurred on the parallel port lines. It could be used to test the empty, full and threshold of the FIFO. It is only valid in ECP and the ECP_MODE is 110b. 7-0 T_FIFO R/W 00h ECP Configuration Register A ⎯ Base + 400h Bit 7 Name IRQ_MODE R/W Default R 0 Description 0: interrupt is ISA pulse. 1: interrupt is ISA level. Only valid in ECP and ECP_MODE is 111b. 39 May, 2010 V0.28P F81865 6-4 IMPID R 001 000: the design is 16-bit implementation. 001: the design is 8-bit implementation (default). 010: the design is 32-bit implementation. 011-111: Reserved. Only valid in ECP and ECP_MODE is 111b. Reserved. 0: when transmitting there is 1 byte waiting in the transceiver that does not affect the FIFO full condition. 1: when transmitting the state of the full bit includes the byte being transmitted. Only valid in ECP and ECP_MODE is 111b. Return 00 when read. Only valid in ECP and ECP_MODE is 111b. 3 Reserved - - 2 BYTETRAN_N R 1 1-0 Reserved R 00 ECP Configuration Register B ⎯ Base + 401h Bit 7 Name COMP R/W Default R 0 Description 0: only send uncompressed data. 1: compress data before sending. Only valid in ECP and ECP_MODE is 111b. Reserved. Return 1 when read. Only valid in ECP and ECP_MODE is 111b. 000: the interrupt selected with jumper. 001: select IRQ 7 (default). 010: select IRQ 9. 011: select IRQ 10. 100: select IRQ 11 101: select IRQ 14. 110: select IRQ 15. 111: select IRQ 5. Only valid in ECP and ECP_MODE is 111b. Return the DMA channel of ECP parallel port. Only valid in ECP and ECP_MODE is 111b. 6 Reserved R 1 5-3 ECP_IRQ_CH R 001 2-0 ECP_DMA_CH R 011 Extended Control Register ⎯ Base + 402h Bit Name R/W Default Description 000: SPP Mode. 001: PS/2 Parallel Port Mode. 010: Parallel Port Data FIFO Mode. 011: ECP Parallel Port Mode. 100: EPP Mode. 101: Reserved. 110: Test Mode. 111: Configuration Mode. Only valid in ECP. 0: disable the interrupt generated on the falling edge of ERR#. 1: enable the interrupt generated on the falling edge of ERR#. 0: disable DMA. 1: enable DMA. DMA starts when SERVICEINTR is 0. 7-5 ECP_MODE R/W 000 4 3 ERRINTR_EN DAMEN R/W R/W 0 0 40 May, 2010 V0.28P F81865 2 SERVICEINTR R/W 1 0: enable the following case of interrupt. DMAEN = 1: DMA mode. DMAEN = 0, DIR = 0: set to 1 whenever there are writeIntrThreshold or more bytes are free in the FIFO. DMAEN = 0, DIR = 0: set to 1 whenever there are readIntrThreshold or more bytes are valid to be read in the FIFO. 0: The FIFO has at least 1 free byte. 1: The FIFO is completely full. 0: The FIFO contains at least 1 byte. 1: The FIFO is completely empty. 1 0 FIFOFULL FIFOEMPTY R R 0 0 7.5. Keyboard Controller The KBC circuit provides the functions included a keyboard and/or a PS/2 mouse, and can be used with IBM-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The controller will assert an interrupt to the system when data are placed in its output buffer. Output Buffer The output buffer is an 8-bit read-only register at I/O address 60h. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. Input Buffer The input buffer is an 8-bit write-only register at I/O address 60h or 64h. Writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. Data written to I/O address 60h is sent to keyboard through the controller's input buffer only if the input buffer full bit in the status register is “0”. Status Register The status register is an 8-bit read-only register at I/O address 64h that holds information about the status of the keyboard controller and interface. It may be read at any time. BIT 0 1 BIT FUNCTION Output Buffer Full Input Buffer Full 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller (KCCB). It defaults to 0 after a power-on reset. DESCRIPTION 2 System Flag 41 May, 2010 V0.28P F81865 3 4 5 6 7 Command/Data Inhibit Switch Mouse Output Buffer General Purpose Time-out Parity Error 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Muse output buffer empty 1: Mouse output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) Commands COMMAND 20h 60h Read Command Byte Write Command Byte BIT 0 1 2 3 4 5 6 7 A7h A8h A9h DESCRIPTION Enable Keyboard Interrupt Enable Mouse Interrupt System flag Reserve Disable Keyboard Interface Disable Mouse interface IBM keyboard Translate Mode Reserve FUNCTION Disable Auxiliary Device Interface Enable Auxiliary Device Interface Auxiliary Interface Test 8’h00: indicate Auxiliary interface is ok. 8’h01: indicate Auxiliary clock is low. 8’h02: indicate Auxiliary clock is high 8’h03: indicate Auxiliary data is low 8’h04: indicate Auxiliary data is high AAh ABh Self-test Return 55h if self test succeeds keyboard Interface Test 8’h00: indicate keyboard interface is ok. 8’h01: indicate keyboard clock is low. 8’h02: indicate keyboard clock is high 8’h03: indicate keyboard data is low 8’h04: indicate keyboard data is high ADh Disable Keyboard Interface 42 May, 2010 V0.28P F81865 AEh C0h C1h C2h CAh CBh D0h D1h D2h D3h D4h FEh Enable Keyboard Interface Read Input Port(P1) and send data to the system Continuously puts the lower four bits of Port1 into STATUS register Continuously puts the upper four bits of Port1 into STATUS register Read the data written by CBh command. Written a scratch data. This byte could be read by CAh command. Send Port2 value to the system Only set/reset GateA20 line based on the system data bit 1 Send data back to the system as if it came from Keyboard Send data back to the system as if it came from Muse Output next received byte of data from system to Mouse Low pulse on KBRST# about 6μS KBC Command Description PS/2 wakeup function The KBC supports keyboard and mouse wakeup function. KBC will assert PME or PSOUT# signal. Those wakeup conditions are controlled by configuration register. 7.6. Hardware Monitor 7.6.1 General Description Voltage For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is 2.04V. Therefore the voltage under 2.04V (ex:1.5V) can be directly connected to these analog inputs. The voltage higher than 2.04V should be reduced by a factor with external resistors so as to obtain the input range. Only 3Vcc is an exception for it is main power of the F81865. Therefore 3Vcc can directly connect to this chip’s power pin and need no external resistors. There are two functions in this pin with 3.3V. The first function is to supply internal analog power of the F81865 and the second function is that voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The internal serial resistors are two 150K ohm, so that the internal reduced voltage is half of +3.3V (See figure 7-1). There are four voltage inputs in the F81865 and the voltage divided formula is shown as follows: VIN = V+12 V × R2 R1 + R 2 where V+12V is the analog input voltage, for example. If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which is within the tolerance. As for application circuit, it can be refer to the figure shown as follows. 43 May, 2010 V0.28P F81865 3Vcc Voltage Inputs VIN (< 2.04V) VIN (> 2.04V) (directly connect to the chip) (directly connect to the chip) R 1 150K VIN3.3 150K R2 8-bit ADC with 8 mV LSB VREF R 10K, 1% D+ Typical BJT Connection 2N3906 R Typical Thermister THM Connection 10K, 25 C D- Fig 7-1 PME# interrupt for voltage is shown as figure 7-2. Voltage exceeding or going below high limit will cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register. (pulse mode) * * *Interrupt Reset when Interrupt Status Registers are written 1 Voltage PME# Mode Fig 7-2 Temperature Sensor The F81865 monitors two remote temperature sensors. These sensors can be measured from -40°C to 127°C (for thermal diode) & 0°C to 127°C (for thermistor). More detail please refer to the register description. Remote-sensor transistor manufacturers Manufacturer Panasonic Philips Model Number 2SB0709 2N3906 PMBT3906 (1) Monitor Temperature from “thermistor” The F81865 can connect two thermistors to measure environment temperature or remote 44 May, 2010 V0.28P F81865 temperature. The specification of thermistor should be considered to (1) β value is 3435K (2) resistor value is 10K ohm at 25°C. In the Figure 7-1, the thermistor is connected by a serial resistor with 10K ohm, then connected to VREF. (2) Monitor Temperature from “thermal diode” Also, if the CPU, GPU or external circuits provide thermal diode for temperature measurement, the F81865 is capable to these situations. The build-in reference table is for PNP 2N3906 transistor. In the Figure 7-1, the transistor is directly connected into temperature pins. ADC Noise Filtering The ADC is integrating type with inherently good noise rejection. Micro-power operation places constraints on high-frequency noise rejection; therefore, careful PCB board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environment. High frequency EMI is best filtered at D+ and D- with an external 2200pF or 3300pF capacitor. Too high capacitance may introduce errors due to the rise time of the switched current source. Nearly all noise sources tested cause the ADC measurement to be higher than the actual temperature, depending on the frequency and amplitude. Over Temperature Signal (OVT#) OVT# alert for temperature is shown as figure 7-3. When monitored temperature exceeds the over-temperature threshold value, OVT# will be asserted until the temperature goes below the hysteresis temperature. To T HYST OVT# (Level mode) OVT# (SMI mode) Fig 7-3 Temperature PME# PME# interrupt for temperature is shown as figure 7-4. Temperature exceeding high limit or going below hysteresis will cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register. 45 May, 2010 V0.28P F81865 To T HYST (pulse mode) * * *Interrupt Reset when Interrupt Status Registers are written 1 Fig 7-4 Fan Fan speed count Inputs are provided by the signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage cannot be over 5V. If the input signals from the tachometer outputs are over the 5V, the external trimming circuit should be added to reduce the voltage to obtain the input specification. Determine the fan counter according to: Count = 1.5 × 10 6 RPM In other words, the fan speed counter (12 bit resolution) has been read from register, the fan speed can be evaluated by the following equation. RPM = 1.5 × 10 6 Count As for fan, it would be best to use 2 pulses (4 phases fan) tachometer output per round. So the parameter “Count” under 5 bit filter is 4096~64 and RPM is 366~23438 based on the above equation. If using 8 phases fan, RPM would be from 183~11719. Fan speed control The F81865 provides 2 fan speed control methods: 1. DAC FAN CONTROL 2. PWM DUTY CYCLE 46 May, 2010 V0.28P F81865 DAC Fan Control The range of DC output is 0~VCC, controlled by 8-bit register. 1 LSB is about 0.013V (VCC=3.3V). The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN OPERATION VOLTAGE, 12V. The output voltage will be given as followed: Output_vol tage (V) = VCC × Programmed 8bit Register Value 256 And the suggested application circuit for linear fan control would be: +12V R 4.7K 8 3 DC OUTPUT VOLTAGE 2 U1A 1 LM358 PMOS Q1 D1 1N4148 R 4.7K JP1 + 4 R 10K C 47u 3 2 1 CON3 R C 0.1u 27K R 10K FANIN MONITOR R 3.6K Fig 7-5 PWM duty Fan Control The duty cycle of PWM can be programmed by a 8-bit register. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Duty_cycle(%) = Programmed 8bit Register Value × 100% 255 47 May, 2010 V0.28P F81865 +12V R1 R2 G PNP Transistor D NMOS S C + FAN Fig 7-6 Fan speed control mechanism There are some modes to control fan speed and they are 1.Manual mode, 2.Stage auto mode, 3. Linear auto mode. More detail, please refer the description of registers. Manual mode For manual mode, it generally acts as software fan speed control. Stage auto mode At this mode, the F81865 provides automatic fan speed control related to temperature variation of CPU/GPU or the system. The F81865 can provide four temperature boundaries and five intervals, and each interval has its related fan speed count. All these values should be set by BIOS first. Take figure 7-7 as example. When temperature boundaries are set as 45, 55, 65, and 75°C and there are five intervals (each interval is 10° C). The related desired fan speed counts for each interval are 0500h, 0400h, 0300h, 0200h and 0100h. When the temperature is within 55~65°C, the fan speed count 300h will be load into FAN EXPECT COUNT that define in registers. Then, the F81865 will adjust PWMOUT duty-cycle to meet the expected value. It can be said that the fan will be turned on with a specific speed set by BIOS and automatically controlled with the temperature variation. The F81865 will take charge of all the fan speed control and need no for software support. Desired Counts 75 Degree C 65 Degree C 0300h 55 Degree C 0400h 45 Degree C 0500h 0100h 0200h Figure 7-7 There are some examples as below: 48 May, 2010 V0.28P F81865 A. Stage auto mode (PWM Duty) Set temperature as 60°C, 50°C, 40°C, 30°C and Duty as 100%, 90%, 80%, 70%, 60% PWM duty 60 Degree C 50 Degree C hysteresis 47 Degree C 100% 90% 80% 70% 0xFF 0xE5 0xCC 0xB2 0x99 40 Degree C 30 Degree C Temp. Fan Speed 60% a b c d a. Once temp. is under 30°C, the lowest fan speed keeps 60% PWM duty b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 60% to 90% PWM duty and increase with temp. level. c. Once temp. keeps in 55°C, fan speed keeps in 90% PWM duty If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed reduces to 80% PWM duty and stays there. B. Stage auto mode (RPM%) Set temperature as 60°C, 50°C, 40°C, 30°C and assume the Full Speed is 6000 RPM, set 90% of full speed RPM(5400 RPM), 80%(4800 RPM), 70%(4200 RPM), 60%(3600 RPM) of full speed RPM 60 Degree C 50 Degree C hysteresis 47 Degree C 40 Degree C 70%(4200RPM) 30 Degree C Temp. Fan Speed 60%(3600RPM) a b c d 6000RPM 90%(5400RPM) 80%(4800RPM) a. Once temp. is under 30°C, the lowest fan speed keeps 60% of full speed (3600RPM). b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 3600RPM to 5400RPM and increase with temp. level. c. Once temp. keeps in 55°C, fan speed keeps in 90% of full speed (5400RPM) d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed reduces to 4800RPM and stays there. . 49 May, 2010 V0.28P F81865 Linear auto mode Furthermore, F81865 also supports linear auto mode. Below two examples describe this mode. More detail, please refer to the register description. A. Linear auto mode (PWM Duty I) Set temperature as 70°C, 60°C, 50°C, 40°C and Duty as 100%, 70%, 60%, 50%, 40% PWM duty 70 Degree C hysteresis 65 Degree C 60 Degree C 60% 50 Degree C 50% 40 Degree C Temp. Fan Speed 40% a b c d 100% 70% a. Once temp. is under 40°C, the lowest fan speed keeps 40% PWM duty b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% PWM duty and linearly increase with temp. variation. The temp.-fan speed monitoring and flash interval is 1sec. c. Once temp. goes over 70°C, fan speed will directly increase to 100% PWM duty (full speed) d. If set the hysteresis as 5°C(default is 4°C), once temp reduces under 65°C (not 70°C), fan speed reduces from 100% PWM duty and decrease linearly with temp.. B. Linear auto mode (RPM%) Set temperature as 70°C, 60°C, 50°C, 40°C and if full speed is 6000RPM, setting 100%, 70%, 60%, 50%, 40% of full speed. 6000RPM 70 Degree C hysteresis 65 Degree C 60 Degree C 60%(3600RPM) 50 Degree C 50%(3000RPM) 40 Degree C 40%(2400RPM) Temp. Fan Speed a b c d 70%(4200RPM) a. Once temp. is under 40°C, the lowest fan speed keeps 40% of full speed (2400RPM) b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% of full speed and almost linearly increase with temp. variation. The temp.-fan speed monitoring and flash interval is 1sec. 50 May, 2010 V0.28P F81865 c. Once temp. goes over 70°C, fan speed will directly increase to full speed 6000RPM. d. If set the hysteresis as 5°C, once temp reduces under 65°C (not 70°C), fan speed reduces from full speed and decrease linearly with temp.. PWMOUT Duty-cycle operating process In both “Manual RPM” and “Temperature RPM” modes, the F81865 adjust PWMOUT duty-cycle according to current fan count and expected fan count. It will operate as follows: 1. 2. 3. When expected count is 0xFFF, PWMOUT duty-cycle will be set to 0x00 to turn off fan. When expected count is 0x000, PWMOUT duty-cycle will be set to 0xFF to turn on fan with full speed. If both (1) and (2) are not true, When PWMOUT duty-cycle decrease to MIN_DUTY(≠ 00h), obviously the duty-cycle will decrease to 00h next, the F81865 will keep duty-cycle at 00h for 1.6 seconds. After that, the F81865 starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. This ensures that if there is any glitch during the period, the F81865 will ignore it. Start Duty Stop Duty Fig 7-8 FAN_FAULT# Fan_Fault# will be asserted when the fan speed doesn’t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to PWM duty-cycle which should be able to turn on the fan. There are two conditions may cause the FAN_FAULT# event. (1). When PWM_Duty reaches 0xFF, the fan speed count can’t reach the fan expected count on time. (Figure 7-9) 11 sec(default) Current Fan Count Expected Fan Count 100% Duty-cycle Fan_Fault# Fig 7-9 51 May, 2010 V0.28P F81865 (2). After the period of detecting fan full speed, when PWM_Duty > Min. Duty, and fan count is still in 0xFFF. 7.6.2 Hardware Monitor Device Registers Before the device registers, the following is a register map order which shows a summary of all registers. Please refer each register if you want more detail information. Register CR01 ~ CR0E Configuration Registers Register CR10 ~ CR32 Voltage Setting Register Register CR60 ~ CR8F Temperature Setting Register Register CR90 ~ CRBF Fan Control Setting Register Fan1 Detail Setting CRA0 ~ CRAF Fan2 Detail Setting CRB0 ~ CRBF 7.6.2.1Configuration Setting Configuration Register ⎯ Index 01h Bit 7-3 2 1 0 Name Reserved POWER_DOWN FAN_START V_T_START R/W Default 0h R/W R/W R/W 0 0 1 1 Reserved Hardware monitor function power down. Set one to enable startup of fan monitoring operations; a zero puts the part in standby mode. Set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. Description Configuration Register ⎯ Index 02h Bit 7 6 Name DUMMY_REG CASE_BEEP_EN R/W Default R/W R/W 0 0 Dummy register. 0: Disable case open event output via BEEP. 1: Enable case open event output via BEEP. 00: The OVT# will be level mode. 01: The OVT# will be 500us pulse mode (SMI). 10: The OVT# will indicate by 1Hz LED function. 11: The OVT# will indicate by (400/800HZ) BEEP output. Dummy register. 0: Disable case open event output via PME. 1: Enable case open event output via PME. 00: The ALERT# will be low active level mode. 01: The ALERT# will be high active level mode. 10: The ALERT# will indicate by 1Hz LED function. 11: The ALERT# will indicate by (400/800HZ) BEEP output. Description 5-4 3 2 OVT_MODE DUMMY_REG CASE_PME_EN R/W R/W R/W 0 0 0 1-0 ALERT_MODE R/W 0 Configuration Register ⎯ Index 03h Bit 7-1 0 Name Reserved CASE_STS R/W Default R/W R/W 0 0 Reserved Case open event status, write 1 to clear if case open event cleared. Description CPU Temperature Measure Method Register ⎯ Index 0Ah Bit 7-6 5 Name Reserved T1_IIR_EN R/W Default R/W R/W 0 0 Reserved. Set one to enable the IIR filter when CPU measure mode is PECI Description 52 May, 2010 V0.28P F81865 4 Reserved R/W 0 Reserved. This register is used to select the output voltage for PECI. 00: 1.23V 01: 1.13V 10: Reserved. 11: 1.00V This register selects the method for measuring the CPU temperature. 00: normal diode. 01: PECI 10: Reserved. 11: Reserved. 3-2 VTT_SEL R/W 0 1-0 MEAS_TYPE R/W 0 CPU Select Register ⎯ Index 0Bh Bit 7-4 3-1 0 Name CPU_SEL Reserved DOMAIN R/W Default R/W R/W R/W 0 0 0 Reserved. Set one to enable getting dual core CPU temperature. Description Each bit indicates one CPU. Set only one bit at a time. TCC Temperature Register ⎯ Index 0Ch Bit 0 Name TCC_TEMP R/W Default R/W 0x55 Description This indicates the TCC temperature for the PECI. The absolute temperature is achieved by adding the reading from PECI to this register. PECI Slope Control Register ⎯ Index 0Eh Bit 7-4 3 Name Reserved PECI_ADD R/W Default R/W 0 Reserved. Refer to PECI_SCALE. This register accompany with PECI_ADD defines the PECI reading slope. (PECI_READ indicates the reading for host, PECI_TMP indicates the reading from PECI in the following description) When PECI_ADD is 0: 000: PECI_READ = PECI_TMP. 001: PECI_READ = PECI_TMP - 1/2* (PECI_TMP). 010: PECI_READ = PECI_TMP - 1/4* (PECI_TMP). 011: PECI_READ = PECI_TMP - 1/8* (PECI_TMP). 100: PECI_READ = PECI_TMP - 1/16* (PECI_TMP). 101: PECI_READ = PECI_TMP - 1/32* (PECI_TMP). 110: PECI_READ = PECI_TMP - 1/64* (PECI_TMP). 111: PECI_READ = PECI_TMP - 1/128* (PECI_TMP). When PECI_ADD is 1: 000: PECI_READ = PECI_TMP. 001: PECI_READ = PECI_TMP + 1/2* (PECI_TMP). 010: PECI_READ = PECI_TMP + 1/4* (PECI_TMP). 011: PECI_READ = PECI_TMP + 1/8* (PECI_TMP). 100: PECI_READ = PECI_TMP + 1/16* (PECI_TMP). 101: PECI_READ = PECI_TMP + 1/32* (PECI_TMP). 110: PECI_READ = PECI_TMP + 1/64* (PECI_TMP). 111: PECI_READ = PECI_TMP + 1/128* (PECI_TMP). Description 2-0 PECI_SCALE R/W 0 53 May, 2010 V0.28P F81865 7.6.2.2 Voltage Setting Voltage PME Enable Register ⎯ Index 10h Bit 7-2 1 0 Name Reserved VIN0_PME_EN Reserved R/W Default R/W R/W R/W 0 0 0 Reserved. 0: disable VIN0 PME. 1: enable VIN0 PME. See VIN0_EXC_STS for detail. Reserved. Description Voltage Exceed Status Register ⎯ Index 11h Bit 7-2 1 0 Name Reserved VIN0_EXC_STS Reserved R/W Default R/W R/W R/W 0 0 0 Reserved. This bit records the change of VIN0 real time exceeding status. When VIN0 exceeds VIN0_HIGH_LIMIT or VIN0 returns to the normal range, this bit will be set to “1”. Write “1” to clear this bit. Return 0 when read. Description Voltage Real Time Exceed Status Register ⎯ Index 12h Bit 7-2 1 0 Name Reserved VIN0_EXC Reserved R/W Default R/W R/W R/W 0 0 0 Reserved. 0: VIN0 is less or equal than VIN0_HIGH_LIMIT. 1: VIN0 is great than VIN0_HIGH_LIMIT. Return 0 when read. Description Voltage BEEP Enable Register ⎯ Index 13h Bit 7-2 1 0 Name Reserved VIN0_BEEP_EN Reserved R/W Default R/W R/W R/W 0 0 0 Reserved. 0: disable VIN0 BEEP. 1: enable VIN0 BEEP. See VIN0_EXC for detail. Reserved. Description Voltage reading and limit⎯ Index 20h- 2Fh Address 20h 21h 22h 23h 24h 25h 26h 29~2Fh Attribute RO RO RO RO RO RO RO RO Default Value -------FF Description VCC3V reading. The unit of reading is 16mV. VIN0 (Vcore) reading. The unit of reading is 8mV. VIN1 reading. The unit of reading is 8mV. VIN2 reading. The unit of reading is 8mV. VIN3 reading. The unit of reading is 8mV. VSB3V reading. The unit of reading is 16mV. VBAT reading. The unit of reading is 16mV. Reserved Voltage VIN0 High Limit Register ⎯ Index 32h Bit 7-0 Name VIN1_HIGH_LIMIT R/W Default R/W ffh Description This defines the VIN1 voltage high limit. 54 May, 2010 V0.28P F81865 7.6.2.3 Temperature Setting Temperature PME# Enable Register ⎯ Index 60h Bit 7 6 5 4 3 2 1 0 Name Reserved EN_ T2_ OVT_PME EN_ T1_ OVT_PME Reserved Reserved EN_ T2_EXC_PME EN_ T1_EXC_PME Reserved R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Reserved If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT setting. If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT setting. Reserved Reserved If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high limit setting. If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high limit setting. Reserved Description Temperature Interrupt Status Register ⎯ Index 61h Bit 7 6 Name Reserved T2_OVT _STS R/W Default R/W 0 Reserved A one indicates TEMP2 temperature sensor has exceeded OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be ignored. A one indicates TEMP1 temperature sensor has exceeded OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be ignored. Reserved Reserved A one indicates TEMP2 temperature sensor has exceeded high limit or below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will be ignored. A one indicates TEMP1 temperature sensor has exceeded high limit or below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will be ignored. Reserved Description 5 4 3 2 T1_OVT _STS Reserved Reserved T2_EXC _STS R/W R/W 0 0 1 0 T1_EXC _STS Reserved R/W - 0 - Temperature Real Time Status Register ⎯ Index 62h Bit 7 6 5 4 3 2 1 0 Name Reserved T2_OVT T1_OVT Reserved Reserved T2_EXC T1_EXC Reserved R/W Default R/W R/W R/W R/W R/W 0 0 0 0 0 Reserved Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is below the “OVT limit –hysteresis” temperature. Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is below the “OVT limit –hysteresis” temperature. Reserved Reserved Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is below the “high limit –hysteresis” temperature. Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is below the “high limit –hysteresis” temperature. Reserved Description 55 May, 2010 V0.28P F81865 Temperature BEEP Enable Register ⎯ Index 63h Bit 7 6 5 4 3 2 1 0 Name Reserved R/W Default R/W 0 0 0 0 0 0 0 0 Reserved If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT limit setting. If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT limit setting. Reserved Reserved If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high limit setting. If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high limit setting. Reserved Description EN_ T2_ OVT_BEEP R/W EN_ T1_ OVT_BEEP R/W Reserved Reserved R/W R/W EN_ T2_EXC_BEEP R/W EN_ T1_EXC_BEEP R/W Reserved R/W OVT Output Enable Register 1 ⎯ Index 66h Bit 7 6 5 4 3 2 1 0 Name Reserved EN_T2_ALERT EN_T1_ALERT Reserved Reserved EN_T2_OVT EN_T1_OVT Reserved R/W Default R R/W R/W R R R/W R/W R 0h 0 1 0h 0h 0 1 0h Reserved. Enable temperature alert (ALERT) mechanism of temperature2. Enable temperature alert (ALERT) mechanism of temperature1. Reserved. Reserved. Enable over temperature (OVT) mechanism of temperature2. Enable over temperature (OVT) mechanism of temperature1. Reserved. Description Temperature Sensor Type Register ⎯ Index 6Bh Bit 7-4 3 2 1 0 Name Reserved Reserved T2_MODE T1_MODE Reserved R/W Default RO R R/W R/W R 0 0h 1 1 0h --0: TEMP2 is connected to a thermistor. 1: TEMP2 is connected to a BJT. (default) 0: TEMP1 is connected to a thermistor 1: TEMP1 is connected to a BJT.(default) -Description TEMP1 Limit Hystersis Select Register -- Index 6Ch Bit 7-4 3-0 Name TEMP1_HYS Reserved R/W Default R/W R 4h 0h Description Limit hysteresis. (0~15°C) Temperature and below the (boundary – hysteresis). -- TEMP2 Limit Hystersis Select Register -- Index 6Dh Bit 7-4 3-0 Name Reserved TEMP2_HYS R/W Default R R/W 0h 4h -Limit hysteresis. (0~15°C) Temperature and below the (boundary – hysteresis). Description 56 May, 2010 V0.28P F81865 DIODE OPEN Status Register -- Index 6Fh Bit 7-4 3 2 1 0 Name Reserved Reserved T2_DIODE_OPEN T1_DIODE_OPEN Reserved R/W Default RO RO RO RO R Default Value -----------64h 55h 64h 55h ----Reserved Reserved Temperature 1 reading (TEMP1). The unit of reading is 1ºC.At the moment of reading this register. Reserved Temperature 2 reading (TEMP2). The unit of reading is 1ºC.At the moment of reading this register. Reserved Reserved Reserved Reserved Reserved Reserved Temperature sensor 1 OVT limit. The unit is 1ºC. Temperature sensor 1 high limit. The unit is 1ºC. Temperature sensor 2 OVT limit. The unit is 1ºC. Temperature sensor 2 high limit. The unit is 1ºC. Reserved Reserved Reserved Reserved 0h 0h 0h 0h 0h Reserved Reserved External diode 2 is open External diode 1 is open -Description Temperature ⎯ Index 70h- 8Fh Address 70h 71h 72h 73h 74h 75h 76h 77-7Bh 7C-7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88-8Bh 8C~8Fh Attribute Reserved Reserved RO Reserved RO Reserved Reserved Reserved Reserved Reserved Reserved R/W R/W R/W R/W Reserved Reserved Reserved Reserved Description 7.6.2.4 Fan Control Setting FAN PME# Enable Register ⎯ Index 90h Bit 7-2 1 Name Reserved EN_FAN2_PME R/W Default RO R/W 0h 0h Reserved A one enables the corresponding interrupt status bit for PME# interrupt. Set this bit 1 to enable PME# function for Fan2. Description 57 May, 2010 V0.28P F81865 0 EN_FAN1_PME R/W 0h A one enables the corresponding interrupt status bit for PME# interrupt. Set this bit 1 to enable PME# function for Fan1. FAN Interrupt Status Register ⎯ Index 91h Bit 7-2 1 0 Name Reserved FAN2_STS FAN1_STS R/W Default RO R/W R/W 0 --Reserved This bit is set when the fan2 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. This bit is set when the fan1 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. Description FAN Real Time Status Register ⎯ Index 92h Bit 7-2 1 0 Name Reserved FAN2_EXC FAN1_EXC R/W Default -RO RO 0 --Reserved This bit set to high mean that fan2 count can’t meet expect count over than PME time(CR9F) or when duty not zero but fan stop over then 3 sec. This bit set to high mean that fan1 count can’t meet expect count over than PME time(CR9F) or when duty not zero but fan stop over then 3 sec. Description FAN BEEP# Enable Register ⎯ Index 93h Bit 7 6 5 4 3 2 1 0 Name Reserved R/W Default R/W 0 0 0 0 0 0 0 0 Reserved Set this bit to one will trig all fans to full speed when T2 is over the high limit. Set this bit to one will trig all fans to full speed when T1 is over the high limit. Reserverd Reserved Reserved A one enables the corresponding interrupt status bit for BEEP. A one enables the corresponding interrupt status bit for BEEP. Description FULL_WITH_T2_EN R/W FULL_WITH_T1_EN R/W Reserved Reserved Reserved EN_FAN2_ BEEP EN_FAN1_ BEEP R/W RO RO R/W R/W Fan Type Select Register -- Index 94h Bit 7-6 5-4 Name Reserved Reserved R/W Default ----Reserved. Reserved Description 3-2 FAN2_TYPE R/W 1-0 FAN1_TYPE R/W 00: Output PWM mode (pushpull) to control fans. 01: Use linear fan application circuit to control fan speed by fan’s power 2’b 0S terminal. 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. 00: Output PWM mode (push pull) to control fans. 01: Use linear fan application circuit to control fan speed by fan’s power 2’b 0S terminal. 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. S: Register default values are decided by trapping. Fan mode Select Register -- Index 96h Bit 7-6 Name Reserved R/W Default --Reserved Description 58 May, 2010 V0.28P F81865 5-4 Reserved --Reserved 00: Auto fan speed control, fan speed will follow different temperature by different RPM that define in 0xB6-0xBE. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle (voltage) that defined in 0xB6-0xBE. 10: Manual mode fan control, user can write expect RPM count to 0xB2-0xB3, and F81865 will auto control duty cycle (PWM fan type) or voltage (linear fan type) to control fan speed. 11: Manual mode fan control, user can write expected duty cycle (PWM fan type) or voltage (linear fan type) to 0xB3, it will output that value duty or voltage to controlled fan speed. 00: Auto fan speed control, fan speed will follow different temperature by different RPM that define in 0xA6-0xAE. 01: Auto fan speed control, fan speed will follow different temperature by different duty cycle that defined in 0xA6-0xAE. 10: Manual mode fan control, user can write expect RPM count to 0xA2-0xA3, and F81865 will auto control duty cycle (PWM fan type) or voltage (linear fan type) to control fan speed. 11: Manual mode fan control, user can write expected duty cycle (PWM fan type) or voltage (linear fan type) to 0xA3, it will output that value duty or voltage to control fan speed. 3-2 FAN2_MODE R/W 1h 1-0 FAN1_MODE R/W 1h Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h Bit 7-4 Name FAN2_HYS R/W Default R/W 4h Description 0000: Boundary hysteresis. (0~15 degree C) Segment will change when the temperature over the boundary temperature and below the (boundary – hysteresis ). 0000: Boundary hysteresis. (0~15 degree C) Segment will change when the temperature over the boundary temperature and below the (boundary – hysteresis ). 3-0 FAN1_HYS R/W 4h Auto Fan1 and Fan2 Update Rate Select Register -- Index 9Bh Bit 7-6 5-4 Name Reserved Reserved R/W Default ----Reserved Reserved Fan2 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan1 duty update rate: 00: 2Hz 01: 5Hz (default) 10: 10Hz 11: 20Hz Description 3-2 FAN2_RATE_SEL R/W 01 1-0 FAN1_RATE_SEL R/W 01 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE ⎯ Index 9Ch Bit 7-4 Name FAN2_STOP_DUTY R/W Default R/W 5h Description When fan start, the FAN_CTRL2 will increase duty-cycle from 0 to this (value x 8) directly. And if fan speed is down, the FAN_CTRL 2 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). 59 May, 2010 V0.28P F81865 3-0 FAN1_STOP_DUTY R/W 5h When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 to this (value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). Fan Fault Time Register -- Index 9Fh Bit 7-5 4 Name Reserved START_DUTY_SEL R/W Default -R/W --Reserved. 0: The power on fan speed is 100% 1: The power on fan speed is 60%. This bit is power on trap by FAN_100_60. Default is 60%. This is the time value in second for the fan fault mechanism. If the duty is 100% in RPM mode and the fan speed can’t exceed the expected value. After the time set by this byte, the fan fault will asserts if it is enabled. Description 3-0 FAN_PME_TIME R/W 0Ah Fan1 Index A0h- AFh Address A0h A1h A2h~ A3h A4h A5h Attribute RO RO Reserved R/W R/W Default Value 8’h0f 8’hff -8’h03 8’hff Description FAN1 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 count reading (LSB). See index 96h FAN1 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN1 full speed count reading (LSB). T1 BOUNDARY 1 TEMPERATURE – Index A6h Bit 7 Name Reserved R/W Default RO 0 Reserved Description 6-0 BOUND1TMP1 R/W st The 1 BOUNDARY temperature for VT1 in temperature mode. When T1 temperature exceeds this boundary, FAN1 expect value will be 3Ch in full speed. o (60 C) When VT1 temperature is below this boundary – hysteresis, FAN1 expect value will load the value calculated from segment2 index ABh. T1 BOUNDARY 2 TEMPERATURE – Index A7 Bit 7 Name Reserved R/W Default RO 0 Reserved Description 6-0 BOUND2TMP1 R/W The 2nd BOUNDARY temperature for VT1 in temperature mode. When T1 temperature exceeds this boundary, FAN1 expect value will load 32h from segment 2 register (index ABh). o (50 C) When T1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 3 register (index ACh). T1 BOUNDARY 3 TEMPERATURE – Index A8h Bit 7 Name Reserved R/W Default RO 0 Reserved. Description 60 May, 2010 V0.28P F81865 6-0 BOUND3TMP1 R/W The 3rd BOUNDARY temperature for VT1 in temperature mode. When T1 temperature exceeds this boundary, FAN1 expect value will load 28h from segment 3 register (index ACh). o (40 C) When T1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 4 register (index ADh). T1 BOUNDARY 4 TEMPERATURE – Index A9 Bit 7 Name Reserved R/W Default RO 0 Reserved. Description 6-0 BOUND4TMP1 R/W th The 4 BOUNDARY temperature for VT1 in temperature mode. When T1 temperature exceeds this boundary, FAN1 expect value will load 1Eh the value calculated from segment 4 (index ADh). o (30 C) When T1 temperature is below this boundary – hysteresis, FAN1 expect value will load from segment 5 register (index AEh). FAN1 SEGMENT 1 SPEED COUNT – Index AAh Bit Name R/W Default Description The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. Ex: FFh 100%:full speed: User must set this register to 0. R/W (100%) 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is (100-X)*32/X 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7-0 SEG1SPEED1 FAN1 SEGMENT 2 SPEED COUNT – Index ABh Bit Name R/W Default Description The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of D9h the full speed in this temperature section. (85%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7-0 SEG2SPEED1 R/W FAN1 SEGMENT 3 SPEED COUNT Bit Name – Index ACh Description R/W Default 7-0 SEG3SPEED1 R/W The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of B2h the full speed in this temperature section. (70%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. FAN1 SEGMENT 4 SPEED COUNT Bit Name – Index ADh Description R/W Default 7-0 SEG4SPEED1 R/W The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of 99h the full speed in this temperature section. (60%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 61 May, 2010 V0.28P F81865 FAN1 SEGMENT 5 SPEED COUNT Bit Name – Index AEh Description R/W Default 7-0 SEG5SPEED1 R/W The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of 80h the full speed in this temperature section. (50%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. FAN1 Temperature Mapping Select Bit 7-6 5 Name Reserved FAN1_UP_T_EN R/W Default -R/W 0 0 – Index AFh Description Reserved 0: Fan1 speed still follows the T1. 1: Fan1 will load the full speed when any temperature exceeds its high limit. 0: When T1 is in the range between BOUND1TMP1 and BOUND4TMP1, the fan expect is SEG2SPEED1. 1: When T1 is in the range between BOUND1TMP1 and BOUND4TMP1, the fan expect is calculated by the equation: fan expect = [(current TEMP – BOUND4TMP1)/(BOUDN1TMP1 – BOUND4TMP1)]*(SEG2SPEED1 – SEG5SPEED1) + SEG5SPEED1. 0: When T1 is over BOUND1TMP1, the duty cycle will increase one by one. 1: When T1 is over BOUND1TMP1, the duty cycle will directly jump to full speed. 0: When T1 is over BOUND1TMP1, the duty cycle will decrease one by one. 1: When T1 is over BOUND1TMP1, the duty cycle will directly jump to the expect value. 0: reserved. 1: fan1 follow temperature 1. 2: fan1 follow temperature 2. 3: reserved. 4 FAN1_INTERPOLATION_ R/W EN 1 3 FAN1_JUMP_HIGH_EN R/W 1 2 FAN1_JUMP_LOW_EN R/W 1 1-0 Fan1_temp_sel R/W 1 Fan2 Index B0h- BFh Address Attribute Default Value 8’h0f 8’hff -8’h03 8’hff Description FAN2 count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN2 count reading (LSB). See index 96h FAN2 full speed count reading (MSB). At the moment of reading this register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. FAN2 full speed count reading (LSB). B0h B1h B2h~B3h B4h B5h RO RO Reserved R/W R/W T2 BOUNDARY 1 TEMPERATURE – Index B6h Bit 7 Name Reserved R/W Default RO 0 Return 0 when read. Description 6-0 BOUND1TMP2 R/W st The 1 BOUNDARY temperature for VT2 in temperature mode. When T1 temperature exceeds this boundary, FAN2 expect value will be 3Ch in full speed. o (60 C) When T2 temperature is below this boundary – hysteresis, FAN2 expect value will load the value calculated from segment2 (index BBh). 62 May, 2010 V0.28P F81865 T2 BOUNDARY 2 TEMPERATURE – Index B7 Bit 7 Name Reserved R/W Default RO 0 Return 0 when read. Description 6-0 BOUND2TMP2 R/W The 2nd BOUNDARY temperature for VT2 in temperature mode. When T2 temperature exceeds this boundary, FAN2 expect value will load 32 from segment 2 register (index BBh). o (50 C) When T2 temperature is below this boundary – hysteresis, FAN2 expect value will load from segment 3 register (index BCh). T2 BOUNDARY 3 TEMPERATURE – Index B8h Bit 7 Name Reserved R/W Default RO 0 Return 0 when read. Description 6-0 BOUND3TMP2 R/W The 3rd BOUNDARY temperature for VT2 in temperature mode. When T2 temperature exceeds this boundary, FAN2 expect value will load 28h from segment 3 register (index BCh). o (40 C) When T2 temperature is below this boundary – hysteresis, FAN2 expect value will load from segment 4 register (index BDh). T2 BOUNDARY 4 TEMPERATURE – Index B9 Bit 7 Name Reserved R/W Default RO 0 Return 0 when read. Description 6-0 BOUND4TMP2 R/W th The 4 BOUNDARY temperature for VT2 in temperature mode. When T2 temperature exceeds this boundary, FAN2 expect value will load 1Eh the value calculated from segment2 (index BDh). o (30 C) When T2 temperature is below this boundary – hysteresis, FAN2 expect value will load from segment 5 register (index BEh). FAN2 SEGMENT 1 SPEED COUNT – Index BAh Bit Name R/W Default Description The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. Ex: FFh 100%: full speed: User must set this register to 0. R/W (100%) 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is ( (100-X)*32/X 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7-0 SEG1SPEED2 FAN2 SEGMENT 2 SPEED COUNT – Index BBh Bit Name R/W Default Description The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of D9h the full speed in this temperature section. (85%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7-0 SEG2SPEED2 R/W FAN2 SEGMENT 3 SPEED COUNT – Index BCh Bit Name R/W Default Description The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of B2h the full speed in this temperature section. (70%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7-0 SEG3SPEED2 R/W 63 May, 2010 V0.28P F81865 FAN2 SEGMENT 4 SPEED COUNT – Index BDh Bit Name R/W Default Description The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of 99h the full speed in this temperature section. (60%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7-0 SEG4SPEED2 R/W FAN2 SEGMENT 5 SPEED COUNT – Index BEh Bit Name R/W Default Description The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of 80h the full speed in this temperature section. (50%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 7-0 SEG5SPEED2 R/W FAN2 Temperature Mapping Select – Index BFh Bit 7-6 5 Name Reserved FAN2_UP_T_EN R/W Default -R/W 0 0 Reserved 0: Fan2 speed still follows the T2. 1: Fan2 will load the full speed when any temperature exceeds its high limit. 0: When T2 is in the range between BOUND1TMP2 and BOUND4TMP2, the fan expect is SEG2SPEED2. 1: When T2 is in the range between BOUND1TMP2 and BOUND4TMP2, the fan expect is calculated by the equation: fan expect = [(current TEMP – BOUND4TMP2)/(BOUDN1TMP2 – BOUND4TMP2)]*(SEG2SPEED2 – SEG5SPEED2) + SEG5SPEED2. 0: When T2 is over BOUND1TMP2, the duty cycle will increase one by one. 1: When T2 is over BOUND1TMP2, the duty cycle will directly jump to full speed. 0: When T2 is over BOUND1TMP2, the duty cycle will decrease one by one. 1: When T2 is over BOUND1TMP2, the duty cycle will directly jump to the expect value. 0: reserved. 1: fan1 follow temperature 1. 2: fan1 follow temperature 2. 3: reserved. Description 4 FAN2_INTERPOLATI R/W ON_EN 1 3 FAN2_JUMP_HIGH_ R/W EN 1 2 FAN2_JUMP_LOW_ R/W EN 1 1-0 Fan2_temp_sel R/W 2 7.7. SPI Interface Communication between the two devices is handling via the serial peripheral interface (SPI). Every SPI system consist of one master and one or more slaves, where a master provides the SPI clock and slave receives clock from the master. This design is only master function, for basic signal, master-out/slave-in (MOSI), master-in/slave-out (MISO), serial clock (SCK), and 2 slaves select (SS), are needed for SPI interface. Each of slave select supports from 512kbits to 8Mbits flash is decided by configuration register. Serial clock (SCK) signal frequency is varied from 1.7MHz to 33MHz. The serial data (MOSI) for SPI interface translates to depend on SCK rising edge or falling edge is decided by 64 May, 2010 V0.28P F81865 configuration register. 7.8. ACPI Function The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of power in a computer. It lets computer manufacturer and user to determine the computer’s power usage dynamically. There are three ACPI states that are of primary concern to the system designer and they are designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this state. The other two are called sleep states and reflect different power consumption when power-down. S3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. S5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. Take S3 and S5 as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3. There are 4 modes under power loss state via setting ACPI control register. The always on, always off, keep last state & bypass mode.. In keep last state mode, one register will latch the status before power loss. If it is power on before power loss, it will automatically power on when power is resumed. If it is power off before power loss, it will remain power off when power is resumed. PWROK Signals VDD3VOK ATXPWGD DELAY PWROK PWROK is delayed 400ms (default) as VCC arrives 2.8V, and the delay timing can be programmed via register (100ms ~ 400ms). 7.9. Watchdog Timer Function Watch dog timer is provided for system controlling. If time-out can trigger one signal to high/low level/pulse, the signal is depend on register setting. The time unit has two ways from 1sec or 60sec. In pulse mode, there are four pulse widths can be selected (1ms/25ms/125ms/5sec). Others, please refer the device register description as below. Watchdog Timer Configuration Register 1⎯ base address + 05h Bit 7 6 Name Reserved WDTMOUT_STS R/W Default R R/W 0 0 Reserved If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to this bit will clear it to 0. Description 65 May, 2010 V0.28P F81865 5 4 3 2 1-0 WD_EN WD_PULSE WD_UNIT WD_HACTIVE WD_PSWIDTH R/W R/W R/W R/W R/W 0 0 0 0 0 If this bit is set to 1, the counting of watchdog time is enabled. Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit. Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. Select output polarity of RSTOUT# (1: high active, 0: low active) by setting this bit. Select output pulse width of RSTOUT# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec Watchdog Timer Configuration Register 2 ⎯ base address + 06h Bit 7-0 Name WD_TIME R/W Default R/W 0 Time of watchdog timer Description Watchdog PME Control Register ⎯ base address + 0Ah Bit 7 6 5-1 0 Name WDT_PME WDT_PME_EN Reserved WDOUT_EN R/W Default R R/W -R/W -0 -0 Description The PME Status. This bit will set when WDT_PME_EN is set and the watchdog timer is 1 unit before time out (or time out). 0: Disable Watchdog PME. 1: enable Watchdog PME. Reserved. 0: disable Watchdog time out output via WDTRST#. 1: enable Watchdog time out output via WDTRST#. 7.10. RTC Function The RTC function is a full binary-coded decimal (BCD) low-power real time clock and calendar chip which provides seconds, minutes, hours, day, date, month, and year information. Functions can be upgraded flexibly for special MB system. More detail description and setting, please refer to the device register as below. Seconds Register ⎯ Index 00h Bit 7 6-0 Name Reserved SEC R/W R R/W Default 0 00h Reserved Seconds (SEC). To write this SEC, “SET” bit (CR0B[7]) must be set to 1. Description Seconds Alarm Register ⎯ Index 01h Bit 7 6-0 Name SEC_ALARM_EN SEC_ALARM R/W R/W R/W Default 0 00h Description Seconds Alarm Enable (SEC_ALARM_EN). To compare SEC_ALARM with SEC, this bit must be set to 1. If this bit is not set to 1, it means that you don’t care about second alarm. Seconds Alarm (SEC_ALARM). Minutes Register ⎯ Index 02h Bit 7 6-0 Name Reserved MIN R/W R R/W Default 0 00h Reserved Minutes (MIN). To write MIN, “SET” bit (CR0B[7]) must be set to 1. Description 66 May, 2010 V0.28P F81865 Minutes Alarm Register ⎯ Index 03h Bit 7 6-0 Name MIN_ALARM_EN MIN_ALARM R/W R/W R/W Default 0 00h Description Minutes Alarm Enable. To compare MIN_ALARM with MIN, this bit must be set to 1. If this bit is not set to 1, it means that you don’t care about minutes alarm. Minutes Alarm (MIN_ALARM). Hours Register ⎯ Index 04h Bit Name R/W Default Description PM Flag (PM_FLAG) This bit is used to indicate that hour is at AM or PM. It only makes sense when “M24” bit (CR0C[1]) is set to 0. To write this bit, “SET” bit (CR0C[7]) must be set to 1. 0: AM 1: PM Reserved Hours (HRS). To write HRS, “SET” bit (CR0C[7]) must be set to 1. 7 PM_FLAG R/W 0 6 5-0 Reserved HRS R R/W 0 12h Hours Alarm Register ⎯ Index 05h Bit 7 6 5-0 Name HRS_ALARM_EN PM_ALARM HRS_ALARM R/W R/W R/W R/W Default 0 0 00h Description Hours Alarm Enable (HRS_ALARM_EN) To compare HRS_ALARM/PM_ALARM with HRS/PM_FLAG, this bit must be set to 1. If this bit is not set to 1, it means that you don’t care about hours alarm. PM Flag Alarm (PM_ALARM) Hours Alarm (HRS_ALARM). Day of Week Register ⎯ Index 06h Bit 7-3 Name Reserved R/W R Default 0 Reserved Day of Week (WEEK). To write WEEK, “SET” bit (CR0C[7]) must be set to 1. 001: Sunday 010: Monday 011: Tuesday 100: Wednesday 101: Thursday 110: Friday 111: Saturday Description 2-0 WEEK R/W 001b Date of Month Register ⎯ Index 07h Bit 7-6 5-0 Name Reserved DOM R/W R R/W Default 0 01h Reserved Date of Month (DOM). To write DOM, “SET” bit (CR0C[7]) must be set to 1. Description Month Register ⎯ Index 08h Bit 7-5 4-0 Name Reserved MTH R/W R R/W Default 0 01h Reserved Month (MTH). To write MTH, “SET” bit (CR0C[7]) must be set to 1. Description 67 May, 2010 V0.28P F81865 Year Register ⎯ Index 09h Bit 7-0 Name YEAR R/W R/W Default 07h Description Year (YEAR) To write YEAR, “SET” bit (CR0C[7]) must be set to 1. Control Register 1 ⎯ Index 0Ah Bit 7 6-4 Name UIP Reserved R/W R R/W Default 0 010b Description Update Cycle In Progress (UIP). UIP is cleared in the end of an update cycle and when “SET” (CR0C[7]) is 1. Reserved 3-0 PIR R/W Periodic Interrupt Rate (PIR) 0000: NONE 0001: 16 kHz 0010: 8 kHz 0011: 4 kHz 0100: 2 kHz 0101: 1 kHz 0110: 512 Hz 0000b 0111: 256 Hz 1000: 128 Hz 1001: 64 Hz 1010: 32 Hz 1011: 16 Hz 1100: 8 Hz 1101: 4 Hz 1110: 2 Hz 1111: 1 Hz Control Register 2 ⎯ Index 0Bh Bit 7 6 5 4 3 2 Name SET PIE AIE UIE Reserved DM R/W R/W R/W R/W R/W R R/W Default 0 0 0 0 0 0 Description Set Calendar Registers (SET) This bit must be set to 1 to enable writing calendar registers. When this bit is set, the calendar update process will be stop. Periodic Interrupt Enable (PIE) The bit is set to 1 to enable the generation of interrupt by PF (CR0E[6]). Alarm Interrupt Enable (AIE) This bit is set to 1 to enable the generation of interrupt by UF (CR0E[5]). Update-Ended Interrupt Enable (UIE) This bit is set to 1 to enable the generation of interrupt by UF (CR0E[4]) Reserved Data Mode (DM) 0: Binary Coded Decimal Mode (BCD mode) 1: Binary Mode 24/12 Hours Mode (M24) 0: AM/PM 12 Hours Mode 1: 24 Hours Mode Daylight Saving Enable (DSE) 0: Disable Special Updates 1: Enable Special Updates: (a) The last Sunday of April, the time increases from AM 01:59:59 to AM 03:00:00. (b) The last Sunday of October, the time decreases from AM 01:59:59 to AM 01:00:00 1 M24 R/W 0 0 DSE R/W 0 68 May, 2010 V0.28P F81865 Status Register ⎯ Index 0Ch Bit Name R/W Default Description RTC Interrupt Request Flag (RTC_INT_N). The interrupt request flag is set to 0 if one of the following cases are true: FP*PIE = “1” AF*AIE = “1” UF*UIE = “1” Periodic Interrupt Flag (PF) This bit is set to 1 when a rising edge is detected on the selected PIR clock. PF is set to 1 regardless of the state of PIE bit. This bit is cleared after CR0E is read. Alarm Interrupt Flag (AF) This bit is set to 1 when the current time has reached the alarm time. AF is set to 1 regardless of the state of AIE bit. This bit is cleared after CR0E is read. Update-Ended Interrupt Flag (UF) This bit is set to 1 after the end of each update cycle. UF is set to 1 regardless of the state of UIE bit. This bit is cleared after CR0E is read. Reserved 7 RTC_INT_N R 1 6 PF R 0 5 AF R 0 4 3-0 Bit 7 6 5-0 UF Reserved Name DATA_VALID DOM_ALARM_EN DOM_ALARM R R R/W R R/W R/W 0 0 Default 1 0 00h Data Valid Register ⎯ Index 0Dh Description Data Valid Flag (DATA_VALID) Read this bit in LSH0051A will always return 1. Date of Month Alarm Enable (DOM_ALARM_EN). To compare DOM_ALARM with DOM, this bit must be set to 1. If this bit is not set to 1, it means that you don’t care about date of month alarm. Date of Month Alarm (DOM_ALARM). RAM Data Register ⎯ Index 0Eh ~ IndexFFh (Total 242 Bytes) 8. Register Description The configuration register is used to control the behavior of the corresponding devices. To configure the register, using the index port to select the index and then writing data port to alter the parameters. The default index port and data port are 0x4E and 0x4F respectively. Pull down the SOUT1 pin to change the default value to 0x2E/0x2F. To enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0xAA to the index port. Following is a example to enable configuration and disable configuration by using debug. -o 4e 87 -o 4e 87 -o 4e aa ( enable configuration ) ( disable configuration ) The Following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of all registers and their default value. Please refer to each device chapter if you want more detail information. 69 May, 2010 V0.28P F81865 Global Control Registers “-“ Reserved or Tri-State Global Control Registers Register 0x[HEX] 02 07 20 21 23 24 25 26 27 28 29 2A-1 2A-2 2B 2C 2D Register Name Software Reset Register Logic Device Number Register (LDN) Chip ID Register Chip ID Register Vender ID Register Vender ID Register I2C Address Select Register Clock Select Register ROM Address Select Register GPIO4 Enable Register GPIO3 Enable Register LED Mode Select Register Full UR5 UR6 Select GPIO1 Enable Register GPIO2 Enable Register Wakeup Control Register Default Value MSB 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0/1 0 0 0 0 0 0 0 0 0 1 0/1 1/0 0 0 0 0 0 0 0 0 1 1 0/1 0 1/0 0 0 0 1 0 0 0 0 1 0 0/1 0/1 0 0 0 0 1 0 1 0 1 1 0 1 0/1 0/1 0 0 0 0 1 0 0 LSB 0 1 0 0 0 0/1 0/1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 Device Configuration Registers “-“ Reserved or Tri-State FDC Device Configuration Registers (LDN CR00) Register 0x[HEX] 30 60 61 70 74 F0 F2 F4 Register Name FDC Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register DMA Channel Select Register FDD Mode Register FDD Drive Type Register FDD Selection Register Default Value MSB 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 LSB 1 0 1 1 1 1 0 1 1 0 0 0 0 1 0 Parallel Port Device Configuration Registers (LDN CR03) Register 0x[HEX] Register Name Default Value MSB LSB 70 May, 2010 V0.28P F81865 30 60 61 70 74 F0 Parallel Port Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register DMA Channel Select Register PRT Mode Select Register 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 1 1 1 0 1 1 0 Hardware Monitor Device Configuration Registers (LDN CR04) Register 0x[HEX] 30 60 61 70 Register Name H/W Monitor Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Default Value MSB 0 1 0 0 0 0 0 1 0 0 0 0 1 0 LSB 1 0 0 1 0 1 0 KBC Device Configuration Registers (LDN CR05) Register 0x[HEX] 30 60 61 70 72 FE F0 Register Name KBC Device Enable Register Base Address High Register Base Address Low Register KB IRQ Channel Select Register Mouse IRQ Channel Select Register PS/2 Swap Register User Wakeup Code Default Value MSB 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 LSB 0 0 0 0 0 0 1 0 0 0 0 1 1 GPIO Device Configuration Registers (LDN CR06) Register 0x[HEX] 30 60 61 70 F1 F2 F3 F4 F5 F6 F7 F8 Register Name H/W Monitor Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register GPIO0 Output Data Register GPIO0 Pin Status Register GPIO0 Drive Enable Register GPIO0 Mode Select 1 Register GPIO0 Mode Select 2 Register GPIO0 Pulse Width Select 1 Register GPIO0 Pulse Width Select 2 Register GPIO0 Interrupt Enable Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71 May, 2010 V0.28P F81865 F9 E0 E1 E2 E3 EF D0 D1 D2 D3 C0 C1 C2 C3 B0 B1 B2 B3 A0 A1 A2 A3 90 91 92 93 GPIO0 Interrupt Status Register GPIO1 Output Enable Register GPIO1 Output Data Register GPIO1 Pin Status Register GPIO1 Drive Enable Register LED Mode Register GPIO2 Output Enable Register GPIO2 Output Data Register GPIO2 Pin Status Register GPIO2 Drive Enable Register GPIO3 Output Enable Register GPIO3 Output Data Register GPIO3 Pin Status Register GPIO3 Drive Enable Register GPIO4 Output Enable Register GPIO4 Output Data Register GPIO4 Pin Status Register GPIO4 Drive Enable Register GPIO5 Output Enable Register GPIO5 Output Data Register GPIO5 Pin Status Register GPIO5 Drive Enable Register GPIO6 Output Enable Register GPIO6 Output Data Register GPIO6 Pin Status Register GPIO6 Drive Enable Register 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 WDT Device Configuration Registers (LDN CR07) Register 0x[HEX] 30 60 61 F5 F6 FA Register Name WDT Device Enable Register Base Address High Register Base Address Low Register WDT Control Register WDT Timer Register WDT PME Enable Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB 0 0 0 0 0 0 0 0 0 0 SPI Device Configuration Registers (LDN CR08) Register 0x[HEX] Register Name Default Value MSB LSB 72 May, 2010 V0.28P F81865 F0 F1 F2 F3 F4 F5 F6 F7 F8 FA FB FC FD FE FF SPI Control Register SPI Timeout Value Register SPI Baud Rate Divisor Register SPI Status Register SPI High Byte Data Register SPI Command Data Register SPI Chip Select Register SPI Memory Mapping Register SPI Operate Register SPI Low Byte Data Register SPI Address High Byte Register SPI Address Medium Byte Register SPI Address Low Byte Register SPI Program Byte Register SPI Write Data Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 PME and ACPI Device Configuration Registers (LDN CR0A) Register 0x[HEX] 30 F0 F1 F2 F3 F4 F5 F6 Register Name RTC Device Enable Register PME Event Enable 1 Register PME Event Enable 2 Register PME Event Status 1 Register PME Event Status 2 Register ACPI Control Register ACPI Control Register ACPI Control Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 LSB 0 0 1 0 0 0 0 0 0 0 0 RTC Device Configuration Registers (LDN CR0B) Register 0x[HEX] 30 60 61 70 Register Name RTC Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB 0 0 0 0 0 0 0 UART1 Device Configuration Registers (LDN CR10) Register 0x[HEX] 30 60 Register Name Device Enable Register Base Address High Register Default Value MSB 0 0 0 0 0 0 LSB 1 1 1 73 May, 2010 V0.28P F81865 61 70 F0 F2 F4 F5 Base Address Low Register IRQ Channel Select Register Control Register Clock Select Register Slave Address Register Slave Address Enable Register 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART2 Device Configuration Registers (LDN CR11) Register 0x[HEX] 30 60 61 70 F0 F2 F4 F5 Register Name Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Control Register Clock Select Register Slave Address Register Slave Address Enable Register Default Value MSB 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 LSB 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 UART3 Device Configuration Registers (LDN CR12) Register 0x[HEX] 30 60 61 70 F0 F2 F4 F5 Register Name Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Control Register Clock Select Register Slave Address Register Slave Address Enable Register Default Value MSB 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 LSB 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 UART4 Device Configuration Registers (LDN CR13) Register 0x[HEX] 30 60 61 70 F0 F2 F4 Register Name Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Control Register Clock Select Register Slave Address Register Default Value MSB 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 LSB 1 0 1 0 0 0 1 0 0 1 0 0 0 74 May, 2010 V0.28P F81865 F5 Slave Address Enable Register 0 0 0 0 0 0 0 0 UART5 Device Configuration Registers (LDN CR14) Register 0x[HEX] 30 60 61 70 F0 F2 F4 F5 Register Name Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Control Register Clock Select Register Slave Address Register Slave Address Enable Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART6 Device Configuration Registers (LDN CR15) Register 0x[HEX] 30 60 61 70 F0 F1 F2 F4 F5 Register Name Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Control Register IR Mode Register Clock Select Register Slave Address Register Slave Address Enable Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8.1 8.1.1 Bit 7-1 0 Global Control Registers Software Reset Register ⎯ Index 02h Name Reserved SOFT_RST R/W Default R/W 0 Reserved Write 1 to reset the register and device powered by VDD (VCC). Description 75 May, 2010 V0.28P F81865 8.1.2 Bit Logic Device Number Register (LDN) ⎯ Index 07h Name R/W Default Description 00h: Select FDC device configuration registers. 03h: Select Parallel Port device configuration registers. 04h: Select Hardware Monitor device configuration registers. 05h: Select KBC device configuration registers. 06h: Select GPIO device configuration registers. 07h: Select WDT device configuration registers. 08h: Select SPI device configuration registers. 0Ah: Select PME & ACPI device configuration registers. 0Bh: Select RTC device configuration registers. 10h: Select UR1 device configuration registers. 11h: Select UR2 device configuration registers. 12h: Select UR3 device configuration registers. 13h: Select UR4 device configuration registers. 14h: Select UR5 device configuration registers. 15h: Select UR6 device configuration registers. 7-0 LDN R/W 00h 8.1.3 Bit 7-0 Chip ID Register ⎯ Index 20h Name CHIP_ID1 R/W Default R 07h Chip ID 1. Description 8.1.4 Bit 7-0 8.1.5 Bit 7-0 8.1.6 Bit 7-0 Chip ID Register ⎯ Index 21h Name CHIP_ID2 R/W Default R 04h Chip ID2. Description Vendor ID Register ⎯ Index 23h Name VENDOR_ID1 R/W Default R 19h Vendor ID 1. Description Vendor ID Register ⎯ Index 24h Name VENDOR_ID2 R/W Default R 34h Vendor ID 2. Description 8.1.7 Bit I2C Address Select Register ⎯ Index 25h Name R/W Default Description The default value is determined by power on trap pin RTS1#. The default I2C address is 0x5C and 0x5A for pull-up and pull-down respective. By writing 0x07, 0x04 and then new I2C_ADDR, programmer could change the default I2C address. Write the same value again will disable the programmed I2C_ADDR and return to the default address. Caution: during the enable sequence, the EN_ARA_MODE will be also changed. User should program the correct value of EN_ARA_MODE after changing I2C_ADDR. 7-1 I2C_ADDR R/W - 76 May, 2010 V0.28P F81865 0 EN_ARA_MODE R/W 0 0: disable I2C ARA. 1: enable I2C ARA. 8.1.8 Bit 7 6-5 Clock Select Register ⎯ Index 26h Name CLK24M_SEL Reserved R/W Default R/W 0 0: the CLKIN is 48MHz. 1: the CLKIN is 24MHz. Reserved. SPI time out status reset source select: 0: reset by internal VDD3VOK. 1: reset by internal VSBOK. This bit is powered by VBAT. Reserved. This bit is used to select the Index 2Ah. 0: Index 2Ah is the LED Mode Select Register. 1: Index 2Ah is the Full UR5 UR6 Select Register. Description 4 SPI_TM_RST_SEL R/W 0 3-1 0 Reserved UR_GP_PROG_EN R/W 0 8.1.9 Bit 7 ROM Address Select Register ⎯ Index 27h Name ROM_WR_EN R/W Default R/W 0 Description 0: disable the memory write cycle, the memory write cycle will be ignored. 1: enable the memory write cycle. SPI enable: 0: the SPI is disabled. 6 SPI_EN R/W - 1: the SPI is enabled. The default value is determined by the power on trap pin SOUT2. Pull down this pin to enable SPI. This bit is powered by VSB3V. FWH enable: 0: the FWH is disabled. 1: the FWH is enabled. The default value is determined by the power on trap pin DTR2#. Pull up this pin to enable FWH. Accompany with SPI_EN. 5 FWH_EN R/W - BIOS system as below list: FWH_EN 1 0 SPI_EN x 1 Description This architecture uses FWH as primary BIOS This architecture doesn’t implement FWH and uses SPI as primary BIOS. 0: The configuration register port is 2E/2F. 4 PORT_4E_EN R/W 1: The configuration register port is 4E/4F. This register is power on trapped by SOUT1. Pull down to select port 2E/2F. 77 May, 2010 V0.28P F81865 Memory address 0x000E_0000 to 0x000E_FFFF decode enable. 0: disable this range. 3 SEG_000E_EN R/W 1: enable this range. The default value is determined by power on trap pin SOUT2. Pull down to enable this bit. Memory address 0xFFF8_0000 to 0xFFFF_FFFF and 0x000F_0000 to 0x000F_FFFF decode enable. 2 SEG_FFF8_EN R/W 0: disable these ranges. 1: enable these ranges. The default value is determined by power on trap pin SOUT2. Pull down to enable this bit. Memory address 0xFFEE_0000 to 0xFFEF_FFFF decode enable. 0: disable this range. 1 SEG_FFEF_EN R/W 1: enable this range. The default value is determined by power on trap pin SOUT2. Pull down to enable this bit. Memory address 0xFFF0_0000 to 0xFFF7_FFFF decode enable. 0 SEG_FFF0_EN R/W 0 0: disable this range. 1: enable this range. 8.1.10 Bit 7 6 5 4 3 2 1 0 GPIO4 Enable Register ⎯ Index 28h Name GPIO47_SEL GPIO46_SEL GPIO45_SEL GPIO44_SEL GPIO43_SEL GPIO42_SEL GPIO41_SEL GPIO40_SEL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: the function of SIN4/GPIO47 is SIN4. 1: the function of SIN4/GPIO47 is GPIO47. 0: the function of SOUT4/GPIO46 is SOUT4. 1: the function of SOUT4/GPIO47 is GPIO46. 0: the function of DSR4#/GPIO45 is DSR4#. 1: the function of DSR4#/GPIO45 is GPIO45. 0: the function of RTS4#/GPIO44 is RTS4#. 1: the function of RTS4#/GPIO44 is GPIO44. 0: the function of DTR4#/GPIO43 is DTR4#. 1: the function of DTR4#/GPIO43 is GPIO43. 0: the function of CTS4#/GPIO42 is CTS4#. 1: the function of CTS4#/GPIO42 is GPIO42. 0: the function of RI4#/GPIO41 is RI4#. 1: the function of RI4#/GPIO41 is GPIO41. 0: the function of DCD4#/GPIO40 is DCD4#. 1: the function of DCD4#/GPIO40 is GPIO40. 8.1.11 Bit 7 GPIO3 Enable Register ⎯ Index 29h Name GPIO37_SEL R/W Default R/W 0 Description 0: the function of SIN3/GPIO37 is SIN3. 1: the function of SIN3/GPIO37 is GPIO37. 78 May, 2010 V0.28P F81865 6 5 4 3 2 1 0 GPIO36_SEL GPIO35_SEL GPIO34_SEL GPIO33_SEL GPIO32_SEL GPIO31_SEL GPIO30_SEL R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0: the function of SOUT3/GPIO36 is SOUT3. 1: the function of SOUT3/GPIO37 is GPIO36. 0: the function of DSR3#/GPIO35 is DSR3#. 1: the function of DSR3#/GPIO35 is GPIO35. 0: the function of RTS3#/GPIO34 is RTS3#. 1: the function of RTS3#/GPIO34 is GPIO34. 0: the function of DTR3#/GPIO33 is DTR3#. 1: the function of DTR3#/GPIO33 is GPIO33. 0: the function of CTS3#/GPIO32 is CTS3#. 1: the function of CTS3#/GPIO32 is GPIO32. 0: the function of RI3#/GPIO31 is RI3#. 1: the function of RI3#/GPIO31 is GPIO31. 0: the function of DCD3#/GPIO30 is DCD3#. 1: the function of DCD3#/GPIO30 is GPIO30. 8.1.12 Bit LED Mode Select Register (UR_GP_PROG_EN = 0)⎯ Index 2Ah (Powered by VSB3V) Name R/W Default VSBLED function select. 00: VSBLED drives low. 01: VSBLED is tri-state. 10: VSBLED drives a 0.5HZ clock. 11: VSBLED drives a 1HZ clock. (Clock output is inversed with VCCLED clock output). VCCLED function select. 00: VCCLED drives low. 01: VCCLED is tri-state. 10: VCCLED drives a 0.5HZ clock. 11: VCCLED drives a 1HZ clock. (Clock output is inversed with VSBLED clock output). Description 7-6 VSBLED_SEL R/W 2’b00 5-4 VCCLED_SEL R/W 2’b00 79 May, 2010 V0.28P F81865 FDC_GP_EN, UR6_FULL_EN, UR5_FULL_EN, UR6_ALT_EN, IR_ALT_EN and RTS6_ALT_EN will determine the functions of pin 9 to pin 21. Pin 17 to pin 21 FDC_GP_EN UR5_FULL_EN UR6_FULL_EN Function 0 X 1 X Pin 12 to pin 16 FDC_GP_EN 0 1 0 0 UR5_FULL_EN 0 X X 1 UR6_FULL_EN FDC inputs UR5 Modem Control GPIO60 ~ GPIO64 GPIO60 ~ GPIO64 Function 0 X 1 3 FDC_GP_EN R/W 0 X Pin 10 to pin 11 FDC_GP_EN 0 X X 1 UR6_ALT_EN 0 1 0 0 IR_ALT_EN FDC outputs UR6 Modem Control GPIO53 ~ GPIO57 GPIO53 ~ GPIO57 Function 0 X X 1 Pin 9 FDC_GP_EN 0 1 0 0 RTS6_ALT_EN 0 X 1 0 FDC outputs* SIN6_2/SOUT6_2 IRRX_2/IRTX_2 GPIO51 ~ GPIO52 Function 0 X 1 0 1 0 FDC outputs* RTS6_2# GPIO50 *When UR5_FULL_EN or UR6_FULL_EN is set to “1”, the pin function will become GPIOs. This bit accompanying with IR_GP_EN will determine the function of GPIO05/SOUT6/IRTX and GPIO06/SIN6/IRRX. UR6_GP_EN 2 UR6_GP_EN R/W 0 0 1 0 IR_GP_EN 0 x 1 Function GPIO05/GPIO06 SOUT6_1/SIN6_1 IRTX_1/IRRX_1 1 UR5_GP_EN R/W 0 0 8.1.13 Bit 7 IR_GP_EN R/W 0 UR5 enable. (This bit affects the pin function only when GPIO12_SEL and GPIO13_SEL is “0”). 0: the function of GPIO12/SCL/SOUT5 and GPIO13/SDA/SIN5 will be determined by GPIO12_SEL and GPIO13_SEL. 1: the function of GPIO12/SCL/SOUT5 and GPIO13/SDA/SIN5 will be SOUT5 and SIN5 respectively if GPIO12_SEL and GPIO13_SEL is “0”. See UR6_GP_EN for detail. Full UR5 UR6 Select Register (UR_GP_PROG_EN = 1) ⎯ Index 2Ah (Powered by VSB3V) Name Reserved R/W Default Reserved. Description 80 May, 2010 V0.28P F81865 6 RTS6_2_ALT_EN R/W 0 0: Set this bit “1” will enable RTS6_2# output from DENSEL#/GPIO50/RTS6_2#. 0: Pin 10, Pin 11 will function as MOA#/GPIO51/IRRX_2 and DRVA#/GPIO52/IRTX_2 respectively. 1: Pin 10, Pin 11 will function as SIN6_2 and SOUT6_2 respectively. This bit only has effect if UR6_ALT_EN is “0” 0: Pin 10, Pin 11 will function as MOA#/GPIO51 and DRVA#/GPIO52 respectively. 1: Pin 10, Pin 11 will function as IRRX_2 and IRTX_2 respectively. If 5 UR6_ALT_EN R/W 0 4 IR_ALT_EN R/W 0 IR_ALT_EN is set “1”, the IR receiver input is determined by IRRX2_2. Set this bit will disable FDC and change the following pins to UR6 Modem control pins: WDATA# DIR# 3 UR6_FULL_EN R/W 0 STEP# HDSEL# WGATE# GPIO07 DCD6# CTS6# DTR6# DSR6# RTS6# RI6# See FDC_GP_EN for other FDC pins’ function. Set this bit will enable RTS6# function. 2 RTS6_EN R/W 0 0: GPIO07/RTS6# functions as GPIO07 1: GPIO07/RTS6# functions as RTS6#. Set this bit will disable FDC and change the following pins to UR5 Modem control pins: RDATA# TRK0# 1 UR5_FULL_EN R/W 0 INDEX# WPT# GPIO14 DSKCHG# DCD5# RI5# CTS5# DTR5# DSR5# RTS5# See FDC_GP_EN for other FDC pins’ function. Set this bit will enable RTS5# function. 0 RTS5_EN R/W 0 0: GPIO14/RTS5# functions as GPIO14 1: GPIO14/RTS5# functions as RTS5#. 8.1.14 Bit 7 6 5 4 3 GPIO1 Enable Register ⎯ Index 2Bh (Powered by VSB3V) Name GPIO17_SEL GPIO16_SEL GPIO15_SEL GPIO14_SEL GPIO13_SEL R/W Default R/W R/W R/W R/W R/W 0 0 0 1 1 Description 0: the function of PECI/GPIO17 is PECI. 1: the function of PECI/GPIO17 is GPIO17. 0: the function of BEEP/GPIO16 is BEEP. 1: the function of BEEP/GPIO17 is GPIO16. 0: the function of WDTRST#/GPIO15 is WDTRST#. 1: the function of WDTRST#/GPIO15 is GPIO15. Dummy register. 0: the function of GPIO13/SDA/SIN4 is SDA. 1: the function of GPIO13/SDA/SIN4 is GPIO13. 81 May, 2010 V0.28P F81865 2 1 0 GPIO12_SEL GPIO11_SEL GPIO10_SEL R/W R/W R/W 1 1 1 0: the function of GPIO12/SCL/SOUT4 is SCL. 1: the function of GPIO12/SCL/SOUT4 is GPIO12. 0: the function of GPIO11/VCCLED is VCCLED. 1: the function of GPIO11/VCCLED is GPIO11. 0: the function of GPIO10/VSBLED is VSBLED. 1: the function of GPIO10/VSBLED is GPIO10. 8.1.15 Bit 7 6 5 4 3 2 1 0 GPIO2 Enable Register ⎯ Index 2Ch (Powered by VSB3V) Name GPIO27_SEL GPIO26_SEL GPIO25_SEL GPIO24_SEL GPIO23_SEL GPIO22_SEL GPIO21_SEL GPIO20_SEL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: the function of RSMRST#/GPIO27 is RSMRST#. 1: the function of RSMRST#/GPIO27 is GPIO27. 0: the function of PWROK/GPIO26 is PWROK. 1: the function of PWROK/GPIO27 is GPIO26. 0: the function of PSON#/GPIO25 is PSON#. 1: the function of PSON#/GPIO25 is GPIO25. 0: the function of S3_IN#/GPIO25 is S3_IN#. 1: the function of S3_IN#/GPIO25 is GPIO25. 0: the function of PWSOUT#/GPIO23 is PWSOUT#. 1: the function of PWSOUT#/GPIO23 is GPIO23. 0: the function of PWSIN#/GPIO22 is PWSIN#. 1: the function of PWSIN#/GPIO22 is GPIO22. 0: the function of ATXPG/GPIO21 is ATXPG. 1: the function of ATXPG/GPIO21 is GPIO21. 0: the function of ALERT#/GPIO20 is ALERT#. 1: the function of ALERT#/GPIO20 is GPIO20. 8.1.16 Bit 7 6-4 3 Wakeup Control Register ⎯ Index 2Dh (Powered by VBAT) Name Reserved Reserved WAKEUP_EN R/W Default R/W 1 Reserved Reserved 0: disable KB/Mouse wakeup function. 1: enable KB/Mouse wakeup function. Description 82 May, 2010 V0.28P F81865 Select the keyboard wakeup key. Accompany with KEY_SEL_ADD, there are several key select as list KEY_SEL_ADD 0 0 2-1 KEY_SEL R/W 00 0 0 1 1 1 1 KEY_SEL 00 01 10 11 00 01 10 11 Wake Key Ctrl + Esc Ctrl + F1 Ctrl + Space Any Key Windows Wakeup Key Windows Power Key Ctrl + Alt + Backspace Ctrl + Alt + Delete Select the mouse wakeup key. 0 MO_SEL R/W 0 0: Wakeup by mouse clicking. 1: Wakeup by mouse clicking or movement. 8.2 Bit 7-1 0 FDC Registers (CR00) Name Reserved FDC_EN R/W Default R/W 1 Reserved 0: disable FDC. 1: enable FDC. Description FDC Device Enable Register ⎯ Index 30h Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 03h The MSB of FDC base address. Description Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W F0h The LSB of FDC base address. Description IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELFDCIRQ R/W Default R/W 06h Reserved. Select the IRQ channel for FDC. Description DMA Channel Select Register ⎯ Index 74h Bit 7-3 2-0 Name Reserved SELFDCDMA R/W Default R/W 010 Reserved. Select the DMA channel for FDC. Description FDD Mode Register ⎯ Index F0h Bit 7-5 4 Name Reserved FDC_SW_WP R/W Default R/W 0 Reserved. FDC Software Write Protect. 0: Write protect is determined by WPT# pin. 1: Enable Write Protect. Description 83 May, 2010 V0.28P F81865 3-2 IF_MODE R/W 11 00: Model 30 mode. 01: PS/2 mode. 10: Reserved. 11: AT mode (default). 0: enable burst mode. 1: non-busrt mode (default). Reserved.(Fintek test mode) 1 0 FDMAMODE Reserved R/W R/W 1 0 FDD Drive Type Register ⎯ Index F2h Bit 7-2 1-0 Name Reserved FDD_TYPE R/W Default R/W 11 Reserved. FDD drive type. Description FDD Selection Register ⎯ Index F4h Bit 7-5 Name Reserved R/W Default Reserved. Data rate table select, refer to table A. 00: select regular drives and 2.88 format. 01: reserved. 10: 2 mega tape. 11: reserved. Reserved. Drive type select, refer to table B. Description 4-3 FDD_DRT R/W 00 2 1-0 TABLE A Reserved FDD_DT R/W 00 Data Rate Table Select FDD_DRT[1] FDD_DRT[0] 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 Data Rate DATARATE1 DATARATE0 0 1 0 1 0 1 0 1 0 1 0 1 Selected Data Rate MFM 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K 1Meg FM 250K 150K 125K --250K 250K 125K --250K --125K --- DENSEL 1 0 0 1 1 0 0 1 1 0 0 1 84 May, 2010 V0.28P F81865 TABLE B Drive Type FDD_DT1 0 0 1 1 FDD_DT0 0 1 0 1 DRVDEN0 Remark 4/2/1 MB 3.5” 2/1 MB 5.25” 1/1.6/1 MB 3.5” (3-Mode ) DENSEL DATARATE1 DENSEL# DATARATE0 8.3 Bit 7-1 0 Parallel Port Registers (CR03) Name Reserved PRT_EN R/W Default R/W 1 Reserved 0: disable Parallel Port. 1: enable Parallel Port. Description Parallel Port Device Enable Register ⎯ Index 30h Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 03h Description The MSB of Parallel Port base address. Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W 78h Description The LSB of Parallel Port base address. IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELPRTIRQ R/W Default R/W 7h Reserved. Select the IRQ channel for Parallel Port. Description DMA Channel Select Register ⎯ Index 74h Bit 7-5 4 3 2-0 Name Reserved ECP_DMA_MODE Reserved SELPRTDMA R/W Default R/W R/W 0 011 Reserved. 0: non-burst mode DMA. 1: enable burst mode DMA. Reserved. Select the DMA channel for Parallel Port. Description PRT Mode Select Register ⎯ Index F0h Bit 7 6-3 Name Reserved ECP_FIFO_THR R/W Default R/W 1000 Reserved. ECP FIFO threshold. Description 85 May, 2010 V0.28P F81865 000: Standard and Bi-direction (SPP) mode. 001: EPP 1.9 and SPP mode. 010: ECP mode (default). 011: ECP and EPP 1.9 mode. 100: Printer mode. 101: EPP 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP1.7 mode. 2-0 PRT_MODE R/W 010 8.4 Bit 7-1 0 Hardware Monitor Registers (CR04) Name Reserved HM_EN R/W Default R/W 1 Reserved 0: disable Hardware Monitor. 1: enable Hardware Monitor. Description Hardware Monitor Device Enable Register ⎯ Index 30h Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 02h Description The MSB of Hardware Monitor base address. Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W 95h Description The LSB of Hardware Monitor base address. IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELHMIRQ R/W Default R/W 0000 Reserved. Select the IRQ channel for Hardware Monitor. Description 8.5 Bit 7-1 0 KBC Registers (CR05) Name Reserved KBC_EN R/W Default R/W 1 Reserved 0: disable KBC. 1: enable KBC. Description KBC Device Enable Register ⎯ Index 30h Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 00h Description The MSB of KBC command port address. The address of data port is command port address + 4 Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W 60h Description The LSB of KBC command port address. The address of data port is command port address + 4. KB IRQ Channel Select Register ⎯ Index 70h Bit Name R/W Default R/W 0h Reserved. Select the IRQ channel for keyboard interrupt. Description 7-4 Reserved 3-0 SELKIRQ 86 May, 2010 V0.28P F81865 Mouse IRQ Channel Select Register ⎯ Index 72h Bit Name R/W Default R/W 0h Reserved. Select the IRQ channel for PS/2 mouse interrupt. Description 7-4 Reserved 3-0 SELMIRQ PS/2 Swap Register ⎯ Index FEh (Powered by VBAT) Bit Name R/W Default Description PS/2 auto detect enable. 0: disable auto detect. 1: enable auto detect, KB_MO_SWAP will be updated by hardware after LRESET# de-assert. Reserved Keyboard Mouse Swap. 0: Keyboard/Mouse is not swapped. 1: Keyboard/Mouse is swapped. This bit could be programmed by user. If AUTO_DET_EN is set, this bit is also updated by hardware. Fintek test mode bits. 7 AUTO_DET_EN R/W 0 6-5 Reserved - - 4 KB_MO_SWAP R/W 0 3-0 KBC_TEST_BIT R/W 1h 8.6 GPIO Registers (CR06) *Index Port = Base Address + 5 GPIO Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved GPIO_EN R/W Default R/W 0 Reserved 0: disable GPIO I/O port. 1: enable GPIO I/O port. Description Base Address High Register ⎯ Index 60h Bit Name R/W Default 00h Description The MSB of GPIO I/O port address. 7-0 GP_BASE_ADDR_HI R/W Base Address Low Register ⎯ Index 61h Bit 7-0 Name R/W Default 60h Description The LSB of GPIO I/O port address. GP_BASE_ADDR_L R/W O GPIRQ Channel Select Register ⎯ Index 70h Bit Name R/W Default R/W 0h Reserved. Select the IRQ channel for GPIO interrupt. Description 7-4 Reserved 3-0 SELGPIRQ 87 May, 2010 V0.28P F81865 GPIO0 Output Enable Register ⎯ Index F0h Bit 7 6 5 4 3 2 1 0 Name GPIO07_OE GPIO06_OE GPIO05_OE GPIO04_OE GPIO03_OE GPIO02_OE GPIO01_OE GPIO00_OE R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0: GPIO07 is input. 1: GPIO07 is output. 0: GPIO06 is input. 1: GPIO06 is output. 0: GPIO05 is input. 1: GPIO05 is output. 0: GPIO04 is input. 1: GPIO04 is output. 0: GPIO03 is input. 1: GPIO03 is output. 0: GPIO02 is input. 1: GPIO02 is output. 0: GPIO01 is input. 1: GPIO01 is output. 0: GPIO00 is input. 1: GPIO00 is output. Description GPIO0 Output Data Register ⎯ Index F1h Bit 7 6 5 4 3 2 1 0 Name GPIO07_DATA GPIO06_DATA GPIO05_DATA GPIO04_DATA GPIO03_DATA GPIO02_DATA GPIO01_DATA GPIO00_DATA R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description GPIO07 output data in output mode. GPIO06 output data in output mode. GPIO05 output data in output mode. GPIO04 output data in output mode. GPIO03 output data in output mode. GPIO02 output data in output mode. GPIO01 output data in output mode. GPIO00 output data in output mode. GPIO0 Pin Status Register ⎯ Index F2h Bit 7 6 5 4 3 2 1 0 Name GPIO07_ST GPIO06_ST GPIO05_ST GPIO04_ST GPIO03_ST GPIO02_ST GPIO01_ST GPIO00_ST R/W Default R R R R R R R R 1 1 1 1 1 1 1 1 GPIO07 pin status. GPIO06 pin status. GPIO05 pin status. GPIO04 pin status. GPIO03 pin status. GPIO02 pin status. GPIO01 pin status. GPIO00 pin status. Description 88 May, 2010 V0.28P F81865 GPIO0 Drive Enable Register ⎯ Index F3h Bit 7 Name GPIO07_DRV_EN R/W Default R/W 0 GPIO07 Drive Enable. 0: GPIO07 is open drain. 1: GPIO07 is push pull. GPIO06 Drive Enable. 0: GPIO06 is open drain. 1: GPIO06 is push pull. GPIO05 Drive Enable. 0: GPIO05 is open drain. 1: GPIO05 is push pull. GPIO04 Drive Enable. 0: GPIO04 is open drain. 1: GPIO04 is push pull. GPIO03 Drive Enable. 0: GPIO03 is open drain. 1: GPIO03 is push pull. GPIO02 Drive Enable. 0: GPIO02 is open drain. 1: GPIO02 is push pull. GPIO01 Drive Enable. 0: GPIO01 is open drain. 1: GPIO01 is push pull. GPIO00 Drive Enable. 0: GPIO00 is open drain. 1: GPIO00 is push pull. Description 6 GPIO06_DRV_EN R/W 0 5 GPIO05_DRV_EN R/w 0 4 GPIO04_DRV_EN R/W 0 3 GPIO03_DRV_EN R/W 0 2 GPIO02_DRV_EN R/W 0 1 GPIO01_DRV_EN R/W 0 0 GPIO00_DRV_EN R/W 0 GPIO0 Output Mode 1 Register ⎯ Index F4h Bit Name R/W Default Description GPIO03 output mode select: 00: Level mode. 01: Inverted level mode. 10: High pulse mode. 11: Low pulse mode. The pulse width is determined by GPIO03_PW_SEL. GPIO02 output mode select: 00: Level mode. 01: Inverted level mode. 10: High pulse mode. 11: Low pulse mode. The pulse width is determined by GPIO02_PW_SEL. GPIO01 output mode select: 00: Level mode. 01: Inverted level mode. 10: High pulse mode. 11: Low pulse mode. The pulse width is determined by GPIO01_PW_SEL. 7-6 GPIO03_MODE R/W 00b 5-4 GPIO02_MODE R/w 00b 3-2 GPIO01_MODE R/W 00b 89 May, 2010 V0.28P F81865 1-0 GPIO00_MODE R/W 00b GPIO00 output mode select: 00: Level mode. 01: Inverted level mode. 10: High pulse mode. 11: Low pulse mode. The pulse width is determined by GPIO00_PW_SEL. GPIO0 Output Mode 2 Register ⎯ Index F5h Bit Name R/W Default Description GPIO07 output mode select: 00: Level mode. 01: Inverted level mode. 10: High pulse mode. 11: Low pulse mode. The pulse width is determined by GPIO07_PW_SEL. GPIO06 output mode select: 00: Level mode. 01: Inverted level mode. 10: High pulse mode. 11: Low pulse mode. The pulse width is determined by GPIO06_PW_SEL. GPIO05 output mode select: 00: Level mode. 01: Inverted level mode. 10: High pulse mode. 11: Low pulse mode. The pulse width is determined by GPIO05_PW_SEL. GPIO04 output mode select: 00: Level mode. 01: Inverted level mode. 10: High pulse mode. 11: Low pulse mode. The pulse width is determined by GPIO04_PW_SEL. 7-6 GPIO07_MODE R/W 00b 5-4 GPIO06_MODE R/w 00b 3-2 GPIO05_MODE R/W 00b 1-0 GPIO04_MODE R/W 00b GPIO0 Pulse Width Select 1 Register ⎯ Index F6h Bit Name R/W Default GPIO03 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. GPIO02 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. Description 7-6 GPIO03_PW_SEL R/W 00b 5-4 GPIO02_PW_SEL R/w 00b 90 May, 2010 V0.28P F81865 3-2 GPIO01_PW_SEL R/W 00b GPIO01 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. GPIO00 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. 1-0 GPIO00_PW_SEL R/W 00b GPIO0 Pulse Width Select 2 Register ⎯ Index F7h Bit Name R/W Default GPIO07 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. GPIO06 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. GPIO05 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. GPIO04 pulse width select: 00: 500us. 01: 1ms. 10: 20ms. 11: 100ms. Description 7-6 GPIO07_PW_SEL R/W 00b 5-4 GPIO06_PW_SEL R/w 00b 3-2 GPIO05_PW_SEL R/W 00b 1-0 GPIO04_PW_SEL R/W 00b GPIO0 Interrupt Enable Register ⎯ Index F8h Bit 7 6 5 4 3 Name GPIO07_INT_EN GPIO06_INT_EN GPIO05_INT_EN GPIO04_INT_EN GPIO03_INT_EN R/W Default R/W R/W R/W R/W R/W 0b 0b 0b 0b 0b Description 0: disable GPIO07 interrupt 1: enable GPIO07 interrupt when GPIO07_INT_ST is set. 0: disable GPIO06 interrupt 1: enable GPIO06 interrupt when GPIO06_INT_ST is set. 0: disable GPIO05 interrupt 1: enable GPIO05 interrupt when GPIO05_INT_ST is set. 0: disable GPIO04 interrupt 1: enable GPIO04 interrupt when GPIO04_INT_ST is set. 0: disable GPIO03 interrupt 1: enable GPIO03 interrupt when GPIO03_INT_ST is set. 91 May, 2010 V0.28P F81865 2 1 0 GPIO02_INT_EN GPIO01_INT_EN GPIO00_INT_EN R/W R/W R/W 0b 0b 0b 0: disable GPIO02 interrupt 1: enable GPIO02 interrupt when GPIO02_INT_ST is set. 0: disable GPIO01 interrupt 1: enable GPIO01 interrupt when GPIO01_INT_ST is set. 0: disable GPIO00 interrupt 1: enable GPIO00 interrupt when GPIO00_INT_ST is set. GPIO0 Interrupt Status Register ⎯ Index F9h Bit Name R/W Default Description This bit only works when GPIO07 is in input mode. 0: no change at GPIO07 input. 1: change had occurred at GPIO07 input. Write “1” to this bit to clear. This bit only works when GPIO06 is in input mode. 0: no change at GPIO06 input. 1: change had occurred at GPIO06 input. Write “1” to this bit to clear. This bit only works when GPIO05 is in input mode. 0: no change at GPIO05 input. 1: change had occurred at GPIO05 input. Write “1” to this bit to clear. This bit only works when GPIO04 is in input mode. 0: no change at GPIO04 input. 1: change had occurred at GPIO04 input. Write “1” to this bit to clear. This bit only works when GPIO03 is in input mode. 0: no change at GPIO03 input. 1: change had occurred at GPIO03 input. Write “1” to this bit to clear. This bit only works when GPIO02 is in input mode. 0: no change at GPIO02 input. 1: change had occurred at GPIO02 input. Write “1” to this bit to clear. This bit only works when GPIO01 is in input mode. 0: no change at GPIO01 input. 1: change had occurred at GPIO01 input. Write “1” to this bit to clear. This bit only works when GPIO00 is in input mode. 0: no change at GPIO00 input. 1: change had occurred at GPIO00 input. Write “1” to this bit to clear. 7 GPIO07_INT_ST R/W 0b 6 GPIO06_INT_ST R/W 0b 5 GPIO05_INT_ST R/W 0b 4 GPIO04_INT_ST R/W 0b 3 GPIO03_INT_ST R/W 0b 2 GPIO02_INT_ST R/W 0b 1 GPIO01_INT_ST R/W 0b 0 GPIO00_INT_ST R/W 0b GPIO1 Output Enable Register ⎯ Index E0h Bit 7 Name GPIO17_OE R/W Default R/W 0 0: GPIO17 is in input mode. 1: GPIO17 is in output mode. Description 92 May, 2010 V0.28P F81865 6 5 4 3 2 1 0 GPIO16_OE GPIO15_OE GPIO14_OE GPIO13_OE GPIO12_OE GPIO11_OE GPIO10_OE R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0: GPIO16 is in input mode. 1: GPIO16 is in output mode. 0: GPIO15 is in input mode. 1: GPIO15 is in output mode. 0: GPIO14 is in input mode. 1: GPIO14 is in output mode. 0: GPIO13 is in input mode. 1: GPIO13 is in output mode. 0: GPIO12 is in input mode. 1: GPIO12 is in output mode. 0: GPIO11 is in input mode. 1: GPIO11 is in output mode. 0: GPIO10 is in input mode. 1: GPIO10 is in output mode. GPIO1 Output Data Register ⎯ Index E1h Bit 7 6 5 4 3 2 1 0 Name GPIO17_VAL GPIO16_VAL GPIO15_VAL GPIO14_VAL GPIO13_VAL GPIO12_VAL GPIO11_VAL GPIO10_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description 0: GPIO17 outputs 0 when in output mode. 1: GPIO17 outputs1 when in output mode. 0: GPIO16 outputs 0 when in output mode. 1: GPIO16 outputs1 when in output mode. 0: GPIO15 outputs 0 when in output mode. 1: GPIO15 outputs 1 when in output mode. 0: GPIO14 outputs 0 when in output mode. 1: GPIO14 outputs 1 when in output mode. 0: GPIO13 outputs 0 when in output mode. 1: GPIO13 outputs 1 when in output mode. 0: GPIO12 outputs 0 when in output mode. 1: GPIO12 outputs 1 when in output mode. 0: GPIO11 outputs 0 when in output mode. 1: GPIO11 outputs 1 when in output mode. 0: GPIO10 outputs 0 when in output mode. 1: GPIO10 outputs 1 when in output mode. GPIO1 Pin Status Register ⎯ Index E2h Bit 7 6 5 4 3 2 1 0 Name GPIO17_IN GPIO16_IN GPIO15_IN GPIO14_IN GPIO13_IN GPIO12_IN GPIO11_IN GPIO10_IN R/W Default R R R R R R R R The pin status of GPIO17. The pin status of GPIO16. The pin status of GPIO15. The pin status of GPIO14. The pin status of GPIO13. The pin status of GPIO12. The pin status of GPIO11. The pin status of GPIO10. Description 93 May, 2010 V0.28P F81865 GPIO1 Drive Enable Register ⎯ Index E3h Bit 7 6 5 4 3 2 1 0 Name GPIO17_DRV_EN GPIO16_DRV_EN GPIO15_DRV_EN GPIO14_DRV_EN GPIO13_DRV_EN GPIO12_DRV_EN GPIO11_DRV_EN GPIO10_DRV_EN R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: GPIO17 is open drain in output mode. 1: GPIO17 is push pull in output mode. 0: GPIO16 is open drain in output mode. 1: GPIO16 is push pull in output mode. 0: GPIO15 is open drain in output mode. 1: GPIO15 is push pull in output mode. 0: GPIO14 is open drain in output mode. 1: GPIO14 is push pull in output mode. 0: GPIO13 is open drain in output mode. 1: GPIO13 is push pull in output mode. 0: GPIO12 is open drain in output mode. 1: GPIO12 is push pull in output mode. 0: GPIO11 is open drain in output mode. 1: GPIO11 is push pull in output mode. 0: GPIO10 is open drain in output mode. 1: GPIO10 is push pull in output mode. LED S3 Mode Register ⎯ Index EFh Bit 7 6-4 Name R/W Default 0 Description 0: VSBLED_S3_MODE & VCCLED_S3_MODE are disabled. 1: VSBLED_S3_MODE & VCCLED_S3_MODE are enabled. Reserved. VSBLED mode in S3 state. 00: VSBLED drives low. 3-2 VSBLED_S3_MODE R/W 2’b00 01: VSBLED is tri-state. 10: VSBLED drives a 0.5HZ clock. 11: VSBLED drives a 1HZ clock. (Clock output is inversed with VCCLED clock output). VCCLED mode in S3 state. 00: VCCLED drives low. 1-0 VCCLED_S3_MODE R/W 2’b00 01: VCCLED is tri-state. 10: VCCLED drives a 0.5HZ clock. 11: VCCLED drives a 1HZ clock. (Clock output is inversed with VSBLED clock output). GPIO2 Output Enable Register ⎯ Index D0h Bit 7 6 5 Name GPIO27_OE GPIO26_OE GPIO25_OE R/W Default R/W R/W R/W 0 0 0 0: GPIO27 is in input mode. 1: GPIO27 is in output mode. 0: GPIO26 is in input mode. 1: GPIO26 is in output mode. 0: GPIO25 is in input mode. 1: GPIO25 is in output mode. Description LED_S3_MODE_EN R/W Reserved - 94 May, 2010 V0.28P F81865 4 3 2 1 0 GPIO24_OE GPIO23_OE GPIO22_OE GPIO21_OE GPIO20_OE R/W R/W R/W R/W R/W 0 0 0 0 0 0: GPIO24 is in input mode. 1: GPIO24 is in output mode. 0: GPIO23 is in input mode. 1: GPIO23 is in output mode. 0: GPIO22 is in input mode. 1: GPIO22 is in output mode. 0: GPIO21 is in input mode. 1: GPIO21 is in output mode. 0: GPIO20 is in input mode. 1: GPIO20 is in output mode. GPIO2 Output Data Register ⎯ Index D1h Bit 7 6 5 4 3 2 1 0 Name GPIO27_VAL GPIO26_VAL GPIO25_VAL GPIO24_VAL GPIO23_VAL GPIO22_VAL GPIO21_VAL GPIO20_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description 0: GPIO27 outputs 0 when in output mode. 1: GPIO27 outputs1 when in output mode. 0: GPIO26 outputs 0 when in output mode. 1: GPIO26 outputs1 when in output mode. 0: GPIO25 outputs 0 when in output mode. 1: GPIO25 outputs 1 when in output mode. 0: GPIO24 outputs 0 when in output mode. 1: GPIO24 outputs 1 when in output mode. 0: GPIO23 outputs 0 when in output mode. 1: GPIO23 outputs 1 when in output mode. 0: GPIO22 outputs 0 when in output mode. 1: GPIO22 outputs 1 when in output mode. 0: GPIO21 outputs 0 when in output mode. 1: GPIO21 outputs 1 when in output mode. 0: GPIO20 outputs 0 when in output mode. 1: GPIO20 outputs 1 when in output mode. GPIO2 Pin Status Register ⎯ Index D2h Bit 7 6 5 4 3 2 1 0 Name GPIO27_IN GPIO26_IN GPIO25_IN GPIO24_IN GPIO23_IN GPIO22_IN GPIO21_IN GPIO20_IN R/W Default R R R R R R R R Description The pin status of RSMRST#/GPIO27. The pin status of PWOK/GPIO26. The pin status of PS_ON#/GPIO25. The pin status of S3#/GPIO24. The pin status of PWSOUT#/GPIO23. The pin status of PWSIN#/GPIO22. The pin status of ATXPG_IN#/GPIO21. The pin status of ALERT#/GPIO20. GPIO2 Drive Enable Register ⎯ Index D3h Bit 7 Name GPIO27_DRV_EN R/W Default R/W 0 Description 0: GPIO27 is open drain in output mode. 1: GPIO27 is push pull in output mode. 95 May, 2010 V0.28P F81865 6 5 4 3 2 1 0 GPIO26_DRV_EN GPIO25_DRV_EN GPIO24_DRV_EN GPIO23_DRV_EN GPIO22_DRV_EN GPIO21_DRV_EN GPIO20_DRV_EN R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0: GPIO26 is open drain in output mode. 1: GPIO26 is push pull in output mode. 0: GPIO25 is open drain in output mode. 1: GPIO25 is push pull in output mode. 0: GPIO24 is open drain in output mode. 1: GPIO24 is push pull in output mode. 0: GPIO23 is open drain in output mode. 1: GPIO23 is push pull in output mode. 0: GPIO22 is open drain in output mode. 1: GPIO22 is push pull in output mode. 0: GPIO21 is open drain in output mode. 1: GPIO21 is push pull in output mode. 0: GPIO20 is open drain in output mode. 1: GPIO20 is push pull in output mode. GPIO3 Output Enable Register ⎯ Index C0h Bit 7 6 5 4 3 2 1 0 Name GPIO37_OE GPIO36_OE GPIO35_OE GPIO34_OE GPIO33_OE GPIO32_OE GPIO31_OE GPIO30_OE R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0: GPIO37 is input. 1: GPIO37 is output. 0: GPIO36 is input. 1: GPIO36 is output. 0: GPIO35 is input. 1: GPIO35 is output. 0: GPIO34 is input. 1: GPIO34 is output. 0: GPIO33 is input. 1: GPIO33 is output. 0: GPIO32 is input. 1: GPIO32 is output. 0: GPIO31 is input. 1: GPIO31 is output. 0: GPIO30 is input. 1: GPIO30 is output. Description GPIO3 Output Data Register ⎯ Index C1h Bit 7 6 5 4 3 2 1 0 Name GPIO37_DATA GPIO36_DATA GPIO35_DATA GPIO34_DATA GPIO33_DATA GPIO32_DATA GPIO31_DATA GPIO30_DATA R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description GPIO37 output data in output mode. GPIO36 output data in output mode. GPIO35 output data in output mode. GPIO34 output data in output mode. GPIO33 output data in output mode. GPIO32 output data in output mode. GPIO31 output data in output mode. GPIO30 output data in output mode. 96 May, 2010 V0.28P F81865 GPIO3 Pin Status Register ⎯ Index C2h Bit 7 6 5 4 3 2 1 0 Name GPIO37_ST GPIO36_ST GPIO35_ST GPIO34_ST GPIO33_ST GPIO32_ST GPIO31_ST GPIO30_ST R/W Default R R R R R R R R 1 1 1 1 1 1 1 1 GPIO37 pin status. GPIO36 pin status. GPIO35 pin status. GPIO34 pin status. GPIO33 pin status. GPIO32 pin status. GPIO31 pin status. GPIO30 pin status. Description GPIO3 Drive Enable Register ⎯ Index C3h Bit 7 Name GPIO37_DRV_EN R/W Default R/W 0 GPIO37 Drive Enable. 0: GPIO37 is open drain. 1: GPIO37 is push pull. GPIO36 Drive Enable. 0: GPIO36 is open drain. 1: GPIO36 is push pull. GPIO35 Drive Enable. 0: GPIO35 is open drain. 1: GPIO35 is push pull. GPIO34 Drive Enable. 0: GPIO34 is open drain. 1: GPIO34 is push pull. GPIO33 Drive Enable. 0: GPIO33 is open drain. 1: GPIO33 is push pull. GPIO32 Drive Enable. 0: GPIO32 is open drain. 1: GPIO32 is push pull. GPIO31 Drive Enable. 0: GPIO31 is open drain. 1: GPIO31 is push pull. GPIO30 Drive Enable. 0: GPIO30 is open drain. 1: GPIO30 is push pull. Description 6 GPIO36_DRV_EN R/W 0 5 GPIO35_DRV_EN R/w 0 4 GPIO34_DRV_EN R/W 0 3 GPIO33_DRV_EN R/W 0 2 GPIO32_DRV_EN R/W 0 1 GPIO31_DRV_EN R/W 0 0 GPIO30_DRV_EN R/W 0 GPIO4 Output Enable Register ⎯ Index B0h Bit 7 6 5 Name GPIO47_OE GPIO46_OE GPIO45_OE R/W Default R/W R/W R/W 0 0 0 0: GPIO47 is input. 1: GPIO47 is output. 0: GPIO46 is input. 1: GPIO46 is output. 0: GPIO45 is input. 1: GPIO45 is output. Description 97 May, 2010 V0.28P F81865 4 3 2 1 0 GPIO44_OE GPIO43_OE GPIO42_OE GPIO41_OE GPIO40_OE R/W R/W R/W R/W R/W 0 0 0 0 0 0: GPIO44 is input. 1: GPIO44 is output. 0: GPIO43 is input. 1: GPIO43 is output. 0: GPIO42 is input. 1: GPIO42 is output. 0: GPIO41 is input. 1: GPIO41 is output. 0: GPIO40 is input. 1: GPIO40 is output. GPIO4 Output Data Register ⎯ Index B1h Bit 7 6 5 4 3 2 1 0 Name GPIO47_DATA GPIO46_DATA GPIO45_DATA GPIO44_DATA GPIO43_DATA GPIO42_DATA GPIO41_DATA GPIO40_DATA R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description GPIO47 output data in output mode. GPIO46 output data in output mode. GPIO45 output data in output mode. GPIO44 output data in output mode. GPIO43 output data in output mode. GPIO42 output data in output mode. GPIO41 output data in output mode. GPIO40 output data in output mode. GPIO4 Pin Status Register ⎯ Index B2h Bit 7 6 5 4 3 2 1 0 Name GPIO47_ST GPIO46_ST GPIO45_ST GPIO44_ST GPIO43_ST GPIO42_ST GPIO41_ST GPIO40_ST R/W Default R R R R R R R R 1 1 1 1 1 1 1 1 GPIO47 pin status. GPIO46 pin status. GPIO45 pin status. GPIO44 pin status. GPIO43 pin status. GPIO42 pin status. GPIO41 pin status. GPIO40 pin status. Description GPIO4 Drive Enable Register ⎯ Index B3h Bit 7 Name GPIO47_DRV_EN R/W Default R/W 0 GPIO47 Drive Enable. 0: GPIO47 is open drain. 1: GPIO47 is push pull. GPIO46 Drive Enable. 0: GPIO46 is open drain. 1: GPIO46 is push pull. GPIO45 Drive Enable. 0: GPIO45 is open drain. 1: GPIO45 is push pull. Description 6 GPIO46_DRV_EN R/W 0 5 GPIO45_DRV_EN R/w 0 98 May, 2010 V0.28P F81865 4 GPIO44_DRV_EN R/W 0 GPIO44 Drive Enable. 0: GPIO44 is open drain. 1: GPIO44 is push pull. GPIO43 Drive Enable. 0: GPIO43 is open drain. 1: GPIO43 is push pull. GPIO42 Drive Enable. 0: GPIO42 is open drain. 1: GPIO42 is push pull. GPIO41 Drive Enable. 0: GPIO41 is open drain. 1: GPIO41 is push pull. GPIO40 Drive Enable. 0: GPIO40 is open drain. 1: GPIO40 is push pull. 3 GPIO43_DRV_EN R/W 0 2 GPIO42_DRV_EN R/W 0 1 GPIO41_DRV_EN R/W 0 0 GPIO40_DRV_EN R/W 0 GPIO5 Output Enable Register ⎯ Index A0h Bit 7 6 5 4 3 2 1 0 Name GPIO57_OE GPIO56_OE GPIO55_OE GPIO54_OE GPIO53_OE GPIO52_OE GPIO51_OE GPIO50_OE R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0: GPIO57 is input. 1: GPIO57 is output. 0: GPIO56 is input. 1: GPIO56 is output. 0: GPIO55 is input. 1: GPIO55 is output. 0: GPIO54 is input. 1: GPIO54 is output. 0: GPIO53 is input. 1: GPIO53 is output. 0: GPIO52 is input. 1: GPIO52 is output. 0: GPIO51 is input. 1: GPIO51 is output. 0: GPIO50 is input. 1: GPIO50 is output. Description GPIO5 Output Data Register ⎯ Index A1h Bit 7 6 5 4 3 2 1 0 Name GPIO57_DATA GPIO56_DATA GPIO55_DATA GPIO54_DATA GPIO53_DATA GPIO52_DATA GPIO51_DATA GPIO50_DATA R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description GPIO57 output data in output mode. GPIO56 output data in output mode. GPIO55 output data in output mode. GPIO54 output data in output mode. GPIO53 output data in output mode. GPIO52 output data in output mode. GPIO51 output data in output mode. GPIO50 output data in output mode. 99 May, 2010 V0.28P F81865 GPIO5 Pin Status Register ⎯ Index A2h Bit 7 6 5 4 3 2 1 0 Name GPIO57_ST GPIO56_ST GPIO55_ST GPIO54_ST GPIO53_ST GPIO52_ST GPIO51_ST GPIO50_ST R/W Default R R R R R R R R 1 1 1 1 1 1 1 1 GPIO57 pin status. GPIO56 pin status. GPIO55 pin status. GPIO54 pin status. GPIO53 pin status. GPIO52 pin status. GPIO51 pin status. GPIO50 pin status. Description GPIO5 Drive Enable Register ⎯ Index A3h Bit 7 Name GPIO57_DRV_EN R/W Default R/W 0 GPIO57 Drive Enable. 0: GPIO57 is open drain. 1: GPIO57 is push pull. GPIO56 Drive Enable. 0: GPIO56 is open drain. 1: GPIO56 is push pull. GPIO55 Drive Enable. 0: GPIO55 is open drain. 1: GPIO55 is push pull. GPIO54 Drive Enable. 0: GPIO54 is open drain. 1: GPIO54 is push pull. GPIO53 Drive Enable. 0: GPIO53 is open drain. 1: GPIO53 is push pull. GPIO52 Drive Enable. 0: GPIO52 is open drain. 1: GPIO52 is push pull. GPIO51 Drive Enable. 0: GPIO51 is open drain. 1: GPIO51 is push pull. GPIO50 Drive Enable. 0: GPIO50 is open drain. 1: GPIO50 is push pull. Description 6 GPIO56_DRV_EN R/W 0 5 GPIO55_DRV_EN R/w 0 4 GPIO54_DRV_EN R/W 0 3 GPIO53_DRV_EN R/W 0 2 GPIO52_DRV_EN R/W 0 1 GPIO51_DRV_EN R/W 0 0 GPIO50_DRV_EN R/W 0 GPIO6 Output Enable Register ⎯ Index 90h Bit 7-5 4 3 Name Reserved GPIO64_OE GPIO63_OE R/W Default R/W R/W 0 0 Reserved. 0: GPIO64 is input. 1: GPIO64 is output. 0: GPIO63 is input. 1: GPIO63 is output. Description 100 May, 2010 V0.28P F81865 2 1 0 GPIO62_OE GPIO61_OE GPIO60_OE R/W R/W R/W 0 0 0 0: GPIO62 is input. 1: GPIO62 is output. 0: GPIO61 is input. 1: GPIO61 is output. 0: GPIO60 is input. 1: GPIO60 is output. GPIO6 Output Data Register ⎯ Index 91h Bit 7-5 4 3 2 1 0 Name Reserved GPIO64_DATA GPIO63_DATA GPIO62_DATA GPIO61_DATA GPIO60_DATA R/W Default R/W R/W R/W R/W R/W 1 1 1 1 1 Reserved. GPIO64 output data in output mode. GPIO63 output data in output mode. GPIO62 output data in output mode. GPIO61 output data in output mode. GPIO60 output data in output mode. Description GPIO6 Pin Status Register ⎯ Index 92h Bit 7-5 4 3 2 1 0 Name Reserved GPIO64_ST GPIO63_ST GPIO62_ST GPIO61_ST GPIO60_ST R/W Default R R R R R 1 1 1 1 1 Reserved. GPIO64 pin status. GPIO63 pin status. GPIO62 pin status. GPIO61 pin status. GPIO60 pin status. Description GPIO6 Drive Enable Register ⎯ Index 93h Bit 7-5 4 Name Reserved GPIO64_DRV_EN R/W Default R/W 0 Reserved. GPIO64 Drive Enable. 0: GPIO64 is open drain. 1: GPIO64 is push pull. GPIO63 Drive Enable. 0: GPIO63 is open drain. 1: GPIO63 is push pull. GPIO62 Drive Enable. 0: GPIO62 is open drain. 1: GPIO62 is push pull. GPIO61 Drive Enable. 0: GPIO61 is open drain. 1: GPIO61 is push pull. GPIO60 Drive Enable. 0: GPIO60 is open drain. 1: GPIO60 is push pull. Description 3 GPIO63_DRV_EN R/W 0 2 GPIO62_DRV_EN R/W 0 1 GPIO61_DRV_EN R/W 0 0 GPIO60_DRV_EN R/W 0 101 May, 2010 V0.28P F81865 8.7 Bit 7-1 0 WDT Registers (CR07) Name Reserved WDT_EN R/W Default R/W 0 0 Reserved 0: disable WDT base address. 1: enable WDT base address. Description WDT Device Base Address Enable Register ⎯ Index 30h Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 00h The MSB of WDT base address. Description Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W 00h The LSB of WDT base address. Description Watchdog Control Configuration Register 1 ⎯ Index F5h Bit 7 6 5 4 3 2 1-0 Name Reserved WDTMOUT_STS WD_EN WD_PULSE WD_UNIT WD_HACTIVE WD_PSWIDTH R/W Default R R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Reserved If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to this bit will clear it to 0. If this bit is set to 1, the counting of watchdog time is enabled. Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit. Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. Select output polarity of RSTOUT# (1: high active, 0: low active) by setting this bit. Select output pulse width of RSTOUT# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec Description Time of watchdog timer (0~255) Description Watchdog Timer Configuration Register 2 ⎯ Index F6h Bit 7-0 Name WD_TIME R/W Default R/W 0 Watchdog PME Enable Configuration Register 2 ⎯ Index FAh Bit 7 6 5-1 0 Name WDT_PME WDT_PME_EN Reserved WDOUT_EN R/W Default R R/W -R/W -0 -0 Description The PME Status. This bit will set when WDT_PME_EN is set and the watchdog timer is 1 unit before time out (or time out). 0: Disable Watchdog PME. 1: enable Watchdog PME. Reserved. 0: disable Watchdog time out output via WDTRST#. 1: enable Watchdog time out output via WDTRST#. 8.8 Bit 7-6 5 SPI Registers (CR08) Name Reserved SPTIE R/W Default R/W 0 Reserved. SPI interrupt enable. Set to 1, SPIE enabled, set to 0 SPIE disabled. Description SPI Control Register ⎯ Index F0h 102 May, 2010 V0.28P F81865 4 MSTR R/W 1 Master mode select. Set to 1, SPI function is master mode; set to 0 is disable SPI function Clock polarity this bit selects inverted or non-inverted SPI clock. Set to 1, active low clock selected; SCK idles high. Set to 0, active high clock selected; SCK idles low. Clock phase. This bit is used to shift the SCK serial clock. Set to 1, the first SCK edge is issued at the beginning of the transfer operation. Set to 0, the first SCK edge is issued one-half cycle into the transfer operation. Reserved This bit control data shift from LSB or MSB. Set to 1, data is transferred from LSB to MSB. Set to 0, data is transferred from MSB to LSB. 3 CPOL R/W 0 2 1 0 CPHA Reserved LSBFE R/W R/W 0 0 0 Reserved ⎯ Index F1h Bit 7-0 Name Reserved R/W Default Reserved Description SPI Baud Rate Divisor Register ⎯ Index F2h Bit 7-3 2-0 Name Reserved Baud_val R/W Default R/W 1 1 Reserved This register decides to SCK frequency. Baud rate divisor equation is 2^ (Baud_val + 1) Description SPI Status Register ⎯ Index F3h Bit 7 6-4 3 2-0 Name SPIE Reserved SPTEF Reserved R/W Default R/W R/W R 0 0 Description SPI interrupt status. When SPI is transferred or received data from device finish, this bit will be set. Write 1 to clear this bit. Reserved. SPI operation status. When SPI is transferred or received data from device, this bit will be set 1, Clear by SPI operation finish. Reserved SPI High Byte Data Register ⎯ Index F4h Bit 7-0 Name H_DATA R/W Default R 0 Description When SPI is received 16 bits data from device. This register saves high byte data. SPI command data Register ⎯ Index F5h Bit 7-0 Name CMD_DATA R/W Default R/W 0 Description This register provides command value for flash command. SPI chip select Register ⎯ Index F6h Bit 7-2 1 0 Name Reserved CS1 CS0 R/W Default R/W R/W 0 0 Reserved Chip select 1. To select device 1 Chip select 0. To select device 0 Description SPI memory mapping Register ⎯ Index F7h Bit 7-3 Name Reserved R/W Default 0 Reserved Description 103 May, 2010 V0.28P F81865 2-0 Mem_map R/W This register decides memory size. 3’b000: 512k bit. 3’b001: 1024k bit. 3’b100: 2048k bit. 3’b011: 4096k bit. 3’b100: 8092k bit. SPI operate Register ⎯ Index F8h Bit 7 Name TYPE R/W Default R/W 0 Description This bit decide flash continuous programming mode. Set to 1, if programming continuous mode is same as the SST flash. Set to 0 if programming continuous mode is same as the ATMEL flash This bit control SPI function transfer 8 bit command to device. Clear 0 by operation finish. This bit control SPI function read status from to device. Clear 0 by operation finish. This bit control SPI function write status to device. Clear 0 by operation finish. This bit control SPI function sector erase device. Clear 0 by operation finish. This bit control SPI function read id from device. Clear 0 by operation finish. This bit control SPI function program data to device or set to 1 when memory cycle for LPC interface program flash. Clear 0 by operation finish. This bit control SPI function read data from device or set to 1 when memory cycle for LPC interface read flash. Clear 0 by operation finish. 6 5 4 3 2 1 0 IO_SPI RDSR WRSR SECTOR_ERASE READ_ID PROG READ R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 SPI Low Byte Data Register ⎯ Index FAh Bit 7-0 Name L_DATA R/W Default R 0 Description When SPI is received 16 bits or 8 bits data from device. This register saves low byte data. SPI address high byte Register ⎯ Index FBh Bit 7-0 Name Addr_H_byte R/W Default R/W 0 Description This register provides high byte address for sector erase, program, read operation. SPI address medium byte Register ⎯ Index FCh Bit 7-0 Name Addr_M_byte R/W Default R/W 0 Description This register provides medium byte address for sector erase, program, read operation. SPI address low byte Register ⎯ Index FDh Bit 7-0 Name Addr_L_byte R/W Default R/W 0 Description This register provides low byte address for sector erase, program, read operation. SPI program byte Register ⎯ Index FEh Bit 7-0 Name PORG_BYTE R/W Default R/W 0 Description This register provides number to program flash for continuous mode. SPI write data Register ⎯ Index FFh Bit 7-0 Name WR_dat R/W Default R/W 0 Description This register provides data to write flash for program, write status function. 104 May, 2010 V0.28P F81865 8.9 Bit 7-1 0 PME and ACPI Registers (CR0A) Name Reserved PME_EN R/W Default R/W 0 Reserved 0: disable PME. 1: enable PME. Description Device Enable Register ⎯ Index 30h PME Event Enable 1 Register ⎯ Index F0h Bit 7 6 Name Reserved WDT_PME_EN R/W Default R/W 0 Reserved Watchdog PME event enable. 0: disable watchdog PME event. 1: enable watchdog PME event. GPIO PME event enable. 0: disable GPIO PME event. 1: enable GPIO PME event. Mouse PME event enable. 0: disable mouse PME event. 1: enable mouse PME event. Keyboard PME event enable. 0: disable keyboard PME event. 1: enable keyboard PME event. Hardware monitor PME event enable. 0: disable hardware monitor PME event. 1: enable hardware monitor PME event. Parallel port PME event enable. 0: disable parallel port PME event. 1: enable parallel port PME event. FDC PME event enable. 0: disable FDC PME event. 1: enable FDC PME event. Description 5 GP_PME_EN R/W 0 4 MO_PME_EN R/W 0 3 KB_PME_EN R/W 0 2 HM_PME_EN R/W 0 1 PRT_PME_EN R/W 0 0 FDC_PME_EN R/W 0 PME Event Enable 2 Register ⎯ Index F1h Bit 7-6 5 Name Reserved UR6_PME_EN R/W Default R/W 0 Reserved UART 6 PME event enable. 0: disable UART 6 PME event. 1: enable UART 6 PME event. UART 5 PME event enable. 0: disable UART 5 PME event. 1: enable UART 5 PME event. UART 4 PME event enable. 0: disable UART 4 PME event. 1: enable UART 4 PME event. UART 3 PME event enable. 0: disable UART 3 PME event. 1: enable UART 3 PME event. Description 4 UR5_PME_EN R/W 0 3 UR4_PME_EN R/W 0 2 UR3_PME_EN R/W 0 105 May, 2010 V0.28P F81865 1 UR2_PME_EN R/W 0 UART 2 PME event enable. 0: disable UART 2 PME event. 1: enable UART 2 PME event. UART 1 PME event enable. 0: disable UART 1 PME event. 1: enable UART 1 PME event. 0 UR1_PME_EN R/W 0 PME Event Status 1 Register ⎯ Index F2h Bit 7 Name Reserved R/W Default Reserved Watchdog PME event status. 0: Watchdog has no PME event. 1: Watchdog has a PME event to assert. Write 1 to clear to be ready for next PME event. GPIO PME event status. 0: GPIO has no PME event. 1: GPIO has a PME event to assert. Write 1 to clear to be ready for next PME event. Mouse PME event status. 0: Mouse has no PME event. 1: Mouse has a PME event to assert. Write 1 to clear to be ready for next PME event. Keyboard PME event status. 0: Keyboard has no PME event. 1: Keyboard has a PME event to assert. Write 1 to clear to be ready for next PME event. Hardware monitor PME event status. 0: Hardware monitor has no PME event. 1: Hardware monitor has a PME event to assert. Write 1 to clear to be ready for next PME event. Parallel port PME event status. 0: Parallel port has no PME event. 1: Parallel port has a PME event to assert. Write 1 to clear to be ready for next PME event. FDC PME event status. 0: FDC has no PME event. 1: FDC has a PME event to assert. Write 1 to clear to be ready for next PME event. Description 6 WDT_PME_ST R/W - 5 GP_PME_ST R/W - 4 MO_PME_ST R/W - 3 KB_PME_ST R/W - 2 HM_PME_ST R/W - 1 PRT_PME_ST R/W - 0 FDC_PME_ST R/W - PME Event Status 1 Register ⎯ Index F3h Bit 7-6 Name Reserved R/W Default Reserved UART 6 PME event status. 0: UART 6 has no PME event. 1: UART 6 has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 5 PME event status. 0: UART 5 has no PME event. 1: UART 5 has a PME event to assert. Write 1 to clear to be ready for next PME event. Description 5 UR6_PME_ST R/W - 4 UR5_PME_ST R/W - 106 May, 2010 V0.28P F81865 3 UR4_PME_ST R/W UART 4 PME event status. 0: UART 4 has no PME event. 1: UART 4 has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 3 PME event status. 0: UART 3 has no PME event. 1: UART 3 has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 2 PME event status. 0: UART 2 has no PME event. 1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 1 PME event status. 0: UART 1 has no PME event. 1: UART 1 has a PME event to assert. Write 1 to clear to be ready for next PME event. 2 UR3_PME_ST R/W - 1 UR2_PME_ST R/W - 0 UR1_PME_ST R/W - ACPI Control Register ⎯ Index F4h Bit 7 6 5 4 3 Name TS3 SPI_RST_EN KEY_SEL_ADD EN_KBWAKEUP EN_MOWAKEUP R/W Default R/W R/W R/W R/W R/W 0 0 0 0 0 Description KBC S3 test mode register. (Fintek only) Set one to force KBC into S3 state. 0: disable SPI time out reset via PWROK. 1: enable SPI time out reset via PWROK. See KEY_SEL for detail. Set one to enable keyboard wakeup event asserted via PWSOUT#. Set one to enable mouse wakeup event asserted via PWSOUT#. The ACPI Control the PSON_N to the following stages 00 : keep last state 01 :Bypass mode (Always on without PSOUT#) 10 : Always on 11: Always off When VSB 3V comes, it will set to 1 (default). Then write 1 to clear it. 2-1 PWRCTRL R/W 11 0 VSB_PWR_LOSS R/W 0 ACPI Control Register ⎯ Index F5h Bit 7 Name SOFT_RST_ACPI R/W Default R/W 0 PWROK additional delay. 00: 0ms 01: 100ms. 10: 200ms. 11: 400ms. The PWROK delay timing from VDD3VOK by followed setting 4-3 DELAY R/W 11 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms Enable the PCIRSTIN_N and ATXPWGD de-bounce. Reserved Description Software Reset to ACPI (auto clear after reset) 6-5 PWROK_DELAY R/W 00 2 1-0 VINDB_EN Reserved R/W - 1 - 107 May, 2010 V0.28P F81865 ACPI Control Register ⎯ Index F6h Bit 7 6-5 4 3-2 1 0 Name S3_SEL Reserved PSON_DEL_EN Reserved BYPASS_DB_ACPI TEST_PWR_EN R/W Default R/W R/W R/W R/W 0 0 0 0 Description 0: The S3 state for KBC is controlled by VDD3VOK. 1: The S3 state for KBC is force to 1 or inverted of S3# select by TS3. Reserved. PSON# delay enable. 0: PSON# is the invert of S3#. 1: PSON# will delay 4 seconds to turn on after last turn off. Reserved Disable all the de-bounce circuit. For testing only. 8.10 RTC Registers (CR0B) Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved RTC_EN R/W Default R/W 0 Reserved 0: disable RTC I/O access. 1: enable RTC I/O access. Description Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 00h Description The MSB of RTC I/O port address. Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W 60h Description The LSB of RTC I/O port address. KB IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELRTCIRQ R/W Default R/W 0h Reserved. Select the IRQ channel for RTC interrupt. Description 8.11 UART1 Registers (CR10) UART 1 Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved UR1_EN R/W Default R/W 1 Reserved 1: disable UART 1. 1: enable UART 1. Description Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 03h Description The MSB of UART 1 base address. Base Address Low Register ⎯ Index 61h Bit Name R/W Default R/W F8h Description The LSB of UART 1 base address. 7-0 BASE_ADDR_LO 108 May, 2010 V0.28P F81865 IRQ Channel Select Register ⎯ Index 70h Bit Name R/W Default R/W 4h Reserved. Select the IRQ channel for UART 1. Description 7-4 Reserved 3-0 SELUR1IRQ IRQ Share Register ⎯ Index F0h Bit 7 Name UR1_9BIT_MODE R/W Default R/W 0 Description 0: normal UART function 1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit. This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_UR1 and SADEN_UR1) Invert RTS# if UR1_RS485_EN is set. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# high when transmitting data, otherwise is kept low. Reserved. 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode. This bit is effective in IRQ sharing mode. 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. Description Reserved. Select the clock source for UART1. 00: 1.8432MHz. 01: 18.432MHz. 10: 24MHz. 11: 14.769MHz. 6 UR1_AUTO_ADDR R/W 0 5 4 3-2 1 0 UR1_RS485_INV UR1_RS485_EN Reserved UR1IRQ_MODE UR1IRQ_SHARE R/W R/W R/W R/W 0 0 0 0 Clock Register ⎯ Index F2h Bit 7-2 Name Reserved R/W Default - 1-0 UR1_CLK_SEL R/W 00b 9bit-mode Slave Address Register ⎯ Index F4h Bit Name R/W Default Description This byte accompanying with SADEN_UR1 will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 1. given address: If bit n of SADEN_UR1 is “0”, then the corresponding bit of SADDR_UR1 is don’t care. 2. broadcast address: If bit n of ORed SADDR_UR1 and SADEN_UR1 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR1 0101_1100b SADEN_UR1 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b 7-0 SADDR_UR1 R/W 00h 109 May, 2010 V0.28P F81865 9bit-mode Slave Address Mask Register ⎯ Index F5h Bit Name R/W Default Description This byte accompanying with SADDR_UR1 will determine the given address and broadcast address in 9-bit mode. The UART_UR1 will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 3. given address: If bit n of SADEN_UR1 is “0”, then the corresponding bit of SADDR_UR1 is don’t care. 4. broadcast address: If bit n of ORed SADDR_UR1 and SADEN_UR1 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR1 0101_1100b SADEN_UR1 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b 7:0 SADEN_UR1 R/W 00h 8.12 UART2 Registers (CR11) UART 2 Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved UR2_EN R/W Default R/W 1 Reserved 0: disable UART 2 1: enable UART 2. Description Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 02h Description The MSB of UART 2 base address. Base Address Low Register ⎯ Index 61h Bit 7-1 Name BASE_ADDR_LO R/W Default R/W F8h Description The LSB of UART 2 base address. IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELUR12RQ R/W Default R/W 3h Reserved. Select the IRQ channel for UART 2. Description IRQ Share Register ⎯ Index F0h Bit 7 Name UR2_9BIT_MODE R/W Default R/W 0 Description 0: normal UART function 1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit. This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_UR2 and SADEN_UR2) Invert RTS# if UR2_RS485_EN is set. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# high when transmitting data, otherwise is kept low. 6 UR2_AUTO_ADDR R/W 0 5 4 UR2_RS485_INV UR2_RS485_EN R/W R/W 0 0 110 May, 2010 V0.28P F81865 3-2 1 0 Reserved UR2IRQ_MODE UR2IRQ_SHARE R/W R/W 0 0 Reserved. 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode. This bit is effective in IRQ sharing mode. 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. Description Reserved. Select the clock source for UART2. 00: 1.8432MHz. 01: 18.432MHz. 10: 24MHz. 11: 14.769MHz. Description This byte accompanying with SADEN_UR2 will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 5. given address: If bit n of SADEN_UR2 is “0”, then the corresponding bit of SADDR_UR2 is don’t care. 6. broadcast address: If bit n of ORed SADDR_UR2 and SADEN_UR2 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR2 0101_1100b SADEN_UR2 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b Clock Register ⎯ Index F2h Bit 7-2 Name Reserved R/W Default - 1-0 UR2_CLK_SEL R/W 00b 9bit-mode Slave Address Register ⎯ Index F4h Bit Name R/W Default 7-0 SADDR_UR2 R/W 00h 9bit-mode Slave Address Mask Register ⎯ Index F5h Bit Name R/W Default Description This byte accompanying with SADDR_UR2 will determine the given address and broadcast address in 9-bit mode. The UART_UR2 will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 7. given address: If bit n of SADEN_UR2 is “0”, then the corresponding bit of SADDR_UR2 is don’t care. 8. broadcast address: If bit n of ORed SADDR_UR2 and SADEN_UR2 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR2 0101_1100b SADEN_UR2 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b 7:0 SADEN_UR2 R/W 00h 111 May, 2010 V0.28P F81865 8.13 UART3 Registers (CR12) UART 3 Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved UR3_EN R/W Default R/W 1 Reserved 0: disable UART 3. 1: enable UART 3. Description Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 03h Description The MSB of UART 3 base address. Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W E8h Description The LSB of UART 3 base address. IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELUR3IRQ R/W Default R/W 3h Reserved. Select the IRQ channel for UART 3. Description IRQ Share Register ⎯ Index F0h Bit 7 Name UR3_9BIT_MODE R/W Default R/W 0 Description 0: normal UART function 1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit. This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_UR3 and SADEN_UR3) Invert RTS# if UR3_RS485_EN is set. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# high when transmitting data, otherwise is kept low. Reserved. 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode. This bit is effective in IRQ sharing mode. 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. Description Reserved. Select the clock source for UART3. 00: 1.8432MHz. 01: 18.432MHz. 10: 24MHz. 11: 14.769MHz. 6 UR3_AUTO_ADDR R/W 0 5 4 3-2 1 0 UR3_RS485_INV UR3_RS485_EN Reserved UR3IRQ_MODE UR3IRQ_SHARE R/W R/W R/W R/W 0 0 0 0 Clock Register ⎯ Index F2h Bit 7-2 Name Reserved R/W Default - 1-0 UR3_CLK_SEL R/W 00b 112 May, 2010 V0.28P F81865 9bit-mode Slave Address Register ⎯ Index F4h Bit Name R/W Default Description This byte accompanying with SADEN_UR3 will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 9. given address: If bit n of SADEN_UR3 is “0”, then the corresponding bit of SADDR_UR3 is don’t care. 10. broadcast address: If bit n of ORed SADDR_UR3 and SADEN_UR3 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR3 0101_1100b SADEN_UR3 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b Description This byte accompanying with SADDR_UR3 will determine the given address and broadcast address in 9-bit mode. The UART_UR3 will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 11. given address: If bit n of SADEN_UR3 is “0”, then the corresponding bit of SADDR_UR3 is don’t care. 12. broadcast address: If bit n of ORed SADDR_UR3 and SADEN_UR3 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR3 0101_1100b SADEN_UR3 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b 7-0 SADDR_UR3 R/W 00h 9bit-mode Slave Address Mask Register ⎯ Index F5h Bit Name R/W Default 7:0 SADEN_UR3 R/W 00h 8.14 UART4 Registers (CR13) UART 4 Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved UR3_EN R/W Default R/W 1 Reserved 0: disable UART 4. 1: enable UART 4. Description Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 03h Description The MSB of UART 4 base address. Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W E8h Description The LSB of UART 4 base address. IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELUR4IRQ R/W Default R/W 3h Reserved. Select the IRQ channel for UART 4. Description 113 May, 2010 V0.28P F81865 IRQ Share Register ⎯ Index F0h Bit 7 Name UR4_9BIT_MODE R/W Default R/W 0 Description 0: normal UART function 1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit. This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_UR4 and SADEN_UR4) Invert RTS# if UR4_RS485_EN is set. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# high when transmitting data, otherwise is kept low. Reserved. 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode. This bit is effective in IRQ sharing mode. 0 UR4IRQ_SHARE R/W 0 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. Description Reserved. Select the clock source for UART4. 00: 1.8432MHz. 01: 18.432MHz. 10: 24MHz. 11: 14.769MHz. Description This byte accompanying with SADEN_UR4 will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 13. given address: If bit n of SADEN_UR4 is “0”, then the corresponding bit of SADDR_UR4 is don’t care. 14. broadcast address: If bit n of ORed SADDR_UR4 and SADEN_UR4 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR4 0101_1100b SADEN_UR4 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b 6 UR4_AUTO_ADDR R/W 0 5 4 3-2 1 UR4_RS485_INV UR4_RS485_EN Reserved UR4IRQ_MODE R/W R/W R/W 0 0 0 Clock Register ⎯ Index F2h Bit 7-2 Name Reserved R/W Default - 1-0 UR4_CLK_SEL R/W 00b 9bit-mode Slave Address Register ⎯ Index F4h Bit Name R/W Default 7-0 SADDR_UR4 R/W 00h 114 May, 2010 V0.28P F81865 9bit-mode Slave Address Mask Register ⎯ Index F5h Bit Name R/W Default Description This byte accompanying with SADDR_UR4 will determine the given address and broadcast address in 9-bit mode. The UART_UR4 will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 15. given address: If bit n of SADEN_UR4 is “0”, then the corresponding bit of SADDR_UR4 is don’t care. 16. broadcast address: If bit n of ORed SADDR_UR4 and SADEN_UR4 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR4 0101_1100b SADEN_UR4 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b 7:0 SADEN_UR4 R/W 00h 8.15 UART5 Registers (CR14) UART 5 Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved UR5_EN R/W Default R/W 0 Reserved 0: disable UART 5. 1: enable UART 5. Description Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 00h Description The MSB of UART 5 base address. Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W 00h Description The LSB of UART 5 base address. IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELUR5IRQ R/W Default R/W 3h Reserved. Select the IRQ channel for UART 5. Description IRQ Share Register ⎯ Index F0h Bit 7 Name UR5_9BIT_MODE R/W Default R/W 0 Description 0: normal UART function 1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit. This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_UR5 and SADEN_UR5) Invert RTS# if UR5_RS485_EN is set. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# high when transmitting data, otherwise is kept low. 6 UR5_AUTO_ADDR R/W 0 5 4 UR5_RS485_INV UR5_RS485_EN R/W R/W 0 0 115 May, 2010 V0.28P F81865 3-2 1 0 Reserved UR5IRQ_MODE UR5IRQ_SHARE R/W R/W 0 0 Reserved. 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode. This bit is effective in IRQ sharing mode. 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. Description Reserved. Select the clock source for UART5. 00: 1.8432MHz. 01: 18.432MHz. 10: 24MHz. 11: 14.769MHz. Description This byte accompanying with SADEN_UR5 will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 17. given address: If bit n of SADEN_UR5 is “0”, then the corresponding bit of SADDR_UR5 is don’t care. 18. broadcast address: If bit n of ORed SADDR_UR5 and SADEN_UR5 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR5 0101_1100b SADEN_UR5 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b Clock Register ⎯ Index F2h Bit 7-2 Name Reserved R/W Default - 1-0 UR5_CLK_SEL R/W 00b 9bit-mode Slave Address Register ⎯ Index F4h Bit Name R/W Default 7-0 SADDR_UR5 R/W 00h 9bit-mode Slave Address Mask Register ⎯ Index F5h Bit Name R/W Default Description This byte accompanying with SADDR_UR5 will determine the given address and broadcast address in 9-bit mode. The UART_UR5 will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 19. given address: If bit n of SADEN_UR5 is “0”, then the corresponding bit of SADDR_UR5 is don’t care. 20. broadcast address: If bit n of ORed SADDR_UR5 and SADEN_UR5 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR5 0101_1100b SADEN_UR5 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b 7:0 SADEN_UR5 R/W 00h 116 May, 2010 V0.28P F81865 8.16 UART6 Registers (CR15) UART 6 Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved UR6_EN R/W Default R/W 0 Reserved 0: disable UART 6. 1: enable UART 6. Description Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 00h Description The MSB of UART 6 base address. Base Address Low Register ⎯ Index 61h Bit 7-0 Name BASE_ADDR_LO R/W Default R/W 00h Description The LSB of UART 6 base address. IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELUR6IRQ R/W Default R/W 3h Reserved. Select the IRQ channel for UART 6. Description IRQ Share Register ⎯ Index F0h Bit 7 Name UR6_9BIT_MODE R/W Default R/W 0 Description 0: normal UART function 1: enable 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit. This bit works only in 9-bit mode. 0: the SM2 bit will be cleared by host, so that data could be received. 1: the SM2 bit will be cleared by hardware according to the sent address and the given address (or broadcast address derived by SADDR_UR6 and SADEN_UR6) Invert RTS# if UR6_RS485_EN is set. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# high when transmitting data, otherwise is kept low. 0 : No reception delay when SIR is changed from TX to RX. 1 : Reception delay 4 character-time when SIR is changed from TX to RX. 0 : No transmission delay when SIR is changed from RX to TX. 1 : Transmission delay 4 character-time when SIR is changed from RX to TX. 0 : PCI IRQ sharing mode. 1 : ISA IRQ sharing mode. This bit is effective in IRQ sharing mode. 0 : IRQ is not sharing with other device. 1 : IRQ is sharing with other device. Description Reserved. Return 010b when read. 0X: Disable IR1 function. 10 : Enable IR1 function, active pulse is 1.6uS. 11 : Enable IR1 function, active pulse is 3/16 bit time. 6 UR6_AUTO_ADDR R/W 0 5 4 UR6_RS485_INV UR6_RS485_EN R/W R/W 0 0 3 2 RXW4C_IR TXW4C_IR R/W R/W 0 0 1 0 UR6IRQ_MODE UR6IRQ_SHARE R/W R/W 0 0 IR Mode Select Register ⎯ Index F1h Bit 7-5 4-3 Name Reserved IRMODE1 IRMODE0 R/W Default R/W 00b 117 May, 2010 V0.28P F81865 2 HDUPLX R/W 0 0 : Full Duplex function for IR self test. 1 : Half Duplex function. Return 1 when read. 0 : IRTX is not inversed. 1 : Inverse the IRTX. 0 : IRRX is not inversed. 1 : Inverse the IRRX. Description Reserved. Select the clock source for UART6. 00: 1.8432MHz. 01: 18.432MHz. 10: 24MHz. 11: 14.769MHz. Description This byte accompanying with SADEN_UR6 will determine the given address and broadcast address in 9-bit mode. The UART will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 21. given address: If bit n of SADEN_UR6 is “0”, then the corresponding bit of SADDR_UR6 is don’t care. 22. broadcast address: If bit n of ORed SADDR_UR6 and SADEN_UR6 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR6 0101_1100b SADEN_UR6 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b 1 0 TXINV_IR RXINV_IR R/W R/W 0 0 Clock Register ⎯ Index F2h Bit 7-2 Name Reserved R/W Default - 1-0 UR6_CLK_SEL R/W 00b 9bit-mode Slave Address Register ⎯ Index F4h Bit Name R/W Default 7-0 SADDR_UR6 R/W 00h 9bit-mode Slave Address Mask Register ⎯ Index F5h Bit Name R/W Default Description This byte accompanying with SADDR_UR6 will determine the given address and broadcast address in 9-bit mode. The UART_UR6 will response to both given and broadcast address. Follow the description to determine the given address and broadcast address: 23. given address: If bit n of SADEN_UR6 is “0”, then the corresponding bit of SADDR_UR6 is don’t care. 24. broadcast address: If bit n of ORed SADDR_UR6 and SADEN_UR6 is “0”, don’t care that bit. The remaining bit which is “1” is compared to the received address. Ex. SADDR_UR6 0101_1100b SADEN_UR6 1111_1001b Given Address 0101_1xx0b Broadcast Address 1111_11x1b 7:0 SADEN_UR6 R/W 00h 118 May, 2010 V0.28P F81865 9. Electrical Characteristics 9.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage Operating Temperature Operating Temperature-I Storage Temperature RATING -0.5 to 5.5 -0.5 to VDD+0.5 0 to +70 -40 to +85 -55 to 150 UNIT V V °C °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device 9.2 DC Characteristics (TA = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V ) Parameter Temperature Error, Remote Diode Supply Voltage range Average operating supply current Standby supply current Resolution Power on reset threshold Diode source current High Level Low Level Conditions 60 oC < TD < 145 oC, VCC = 3.0V to 3.6V 0 oC