FXO-PC735RFC-2125

for FIBRE CHANNEL 50ppm Model: FXO-PC735RFC-212.5 LVPECL 7 x 5mm Features 3.3V XO Freq: 212.5MHz Low Jitter Low Cost Tri-State Enable / Disable Feature Industry Standard Package Gold over Nickel Termination Finish V DD Enable / Disable X PRESSO ASICs GND FOX OUTPUT Electrical Characteristics Parameters Frequency Frequency Stability 1 Temperature Range Supply Voltage Input Current Output Load Start-Up Time Output Enable / Disable Time Moisture Sensitivity Level Termination Finish MSL TO TSTG VDD IDD Differential TS Standard operating Storage Standard Standard Load Standard Symbol FO Condition Maximum Value (unless otherwise noted) 212.5 MHz 50 ppm -40°C to +85°C -55°C to +125°C 3.3V ± 5% 120 mA 50 ohms into VDD -2.0VDC 10 mS 100 nS 1 Au Note 1 – Stability is inclusive of 25°C tolerance, operating temperature range, input voltage change, load change, aging, shock and vibration. Output Wave Characteristics Parameters Output LOW Voltage Output HIGH Voltage Output Symmetry Output Enable (PIN # 1) Voltage Output Disable (PIN # 1) Voltage Cycle Rise Time Cycle Fall Time DWG- 100751 | Rev. 07/13/2010 Symbol VOL VOH VIH VIL TR TF Condition Standard Load Standard Load @ 50% Vp-p Level Maximum Value (unless otherwise noted) 1.35V ~ 1.65V 2.055V ~ 2.405V 45% ~ 55% ≥70% VDD ≤30% VDD 400 pS 400 pS 20% ~ 80% Vp-p 80% ~ 20% Vp-p DWG- | Rev. 07/13/2010 Page 1 of 2 © 2010 FOX ELECTRONICS | ISO9001:2000 Certified | FOXONLINE for FIBRE CHANNEL 50ppm Model: FXO-PC735RFC-212.5 LVPECL 7 x 5mm 3.3V XO Freq: 212.5MHz Dimensional Drawing & Pad Layout Phase Jitter & Time Interval Error (TIE) (Typical Measurements) Frequency 212.5 MHz Phase Jitter (12kHz to 20MHz) TIE (Sigma of Jitter Distribution) Units pS RMS 1.05 3.6 Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; VDD = 3.3V. TIE was measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; VDD = 3.3V. Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications) Random & Deterministic Jitter Composition (Typical Measurements) Frequency 212.5 MHz Random (Rj) (pS RMS) Deterministic (Dj) (pS P-P) Total Jitter (Tj) (14 x Rj) + Dj 26.1 pS 1.22 8.6 Rj and Dj, measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software. Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications) Pin Functional Description Pin # 1 2 3 4 5 6 Name E/D NC 2 1 Type Logic Ground Output Output Power Function Enable / Disable Control of Output (0 = Disabled) No Connection – Leave Open NOTES: 1 2 GND Output Output 2 VDD 3 Electrical Ground for VDD LVPECL Oscillator Output Complementary LVPECL Output Power Supply Source Voltage Includes pull-up resistor to VDD to provide output when the pin (1) is No Connect. (Also see note 2) An optional pin # 2 Enable / disable is available. Installation should include a 0.01µF bypass capacitor placed between VDD (Pin 6) and GND (Pin 3) to minimize power supply line noise. Page 2 of 2 © 2010 FOX ELECTRONICS | ISO9001:2000 Certified | FOXONLINE 3 DWG- | Rev. 07/13/2010