33389

Freescale Semiconductor Advance Information Document Number: MC33389 Rev. 5.0, 3/2007 System Basis Chip with Low Speed Fault Tolerant CAN The 33389 is a monolithic integrated circuit combining many functions frequently used by automotive Engine Control Units (ECUs). It incorporates a low speed fault tolerant CAN transceiver. Features • Dual Low Drop Voltage Regulators, with Respectively 100 mA and 200 mA Current Capabilities, Current Limitation, and Over Temperature Detection with Pre-warning • 5.0 V Output Voltage for V1 Regulator • Three Operational Modes (Normal, Stand-by, and Sleep Modes) Separated from the CAN Interface Operating Modes • Low Speed 125 kBaud Fault Tolerant CAN Interface, Compatible with 33388 Stand Alone Physical Interface • V1 Regulator Monitoring and Reset Function • Three External High Voltage Wake-Up Inputs, Associated with V3 VBAT Switch • 100 mA Output Current Capability for V3 VBAT Switch Allowing Drive of External Switches or Relays • Low Stand-by and Sleep Current Consumption • VBAT Monitoring and VBAT Failure Detection Capabilities • DC Operating Voltage up to 27 V • 40 V Maximum Transient Voltage • Programmable Software Window Watchdog and Reset • Wake-Up Capabilities (CAN Interface, Local Programmable Cycle Wake • INterface with the MCU through the SPI • Pb-Free Packaging Designated by Suffix Codes VW and EG 33389 SYSTEM BASIS CHIP DH SUFFIX VW SUFFIX (PB-FREE) PLASTIC PACKAGE 98ASH70273A 20-PIN HSOP DW SUFFIX EG SUFFIX (PB-FREE) PLASTIC PACKAGE 98ASB42345B 28-PIN SOICW ORDERING INFORMATION Device MC33389CDH/R2 HSOP-20 MC33389CVW/R2 -40 to 125°C MC33389CDW/R2 SO-28 MC33389DDW/R2 Temperature Range (TA) Package 33389 5.0 V MCU CS SCK MOSI MISO 5.0 V V1 V2 CS SCK MOSI MISO INT RST TX RX VBAT V3 L0 L1 L2 GND RTH CAN H CAN L RTL VPWR Switched VBAT W ake-Up Inputs SPI Twisted CAN Bus Pair Figure 1. 33389 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations Freescale Part No. MC33389CDH MC33389CVW MC33389CDW MC33389DDW The sole difference between the C version and the D version is V1 Reset Threshold. Reference V1 Reset Threshold on V1 on page 9. V1 Undervoltage In V1 undervoltage condition, device remains in permanent reset state until V1 returns to normal conditions. V1 is protected by overcurrent and overtemperature functions. 33389 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM Dual Voltage Regulator VBAT 5V Voltage Control Battery Voltage Failure Detect Voltage Monitor 5V VBAT Switch Supply Mode Control Interrupt Control Reset Control Watchdog & Oscillator L0 L1 L2 Programmable Wake-Up Inputs V2 V2 V1 V3 INT RST CS SCLK MOSI MISO GND SPI Interface Fault-Tolerant CAN Transceiver TX RX RTH CANH CANL RTL Figure 2. 33389 Simplified Internal Block Diagram 33389 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS PIN CONNECTIONS TX V1 RX RST INT MISO MOSI SCLK CS L2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 V3 VBAT RTL V2 CANH GND CANL RTH L0 L1 Figure 3. 33389 Pin Connections Table 1. 33389 Pin Definitions: HSOSP 20-Lead A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number 1 2 3 4 5 6 7 8 9 10 - 12 13 14 15 16 17 18 19 20 Pin Name TX V1 RX RST INT MISO MOSI SCLK CS L0 - L2 Formal Name Transmitter Data Definition Transmitter input of the LS CAN interface Voltage Regulator One This 5.0 V pin is a 3% low drop voltage regulator dedicated to the microcontroller supply. Receiver Data Reset Interrupt Output Master In/Slave Out Master Out/Slave In System Clock Chip Select Level 0 - 2 inputs (L0: L2) RTH CAN Low Ground CAN High Receiver output of the LS CAN interface This is an Input/Output pin. This output is asserted LOW when an enabled interrupt condition occurs. This pin is the tri-state output from the shift register. This pin is for the input of serial instruction data. This pin clocks the internal shift registers. This pin communicates with the system MCU and enables SPI communication. Input interfaces to external circuitry. Levels at these pins can be read by SPI and input can be used as programmable wake-up input in Sleep or Stop mode. Pin for the connection of the bus termination to CANH CAN low input/output This pin is the ground of the integrated circuit. CAN high input/output RTH CANL GND CANH V2 RTL VBAT V3 Voltage Regulator Two This 5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply. RTL Voltage Battery Voltage Regulator Three Pin for the connection of the bus termination to CANL This pin is voltage supply from the battery. This pin is a 10 Ω switch to VBAT, used to supply external contacts or relays. 33389 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS TX V1 RX RST INT GND GND GND GND MISO MOSI SCLK CS L2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 V3 VBAT RTL V2 CANH GND GND GND GND CANL RTH NC L0 L1 Table 2. 33389 Pin Definitions: SOICW 28-Lead A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number 1 2 3 4 5 6 -9 20 - 23 10 11 12 13 14, 15, 16 17 18 19 24 25 26 27 28 Pin Name TX Formal Name Transmitter Data Voltage Regulator One Receiver Data Reset Interrupt Ground Master In/Slave Out Master Out/Slave In System Clock Chip Select Wake-up Input (L0: L2) No Connect Thermal Resistance High CAN Low CAN High Voltage Regulator Two Thermal Resistance Low Voltage Battery Voltage Regulator Three Definition Transmitter input of the LS CAN interface This 5.0 V pin is a 3% low drop voltage regulator dedicated to the microcontroller supply. Receiver output of the LS CAN interface This is an Input/Output pin. This output is asserted LOW when an enabled interrupt condition occurs. These device ground pins are internally connected to the package lead frame to provide a 33389-to-PCB thermal path. This pin is the tri-state output from the shift register. This pin is for the input of serial instruction data. This pin clocks the internal shift registers. This pin communicates with the system MCU and enables SPI communication. Input interfaces to external circuitry. Levels at these pins can be read by SPI and input can be used as programmable wake-up input in Sleep or Stop mode. This pin does not connect. Pin for the connection of the bus termination to CANH CAN low input/output CAN high input/output This 5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply. Pin for the connection of the bus termination to CANL This pin is voltage supply from the battery. This pin is a 10 Ω switch to VBAT, used to supply external contacts or relays. V1 RX RST INT GND MISO MOSI SCLK CS L0: L2 NC RTH CANL CANH V2 RTL VBAT V3 33389 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS DC Voltage at VBAT Pin Transient Voltage at VBAT Pin t < 500 ms (load dump) Symbol Value Unit VBAT VBAT VBAT VBAT -0.3 to 27 40 V V DC Voltage at Pins CANH and CANL Transient Voltage at Pins CANH and CANL 0.0 < V2 < 5.5, VBAT > 0.0, t < 500 ms Coupled Transient Voltage at Pins CANH and CANL With 100 Ω Termination Resistors, Coupled Through 1.0 nF DC Voltage at Pins V1 and V2 DC Current at Output Pins RX, MISO, RST, INT DC Voltage at Input Pins TX, MOSI, CS, RST DC Voltage at Pins L0, L1, L2 0.0 < VBAT < 40 V Current at Pins L0, L1, L2 Transient Current at Pin V3 DC Voltage at pins RTH and RTL ESD Voltage on any Pin (HBM 100 pF, 1.5 K) ESD Voltage on L0, L1, L2, CANH, CANL, VBAT ESD Voltage on any Pin (MM 200 pF, 0 Ω) THERMAL RATINGS Operating Junction Temperature Ambient Temperature Storage Temperature Notes 1. Pulses 1, 2, 3a, and 3b according to ISO7637. (1) -20 to 27 -40 to 40 V V VBAT -100 to 100 V VBAT VBAT VBAT VBAT -0.3 to 6.0 -20 to 20 -0.3 to 6.0 -0.3 to 40 V mA V V VBAT VBAT VBAT VBAT VBAT VBAT -15 -30 to 20 -0.3 to 40 -2.0 to 2.0 -2.0 to 2.0 -150 to 150 mA mA V kV kV V TJ TA TS -40 to 150 -40 to 125 -55 to 165 °C °C °C 33389 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings THERMAL RESISTANCE RTH, RTL Termination Resistance Junction to Heatsink Thermal Resistance for HSOP-20 33% Power on V1, 66% on V2 (including CAN) (2) Junction to Pin Thermal Resistance for SO-28WD (3) Thermal Shutdown Temperature Peak Package Reflow Temperature During Reflow (4), (5) RAS/P TSD TPPRT 17 165 Note 5 °C/W °C °C RRTHRTL RAJC 500 to 16 k 3.1 Ω °C/W Symbol Value Unit Notes 2. Refer to thermal management in device description section. 3. Refer to thermal management in device section. Ground pins 6, 7, 8, 9, 20, 21, 22, and 23 of SO28WB package. 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33389 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER INPUT (VBAT) Nominal VBAT Operating Range Functional VBAT Operating Range VBAT Threshold for BATFAIL Flag Delay for Signalling BATFAIL Overvoltage VBAT Threshold Delay for Setting BATHIGH Flag Supply Current in Sleep Mode Forced Wake-Up and Cyclic Sense Disabled VBAT = 12 V, TJ = 25°C to 150°C Supply Current in Sleep Mode Forced Wake-Up and Cyclic Sense Disabled VBAT = 12 V, TJ = -40°C to 25°C Supply Current in Sleep Mode Forced Wake-Up and Cyclic Sense Enabled VBAT = 12 V, TJ = 25°C to 150°C Supply Current in Sleep Mode Forced Wake-Up and Cyclic Sense Enabled VBAT = 12 V, TJ = -40°C to 25°C Supply Current in Sleep Mode Forced Wake-Up and Cyclic Sense Disabled VBAT = 12 V, TJ = 25°C to 150°C Supply Current in Stand-by Mode Supply Current in Normal Mode Normal Mode with I(V1) = 1 I(V2) = 0 Bus in Recessive State POWER OUTPUT V1 Output Voltage 0 mA < IOUT < 100 mA 5.5 V < VBAT < 27 V V1 Output Voltage IOUT =< 100 mA 27 V < VBAT < 40 V V1 Drop Voltage IOUT =< 100 mA (6) Notes 6. Measured when V1 has dropped 100mV below its nominal value V1DROP V1 Symbol Min Typ Max Unit VBAT VBAT BATFAIL TFAIL 5.5 5.5 2.0 — 18 4.0 — — — — 150 20 18 18 27 4.0 400 22 50 V V V µs V µs µA BATHIGH THIGH ISLEEP1 75 125 ISLEEP2 — — 210 µA ISLEEP3 — 105 155 µA ISLEEP4 — — 250 µA ISLEEP5 — — 300 µA ISTB2 INREC — — 0.5 3.5 1.0 7.0 mA mA V1NOM 4.85 5.0 5.15 V V 4.8 5.0 5.2 — 0.35 0.5 V 33389 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER OUTPUT (CONTINUED) V1 Output Current Limitation V1NOM - 100 mV V1 Overtemperature Shut OFF Threshold Junction Temperature V1 Pre-Warning Temperature Threshold Junction Temperature V1 Temperature Threshold Difference V1 Reset Threshold on V1 5.5 V < VBAT < 27 V (C Version) (D Version) V1 Reset Active V1 Range V1 Reverse Current from V1 to VBAT and GND V1 = 4.9 V, 0 < VBAT < 4.9 V V2 Output Voltage 0 mA < IOUT < 200 mA 5.5 V < VBAT < 40 V V2 Drop Voltage IOUT = 200 mA V2 Drop Voltage IOUT = 20 mA (7) (7) Symbol Min Typ Max Unit I1MAX 130 170 200 mA TV1H 160 — 190 °C TV1L 130 — 160 °C TV1H-TV1L VR1 20 — 40 °C V 4.1 V2 - 0.4 V1R IREV 4.3 V1 - 0.28 VR1 4.8 V1 - 0.1 — 1.0 V mA 1.0 — — V2NOM 4.75 5.0 5.25 V V2DROP — 0.2 0.5 V V2DROP — 0.05 0.15 V V2 Output Current Limitation V2NOM -100 mV V2 Threshold on V2 to Report V2 OFF V2 Nominal VR2 Delay Time V2 Overtemperature Pre-Warning Threshold V2 Junction Temperature V2 Overtemperature Switch-OFF Threshold V2 Junction Temperature V2 Line Regulation 9.0 V < VBAT < 16.5 V2 Load Regulation 4.0 mA < ILOAD < 200 mA V2 Line Ripple Rejection 100 Hz, 1.0 VPP on VBAT (8) I1MAX 220 280 350 mA VR2 VR2 TV2L TV2H V2LR1 4.1 4.55 4.75 V 20 130 — — 70 160 µs °C 155 — 185 °C -15 — +15 mV V2LR2 -75 — +75 mV V2LRR 30 55 — dB Notes 7. Measured when V1 has dropped 100mV below its nominal value 8. Guaranteed by design; however, it is not production tested 33389 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER OUTPUT (CONTINUED) V2 Percentage Difference V2-V1 VBAT > 9.0, IV1 = 20 mA, IV2 = 40 mA V3 High Level Voltage Drop IV3 = -50 mA, 9.0 V < VBAT < 40 V V3 High Level Voltage Drop IV3 = -50 mA, 6.0 V < VBAT < 9.0 V V3 Leakage Output Limitation 5.5 V < VBAT < 27 V V3 Leakage Current V3 = 0 (V3 OFF) V3 Overtemperature Detection Junction Temperature V3 Voltage with -30 mA (negative current for Relay Switch OFF) No Functional Error Allowed for t < 100 ms CAN Transceiver V2 for Forced Bus Stand-by Mode (Fail Safe) CANH/L Differential Receiver, Threshold Voltage CANH/L Differential Receiver, Dominant to Recessive Threshold (Bus Failures 1, 2, and 5) CANH Recessive Output Voltage TX = High, R(RTH) < 4.0 k CANL Recessive Output Voltage TX = High, R(RTH) < 4.0 k CANH Output Voltage, Dominant TX = 0 V, BusNormal Mode, ICANH = - 40 mA CANL Output Voltage, Dominant TX = 0 V, Bus Normal Mode, ICANL = - 40 mA CANH Output Current Limit (VCANH = 0.0 V, TX = 0) CANL Output Current Limit (VCANL = 14 V, TX = 0) Detection Threshold for Short Circuit to Battery Voltage Bus Normal Mode Detection Threshold for Short Circuit to Battery Voltage Bus Stand-by Mode CANH Output Current, Failure 3 Bus Stand-by Mode VCANH = 12 V CANL Output Current, Failure 4 Bus Stand-by Mode, VCANL = 0.0 V, VBAT = 12 V ICANLF4 — 0.0 2.0 µA ICANHF3 — 5.0 10 µA VCANH VBAT/2+3 — VBAT/2+5 V VCANH-VCANL 7.3 7.9 8.9 V ICANL 50 95 130 mA ICANH 50 75 100 mA VCANL — — 1.4 V VCANH V2-1.4 — — V VCANL V2-0.2 — — V VCANH — — 0.2 V VRC2 VCANTH VCANDRTH 3.0 -3.2 -3.2 3.9 — — 4.7 -2.5 -2.5 V V V VV3 0.3 — 0.5 V TV3 155 — 185 °C I3LEAK — — 15 µA I3LIM 100 150 250 mA V3DROP — — 1.5 V V3DROP — 0.4 1.0 V V2V2-V1 -3.0 — 3.0 % Symbol Min Typ Max Unit 33389 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER OUTPUT (CONTINUED) CANL Wake-Up Voltage Threshold Bus Stand-by Mode CANH Wake-Up Voltage Threshold Bus Stand-by Mode Wake-Up Threshold Difference CANH Single Ended Receiver Threshold Failures 4, 6, and 7 CANL Single Ended Receiver Threshold Failures 3 and 8 CANL Pull-Up Current Bus Normal Mode CANH Pull Down Current Bus Normal Mode Receiver Differential Input Impedance CANH/CANL Differential Receiver Common Mode Voltage Range RTL to V2 Switch on Resistance IOUT < -10 mA, Bus Normal Operating Mode RTL to Battery Switch Series Resistance Bus Stand-by Mode RTH to Ground Switch on Resistance IOUT < 10 mA, All Modes CONTROL INTERFACE High Level Input Voltage CS Threshold for SPI Wake-Up SBC in Sleep Mode, V1 < 1.5 V CS Filter Time for SPI Wake-Up SBC in Sleep Mode, V1 < 1.0 V Low Level Input Voltage High Level Input Current on CS VI = 4.0 V Low Level Input Current on CS VI = 1.0 V TX High Level Input Current VI = 4.0 V TX Low Level Input Current VI = 1.0 V SI, SCLK Input Current 0 < VIN < V1 33389 ISISLK -10 — +10 µA ITXL -800 -320 -100 µA ITXH -200 -80 -25 µA ICSL -100 — -20 µA VIL ICSH -0.3 -100 — — 0.3 V1 -20 V µA tCSFT — — 3.0 µs VIH VCSTH 0.7 V1 — — 2.2 V1 + 0.3 V — V V RRTH — 25 70 Ω RRTL 8.0 12.5 20 kΩ RDIFF VCOM RRTL 100 -8.0 10 — — 25 180 8.0 70 kΩ V Ω ICANLPD 45 75 90 µA ICANLPU 45 75 90 µA VCANL 2.8 3.05 3.4 V VWAKEL VWAKEH VCANH 0.2 1.5 — 1.85 — 2.15 V V VWAKEH 1.2 2.0 2.7 V VWAKEL 2.5 3.3 3.9 V Symbol Min Typ Max Unit Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions VBAT, - 40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic CONTROL INTERFACE (CONTINUED) RX, INT, MISO High Level Output Voltage I0 = -250 µA RX, INT, MISO Low Level Output Voltage I0 = -1.5 mA RX, INT, MISO Tri-Stated SO Output Current 0 V < VSO < V1 RST High Level Input Voltage RST Low Level Input Voltage RST High Level Output Current 1 0.0 < VOUT < 0.5 V1 RST High Level Output Current 2 0.5 < VOUT < V1 RST Low Level Output Voltage (I0 = 1.5 mA) 1.0 V < VBAT < 27 V LX/Wake-Up Positive Switching Threshold 6.0 V VDD1 under voltage occurred (RSR2 = 1 in this case), 0 = > no over voltage on V occurred RSR1: 1 = > Software watchdog reset occurred (RSR 2 = 1 in this case), 0 = > no SW watchdog reset occurred RSR2: 1 = > External reset occurred (RSR0 = RSR1= 0 in this case), 0 = > no external reset occurred Events related to the bits in register RSR are latched. All bits can be reset by a Read operation of the register. After a power-ON reset, RSR2 and RSR0 are set to 1. Therefore, the first read out of the register after power-ON delivers RSR[2:0] = [101]. Table 40. Voltage Supply Status Register (VSSR) Address VSSR $01B RESET POR R W — — — — — — — — 0 0 0 0 — 0 — 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 V3SR Bit 2 V2SR Bit 1 VBSR1 Bit 0 VBSR0 This register monitors the status of the V2, V3, and VBAT voltage level. 33389 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 41. VBSR1 VBSR0 VBSR1 0 x 1 VBSR0 0 1 x Description No Failure on VBAT Under Voltage (BATFail) Over Voltage (BATHigh) V2SR: 1 = V2 ON, 0 = V2 OFF V3SR: 1 = V3 over temperature, 0 = V3 no over temperature VBSR1 is real time information. It cannot be reset. Bits V3SR, V2SR, and VBSR0 are latched and can be reset by a Read operation of the register. The next two registers (IMR1 and IMR2) mask the interrupt function. Table 42. Interrupt Mask Control Register 1 (IMR1) Address IMR1 $01D RESET R W — — — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 HV 0 Bit 2 HTPW 0 Bit 1 MTPW 0 Bit 0 BATU 0 Table 43. Interrupt Mask Control Register 2 (IMR2) Address IMR2 $01E RESET R W — — — — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 BUSF 0 Bit 1 SPIE 0 Bit 0 WU 0 To enable the appropriate interrupt, the mask bit has to be set to 1. To disable the interrupt the bit, it must be cleared to 0. After a power-ON reset or RST = Low, the bits are cleared to 0. All interrupts are disabled. Explanation for the abbreviations: HV = VBAT High voltage HT = High temperature on V1 or V2 MTPW = Medium temperature pre-warning on V1 or V2 BATU = Battery under voltage (BATFail) BUSF = CAN bus failure SPIE = SPI error WU = Wake-up The next two registers (ISR1 and ISR2) read the interrupt source. All bits in registers ISR1 and ISR2 are copies of the appropriate bits in different SPI registers. For a faster read-out, these bits are merged in ISR1 and ISR2. A reset cannot be completed for registers ISR1 and ISR2. Table 44. Interrupt Source Register 1 (ISR1) Address ISR $021 RESET R W — — — — 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 HV Bit 2 HTPW Bit 1 MTPW Bit 0 BATU Table 45. Interrupt Source Register 2 (ISR2) Address ISR $022 RESET R W — — — — — 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 BUSF Bit 1 SPIE Bit 0 WU 33389 40 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 46. Transceiver Control/Status Register (TCR) Address TCR $024 RESET R W — — — — 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TOT Bit 2 TSR2 TCR2 0 Bit 1 TSR1 TCR1 0 Bit 0 TSR0 TCR0 0 This register controls the state of the CAN transceiver (CAN transceiver is also dependent upon the SBC mode). When it is read, this register reports the CAN transceiver state and a CAN over temperature condition. Table 47. TCR / TSR Data TCR2 0 0 0 TCR1 0 1 1 TCR0 0 0 1 Description Standard/Term VBAT Standard/Rx Only Standard/RxTx TSR2 0 0 0 TSR1 0 1 1 TSR0 0 0 1 TOT 1 = > Transceiver over temperature 0 = > Normal temperature The MODE bit selects between the standard and extended physical layer mode. Any conditions forcing the transceiver to Term VBAT lead to reset of TCR0 and TCRO1 bits. After power-ON reset all bits of the register are set to 0. The information TOT is latched. Reset TOT by reading the TCR. In case of RST = Low, the register content remains unchanged. 33389 Analog Integrated Circuit Device Data Freescale Semiconductor 41 TYPICAL APPLICATIONS TYPICAL APPLICATIONS 33389 VBAT Ignition Auxiliary 12V Rp0 S0 C1 C2 V1 V3 RST Rs0 CL0 L0 L1 L2 RH RTL CANH CANL RL Rp2 S2 RTH GND INT CS MISO MOSI SCK TX RX V2 Auxiliary 5V C5 C6 VDD C3 C4 RESET INT Rp1 S1 SPI Rs1 CL1 CAN GND Rs2 CL2 CAN bus Figure 22. Typical Application Schematic 1 33389 Ignition switch Rp0 S0 Rs0 CL0 Rp1 Rs1 S1 Rp2 S2 CL1 Rs2 CL2 C1 C2 VBAT V1 Vdd C3 C4 reset Cr 33389 V3 L0 L1 L2 GND Auxiliary local 12V Micro RST Figure 24. Reset Duration Extension Figure 23. Typical Application: V3 Used as Auxiliary ECU Supply 33389 42 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS 33389 VBAT C1 Ignition Auxiliary 12V Rp0 S0 Rs0 CL0 L0 L1 L2 RH CAN bus # 1 RL RTL CANH CANL RTH GND V3 RST INT CS MISO MOSI SCK TX RX C2 V1 V2 Auxiliary 5V C5 C6 VDD RESET INT SPI bus SPI CAN 1 CAN 2 VBAT INH VDD RTL CANH MC33388 CANL RL +12V VSUP LIN bus 1k LIN MC33399 GND INH Tx/Rx RTH GND GND Tx/Rx RH CAN bus # 2 SCI (Wake-up input linked to peripheral circuits: (ex: low speed CAN or LIN transceivers). Figure 25. Typical Application Schematic 2 done at nominal voltage and temperature. By doing this, 5.0 The SBC offers several capabilities to help users debug V is provided to the MCU VDD and reset lines. their application. • External bias of V1 and reset pin Under this condition the SBC is not operational. However, the reset pin is pulled low and is sinking 5 mA to ground. This • Turn OFF software watchdog in the Stand-by mode means, the external circuitry driving reset must have a • Special debug samples with software watchdog disable at current capability higher than 5 mA in order to drive the reset power-up (contact local Motorola representative) in the high-state. DEBUG AND PROGRAM DOWNLOAD INTO FLASH MEMORY While the SBC is powered, it enters Normal Request mode and expects during the 75 ms time period in the NR mode, an SPI trigger word (to enter Normal mode and select the watchdog time period). If this does not occur, the SBC enters the Sleep mode and turns off V1. When the software is debugged, and when using development tools, it is not always easy to make sure these events happen properly. It is thus possible to externally power the V1 line with an external 5.0 V supply, and to force the Reset pin to V1 or to and external 5.0 V. These can be DISABLE OF SOFTWARE WATCHDOG IN STANDBY MODE The software watchdog can be disable in Stand-by mode only. In order to disable it the following operation must be done: • Write to MCR register–data 011 (bit 2, bit 1, bit 0) • Write to MCVR register–data 011 (bit 2, bit 1, bit 0) Then the SBC enters the Stand-by mode without software watchdog. However the V2 can not be turn on, and the CAN cell can not be used. 33389 Analog Integrated Circuit Device Data Freescale Semiconductor 43 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ASH70273A listed below. DH SUFFIX VW SUFFIX (Pb-FREE) 20 PIN PLASTIC PACKAGE 98ASH70273A ISSUE E 33389 44 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS DH SUFFIX VW SUFFIX (Pb-FREE) 20 PIN PLASTIC PACKAGE 98ASH70273A ISSUE E 33389 Analog Integrated Circuit Device Data Freescale Semiconductor 45 PACKAGING PACKAGE DIMENSIONS DW SUFFIX EG SUFFIX (Pb-FREE) 28 PIN PLASTIC PACKAGE 98ASB42345B ISSUE G 33389 46 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS DW SUFFIX EG SUFFIX (Pb-FREE) 28 PIN PLASTIC PACKAGE 98ASB42345B ISSUE G 33389 Analog Integrated Circuit Device Data Freescale Semiconductor 47 REVISION HISTORY REVISION HISTORY DATE 5.0 3/2007 DESCRIPTION OF CHANGES • • • • • • • • Added Revision History Converted to the prevailing Freescale form and style Entire document was edited for wording, labels, and technical accuracy. Added the Pb-FREE package types VW and EG to the ordering information Updated the package drawings Added Peak Package Reflow Temperature During Reflow (4), (5) on page 7 Added notes (4) and (5) Removed all references to MC33389ADW/R2, MC33389ADH/R2, MC33389CEG/R2, and MC33389DEG/R2 from the data sheet. • Restated MC33389DDW in the Device Variations on page 2 33389 48 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007. All rights reserved. MC33389 Rev. 5.0 3/2007