33903

Freescale Semiconductor Technical Data Document Number: MC33903_4_5 Rev. 6.0, 4/2011 SBC Gen2 with CAN High Speed and LIN Interface The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional integrated circuits such as sensors, and CAN transceivers. It has a built-in enhanced high speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and Fail Safe Operation Modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four Wake-Up input pins that can also be configured as output drivers for flexibility. This device implements multiple Low Power (LP) Modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. The 33903/4/5 also implements an innovative and advanced fail-safe state machine and concept solution. 33903/ 33903/4/5 SYSTEM BASIS CHIP EK Suffix (Pb-Free) 98ASA10556D 32-PIN SOIC EK Suffix (Pb-Free) 98ASA10506D 54-PIN SOIC Features • Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with possibility of usage external PNP to extend current capability and share power dissipation • Voltage, current, and temperature protection • Extremely low quiescent current in (LP) Modes • Fully-protected embedded 5.0 V regulator for the CAN driver • Multiple under-voltage detections to address various MCU specifications and system operation modes (i.e. cranking) • Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with over-current detection and under-voltage protection • MUX (except 33903) output pin for device internal analog signal monitoring and power supply monitoring • Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. • Multiple Wake-Up sources in (LP) Modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and VDD over-current detection. • ISO11898-5 high speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s ORDERING INFORMATION See Table of Contents 2 Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2010 - 2011. All rights reserved. TABLE OF CONTENTS TABLE OF CONTENTS Simplified Application Diagrams ................................................................................................................. 3 Device Variations ....................................................................................................................................... 6 Internal Block Diagrams ............................................................................................................................. 7 Pin Connections ....................................................................................................................................... 12 Electrical Characteristics .......................................................................................................................... 17 Maximum Ratings .................................................................................................................................. 17 Static Electrical Characteristics ............................................................................................................. 19 Dynamic Electrical Characteristics ........................................................................................................ 27 Timing Diagrams ................................................................................................................................... 30 Functional Description .............................................................................................................................. 34 Introduction ............................................................................................................................................ 34 Functional Pin Description ..................................................................................................................... 34 Functional Device Operation .................................................................................................................... 38 Mode and State Description .................................................................................................................. 38 LP Modes .............................................................................................................................................. 39 State Diagram ........................................................................................................................................ 40 Mode Change ........................................................................................................................................ 41 Watchdog Operation .............................................................................................................................. 41 Functional Block Operation Versus Mode ............................................................................................. 43 Illustration of Device Mode Transitions. ................................................................................................. 44 Cyclic Sense Operation During LP Modes ............................................................................................ 46 Behavior at Power Up and Power Down ............................................................................................... 48 Fail Safe Operation .................................................................................................................................. 50 CAN Interface ........................................................................................................................................ 54 CAN Interface Description ..................................................................................................................... 54 CAN Bus Fault Diagnostic ..................................................................................................................... 57 LIN Block .................................................................................................................................................. 60 LIN Interface Description ....................................................................................................................... 60 LIN Operational Modes .......................................................................................................................... 60 Serial Peripheral Interface ........................................................................................................................ 62 High Level Overview .............................................................................................................................. 62 Detail Operation ..................................................................................................................................... 63 Detail of Control Bits And Register Mapping ......................................................................................... 66 Flags and Device Status ........................................................................................................................ 83 Typical Applications ................................................................................................................................. 90 Packaging ................................................................................................................................................ 97 33903/4/5 2 Analog Integrated Circuit Device Data Freescale Semiconductor SIMPLIFIED APPLICATION DIAGRAMS SIMPLIFIED APPLICATION DIAGRAMS VBAT D1 33905D Q2 (5.0 V/3.3 V) * = Optional Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE DBG GND VSENSE I/O-0 RST INT MOSI SCLK MISO CS MUX-OUT 5V-CAN TXD RXD TXD-L1 RXD-L1 TXD-L2 RXD-L2 VDD SPI A/D MCU I/O-1 CANH SPLIT CAN Bus LIN Bus LIN Bus CANL LIN-TERM 1 LIN-1 LIN-TERM 2 LIN-2 Figure 1. 33905D Simplified Application Diagram VBAT D1 33905S Q2 (5.0 V/3.3 V) * = Optional Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE DBG GND VSENSE I/O-0 RST INT MOSI SCLK MISO CS MUX-OUT 5V-CAN TXD RXD TXD-L RXD-L VDD SPI A/D MCU I/O-1 CANH SPLIT CAN Bus VBAT CANL LIN-T LIN I/O-3 LIN Bus Figure 2. 33905S Simplified Application Diagram 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 3 SIMPLIFIED APPLICATION DIAGRAMS VBAT D1 33904 Q2 (5.0 V/3.3 V) * = Optional Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE DBG GND VSENSE I/O-0 RST INT MOSI SCLK MISO CS MUX-OUT 5V-CAN TXD RXD VDD SPI A/D MCU I/O-1 CANH VBAT SPLIT CAN Bus CANL I/O-2 I/O-3 Figure 3. 33904 Simplified Application Diagram VBAT D1 33903 VSUP1 DBG SAFE GND VSUP2 VDD RST VDD INT MOSI SCLK MISO CS SPI I/O-0 MCU CANH CAN Bus 5V-CAN TXD RXD SPLIT CANL Figure 4. 33903 Simplified Application Diagram 33903/4/5 4 Analog Integrated Circuit Device Data Freescale Semiconductor SIMPLIFIED APPLICATION DIAGRAMS VBAT D1 33903D Q1* * = Optional VDD VSUP SAFE DBG GND VSENSE IO-0 VE VB VDD RST INT MOSI SCLK MISO CS MUX-OUT 5V-CAN TXD RXD TXD-L1 RXD-L1 TXD-L2 RXD-L2 SPI A/D MCU CANH SPLIT CAN Bus LIN Bus LIN Bus CANL LIN-T1/I/O-2 LIN-1 LIN-T2/IO-3 LIN-2 Figure 5. 33903D Simplified Application Diagram VBAT D1 33903S Q1* * = Optional VSUP SAFE DBG GND VSENSE IO-0 VE VB VDD RST INT VDD MOSI SCLK MISO CS MUX-OUT 5V-CAN TXD RXD TXD-L1 RXD-L1 SPI A/D MCU CANH SPLIT VBAT CAN Bus LIN Bus CANL LIN-T1/I/O-2 LIN-1 I/O-3 Figure 6. 33903S Simplified Application Diagram 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 5 DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations - (All devices rated at TA = -40 TO 125 °C) Freescale Part Number MC33905D (Dual LIN) *MCZ33905BD3EK/R2 MCZ33905D5EK/R2 *MCZ33905BD5EK/R2 MC33905S (Single LIN) *MCZ33905BS3EK/R2 MCZ33905S5EK/R2 *MCZ33905BS5EK/R2 MC33904 *MCZ33904B3EK/R2 MCZ33904A5EK/R2 *MCZ33904B5EK/R2 MC33903 *MCZ33903B3EK/R2 *MCZ33903B5EK/R2 MC33903D (Dual LIN) *MCZ33903BD3EK/R2 *MCZ33903BD5EK/R2 MC33903S (Single LIN) *MCZ33903BS3EK/R2 *MCZ33903BS5EK/R2 3.3 V 5.0 V 1 2 Wake-Up + 1 LIN terms or 3 Wake-Up + no LIN terms SOIC 32 pin exposed pad No Yes Yes 3.3 V 5.0 V 2 1 Wake-Up + 2 LIN terms or 2 Wake-Up + 1 LIN terms or 3 Wake-Up + no LIN terms 3.3 V(1) 5.0 V (1) VDD Output Voltage LIN Interface(s) Wake-up Input / LIN Master Termination Package VAUX VSENSE MUX 3.3 V 5.0 V 2 2 Wake-Up + 2 LIN terms or 3 Wake-Up + 1 LIN terms or 4 Wake-Up + no LIN terms SOIC 54 pin exposed pad Yes Yes Yes 3.3 V 5.0 V 1 3 Wake-Up + 1 LIN terms or 4 Wake-Up + no LIN terms SOIC 32 pin exposed pad Yes Yes Yes 3.3 V 5.0 V no 4 Wake-Up SOIC 32 pin exposed pad Yes Yes Yes no 1 Wake-Up SOIC 32 pin exposed pad No No No SOIC 32 pin exposed pad No Yes Yes Notes 1. VDD does not allow usage of an external PNP on the 33903. Output current limited to 100 mA. * “B” versions are recommended for new design. Design changes in the “B” version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. 33903/4/5 6 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAMS INTERNAL BLOCK DIAGRAMS VBAUX VCAUX VAUX VSUP1 VE VB VSUP2 5 V Auxiliary Regulator VS2-INT VDD Regulator VDD SAFE DBG GND VSENSE RST Fail Safe Power Management INT MOSI Oscillator State Machine SPI SCLK MISO CS Analog Monitoring Signals Condition & Analog MUX MUX-OUT I/O-0 I/O-1 CANH SPLIT CANL VS2-INT LIN-T1 LIN1 VS2-INT LIN-T2 LIN2 VS2-INT Configurable Input-Output 5 V-CAN Regulator 5 V-CAN Enhanced High Speed CAN Physical Interface TXD RXD LIN Term #1 TXD-L1 LIN 2.1 Interface - #1 RXD-L1 TXD-L2 LIN Term #2 LIN 2.1 Interface - #2 RXD-L2 Figure 7. 33905D Internal Block Diagram 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 7 INTERNAL BLOCK DIAGRAMS VBAUX VCAUX VAUX VSUP1 VE VB VSUP2 5 V Auxiliary Regulator VS2-INT VDD Regulator VDD SAFE DBG GND VSENSE RST Fail Safe Power Management INT MOSI Oscillator State Machine SPI SCLK MISO CS Analog Monitoring Signals Condition & Analog MUX MUX-OUT I/O-0 I/O-1 I/O-3 CANH SPLIT CANL VS2-INT LIN-T LIN VS2-INT Configurable Input-Output 5 V-CAN Regulator 5 V-CAN Enhanced High Speed CAN Physical Interface TXD RXD LIN Term #1 TXD-L LIN 2.1 Interface - #1 RXD-L Figure 8. 33905S Internal Block Diagram 33903/4/5 8 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAMS VBAUX VCAUX VAUX VSUP1 VE VB VSUP2 5 V Auxiliary Regulator VS2-INT VDD Regulator VDD SAFE DBG GND VSENSE RST Fail Safe Power Management INT MOSI Oscillator State Machine SPI SCLK MISO CS Analog Monitoring Signals Condition & Analog MUX MUX-OUT I/O-0 I/O-1 I/O-2 I/O-3 CANH SPLIT CANL Configurable Input-Output VS2-INT 5 V-CAN Regulator 5 V-CAN Enhanced High Speed CAN Physical Interface TXD RXD Figure 9. 33904 Internal Block Diagram VSUP1 VSUP2 VS2-INT SAFE VDD Regulator VDD RST INT Power Management DBG GND State Machine MOSI SPI SCLK MISO CS 5 V-CAN Oscillator Configurable Input-Output VS2-INT I/O-0 CANH SPLIT CANL 5 V-CAN Regulator Enhanced High Speed CAN Physical Interface TXD RXD Figure 10. 33903 Internal Block Diagram 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 9 INTERNAL BLOCK DIAGRAMS VSUP VE VB VS-INT SAFE DBG GND VSENSE VDD Regulator VDD RST Fail-safe Power Management INT MOSI Oscillator State Machine SPI SCLK MISO CS Analog Monitoring Signals Condition & Analog MUX VS-INT MUX-OUT IO-0 CANH SPLIT CANL VS-INT LIN-T1 LIN1 VS-INT LIN-T2 LIN2 Configurable Input-Output 5 V-CAN Regulator 5 V-CAN Enhanced High-speed CAN Physical Interface TXD RXD TXD-L1 LIN Term #1 LIN 2.1 Interface - #1 RXD-L1 TXD-L2 LIN Term #2 LIN 2.1 Interface - #2 RXD-L2 Figure 11. 33903D Internal Block Diagram 33903/4/5 10 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAMS VSUP VE VB VS-INT SAFE DBG GND VSENSE VDD Regulator VDD RST Fail Safe Power Management INT MOSI Oscillator State Machine SPI SCLK MISO CS Analog Monitoring Signals Condition & Analog MUX VS-INT MUX-OUT I/O-0 I/O-3 CANH SPLIT CANL VS-INT LIN-T LIN Configurable Input-Output 5 V-CAN Regulator 5 V-CAN Enhanced High Speed CAN Physical Interface TXD RXD LIN Term #1 TXD-L LIN 2.1 Interface - #1 RXD-L Figure 12. 33903S Internal Block Diagram 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 11 PIN CONNECTIONS PIN CONNECTIONS MC33905D NC NC NC VSUP1 VSUP2 LIN-T2/I/O-3 LIN-T1/I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT V-BAUX V-CAUX V-AUX MUX-OUT I/O-0 DBG NC NC NC TXD-L2 GND RXD-L2 LIN-2 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 MC33905S NC NC NC VB VE RXD TXD VDD MISO MOSI SCLK CS INT RST I/O-1 VSENSE RXD-L1 TXD-L1 LIN-1 NC NC NC NC GND NC NC NC VSUP1 VSUP2 I/O-3 LIN-T/I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT V-BAUX V-CAUX V-AUX MUX-OUT I/O-0 DBG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 GROUND 25 24 23 22 21 20 19 18 17 GROUND VB VE RXD TXD VDD MISO MOSI SCLK CS INT RST I/O-1 VSENSE RXD-L TXD-L LIN GND - LEAD FRAME 32 pin exposed package GND - LEAD FRAME 54 pin exposed package MC33904 VSUP1 VSUP2 I/O-3 I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT V-BAUX V-CAUX V-AUX MUX-OUT I/O-0 DBG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 MC33903 VB VE RXD TXD VDD MISO MOSI SCLK CS INT RST I/O-1 VSENSE NC NC NC VSUP1 VSUP2 NC NC SAFE 5V-CAN CANH CANL GND CAN SPLIT NC NC NC NC I/O-0 DBG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 GROUND 25 24 23 22 21 20 19 18 17 GROUND 25 24 23 22 21 20 19 18 17 NC NC RXD TXD VDD MISO MOSI SCLK CS INT RST NC NC NC NC NC GND - LEAD FRAME 32 pin exposed package GND - LEAD FRAME 32 pin exposed package Note: MC33905D, MC33905S, MC33904 and MC33903 are footprint compatible, Figure 13. 33905D, MC33905S, MC33904 and MC33903 Pin Connections 33903/4/5 12 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS MC33903D VB VSUP LIN-T2 / I/O-3 LIN-T1 / I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT MUX-OUT IO-0 DBG TXD-L2 GND RXD-L2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 MC33903S VE RXD TXD VDD MISO MOSI SCLK CS INT RST VSENSE RXD-L1 TXD-L1 LIN1 GND LIN2 VB VSUP I/O-3 LIN-T / I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT MUX-OUT I/O-0 DBG NC GND NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 GROUND 25 24 23 22 21 20 19 18 17 GROUND 25 24 23 22 21 20 19 18 17 VE RXD TXD VDD MISO MOSI SCLK CS INT RST VSENSE RXD-L TXD-L LIN GND NC GND - LEAD FRAME 32 pin exposed package GND - LEAD FRAME 32 pin exposed package Note: MC33903D and MC33903S are footprint compatible. Figure 14. 33905D, MC33905S, MC33904 and MC33903 Pin Connections 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 13 PIN CONNECTIONS Table 2. 33903/4/5 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 34. 54 Pin 32 Pin 32 Pin 33905D 33905S 33904 1-3,2022,2730,3235,5254 4 N/A 32 Pin 32 Pin 32 Pin 33903 33903D 33903S N/A 14, 16, 17 Pin Name N/C Pin Function No Connect Formal Name Definition No Connection 33903S Only - Do NOT connect the N/ C pins to GND. Leave these pins Open. VSUP/1 Power Battery Voltage Supply 1 Supply input for the device internal supplies, power on reset circuitry and the VDD regulator. VSUP and VSUP1 supplies are internally connected on part number MC33903BDEK and MC33903BSEK Supply input for 5 V-CAN regulator, VAUX regulator, I/O and LIN pins. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK 33903D and 33905D - Output pin for the LIN2 master node termination resistor. or 33903S, 33903D, 33904, 33905S and 33905D - Configurable pin as an input or HS output, for connection to external circuitry (switched or small load). The input can be used as a programmable Wake-Up input in (LP) Mode. When used as a HS, no over-temperature protection is implemented. A basic short to GND protection function, based on switch drain-source over-voltage detection, is available. 33905D - Output pin for the LIN1 master node termination resistor. or 33903S, 33903D, 33904, 33905S and 33905D - Configurable pin as an input or HS output, for connection to external circuitry (switched or small load). The input can be used as a programmable Wake-Up input in (LP) Mode. When used as a HS, no over-temperature protection is implemented. A basic short to GND protection function, based on switch drain-source over-voltage detection, is available. Output of the safe circuitry. The pin is asserted LOW if a safe condition is detected (e.g.: software watchdog is not triggered, VDD low, issue on the RESET pin, etc.). Open drain structure. Output voltage for the embedded CAN interface. A capacitor must be connected to this pin. CAN high output. 17, 18, 3-4,1119 14, 1721, 31, 32 1 1 1 2 2 5 2 2 2 N/A N/A VSUP2 Power Battery Voltage Supply 2 6 3 3 N/A 3 3 LIN-T2 or I/O-3 Output or Input/ Output LIN Termination 2 or Input/Output 3 7 4 4 N/A 4 4 LIN-T1 or LIN-T Output or Input/ Output LIN Termination 1 or Input/Output 2 or I/O-2 8 5 5 5 5 5 SAFE Output Safe Output (Active LOW) 9 6 6 6 6 6 5 V-CAN Output 5V-CAN 10 7 7 7 7 7 CANH Output CAN High 33903/4/5 14 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 2. 33903/4/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 34. 54 Pin 32 Pin 32 Pin 33905D 33905S 33904 11 12 13 14 15 16 17 8 9 10 11 12 13 14 8 9 10 11 12 13 14 32 Pin 32 Pin 32 Pin 33903 33903D 33903S 8 9 10 N/A N/A N/A N/A 8 9 10 N/A N/A N/A 11 8 9 10 N/A N/A N/A 11 Pin Name CANL GND-CAN SPLIT VBAUX VCAUX VAUX MUX-OUT Pin Function Output Ground Output Output Output Output Output Formal Name CAN Low GND-CAN SPLIT Output VB Auxiliary VCOLLECTO R Auxiliary VOUT Auxiliary Multiplex Output Definition CAN low output. Power GND of the embedded CAN interface Output pin for connection to the middle point of the split CAN termination Output pin for external path PNP transistor base Output pin for external path PNP transistor collector Output pin for the auxiliary voltage. Multiplexed output to be connected to an MCU A/D input. Selection of the analog parameter available at MUX-OUT is done via the SPI. A switchable internal pull-down resistor is integrated for VDD current sense measurements. Configurable pin as an input or output, for connection to external circuitry (switched or small load). The voltage level can be read by the SPI and via the MUX output pin. The input can be used as a programmable Wake-Up input in LP Mode. In LP, when used as an output, the High Side (HS) or Low Side (LS) can be activated for a cyclic sense function. Input to activate the Debug Mode. In Debug Mode, no watchdog refresh is necessary. Outside of Debug Mode, connection of a resistor between DBG and GND allows the selection of Safe Mode functionality. LIN bus transmit data input. Includes an internal pull-up resistor to VDD. Ground of the IC. LIN bus receive data output. LIN bus input output connected to the LIN bus. LIN bus input output connected to the LIN bus. LIN bus transmit data input. Includes an internal pull-up resistor to VDD. LIN bus receive data output. 18 15 15 15 12 12 I/O-0 Input/ Output Input/Output 0 19 16 16 16 13 13 DBG Input Debug 23 24,31 25 26 36 37 N/A N/A N/A N/A 17 18 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 14 15, 18 16 17 19 20 N/A 15, 18 N/A N/A 19 20 TXD-L2 GND RXD-L2 LIN2 33903D/5D LIN-1 33903S/5S LIN 33903D/5D TXDL11 33903S/5S TXD-L 33903D/5D RXDL1 33903S/5S RXD-L Input Ground Output Input/ Output Input/ Output Input LIN Transmit Data 2 Ground LIN Receive Data LIN bus LIN bus LIN Transmit Data LIN Receive Data 38 19 N/A N/A 21 21 Output 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 15 PIN CONNECTIONS Table 2. 33903/4/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 34. 54 Pin 32 Pin 32 Pin 33905D 33905S 33904 39 20 20 32 Pin 32 Pin 32 Pin 33903 33903D 33903S N/A 22 22 Pin Name VSENSE Pin Function Input Formal Name Sense input Definition Direct battery voltage input sense. A serial resistor is required to limit the input current during high voltage transients. Configurable pin as an input or output, for connection to external circuitry (switched or small load). The voltage level can be read by the SPI and the MUX output pin. The input can be used as a programmable Wake-Up input in (LP) Mode. It can be used in association with I/O-0 for a cyclic sense function in (LP) Mode. This is the device reset output whose main function is to reset the MCU. This pin has an internal pull-up to VDD. The reset input voltage is also monitored in order to detect external reset and safe conditions. This output is asserted low when an enabled interrupt condition occurs. This pin is an open drain structure with an internal pull up resistor to VDD. Chip select pin for the SPI. When the CS is low, the device is selected. In (LP) Mode with VDD ON, a transition on CS is a Wake-Up condition Clock input for the Serial Peripheral Interface (SPI) of the device SPI data received by the device SPI data sent to the MCU. When the CS is high, MISO is high-impedance 5.0 or 3.3 V output pin of the main regulator for the Microcontroller supply. 40 21 21 N/A N/A N/A I/O-1 Input/ Output Input Output 1 41 22 22 22 23 23 RST Output Reset Output (Active LOW) 42 23 23 23 24 24 INT Output Interrupt Output (Active LOW) Chip Select (Active LOW) 43 24 24 24 25 25 CS Input 44 45 46 47 48 49 50 25 26 27 28 29 30 31 25 26 27 28 29 30 31 25 26 27 28 29 30 N/A 26 27 28 29 30 31 32 26 27 28 29 30 31 32 SCLK MOSI MISO VDD TXD RXD VE Input Input Output Output Input Output Serial Data Clock Master Out / Slave In Master In / Slave Out Voltage Digital Drain Transmit Data CAN bus transmit data input. Internal pull-up to VDD Receive Data Voltage Emitter CAN bus receive data output Connection to the external PNP path transistor. This is an intermediate current supply source for the VDD regulator Base output pin for connection to the external PNP pass transistor Ground 51 32 32 N/A 1 1 VB GND Output Ground Voltage Base Ground EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD 33903/4/5 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS(2) V VSUP1/2 VSUP1/2TR VBUSLIN VBUSLINTR VBUS VBUSTR VSAFE VSAFETR VI/O VI/OTR VDIGLIN VDIG VINT VRST VRST VMUX VDBG ILH VREG VREG VE VSENSE -0.3 to 28 -0.3 to 40 V -28 to 28 -28 to 40 V -28 to 28 -32 to 40 V -0.3 to 28 -0.3 to 40 V -0.3 to 28 -0.3 to 40 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to 10 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to 10 200 -0.3 to 5.5 -0.3 to 40 -0.3 to 40 -28 to 40 V V V V V V V mA V V V V Symbol Value Unit Supply Voltage at VSUP/1 and VSUP2 Normal Operation (DC) Transient Conditions (Load Dump) DC voltage on LIN/1 and LIN2 Normal Operation (DC) Transient Conditions (Load Dump) DC voltage on CANL, CANH, SPLIT Normal Operation (DC) Transient Conditions (Load Dump) DC Voltage at SAFE Normal Operation (DC) Transient Conditions (Load Dump) DC Voltage at I/O-0, I/O-1, I/O-2, I/O-3 (LIN-T Pins) Normal Operation (DC) Transient Conditions (Load Dump) DC voltage on TXD-L, TXD-L1 TXD-L2, RXD-L, RXD-L1, RXD-L2 DC voltage on TXD, RXD DC Voltage at INT DC Voltage at RST DC Voltage at MOSI, MSIO, SCLK and CS DC Voltage at MUX-OUT DC Voltage at DBG Continuous current on CANH and CANL DC voltage at VDD, 5V-CAN, VAUX, VCAUX DC voltage at VBASE(3) (4) (4) and VBAUX DC voltage at VE DC voltage at VSENSE Notes 2. The voltage on non-VSUP pins should never exceed the VSUP voltage at any time or permanent damage to the device may occur. 3. 4. If the voltage delta between VSUP/1/2 and VBASE is greater than 6.0 V, the external VDD ballast current sharing functionality may be damaged. Potential Electrical Over Stress (EOS) damage may occur if RXD is in contact with VE while the device is ON. 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings (continued) All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ESD Capability AECQ100(5) Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 Ω) CANH and CANL. LIN1 and LIN2, Pins versus all GND pins all other Pins including CANH and CANL Charge Device Model - JESD22/C101 (CZAP = 4.0 pF) Corner Pins (Pins 1, 16, 17, and 32) All other Pins (Pins 2-15, 18-31) Tested per IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 Ω) Device unpowered, CANH and CANL pin without capacitor, versus GND Device unpowered, LIN, LIN1 and LIN2 pin, versus GND Device unpowered, VS1/VS2 (100 nF to GND), versus GND Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor on VSUP/1/2 pins (See Typical Applications on page 90) CANH, CANL without bus filter LIN, LIN1 and LIN2 with and without bus filter I/O with external components (22 k - 10 nF) THERMAL RATINGS Junction temperature Ambient temperature Storage temperature THERMAL RESISTANCE Thermal resistance junction to ambient(8) Peak package reflow temperature during reflow (6), (7) Symbol Value Unit V VESD1-1 VESD1-2 VESD2-1 VESD2-2 VESD3-1 VESD3-2 VESD3-3 ±8000 ±2000 ±750 ±500 ±15000 ±15000 ±15000 VESD4-1 VESD4-2 VESD4-3 ±9000 ±12000 ±7000 TJ TA TST 150 -40 to 125 -50 to 150 °C °C °C RθJA TPPRT 50(8) Note 7 °C/W °C Notes 5. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Charge Device Model (CDM), and Robotic (CZAP = 4.0 pF). 6. 7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. This parameter was measured according to Figure 15: PCB 100mm x 100mm 8. Top side, 300 sq. mm (20mmx15mm) Bottom side 20mm x 40mm Bottom view Figure 15. PCB with Top and Bottom Layer Dissipation Area (Dual Layer) 33903/4/5 18 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic POWER INPUT Nominal DC Voltage Range(9) Extended DC Low Voltage Range(10) Under-voltage Detector Thresholds, at the VSUP/1 pin, Low threshold (VSUP/1 ramp down) High threshold (VSUP/1 ramp up) Hysteresis Note: function not active in LP Modes Under-voltage Detector Thresholds, at the VSUP2 pin: Low threshold (VSUP2 ramp down) High threshold (VSUP2 ramp up) Hysteresis Note: function not active in LP Modes VSUP Over-voltage Detector Thresholds, at the VSUP/1 pin: Not active in LP Modes Battery loss detection threshold, at the VSUP/1 pin. VSUP/1 to turn VDD ON, VSUP/1 rising VSUP/1 to turn VDD ON, hysteresis (Guaranteed by design) Supply current(11), (12) - from VSUP/1 - from VSUP2, (5V-CAN VAUX, I/O OFF) Supply current, ISUP1 + ISUP2, Normal Mode, VDD ON - 5 V-CAN OFF, VAUX OFF - 5 V-CAN ON, CAN interface in Sleep Mode, VAUX OFF - 5 V-CAN OFF, Vaux ON - 5 V-CAN ON, CAN interface in TXD/RXD Mode, VAUX OFF, I/O-x disabled LP Mode VDD OFF. Wake-up from CAN, I/O-x inputs VSUP ≤ 18 V, -40 to 25 °C VSUP ≤ 18 V, 125 °C LP Mode VDD ON (5.0 V) with VDD under-voltage and VDD over-current monitoring, Wake-Up from CAN, I/O-x inputs VSUP ≤ 18 V, -40 to 25 °C, IDD = 1.0 μA VSUP ≤ 18 V, -40 to 25 °C, IDD = 100 μA VSUP ≤ 18 V, 125 °C, IDD = 100 μA LP Mode, additional current for oscillator (used for: cyclic sense, forced WakeUp, and in LP VDD ON Mode cyclic interruption and watchdog) VSUP ≤ 18 V, -40 to 125 °C Notes 9. All parameters in spec (ex: VDD regulator tolerance). 10. 11. 12. Device functional, some parameters could be out of spec. VDD is active, device is not in Reset Mode if the lowest VDD under-voltage reset threshold is selected (approx. 3.4 V). CAN and I/Os are not operational. In Run Mode, CAN interface in Sleep Mode, 5 V-CAN and VAUX turned OFF. IOUT at VDD < 50 mA. Ballast: turned OFF or not connected. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. Therefore, ISUP1 and ISUP2 cannot be measured individually. IOSC 5.0 9.0 ILPM_ON 20 40 65 85 μA ILPM_OFF 15 35 50 μA ISUP1+2 2.8 4.5 5.0 5.5 8.0 μA BATFAIL VSUP-TH1 VSUP-TH1HYST ISUP1 2.0 150 2.8 4.1 180 2.0 0.05 4.0 0.85 mA 4.0 4.5 V V mV mA VS_HIGH VS2_LOW 5.5 0.22 16.5 6.0 0.35 17 6.5 6.6 0.5 18.5 V VSUP1/VSUP2 VSUP1/VSUP2 VS1_LOW 5.5 0.22 6.0 0.35 6.5 6.6 0.5 V 5.5 4.0 28 5.5 V V V Symbol Min Typ Max Unit 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 19 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic VDD VOLTAGE REGULATOR, VDD PIN Output Voltage VDD = 5.0 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA VDD = 3.3 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA Drop voltage without external PNP pass VDD = 5.0 V, IOUT = 100 mA VDD = 5.0 V, IOUT = 150 mA Drop voltage with external transistor (13) Symbol Min Typ Max Unit V VOUT-5.0 VOUT-3.3 VDROP VDROP-B VSUP1-3.3 4.0 4.0 K ILIM TPW TSD CEXT VDDLP 4.75 3.135 LP-IOUTDC LP-ITH 1.0 0.1 LP-VDROP LP-MINVS VDD_OFF VDD_START UP 5.5 3.0 3.0 1.0 200 400 0.3 mV V V V 5.0 3.3 5.25 3.465 50 mA mA 1.5 150 160 4.7 2.0 350 140 2.5 550 100 mA °C °C μF V 350 500 V 330 450 500 mV 4.9 3.234 5.0 3.3 5.1 3.366 mV transistor(13) IOUT = 200 mA (I_BALLAST + I_INTERNAL) VSUP/1 to maintain VDD within VOUT-3.3 specified voltage range VDD = 3.3 V, IOUT = 150 mA VDD = 3.3 V, IOUT = 200 mA, external transistor implemented External ballast versus internal current ratio (I_BALLAST = K x Internal current) Output Current limitation, without external transistor Temperature pre-warning (Guaranteed by design) Thermal shutdown (Guaranteed by design) Range of decoupling capacitor (Guaranteed by design)(14) LP Mode VDD ON, IOUT ≤ 50 mA (time limited) VDD = 5.0 V, 5.6 V ≤ VSUP ≤ 28 V VDD = 3.3 V, 5.6 V ≤ VSUP ≤ 28 V LP Mode VDD ON, dynamic output current capability (Limited duration. Ref. to device description). LP VDD ON Mode: Over-current Wake-Up threshold. Hysteresis LP Mode VDD ON, drop voltage, at IOUT = 30 mA (Limited duration. Ref. to device description) (13) LP Mode VDD ON, min VSUP operation (Below this value, a VDD, under-voltage reset may occur) VDD when VSUP < VSUP-TH1, at I_VDD ≤ 10 μA (Guaranteed by design) VDD when VSUP ≥ VSUP-TH1, at I_VDD ≤ 40 mA (Guaranteed with parameter VSUP-TH1 Notes 13. For 3.3 V VDD devices, the drop-out voltage test condition leads to a VSUP below the min VSUP threshold (4.0 V). As a result, the dropout voltage parameter cannot be specified. 14. The regulator is stable without an external capacitor. Usage of an external capacitor is recommended for AC performance. 33903/4/5 20 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY, 5.0 V-CAN PIN Output voltage, VSUP/2 = 5.5 to 40 V IOUT 0 to 160 mA Output Current limitation (15) Under-voltage threshold Thermal shutdown (Guaranteed by design) External capacitance (Guaranteed by design) 5V-C OUT 5V-C ILIM 5V-C UV 5V-CTS CEXT-CAN VAUX 4.75 3.135 VAUX-UVTH 4.2 0.06 2.75 VAUX-ILIM 250 230 VAUX CAP VRST-TH1 2.2 360 330 450 430 100 μF 4.5 3.0 4.70 0.12 3.135 mA 5.0 3.3 5.25 3.465 V V 4.75 160 4.1 160 1.0 5.0 280 4.5 5.25 4.7 100 mA V °C μF Symbol Min Typ Max Unit V AUXILIARY OUTPUT, 5.0 AND 3.3 V SELECTABLE PIN VB-AUX, VC-AUX, VAUX VAUX output voltage VAUX = 5.0 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX = 3.3 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX under-voltage detector (VAUX configured to 5.0 V) Low Threshold Hysteresis VAUX under-voltage detector (VAUX configured to 3.3 V, default value) VAUX over-current threshold detector VAUX set to 3.3 V VAUX set to 5.0 V External capacitance (Guaranteed by design) UNDER-VOLTAGE RESET AND RESET FUNCTION, RST PIN VDD under-voltage threshold down - 90% VDD (VDD 5.0 V)(16), (18) VDD under-voltage threshold up - 90% VDD (VDD 5.0 V) VDD under-voltage threshold down - 90% VDD (VDD 3.3 V)(16), (18) VDD under-voltage threshold up - 90% VDD (VDD 3.3 V) VDD under-voltage reset threshold down - 70% VDD (VDD 5.0 V)(17), (18) Hysteresis for threshold 90% VDD, 5.0 V device for threshold 70% VDD, 5.0 V device Hysteresis 3.3 V VDD for threshold 90% VDD, 3.3 V device VDD under-voltage reset threshold down - LP VDD ON Mode (Note: device change to Normal Request Mode). VDD 5.0 V (Note: device change to Normal Request Mode). VDD 3.3 V Notes 15. 16. 17. 18. Current limitation will be reported by setting a flag. Generate a Reset or an INT. SPI programmable Generate a Reset In Non-LP Modes VRST-LP 4.0 2.75 4.5 3.0 4.85 3.135 10 150 V VRST-TH2-5 VRST-HYST 20 10 150 150 4.5 2.75 2.95 4.65 3.0 3.2 4.85 4.90 3.135 3.135 3.45 V mV V V 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 21 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic UNDER-VOLTAGE RESET AND RESET FUNCTION, RST PIN (CONTINUED) Reset VOL @ 1.5 mA, VSUP 5.5 to 28 V Current limitation, Reset activated, VRESET = 0.9 x VDD Pull-up resistor (to VDD pin) VSUP to guaranteed reset low level(19) Reset input threshold Low threshold, VDD = 5.0 V High threshold, VDD = 5.0 V Low threshold, VDD = 3.3 V High threshold, VDD = 3.3 V Reset input hysteresis I/O PINS WHEN FUNCTION SELECTED IS OUTPUT I/O-0 HS switch drop @ I = -12 mA, VSUP = 10.5 V I/O-2 and I/O-3 HS switch drop @ I = -20 mA, VSUP = 10.5 V I/O-1, HS switch drop @ I = -400 μA, VSUP = 10.5 V I/O-0, I/O-1 LS switch drop @ I = 400 μA, VSUP = 10.5 V Leakage current, I/O-x ≤ VSUP I/O PINS WHEN FUNCTION SELECTED IS INPUT Negative threshold Positive threshold Hysteresis Input current, I/O ≤ VSUP/2 I/O-0 and I/O-1 input resistor. I/O-0 (or I/O-1) selected in register, 2.0 V < VI/O-X 2.0 kΩ Internal pull-down resistor for regulator output current sense External capacitor at MUX OUTPUT(20) (Guaranteed by design) Chip temperature sensor coefficient (Guaranteed by design and device characterization) VDD = 5.0 V VDD = 3.3 V Chip temperature: MUX-OUT voltage VDD = 5.0 V, TA = 125 °C VDD = 3.3 V, TA = 125 °C Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) TA = -40 °C, VDD = 5.0 V TA = 25 °C, VDD = 5.0 V TA = -40 °C, VDD = 3.3 V TA = 25 °C, VDD = 3.3 V Gain for VSENSE, with external 1.0 k 1% resistor VDD = 5.0 V VDD = 3.3 V Offset for VSENSE, with external 1.0 k 1% resistor Divider ratio for VSUP/1 VDD = 5.0 V VDD = 3.3 V Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: VDD = 5.0 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1) VDD = 5.0 V, (Gain, MUX-OUT register bit 3 set to 0) VDD = 3.3 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1) VDD = 3.3 V, (Gain, MUX-OUT register bit 3 set to 0) Internal reference voltage VDD = 5.0 V VDD = 3.3 V Current ratio between VDD output & IOUT at MUX-OUT (IOUT at MUX-OUT = IDD out / IDD_RATIO) At IOUT = 50 mA I_OUT from 25 to 150 mA SAFE OUTPUT SAFE low level, at I = 500 μA Safe leakage current (VDD low, or device unpowered). VSAFE 0 to 28 V. Notes 20. When C is higher than CMUX, a serial resistor must be inserted VOL ISAFE-IN 0.0 0.2 0.0 1.0 1.0 V μA 80 62.5 97 97 115 117 IDD_RATIO VREF 2.45 1.64 2.5 1.67 2.55 1.7 VI/O RATIO 3.8 5.6 4.0 2.0 5.8 1.3 4.2 6.2 V VSENSE OFFSET VSUP/1 RATIO 5.335 7.95 5.5 8.18 5.665 8.45 VSENSE GAIN 5.42 8.1 -20 5.48 8.2 5.54 8.3 20 mV VTEMP(GD) 0.12 1.5 0.07 1.08 0.30 1.65 0.19 1.14 0.48 1.8 0.3 1.2 VTEMP 3.6 2.45 3.75 2.58 3.9 2.65 V VOUT_MAX RMI CMUX TEMP-COEFF 20 13.2 21 13.9 22 14.6 V 0.0 0.8 1.9 VDD - 0.5 2.8 1.0 V kΩ nF mv/°C Symbol Min Typ Max Unit 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 23 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic INTERRUPT Output low voltage, IOUT = 1.5 mA Pull-up resistor Output high level in LP VDD ON Mode (Guaranteed by design) Leakage current INT voltage = 10 V (to allow high-voltage on MCU INT pin) Sink current, VINT > 5.0 V, INT low state MISO, MOSI, SCLK, CS PINS Output low voltage, IOUT = 1.5 mA (MISO) Output high voltage, IOUT = -0.25 mA (MISO) Input low voltage (MOSI, SCLK,CS) Input high voltage (MOSI, SCLK,CS) Tri-state leakage current (MISO) Pull-up current (CS) CAN LOGIC INPUT PINS (TXD) High Level Input Voltage Low Level Input Voltage Pull-up Current, TXD, VIN = 0 V VDD =5.0 V VDD =3.3 V CAN DATA OUTPUT PINS (RXD) Low Level Output Voltage IRXD = 5.0 mA High Level Output Voltage IRX = -3.0 mA High Level Output Current VRXD = VDD - 0.4 V Low Level Input Current VRXD = 0.4 V IOUTLOW 2.5 5.0 9.0 IOUTHIGH 2.5 5.0 9.0 mA VOUTHIGH 0.7 x VDD VDD mA VOUTLOW 0.0 0.3 x VDD V V VIH VIL IPDWN -850 -500 -650 -250 -200 -175 0.7 x VDD -0.3 VDD + 0.3 0.3 x VDD V V µA VOL VOH VIL VIH IHZ IPU VDD -0.9 0.7 x VDD -2.0 200 370 0.3 x VDD 2.0 500 1.0 V V V V μA μA VOL RPU VOH-LPVDDON VMAX I SINK 6.5 3.9 2.5 0.2 10 4.3 35 6.0 100 10 1.0 14 V kΩ V Symbol Min Typ Max Unit μA mA 33903/4/5 24 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic CAN OUTPUT PINS (CANH, CANL) Bus pins common mode voltage for full functionality Differential input voltage threshold Differential input hysteresis Input resistance Differential input resistance Input resistance matching CANH output voltage (45 Ω < RBUS < 65 Ω) TXD dominant state TXD recessive state CANL output voltage (45 Ω < RBUS < 65 Ω) TXD dominant state TXD recessive state Differential output voltage (45 Ω < RBUS < 65 Ω) TXD dominant state TXD recessive state CAN H output current capability - Dominant state CAN L output current capability - Dominant state CANL over-current detection - Error reported in register CANH over-current detection - Error reported in register CANH, CANL input resistance to GND, device supplied, CAN in Sleep Mode, V_CANH, V_CANL from 0 to 5.0 V CANL, CANH output voltage in LP VDD OFF and LP VDD ON modes CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device unpowered (VSUP, VDD, 5V-CAN: open).(21) CANH, CANL input current, VCANH, VCANL = -2.0 to 7.0 V, device unpowered (VSUP, VDD, 5V-CAN: open).(21) Differential voltage for recessive bit detection in LP Mode(22) Differential voltage for dominant bit detection in LP Mode(22) CANH AND CANL DIAGNOSTIC INFORMATION CANL to GND detection threshold CANH to GND detection threshold CANL to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V CANH to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V CANL to VDD detection threshold CANH to VDD detection threshold VLG VHG VLVB VHVB VL5 VH5 1.6 1.6 4.0 4.0 1.75 1.75 VSUP -2.0 VSUP -2.0 VDD -0.43 VDD -0.43 2.0 2.0 V V V V V V ICANH ICANL ICANL-OC ICANH-OC RINSLEEP VCANLP ICAN-UN_SUP1 ICAN-UN_SUP2 VDIFF-R-LP VDIFF-D-LP VOH-VOL 1.5 -0.5 30 75 -195 5.0 -0.1 1.15 2.0 0.0 120 -120 0.0 3.0 3.0 0.05 -30 195 -75 50 0.1 10 250 0.4 mA mA mA mA kΩ V µA µA V V VCANL 0.5 2.0 1.5 2.5 2.25 3.0 V VCOM VCANH-VCANL VDIFF-HYST RIN RIN-DIFF RIN-MATCH VCANH 2.75 2.0 3.5 2.5 4.5 3.0 V -12 500 50 5.0 10 -3.0 0.0 12 900 50 100 3.0 V mV mV kΩ kΩ % V Symbol Min Typ Max Unit Notes 21. VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device characterization. 22. Guaranteed by design and device characterization. 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 25 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic SPLIT Output voltage Loaded condition ISPLIT = ±500 µA Unloaded condition Rmeasure > 1.0 MΩ Leakage current -12 V < VSPLIT < +12 V -22 to -12 V < VSPLIT < +12 to +35 V LIN TERMINALS (LIN-T/1, LIN-T2) LIN-T1, LIN-T2, HS switch drop @ I = -20 mA, VSUP > 10.5 V Operating Voltage Range Supply Voltage Range Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V Input Leakage Current at the receiver Driver off; VBUS = 0 V; VBAT = 12 V Leakage Output Current to GND Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT Control unit disconnected from ground (Loss of local ground must not affect communication in the residual network) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V (Guaranteed by design) VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V (Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition). (Guaranteed by design) Receiver Dominant State Receiver Recessive State Receiver Threshold Center (VTH_DOM + VTH_REC)/2 Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) LIN Wake-up threshold from LP VDD ON or LP VDD OFF Mode LIN Pull-up Resistor to VSUP Over-temperature Shutdown (Guaranteed by design) Over-temperature Shutdown Hysteresis (Guaranteed by design) VBUSWU RSLAVE TLINSD TLINSD_HYS VHYS 20 140 5.3 30 160 10 0.175 5.8 60 180 V kΩ °C °C IBUS_NO_GND -1.0 IBUSNO_BAT VBUSDOM VBUSREC 0.6 VBUS_CNT 0.475 0.5 0.525 VSUP VSUP 0.4 VSUP 100 VSUP 1.0 µA IBUS_PAS_REC 20 mA IBUS_PAS_DOM -1.0 µA VLT_HSDRP VBAT VSUP IBUS_LIM 40 90 200 mA 1.0 1.4 V LIN1 & LIN2 33903D/5D PIN - LIN 33903S/5S PIN (Parameters guaranteed for VSUP/1, VSUP2 7.0 V ≤ VSUP ≤ 18 V) 8.0 7.0 18 18 V V mA ILSPLIT 0.0 5.0 200 VSPLIT 0.3 x VDD 0.5 x VDD 0.45 x VDD 0.7 x VDD 0.5 x VDD 0.55 x VDD µA V Symbol Min Typ Max Unit 33903/4/5 26 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic SPI TIMING SPI Operation Frequency (MISO cap = 50 pF) SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Falling Edge of CS to Rising Edge of SCLK Falling Edge of SCLK to Rising Edge of CS MOSI to Falling Edge of SCLK Falling Edge of SCLK to MOSI MISO Rise Time (CL = 50 pF) MISO Fall Time (CL = 50 pF) Time from Falling to MISO Low-impedance Time from Rising to MISO High-impedance Time from Rising Edge of SCLK to MISO Data Valid Delay between rising and falling edge on CS CS low timeout detection SUPPLY, VOLTAGE REGULATOR, RESET VSUP under-voltage detector threshold deglitcher Rise time at turn ON. VDD from 1.0 to 4.5 μV. 2.2 μF at the VDD pin. Deglitcher time to set RESET pin low RESET PULSE DURATION VDD under-voltage (SPI selectable) short, default at power on when BATFAIL bit set medium medium long long Watchdog reset I/O INPUT Deglitcher time (Guaranteed by design) VSENSE INPUT Under-voltage deglitcher time tBFT 30 100 μs tIODT 19 30 41 μs tRST-WD tRST-PULSE 0.9 4.0 8.5 17 0.9 1.0 5.0 10 20 1.0 1.4 6.0 12 24 1.4 ms ms tVS_LOW1/ 2_DGLT Symbol Min Typ Max Unit FREQ tPCLK tWSCLKH tWSCLKL tLEAD tLAG tSISU tSIH tRSO tFSO tSOEN tSODIS tVALID tD2CS tCS-TO 0.25 250 125 125 30 30 30 30 1.0 2.5 - 4.0 N/A N/A N/A N/A N/A N/A N/A 30 30 30 30 30 - MHz ns ns ns ns ns ns ns ns ns ns ns μs ms 30 50 20 50 250 30 100 800 40 μs μs μs tRISE-ON tRST-DGLT 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 27 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic INTERRUPT INT pulse duration (refer to SPI for selection. Guaranteed by design) short (25 to 125 °C) short (-40 °C) long (25 to 125 °C) long (-40 °C) STATE DIGRAM TIMINGS Delay for SPI Timer A, Timer B or Timer C write command after entering Normal Mode (No command should occur within tD_NM. tD_NM delay definition: from CS rising edge of “Go to Normal Mode (i.e. 0x5A00)” command to CS falling edge of “Timer write” command) Tolerance for: watchdog period in all modes, FWU delay, Cyclic sense period tTIMING-ACC and active time, Cyclic Interrupt period, LP Mode over-current (unless otherwise noted)(26) CAN DYNAMIC CHARACTERISTICS TXD Dominant State Timeout Bus dominant clamping detection Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate) Propagation delay TXD to CAN, recessive to dominant Propagation delay CAN to RXD, recessive to dominant Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate) Propagation delay TXD to CAN, dominant to recessive Propagation delay CAN to RXD, dominant to recessive Loop time TXD to RXD, Medium Slew Rate (Selected by SPI) Recessive to Dominant Dominant to Recessive Loop time TXD to RXD, Slow Slew Rate (Selected by SPI) Recessive to Dominant Dominant to Recessive CAN Wake-Up filter time, single dominant pulse detection CAN Wake-Up filter time, 3 dominant pulses detection CAN Wake-Up filter time, 3 dominant pulses detection Figure 38) (24) (23) Symbol Min Typ Max Unit tINT-PULSE 20 20 90 90 25 25 100 100 35 40 130 140 μs tD_NM 60 - - μs -10 - 10 % tDOUT tDOM tLRD tTRD tRRD tLDR tTDR tRDR tLOOP-MSL 300 300 60 100 - 600 600 120 70 45 120 75 50 1000 1000 210 110 140 200 150 140 µs µs ns ns ns ns ns ns ns tLOOP-SSL (See Figure 37) tCAN-WU1-F tCAN-WU3-F (See tCAN-WU3-TO 0.5 300 - 200 200 ns 300 300 2.0 - 5.0 120 μs ns μs timeout(25) Notes 23. No Wake-Up for single pulse shorter than tCAN-WU1 min. Wake-up for single pulse longer than tCAN-WU1 max. 24. 25. 26. Each pulse should be greater than tCAN-WU3-F min. Guaranteed by design, and device characterization. The 3 pulses should occur within tCAN-WU3-TO. Guaranteed by design, and device characterization. Guaranteed by design. 33903/4/5 28 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 KΩ, 6.8 NF / 660 Ω, 10 NF / 500 Ω. SEE Figure 20, PAGE 31. Duty Cycle 1: THREC(MAX) = 0.744 * VSUP THDOM(MAX) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V 0.581 0.396 - D1 D2 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 KΩ, 6.8 NF / 660 Ω, 10 NF / 500 Ω. MEASUREMENT THRESHOLDS. SEE Figure 21, PAGE 32. Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V Duty Cycle 4: THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) SRFAST 20 V / μs 0.590 0.417 - D3 D4 LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS VSUP FROM 7.0 TO 18 V, BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 KΩ, 6.8 NF / 660 Ω, 10 NF / 500 Ω. SEE Figure 20, PAGE 31. Propagation Delay and Symmetry (See Figure 20, page 31 and Figure 21, page 32) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR Bus Wake-up Deglitcher (LP VDD OFF and LP VDD ON modes) (See Figure 22, page 31 for LP VDD OFF Mode and Figure 23, page 32 for LP Mode) Bus Wake-up Event Reported From LP VDD OFF Mode From LP VDD ON Mode TXD Permanent Dominant State Delay (Guaranteed by design) μs t REC_PD t REC_SYM t PROPWL - 2.0 42 4.2 70 6.0 2.0 95 μs μs t WAKE_LPVDD OFF 1.0 0.65 1.0 1500 12 1.35 s t WAKE_LPVDD ON t TXDDOM 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 29 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS tPCLK CS tLEAD tWCLKH tLAG SCLK tWCLKL tSISU tSIH MOSI Undefined tVALID tSOEN Di 0 Don‚ÄöÐÑÐ¥ Di n Don‚ÄöÐÑÐ¥ tSODIS MISO Do 0 Figure 16. SPI Timings Do n TXD 0.3 x VDD RXD tLRD 0.7 x VDD tLDR 0.3 x VDD 0.7 x VDD Figure 17. CAN Signal Propagation Loop Delay TXD to RXD TXD 0.3 x VDD VDIFF tTRD 0.7 x VDD tTDR 0.9 V tRRD 0.5 V tRDR 0.7 x VDD RXD 0.3 x VDD Figure 18. CAN Signal Propagation Delays TXD to CAN and CAN to RXD 33903/4/5 30 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS . 12 V 10 ¬¨ VSUP 5 V_CAN 100 nF CANH Signal generator TXD CANL RXD 15 pF GND SPLIT All pins are not shown RBUS 60 Ω CBus 100 pF 22 ¬¨ Figure 19. Test Circuit for CAN Timing Characteristics TXD tBIT tBIT VLIN_REC THREC(MAX) THDOM(MAX) 74.4% VSUP 58.1% VSUP tBUS_DOM(MAX) tBUS_REC(MIN) Thresholds of receiving node 1 LIN THREC(MIN) THDOM(MIN) 42.2% VSUP 28.4% VSUP Thresholds of receiving node 2 tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2) Figure 20. LIN Timing Measurements for Normal Slew Rate 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 31 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD tBIT tBIT VLIN_REC THREC(MAX) THDOM(MAX) 77.8% VSUP 61.6% VSUP tBUS_DOM(MAX) tBUS_REC(MIN) Thresholds of receiving node 1 LIN THREC(MIN) THDOM(MIN) 38.9% VSUP 25.1% VSUP Thresholds of receiving node 2 tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2) Figure 21. LIN Timing Measurements for Slow Slew Rate V REC LIN 0.4 V SUP Dominant level V BUSWU VDD 3V T PROPWL T WAKE Figure 22. LIN Wake-up LP VDD OFF Mode Timing 33903/4/5 32 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS V LIN_REC LIN 0.4 V SUP Dominant level V BUSWU IRQ T PROPWL T WAKE IRQ stays low until SPI reading command Figure 23. LIN Wake-up LP VDD ON Mode Timing 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The MC33903_4_5 is the second generation of System Basis Chip, combining: - Advanced power management unit for the MCU, the integrated CAN interface and for the additional ICs such as sensors, CAN transceiver. - Built in enhanced high speed CAN interface (ISO118982 and -5), with local and bus failure diagnostic, protection and fail-safe operation mode. - Built in LIN interface, compliant to LIN 2.1 and J2602-2 specification, with local and bus failure diagnostic and protection. - Innovative hardware configurable fail-safe state machine solution. - Multiple LP Modes, with low current consumption. - Family concept with pin compatibility; with and without LIN interface devices. FUNCTIONAL PIN DESCRIPTION POWER SUPPLY (VSUP/1 AND VSUP2) Note: VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. VSUP1 is the input pin for the internal supply and the VDD regulator. VSUP2 is the input pin for the 5 V-CAN regulator, LIN’s interfaces and I/O functions. The VSUP block includes over and under-voltage detections which can generate interrupt. The device includes a loss of battery detector connected to VSUP/1. Loss of battery is reported through a bit (called BATFAIL). This generates a POR (Power On Reset). (Wake-Up detection, timer start for over-current duration monitoring or watchdog refresh). EXTERNAL TRANSISTOR Q1 (VE AND VB) The device has a dedicated circuit to allow usage of an external “P” type transistor, with the objective to share the power dissipation between the internal transistor of the VDD regulator and the external transistor. The recommended bipolar PNP transistor is MJD42C or BCP52-16. When the external PNP is connected, the current is shared between the internal path transistor and the external PNP, with the following typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control is done by SPI. The device is able to operate without an external transistor. In this case, the VE and VB pins must remain open. VDD VOLTAGE REGULATOR (VDD) The regulator has two main modes of operation (Normal Mode and LP Mode). It can operate with or without an external PNP transistor. In Normal Mode, without external PNP, the max DC capability is 150 mA. Current limitation, temperature prewarning flag and over-temperature shutdown features are included. When VDD is turned ON, rise time from 0 to 5.0 V is controlled. Output voltage is 5.0 V. A 3.3 V option is available via dedicated part number. If current higher than 150 mA is required, an external PNP transistor must be connected to VE (PNP emitter) and VB (PNP base) pins, in order to increase total current capability and share the power dissipation between internal VDD transistor and the external transistor. See External Transistor Q1 (VE and VB). The PNP can be used even if current is less than 150 mA, depending upon ambient temperature, maximum supply and thermal resistance. Typically, above 100-200 mA, an external ballast transistor is recommended. 5 V-CAN VOLTAGE REGULATOR FOR CAN AND ANALOG MUX This regulator is supplied from the VSUP/2 pin. A capacitor is required at 5 V-CAN pin. Analog MUX and part of the LIN interfaces are supplied from 5 V-CAN. Consequently, the 5 V-CAN must be ON in order to have Analog MUX operating and to have the LIN interface operating in TXD/RXD Mode. The 5 V-CAN regulator is OFF by default and must be turned ON by SPI. In Debug Mode, the 5 V-CAN is ON by default. V AUXILIARY OUTPUT, 5.0 AND 3.3 V SELECTABLE (VB-AUX, VC-AUX, AND VCAUX) Q2 The VAUX block is used to provide an auxiliary voltage output, 5.0 or 3.3 V, selectable by the SPI. It uses an external PNP pass transistor for flexibility and power dissipation constraints. The external recommended bipolar transistors are MJD42C or BCP52-16. An over-current and under-voltage detectors are provided. VDD REGULATOR IN LP MODE When the device is set in LP VDD ON Mode, the VDD regulator is able to supply the MCU with a DC current below typically 1.5 mA (LP-ITH). Transient current can also be supplied up to a tenth of a mA. Current in excess of 1.5 mA is detected, and this event is managed by the device logic 33903/4/5 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION VAUX is controlled via the SPI, and can be turned ON or OFF. VAUX low threshold detection and over-current information will disable VAUX, and are reported in the SPI and can generate INT. VAUX is OFF by default and must be turned ON by the SPI. When cyclic sense is used, I/O-0 is the HS/LS switch, I/O1, -2 and -3 are the wake inputs. I/O-2 and I/O-3 pins share the LIN Master pin function. VSENSE INPUT (VSENSE) This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a capacitor to GND. It incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX-OUT pin. UNDER-VOLTAGE RESET AND RESET FUNCTION (RST) The RESET pin is an open drain structure with an internal pull-up resistor. The LS driver has limited current capability when asserted low, in order to tolerate a short to 5.0 V. The RESET pin voltage is monitored in order to detect failure (e.g. RESET pin shorted to 5.0 V or GND). The RESET pin reports an under-voltage condition to the MCU at the VDD pin, as well as failure in the watchdog refresh operation. VDD under-voltage reset also operates in LP VDD ON Mode. Two VDD under-voltage thresholds are included. The upper (typically 4.65 V, RST-TH1-5) can lead to a Reset or an Interrupt. This is selected by the SPI. When “RST-TH2-5“is selected, in Normal Mode, an INT is asserted when VDD falls below “RST-TH1-5“, then, when VDD falls below “RST-TH2-5” a Reset will occur. This will allow the MCU to operate in a degraded mode (i.e., with 4.0 V VDD). MUX-OUTPUT (MUXOUT) The MUX-OUT pin (Figure 24) delivers an analog voltage to the MCU A/D input. The voltage to be delivered to MUXOUT is selected via the SPI, from one of the following functions: VSUP/1, VSENSE, I/O-0, I/O-1, Internal 2.5 V reference, die temperature sensor, VDD current copy. Voltage divider or amplifier is inserted in the chain, as shown in Figure 24. For the VDD current copy, a resistor must be added to the MUX-OUT pin, to convert current into voltage. Device includes an internal 2.0 k resistor selectable by the SPI. Voltage range at MUX-OUT is from GND to VDD. It is automatically limited to VDD (max 3.3 V for 3.3 V part numbers). The MUX-OUT buffer is supplied from 5 V-CAN regulator, so the 5 V-CAN regulator must be ON in order to have: 1) MUX-OUT functionality and 2) SPI selection of the analog function. If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND and the SPI command that selects one of the analog inputs is ignored. Delay must be respected between SPI commands for 5 VCAN turned ON and SPI to select MUX-OUT function. The delay depends mainly upon the 5 V-CAN capacitor and load on 5 V-CAN. The delay can be estimated using the following formula: delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN. C = cap at 5 V-CAN regulator, U = 5.0 V, I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator (parameter 5 V-C ILIM). I/O PINS (I/O-0: I/O-3) I/Os are configurable input/output pins. They can be used for small loads or to drive external transistors. When used as output drivers, the I/Os are either a HS or LS type. They can also be set to high-impedance. I/Os are controlled by the SPI and at power on, the I/Os are set as inputs. They include over-load protection by temperature or excess of a voltage drop. When I/O-0/-1/-2/-3 voltage is greater than VSUP/2 voltage, the leakage current (II/O_LEAK) parameter is not applicable • I/O-0 and I/O-1 will have current flowing into the device through three diodes limited by an 80 kOhm resistor (in series). • I/O-2 and I/O-3 will have unlimited current flowing into the device through one diode. In LP Mode, the state of the I/O can be turned ON or OFF, with extremely low power consumption (except when there is a load). Protection is disabled in LP Mode. 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION VBAT D1 VSUP/1 VSENSE RSENSE 1.0 k S_in Multiplexer S_in S_iddc 5 V-CAN buffer S_g3.3 S_I/O_att VDD-I_COPY 5 V-CAN MCU MUX-OUT A/D in RMI S_ir RM(*) (*)Optional I/O-0 S_in S_g5 Temp VREF: 2.5 V S_I/O_att I/O-1 S_in All swicthes and resistor are configured and controlled via the SPI RM: internal resistor connected when VREG current monitor is used S_g3.3 and S_g5 for 5.0 V or 3.3 V VDD versions S_iddc to select VDD regulator current copy S_in1 for LP Mode resistor bridge disconnection S_ir to switch on/off of the internal RMI resistor S_I/O_att for I/O-0 and I/O-1 attenuation selection Figure 24. Analog Multiplexer Block Diagram DGB (DGB) AND DEBUG MODE Primary Function It is an input used to set the device in Debug Mode. This is achieved by applying a voltage between 8.0 and 10 V at the DEBUG pin and then, powering up the device (See State Diagram 40). When the device leaves the INIT Reset Mode and enters into INIT Mode, it detects the voltage at the DEBUG pin to be between a range of 8.0 to 10 V, and activates the Debug Mode. When Debug Mode is detected, no Watchdog SPI refresh commands are necessary. This allows an easy debug of the hardware and software routines (i.e. SPI commands). When the device is in Debug Mode it is reported by the SPI flag. While in Debug Mode, and the voltage at DBG pin falls below the 8.0 to 10 V range, the Debug Mode is left, and the device starts the watchdog operation, and expects the proper watchdog refresh. The Debug Mode can be left by SPI. This is recommended to avoid staying in Debug Mode when an unwanted Debug Mode selection (FMEA pin) is present. The SPI command has a higher priority than providing 8.0 to 10 V at the DEBUG pin. Secondary Function The resistor connected between the DBG pin and the GND selects the Fail-Safe Mode operation. DBG pin can also be connected directly to GND (this prevents the usage of Debug Mode). Flexibility is provided to select SAFE output operation via a resistor at the DBG pin or via a SPI command. The SPI command has higher priority than the hardware selection via Debug resistor. When the Debug Mode is selected, the SAFE modes cannot be configured via the resistor connected at DBG pin. SAFE Safe Output Pin This pin is an output and is asserted low when a fault event occurs. The objective is to drive electrical safe circuitry and set the ECU in a known state, independent of the MCU and SBC, once a failure has been detected. The SAFE output structure is an open drain, without a pullup. INTERRUPT (INT) The INT output pin is asserted low or generates a low pulse when an interrupt condition occurs. The INT condition is enabled in the INT register. The selection of low level or pulse and pulse duration are selected by SPI. No current will flow inside the INT structure when VDD is low, and the device is in LP VDD OFF Mode. This allows the connection of an external pull-up resistor and connection of an INT pin from other ICs without extra consumption in unpowered mode. 33903/4/5 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION INT has an internal pull-up structure to VDD. In LP VDD ON Mode, a diode is inserted in series with the pull-up, so the high level is slightly lower than in other modes. CANH, CANL, SPLIT, RXD, TXD These are the pins of the high speed CAN physical interface, between the CAN bus and the micro controller. A detail description is provided in the document. LIN, LIN-T, TXDL AND RXDL These are the pins of the LIN physical interface. Device contains zero, one or two LIN interfaces. The MC33903 and MC33904 do not have a LIN interface. However, the MC33903S/5S (S = Single) and MC33903D/5D (D=Dual) contain 1 and 2 LIN interfaces, respectively. LIN, LIN1 and LIN2 pins are the connection to the LIN sub buses. LIN interfaces are connected to the MCU via the TXD, TXD-L1 and TXD-L2 and RXD, RXD-L1 and RXD-L2 pins. The device also includes one or two HS switches to VSUP/ 2 pin which can be used as a LIN master termination switch. Pins LINT, LINT-1 and LINT-2 pins are the same as I/O-2 and I/O-3. 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION The device has several operation modes. The transitions and conditions to enter or leave each mode are illustrated in the state diagram. A watchdog refresh SPI command is necessary to transition to NORMAL Mode. The duration of the Normal request mode is 256 ms when Normal Request Mode is entered after RESET Mode. Different durations can be selected by SPI when normal request is entered from LP VDD ON Mode. If the watchdog refresh SPI command does not occur within the 256 ms (or the shorter user defined time out), then the device will enter into RESET Mode for a duration of typically 1.0 ms. Note: in init reset, init, reset and normal request modes as well as in LP Modes, the VDD external PNP is disabled. INIT RESET This mode is automatically entered after the device is “powered on”. In this mode, the RST pin is asserted low, for a duration of typically 1.0 ms. Control bits and flags are “set” to their default reset condition. The BATFAIL is set to indicate the device is coming from an unpowered condition, and all previous device configurations are lost and “reset” the default value. The duration of the INIT reset is typically 1.0 ms. INIT reset mode is also entered from INIT Mode if the expected SPI command does not occur in due time (Ref. INIT Mode), and if the device is not in the debug mode. NORMAL In this mode, all device functions are available. This mode is entered by a SPI watchdog refresh command from Normal Request Mode, or from INIT Mode. During Normal Mode, the device watchdog function is operating, and a periodic watchdog refresh must occur. When an incorrect or missing watchdog refresh command is initiated, the device will enter into Reset Mode. While in Normal Mode, the device can be set to LP Modes (LP VDD ON or LP VDD OFF) using the SPI command. Dedicated, secured SPI commands must be used to enter from Normal Mode to Reset Mode, INIT Mode or Flash Mode. INIT This mode is automatically entered from the INIT Reset Mode. In this mode, the device must be configured via SPI within a time of 256 ms max. Four registers called INIT Wdog, INIT REG, INIT LIN I/O and INIT MISC must be, and can only be configured during INIT Mode. Other registers can be written in this and other modes. Once the INIT register configuration is done, a SPI Watchdog Refresh command must be sent in order to set the device into Normal Mode. If the SPI watchdog refresh does not occur within the 256 ms period, the device will return into INIT Reset Mode for typically 1.0 ms, and then re enter into INIT Mode. Register read operation is allowed in INIT Mode to collect device status or to read back the INIT register configuration. When INIT Mode is left by a SPI watchdog refresh command, it is only possible to re-enter the INIT Mode using a secured SPI command. In INIT Mode, the CAN, LIN1, LIN2, VAUX, I/O_x and Analog MUX functions are not operating. The 5 V-CAN is also not operating, except if the Debug Mode is detected. FLASH In this mode, the software watchdog period is extended up to typically 32 seconds. This allow programming of the MCU flash memory while minimizing the software over head to refresh the watchdog. The flash mode is entered by Secured SPI command and is left by SPI command. Device will enter into Reset Mode. When an incorrect or missing watchdog refresh command device will enter into Reset Mode. An interrupt can be generated at 50% of the watchdog period. CAN interface operates in Flash Mode to allow flash via CAN bus, inside the vehicle. RESET In this mode, the RST pin is asserted low. Reset Mode is entered from Normal Mode, Normal Request Mode, LP VDD on Mode and from the Flash Mode when the watchdog is not triggered, or if a VDD low condition is detected. The duration of reset is typically 1.0 ms by default. You can define a longer Reset pulse activation only when the Reset Mode is entered following a VDD low condition. Reset pulse is always 1.0 ms, when reset mode is entered due to wrong watchdog refresh command. Reset Mode can be entered via the secured SPI command. DEBUG Debug is a special operation mode of the device which allows for easy software and hardware debugging. The debug operation is detected after power up if the DBG pin is set to 8.0 to 10 V range. When debug is detected, all the software watchdog operations are disabled: 256 ms of INIT Mode, watchdog refresh of Normal Mode and Flash Mode, Normal Request time out (256 ms or user defined value) are not operating and will not lead to transition into INIT reset or Reset Mode. When the device is in Debug Mode, the SPI command can be sent without any time constraints with respect to the watchdog operation and the MCU program can be “halted” or “paused” to verify proper operation. NORMAL REQUEST This mode is automatically entered after RESET Mode, or after a Wake-Up from LP VDD ON Mode. 33903/4/5 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LP MODES Debug can be left by removing 8 to 10 V from the DEBUG pin, or by the SPI command (Ref. to MODE register). The 5 V-CAN regulator is ON by default in Debug Mode. LP MODES The device has two main LP modes: LP Mode with VDD OFF, and LP Mode with VDD ON. Prior to entering into LP Mode, I/O and CAN Wake-Up flags must be cleared (Ref. to mode register). If the Wake-Up flags are not cleared, the device will not enter into LP Mode. In addition, the CAN failure flags (i.e. CAN_F and CAN_UF) must be cleared, in order to meet the LP current consumption specification. During this mode, the 5 V-CAN and VAUX regulators are OFF. The optional external PNP at VDD will also be automatically disabled when entering this mode. The same Wake-Up events as in LP VDD OFF Mode (CAN, LIN, I/O, timer, cyclic sense) are available in LP VDD on Mode. In addition, two additional Wake-Up conditions are available. • Dedicated SPI command. When device is in LP VDD ON Mode, the Wake-Up by SPI command uses a write to “Normal Request Mode”, 0x5C10. • Output current from VDD exceeding LP-ITH threshold. In LP VDD ON Mode, the device is able to source several tenths of mA DC. The current source capability can be time limited, by a selectable internal timer. Timer duration is up to 32 ms, and is triggered when the output current exceed the output current threshold typically 1.5 mA. This allows for instance, a periodic activation of the MCU, while the device remains in LP VDD on Mode. If the duration exceed the selected time (ex 32 ms), the device will detect a Wake-Up. Wake-up events are reported to the MCU via a low level pulse at INT pulse. The MCU will detect the INT pulse and resume operation. Watchdog Function in LP VDD ON Mode It is possible to enable the watchdog function in LP VDD ON Mode. In this case, the principle is timeout. Refresh of the watchdog is done either by: • a dedicated SPI command (different from any other SPI command or simple CS activation which would WakeUp - Ref. to the previous paragraph) • or by a temporary (less than 32 ms max) VDD over current Wake-Up (IDD > 1.5 mA typically). As long as the watchdog refresh occurs, the device remains in LP VDD on Mode. Mode Transitions Mode transitions are either done automatically (i.e. after a timeout expired or voltage conditions), or via a SPI command, or by an external event such as a Wake-Up. Some mode changes are performed using the Secured SPI commands. LP - VDD OFF In this mode, VDD is turned OFF and the MCU connected to VDD is unsupplied. This mode is entered using SPI. It can also be entered by an automatic transition due to fail safe management. 5 V-CAN and VAUX regulators are also turned OFF. When the device is in LP VDD OFF Mode, it monitors external events to Wake-Up and leave the LP Mode. The Wake-Up events can occur from: • CAN • LIN interface, depending upon device part number • Expiration of an internal timer • I/O-0, and I/O-1 inputs, and depending upon device part number and configuration, I/O-2 and/or -3 input • Cyclic sense of I/O-1 input, associated by I/O-0 activation, and depending upon device part number and configuration, cyclic sense of I/O-2 and -3 input, associated by I/O-0 activation When a Wake-Up event is detected, the device enters into Reset Mode and then into Normal Request Mode. The WakeUp sources are reported to the device SPI registers. In summary, a Wake-Up event from LP VDD OFF leads to the VDD regulator turned ON, and the MCU operation restart. LP - VDD ON In this mode, the voltage at the VDD pin remains at 5.0 V (or 3.3 V, depending upon device part number). The objective is to maintain the MCU powered, with reduced consumption. In such mode, the DC output current is expected to be limited to 100 μA or a few mA, as the ECU is in reduced power operation mode. 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION STATE DIAGRAM STATE DIAGRAM VSUP fall POWER DOWN VSUP/1 rise > VSUP-TH1 & VDD > VDD_UVTH start T_IR (T_IR = 1.0 ms) INIT Reset Debug mode detection VSUP fall watchdog refresh by SPI T_INIT expired or VDD no Wake-Up Cyclic sense active time I/O-1 I/O-1 deglitcher time (typically 30 us) S1 closed S1 open Zoom Cyclic sense active time (ex 200 us) NORMAL MODE LP MODE RESET or NORMAL REQUEST MODE Wake-up event detected Wake-up detected. R R R R R R I/O-0 I/O-1 S1 S1 I/O-0 I/O-1 I/O-2 S2 S2 I/O-2 S3 I/O-3 S3 I/O-3 Upon entering in LP Mode, all 3 contact switches are closed. In LP Mode, 1 contact switch is open. High level is detected on I/O-x, and device wakes up. Figure 28. Cyclic Sense Operation - Switch to GND, Wake-up by Open Switch 33903/4/5 46 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION CYCLIC INT OPERATION DURING LP VDD ON MODE CYCLIC INT OPERATION DURING LP VDD ON MODE Principle This function can be used only in LP VDD ON Mode (LP VDD ON). When Cyclic INT is selected and device is in LP VDD ON Mode, the device will generate a periodic INT pulse. Upon reception of the INT pulse, the MCU must acknowledge the INT by sending SPI commands before the end of the next INT period in order to keep the process going. When Cyclic INT is selected and operating, the device remains in LP VDD ON Mode, assuming the SPI commands are issued properly. When no/improper SPI commands are sent, the device will cease Cyclic INT operation and leave LP VDD ON Mode by issuing a reset. The device will then enter into Normal Request Mode. VDD current capability and VDD regulator behavior is similar as in LP VDD ON Mode. Operation Cyclic INT period selection: register timer B SPI command in hex 0x56xx [example; 0x560E for 512ms cyclic Interrupt period (SPI command without parity bit)]. This command must be send while the device is in Normal Mode. Prepare LP VDD ON with Cyclic INT INT SPI Timer B Cyclic INT period 1st period Cyclic INT period 2nd period Cyclic INT period 3rd period Cyclic INT period LP VDD ON Mode SPI commands to acknowledge INT: (2 commands) - read the Random code via the watchdog register address using the following command: MOSI 0x1B00 device report on MISO second byte the RNDM code (MISO bit 0-7). - write watchdog refresh command using the random code inverted: 0x5A RNDb. These commands can occur at any time within the period. Initial entry in LP Mode with Cyclic INT: after the device is set in LP VDD ON Mode, with cyclic INT enable, no SPI command is necessary until the first INT pulse occurs. The acknowledge process must start only after the 1st INT pulse. Leave LP Mode with Cyclic INT: This is done by a SPI Wake-Up command, similar to SPI Wake-Up from LP VDD ON Mode: 0x5C10. The device will enter into Normal Request Mode. Improper SPI command while Cyclic INT operates: When no/improper SPI commands are sent, while the device is in LP VDD ON Mode with Cyclic INT enable, the device will cease Cyclic INT operation and leave LP VDD ON Mode by issuing a reset. The device will then enter into Normal Request Mode. The figure below (Figure 29) describes the complete Cyclic Interrupt operation. Leave LP VDD ON Mode In LP VDD ON with Cyclic INT NORMAL MODE LP VDD ON MODE NORMAL REQUEST MODE Legend for SPI commands Write Timer B, select Cyclic INT period (ex: 512 ms, 0x560E) Write Device Mode: LP VDD ON with Cyclic INT enable (example: 0x5C90) Read RNDM code Write RNDM code inv. SPI Wake-Up: 0x5C10 Leave LP VDD ON and Cyclic INT due to improper operation INT SPI Improper or no acknowledge SPI command RST Cyclic INT period RESET and NORMAL REQUEST MODE LP VDD ON MODE Figure 29. Cyclic Interrupt Operation 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 47 FUNCTIONAL DEVICE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN BEHAVIOR AT POWER UP AND POWER DOWN DEVICE POWER UP This section describe the device behavior during ramp up, and ramp down of VSUP/1, and the flexibility offered mainly by the Crank bit and the two VDD under-voltage reset thresholds. The figures below illustrate the device behavior during VSUP/1 ramp up. As the Crank bit is by default set to 0, VDD is enabled when VSUP/1 is above VSUP TH 1 parameters. VSUP_NOMINAL (ex 12 V) VDD NOMINAL (ex 5.0 V) VDD_UV TH (typically 4.65 V) VSUP slew rate VBAT D1 VSUP/1 3390X I_VDD VSUP/1 VDD VSUP_TH1 VDD_START UP 90% VDD_START UP 10% VDD_START UP VDD RESET 1.0 ms VDD_OFF Gnd Figure 30. VDD Start-up Versus VSUP/1 Tramp DEVICE POWER DOWN The figures below illustrate the device behavior during VSUP/1 ramp down, based on Crank bit configuration, and VDD under-voltage reset selection. Crank Bit Reset (INIT Watchdog Register, Bit 0 =0) Bit 0 = 0 is the default state for this bit. During VSUP/1 ramp down, VDD remain ON until device enters in Reset Mode due to a VDD under-voltage condition (VDD < 4.6 V or VDD < 3.2 V typically, threshold selected by the SPI). When device is in Reset, if VSUP/1 is below “VSUP_TH1”, VDD is turned OFF. Crank Bit Set (INIT Watchdog Register, Bit 0 =1) The bit 0 is set by SPI write. During VSUP/1 ramp down, VDD remains ON until device detects a POR and set BATFAIL. This occurs for a VSUP/1 approx 3.0 V. 33903/4/5 48 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN VBAT VSUP_NOMINAL (ex 12 V) VSUP/1 VBAT VSUP_NOMINAL (ex 12 V) VSUP/1 VDD (5.0 V) VDD_UV TH (typically 4.65 V) VSUP_TH1 (4.1 V) VDD (5.0 V) VDD_UV TH (typically 4.65 V) BATFAIL (3.0 V) VDD VDD RESET RESET Case 1: “VDD UV TH 4.6V”, with bit Crank = 0 (default value) Case 2: “VDD UV 4.6V”, with bit Crank = 1 VBAT VSUP_NOMINAL (ex 12 V) VSUP/1 VBAT VSUP_NOMINAL (ex 12 V) VSUP/1 VSUP_TH1 (4.1 V) VDD (5.0 V) VDD_UV TH (typically 4.65 V) VDD (5.0 V) VDD_UV TH (typically 4.65 V) BATFAIL (3.0 V) VDD VDD_UV TH2 (typically 3.2 V) (2) INT RESET (1) (1) reset then (2) VDD turn OFF VDD VDD_UV TH2 (typically 3.2 V) INT RESET Case 1: “VDD UV TH 3.2V”, with bit Crank = 0 (default value) Case 2: “VDD UV 3.2V”, with bit Crank = 1 Figure 31. VDD Behavior During VSUP/1 Ramp Down 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 49 FAIL SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN FAIL SAFE OPERATION OVERVIEW Fail Safe Mode is entered when specific fail conditions occur. The “Safe state” condition is defined by the resistor connected at the DGB pin. Safe Mode is entered after additional event or conditions are met: time out for CAN communication and state at I/O-1 pin. Exiting the safe state is always possible by a Wake-Up event: in the safe state, the device can automatically be awakened by CAN and I/O (if configured as inputs). Upon Wake-Up, the device operation is resumed: enter in Reset Mode. to properly control the device and properly refresh the watchdog). Modes B1, B2 and B3 Upon SAFE activation, the system continues to monitor external event, and disable the MCU supply (turn VDD OFF). The external events monitored are: CAN traffic, I/O-1 low level or both of them. 3 sub cases exist, B1, B2 and B3. Note: no CAN traffic indicates that the ECU of the vehicle are no longer active, thus that the car is being parked and stopped. The I/O low level detection can also indicate that the vehicle is being shutdown, if the I/O-1 pin is connected for instance to a switched battery signal (ignition key on/off signal). The selection of the monitored events is done by hardware, via the resistor connected at DBG pin, but can be over written by software, via a specific SPI command. By default, after power up the device detect the resistor value at DBG pin (upon transition from INIT to Normal Mode), and, if no specific SPI command related to Debug resistor change is send, operates according to the detected resistor. The INIT MISC register allow you to verify and change the device behavior, to either confirm or change the hardware selected behavior. Device will then operate according to the SAFE Mode configured by the SPI. Table 7 illustrates the complete options available: FAIL SAFE FUNCTIONALITY Upon dedicated event or issue detected at a device pin (i.e. RESET), the Safe Mode can be entered. In this mode, the SAFE pin is active low. Description Upon activation of the SAFE pin, and if the failure condition that make the SAFE pin activated have not recovered, the device can help to reduce ECU consumption, assuming that the MCU is not able to set the whole ECU in LP Mode. Two main cases are available: Mode A Upon SAFE activation, the MCU remains powered (VDD stays ON), until the failure condition recovers (i.e. S/W is able Table 7. Fail Safe Options Resistor at DBG pin SPI coding - register INIT MISC bits [2,1,0] (higher priority that Resistor coding) Safe Mode code A B1 B2 B3 VDD status safe state B3 I/O-1 I/O-1 high to low transition CAN bus idle time step 1: Failure illustration VDD failure event, i.e. watchdog 1st RST SAFE OFF state ON state 2nd 8th step 3: Consequences for VDD VDD RST SAFE 8 x 256 ms delay time to enter in SAFE Mode to evaluate resistor at the DBG pin and monitor ECU external events failure event, VDD low If VDD failure recovered VDD GND RST SAFE VDD_UV TH VDD GND RST VDD < VDD_UV TH VDD OFF OFF state ON state 100 ms SAFE failure event, Reset s/c GND VDD RST SAFE OFF state 2.5 V ON state VDD RST SAFE If Reset s/c GND recovered VDD OFF 100 ms 100 ms deglitcher time to activate SAFE and enter in SAFE Mode to evaluate resistor at DBG pin and monitor ECU external events Figure 34. SAFE Modes B1, B2, or B3 Behavior Illustration 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor W and monitor ECU external events ak eU 100 ms delay time to enter in SAFE Mode to evaluate resistor at DBG pin E m CU et e => xte V rna D l D di c on sa d bl itio e n p 53 CAN INTERFACE CAN INTERFACE DESCRIPTION CAN INTERFACE CAN INTERFACE DESCRIPTION The figure below is a high level schematic of the CAN interface. It exist in a LS driver between CANL and GND, and a HS driver from CANH to 5 V-CAN. Two differential receivers are connected between CANH and CANL to detect a bus state and to Wake-Up from CAN Sleep Mode. An internal 2.5 V reference provides the 2.5 V recessive levels via the matched RIN resistors. The resistors can be switched to GND in CAN Sleep Mode. A dedicated split buffer provides a low-impedance 2.5 V to the SPLIT pin, for recessive level stabilization. VSUP/2 SPI & State machine Pattern Detection Wake-up Receiver 5 V-CAN Driver 2.5 V RIN QH CANH RXD Differential Receiver RIN 5 V-CAN CANL TXD Thermal Driver SPI & State machine QL 5 V-CAN Buffer SPLIT SPI & State machine Failure Detection & Management Figure 35. CAN Interface Block Diagram Can Interface Supply The supply voltage for the CAN driver is the 5 V-CAN pin. The CAN interface also has a supply pass from the battery line through the VSUP/2 pin. This pass is used in CAN Sleep Mode to allow Wake-Up detection. During CAN communication (transmission and reception), the CAN interface current is sourced from the 5 V-CAN pin. During CAN LP Mode, the current is sourced from the VSUP/ 2 pin. TXD/RXD Mode In TXD/RXD Mode, both the CAN driver and the receiver are ON. In this mode, the CAN lines are controlled by the TXD pin level and the CAN bus state is reported on the RXD pin. The 5 V-CAN regulator must be ON. It supplies the CAN driver and receiver.The SPLIT pin is active and a 2.5 V biasing is provided on the SPLIT output pin. Receive Only Mode This mode is used to disable the CAN driver, but leave the CAN receiver active. In this mode, the device is only able to report the CAN state on the RXD pin. The TXD pin has no effect on CAN bus lines. The 5 V-CAN regulator must be ON. The SPLIT pin is active and a 2.5 V biasing is provided on the SPLIT output pin. Operation in TXD/RXD Mode The CAN driver will be enabled as soon as the device is in Normal Mode and the TXD pin is recessive. 33903/4/5 54 Analog Integrated Circuit Device Data Freescale Semiconductor CAN INTERFACE CAN INTERFACE DESCRIPTION When the CAN interface is in Normal Mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD pin. The bus state is reported through the RXD pin. When TXD is high, the driver is set in the recessive state, and CANH and CANL lines are biased to the voltage set with 5 V-CAN divided by 2, or approx. 2.5 V. When TXD is low, the bus is set into the dominant state, and CANL and CANH drivers are active. CANL is pulled low and CANH is pulled high. The RXD pin reports the bus state: CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV). If “CANH minus CANL” is below the threshold, the bus is recessive and RXD is set high. If “CANH minus CANL” is above the threshold, the bus is dominant and RXD is set low. The SPLIT pin is active and provides a 2.5 V biasing to the SPLIT output. TXD/RXD Mode and Slew Rate Selection The CAN signal slew rate selection is done via the SPI. By default and if no SPI is used, the device is in the fastest slew rate. Three slew rates are available. The slew rate controls the recessive to dominant, and dominant to recessive transitions. This also affects the delay time from the TXD pin . TXD Dominant state CANH-DOM CANH 2.5 V CANL RXD SPLIT 2.5 V Bus Driver CANL/CANH-REC CANH-CANL CANL-DOM Recessive state to the bus and from the bus to the RXD. The loop time is thus affected by the slew rate selection. Minimum Baud Rate The minimum baud rate is determined by the shortest TXD permanent dominant timing detection. The maximum number of consecutive dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag). The shortest TXD dominant detection time of 300 μs lead to a single bit time of: 300 μs / 12 = 25 μs. So the minimum Baud rate is 1 / 25 μs = 40 kBaud. Sleep Mode Sleep Mode is a reduced current consumption mode. CANH and CANL drivers are disabled and CANH and CANL lines are terminated to GND via the RIN resistor, the SPLIT pin is high-impedance. In order to monitor bus activities, the CAN Wake-Up receiver can be enabled. It is supplied internally from VSUP/2. Wake-up events occurring on the CAN bus pin are reporting by dedicated flags in SPI and by INT pulse, and results in a device Wake-Up if the device was in LP Mode. When the device is set back into Normal Mode, CANH and CANL are set back into the recessive level. This is illustrated in Figure 36. High ohmic termination (50 kohm) to GND Receiver (bus dominant set by other IC) Normal or Listen Only Mode High-impedance Go to sleep, Sleep or Stand-by Mode Normal or Listen Only Mode Figure 36. Bus Signal in TXD/RXD and LP Mode Wake-up When the CAN interface is in Sleep Mode with Wake-Up enabled, the CAN bus traffic is detected. The CAN bus WakeUp is a pattern Wake-Up. The Wake-Up by the CAN is enabled or disabled via the SPI. 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 55 CAN INTERFACE CAN INTERFACE DESCRIPTION CAN bus Dominant Pulse # 1 CANH CANL Dominant Pulse # 2 Internal differential Wake-Up receiver signal Internal Wake-Up signal Can Wake-Up detected tCAN WU1-F Figure 37. Single Dominant Pulse Wake-up Pattern Wake-up In order to Wake-Up the CAN interface, the Wake-Up receiver must receive a series of three consecutive valid dominant pulses, by default when the CANWU bit is low. CANWU bit can be set high by SPI and the Wake-Up will occur after a single pulse duration of 2.0 μs (typically). . CAN bus CANH CANL Dominant Pulse # 3 A valid dominant pulse should be longer than 500 ns. The three pulses should occur in a time frame of 120 μs, to be considered valid. When three pulses meet these conditions, the wake signal is detected. This is illustrated by the following figure. Dominant Pulse # 1 Dominant Pulse # 2 Dominant Pulse # 4 Internal differential Wake-Up receiver signal Internal Wake-Up signal Can Wake-Up detected tCAN WU3-F tCAN WU3-F tCAN WU3-TO Dominant Pulse # n: duration 1 or multiple dominant bits tCAN WU3-F Figure 38. Pattern Wake-up - Multiple Dominant Detection BUS TERMINATION The device supports the two main types of bus terminations: • Differential termination resistors between CANH and CANL lines. • SPLIT termination concept, with the mid point of the differential termination connected to GND through a capacitor and to the SPLIT pin. • In application, the device can also be used without termination. • Figure 39 illustrates some of the most common terminations. 33903/4/5 56 Analog Integrated Circuit Device Data Freescale Semiconductor CAN INTERFACE CAN BUS FAULT DIAGNOSTIC CANH SPLIT No connect 120 CANH SPLIT No connect CAN bus CAN bus CANL ECU connector CANL ECU connector Standard termination No termination CANH 60 SPLIT 60 CANL ECU connector CAN bus Figure 39. Bus Termination Options CAN BUS FAULT DIAGNOSTIC The device includes diagnostic of bus short-circuit to GND, VBAT, and internal ECU 5.0 V. Several comparators are implemented on CANH and CANL lines. These comparators H5 Hb TXD Diag Hg Lg Vr5 VBAT (12-14 V) Vrvb VDD CANH CANL Vrvb Vr5 VRVB (VSUP-2.0 V) VDD (5.0 V) VR5 (VDD-.43 V) CANH dominant level (3.6 V) Recessive level (2.5 V) VRG (1.75 V) CANL dominant level (1.4 V) GND (0.0 V) monitor the bus level in the recessive and dominant states. The information is then managed by a logic circuitry to properly determine the failure and report it. Vrg Logic Vrg Lb L5 Figure 40. CAN Bus Simplified Structure Truth Table for Failure Detection The following table indicates the state of the comparators when there is a bus failure, and depending upon the driver state. Table 8. Failure Detection Truth Table Failure Description No failure CANL to GND CANH to GND No failure CANL to VBAT CANH to VBAT Driver Recessive State Lg (threshold 1.75 V) 1 0 0 Lb (threshold VSUP -2.0 V) 0 1 1 Hg (threshold 1.75 V) 1 0 0 Hb (threshold VSUP -2.0 V) 0 1 1 0 0 0 Lb (threshold VSUP -2.0 V) 0 1 0 Driver Dominant State Lg (threshold 1.75 V) Hg (threshold 1.75 V) 1 1 0 Hb (threshold VSUP -2.0 V) 0 1 1 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 57 CAN INTERFACE CAN BUS FAULT DIAGNOSTIC Table 8. Failure Detection Truth Table Failure Description Driver Recessive State Lg (threshold 1.75 V) L5 (threshold VDD -0.43 V) No failure CANL to 5.0 V CANH to 5.0 V 0 1 1 Hg (threshold 1.75 V) H5 (threshold VDD -0.43 V) 0 1 1 Driver Dominant State Lg (threshold 1.75 V) L5 (threshold VDD -0.43 V) 0 1 0 Hg (threshold 1.75 V) H5 (threshold VDD -0.43 V) 0 1 1 DETECTION PRINCIPLE In the recessive state, if one of the two bus lines are shorted to GND, VDD (5.0 V), or VBAT, the voltage at the other line follows the shorted line, due to the bus termination resistance. For example: if CANL is shorted to GND, the CANL voltage is zero, the CANH voltage measured by the Hg comparator is also close to zero. In the recessive state, the failure detection to GND or VBAT is possible. However, it is not possible with the above implementation to distinguish which of the CANL or CANH lines are shorted to GND or VBAT. A complete diagnostic is possible once the driver is turned on, and in the dominant state. Number of Samples for Proper Failure Detection The failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. The error will be fully detected after five cycles of the recessive-dominant states. As long as the failure detection circuitry has not detected the same error for five recessivedominant cycles, the error is not reported. This condition could occur when the CANH line is shorted to a high-voltage. In this case, current will flow from the highvoltage short-circuit, through the bus termination resistors (60 Ω), into the SPLIT pin (if used), and into the device CANH and CANL input resistors, which are terminated to internal 2.5 V biasing or to GND (Sleep Mode). Depending upon the high-voltage short-circuit, the number of nodes, usage of the SPLIT pin, RIN actual resistor and mode state (Sleep or Active) the voltage across the bus termination can be sufficient to create a positive dominant voltage between CANH and CANL, and the RXD pin will be low. This would prevent start of any CAN communication and thus, proper failure identification requires five pulses on TXD. The bus dominant clamp circuit will help to determine such failure situation. RXD PERMANENT RECESSIVE FAILURE The aim of this detection is to diagnose an external hardware failure at the RXD output pin and ensure that a permanent failure at RXD does not disturb the network communication. If RXD is shorted to a logic high signal, the CAN protocol module within the MCU will not recognize any incoming message. In addition, it will not be able to easily distinguish the bus idle state and can start communication at any time. In order to prevent this, RXD failure detection is necessary. BUS CLAMPING DETECTION If the bus is detected to be in dominant for a time longer than (TDOM), the bus failure flag is set and the error is reported in the SPI. TXD Diag VDD/2 VDD RXD RXD driver Diff CANL Rxsense VDD CANH 60 RXD output RXD flag Prop delay Logic TXD driver Diff output CANL&H Sampling Sampling RXD short to VDD RXD flag latched The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 41. RXD Path Simplified Schematic, RXD Short to VDD Detection Implementation for Detection The implementation senses the RXD output voltage at each low to high transition of the differential receiver. Excluding the internal propagation delay, the RXD output should be low when the differential receiver is low. When an external short to VDD at the RXD output, RXD will be tied to 33903/4/5 a high level and can be detected at the next low to high transition of the differential receiver. As soon as the RXD permanent recessive is detected, the RXD driver is deactivated. Once the error is detected the driver is disabled and the error is reported via SPI in CAN register. 58 Analog Integrated Circuit Device Data Freescale Semiconductor CAN INTERFACE CAN BUS FAULT DIAGNOSTIC Recovery Condition The internal recovery is done by sampling a correct low level at TXD as shown in the following illustration. CANL&H Diff output Sampling RXD short to VDD RXD no longer shorted to VDD Sampling RXD output RXD flag latched RXD flag The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 42. RXD Path Simplified Schematic, RXD Short to VDD Detection TXD PERMANENT DOMINANT Principle If the TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible. The device has a TXD permanent timeout detector. After the timeout, the bus driver is disabled and the bus is released into a recessive state. The TXD permanent flag is set. Recovery The TXD permanent dominant is used and activated when there is a TXD short to RXD. The recovery condition for a TXD permanent dominant (recovery means the re-activation of the CAN drivers) is done by entering into a Normal Mode controlled by the MCU or when TXD is recessive while RXD change from recessive to dominant. low and drives CANH and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is possible. Detection and Recovery The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next incoming dominant bit, the bus will then be stuck in dominant again. The recovery condition is same as the TXD dominant failure IMPORTANT INFORMATION FOR BUS DRIVER REACTIVATION The driver stays disabled until the failure is/are removed (TXD and/or RXD is no longer permanent dominant or recessive state or shorted) and the failure flags cleared (read). The CAN driver must be set by SPI in TXD/RXD Mode in order to re enable the CAN bus driver. TXD TO RXD SHORT-CIRCUIT Principle When TXD is shorted to RXD during incoming dominant information, RXD is set to low. Consequently, the TXD pin is 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 59 LIN BLOCK LIN INTERFACE DESCRIPTION LIN BLOCK LIN INTERFACE DESCRIPTION The physical interface is dedicated to automotive LIN subbus applications. The interface has 20 kbps and 10 kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has excellent ESD robustness and immunity against disturbance, and radiated emission performance. It has safe behavior when a LIN bus short-to-ground, or a LIN bus leakage during LP Mode. Digital inputs are related to the device VDD pin. The LIN pin exhibits no reverse current from the LIN bus line to VSUP/2, even in the event of a GND shift or VSUP/2 disconnection. The transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by SPI. Receiver Characteristics The receiver thresholds are ratiometric with the device VSUP/2 voltage. If the VSUP/2 voltage goes below typically 6.1 V, the LIN bus enters into a recessive state even if communication is sent on TXD. If LIN driver temperature reaches the over-temperature threshold, the transceiver and receiver are disabled. When the temperature falls below the over-temperature threshold, LIN driver and receiver will be automatically enabled. POWER SUPPLY PIN (VSUP/2) The VSUP/2 pin is the supply pin for the LIN interface. To avoid a false bus message, an under-voltage on VSUP/2 disables the transmission path (from TXD to LIN) when VSUP/2 falls below 6.1 V. GROUND PIN (GND) When there is a ground disconnection at the module level, the LIN interface do not have significant current consumption on the LIN bus pin when in the recessive state. DATA INPUT PIN (TXD-L, TXD-L1, TXD-L2) The TXD-L,TXD-L1 and TXD-L2 input pin is the MCU interface to control the state of the LIN output. When TXD-L is LOW (dominant), LIN output is LOW. When TXD-L is HIGH (recessive), the LIN output transistor is turned OFF. This pin has an internal pull-up current source to VDD to force the recessive state if the input pin is left floating. If the pin stays low (dominant sate) more than t TXDDOM, the LIN transmitter goes automatically in recessive state. This is reported by flag in LIN register. LIN BUS PIN (LIN, LIN1, LIN2) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN bus specification 2.1 and SAEJ2602-2. The LIN interface is only active during Normal Mode. Driver Characteristics The LIN driver is a LS MOSFET with internal over-current thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 kΩ must be added when the device is used in the master node. The 1.0 kΩ pull-up resistor can be connected to the LIN pin or to the ECU battery supply. DATA OUTPUT PIN (RXD-L, RXD-L1, RXD-L2) This output pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high voltage on RXD, LIN LOW (dominant) is reported by a low voltage on RXD. LIN OPERATIONAL MODES The LIN interface have two operational modes, Transmit receiver and LIN disable modes. When the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition. The LIN interface can be set by the SPI command in TXD/RXD Mode, only when TXD-L is at a high level. When the SPI command is send while TXD-L is low, the command is ignored. TRANSMIT RECEIVE In the TXD/RXD Mode, the LIN bus can transmit and receive information. When the 20 kbps baud rate is selected, the slew rate and timing are compatible with LIN protocol specification 2.1. When the 10 kbps baud rate is selected, the slew rate and timing are compatible with J2602-2. SLEEP MODE This mode is selected by SPI, and the transmission path is disabled. Supply current for LIN block from VSUP/2 is very low (typically 3.0 μA). LIN bus is monitor to detect Wake-Up 33903/4/5 60 Analog Integrated Circuit Device Data Freescale Semiconductor LIN BLOCK LIN OPERATIONAL MODES event. In the Sleep Mode, the internal 725 kOhm pull-up resistor is connected and the 30 kOhm disconnected. The LIN block can be awakened from Sleep Mode by detection of LIN bus activity. LIN Bus Activity Detection The LIN bus Wake-Up is recognized by a recessive to dominant transition, followed by a dominant level with a duration greater than 70 μs, followed by a dominant to Table 9. LIN Block Failure FAULT LIN supply under-voltage TXD Pin Permanent Dominant LIN Thermal Shutdown TXD RXD FUNCTIONNAL MODE CONDITION recessive transition. This is illustrated in Figures 22 and 23. Once the Wake-Up is detected, the event is reported to the device state machine. An INT is generated if the device is in LP VDD ON Mode, or VDD will restart if the device was in LP VDDOFF Mode. The Wake-Up can be enable or disable by the SPI. Fail safe Features Table 9 describes the LIN block behavior when there is a failure. CONSEQUENCE LIN transmitter in recessive State LIN transmitter in recessive State LIN transmitter and receiver disabled HS turned off RECOVERY Condition gone Condition gone Condition gone LIN supply voltage < 6.0 V (typically) TXD pin low for more than t TXDDOM LIN driver temperature > 160°C (typically) TXD RXD 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 61 SERIAL PERIPHERAL INTERFACE HIGH LEVEL OVERVIEW SERIAL PERIPHERAL INTERFACE HIGH LEVEL OVERVIEW The device uses a 16 bits SPI, with the following arrangements: MOSI, Master Out Slave In bits: • bits 15 and 14 (called C1 and C0) are control bits to select the SPI operation mode (write control bit to device register, read back of the control bits, read of device flag). • bit 13 to 9 (A4 to A0) to select the register address. • bit 8 (P/N) has two functions: parity bit in write mode (optional, = 0 if not used), Next bit ( = 1) in read mode. • bit7 to 0 (D7 to D0): control bits MISO, Master In Slave Out bits: • bits 15 to 8 (S15 to S8) are device status bits • bits 7 to 0 (Do7 to Do0) are either extended device status bits, device internal control register content or device flags. The SPI implementation does not support daisy chain capability. Figure 43 is an overview of the SPI implementation. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 P/N Bit 7 Bit 6 D7 D6 Bit 5 D5 Bit 4 Bit 3 D4 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 MOSI C1 C0 A4 A3 A2 A1 A0 control bits register address Parity (optional) or Next bit = 1 S9 S8 Do7 Do6 data MISO S15 S14 S13 S12 S11 S10 Do5 Do4 Do3 Do2 Do1 Do0 Device Status CS SCLK MOSI Don’t Care MISO Tri-state C1 S15 C0 S14 D0 Do0 Extended Device Status, Register Control bits or Device Flags CS active low. Must rise at end of 16 clocks, for write commands, MOSI bits [15, 14] = ¬¨‚Ć[0 SCLK signal is low outside of CS active Don’t Care Tri-state MOSI and MISO data changed at SCLK rising edge and sampled at falling edge. Msb first. MISO tri-state outside of CS active SPI Wave Form, and Signals Polarity Figure 43. SPI Overview 33903/4/5 62 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OPERATION DETAIL OPERATION BITS 15, 14 AND 8 FUNCTIONS Table 10 summarizes the various SPI operation, depending upon bit 15, 14, and 8. Table 10. SPI Operations (bits 8, 14 & 15) Control Bits MOSI[15-14], C1-C0 Type of Command Parity/Next MOSI[8] P/N Note for Bit 8 P/N 00 Read back of register content and block (CAN, I/O, INT, LINs) real time state. See Table 37. Write to register address, to control the device operation Reserved Read of device flags form a register address 1 Bit 8 must be set to 1, independently of the parity function selected or not selected. 01 0 If bit 8 is set to “0”: means parity not selected OR parity is selected AND parity = 0 1 10 11 if bit 8 is set to “1”: means parity is selected AND parity = 1 1 Bit 8 must be set to 1, independently of the parity function selected or not selected. BITS 13-9 FUNCTIONS The device contains several registers coded on five bits (bits 13 to 9). Each register controls or reports part of the device’s function. Data can be written to the register to control the device operation or to set the default value or behavior. Every register can also be read back in order to ensure that it’s content (default setting or value previously written) is correct. In addition, some of the registers are used to report device flags. Table 11. Device Registers with Corresponding Address Address MOSI[13-9] A4...A0 0_0000 0_0001 0_0010 0_0011 0_0100 0_0101 0_0110 0_0111 0_1000 0_1001 Description Analog Multiplexer Memory byte A Memory byte B Memory byte C Memory byte D Initialization Regulators Initialization Watchdog Initialization LIN and I/O Initialization Miscellaneous functions Specific modes Device Status on MISO When a write operation is performed to store data or control bits into the device, the MISO pin reports a 16 bit fixed device status composed of 2 bytes: Device Fixed Status (bits 15 to 8) + extended Device Status (bits 7 to 0). In a read operation, MISO will report the Fixed device status (bits 15 to 8) and the next eight bits will be the content of the selected register. REGISTER ADRESS TABLE Table 11 is a list of device registers and addresses, coded with bits 13 to 9. Quick Ref. Name MUX RAM_A RAM_B RAM_C RAM_D Init REG Init watchdog Init LIN I/O Init MISC SPE_MODE Functionality 1) Write “device control bits” to register address. 2) Read back register “control bits” 1) Write “data byte” to register address. 2) Read back “data byte” from register address 1) Write “device initialization control bits” to register address. 2) Read back “initialization control bits” from register address 1) Write to register to select device Specific mode, using “Inverted Random Code”. 2) Read “Random Code” 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 63 SERIAL PERIPHERAL INTERFACE DETAIL OPERATION Table 11. Device Registers with Corresponding Address 0_1010 0_1011 0_1100 0_1101 0_1110 Timer_A: watchdog & LP MCU consumption Timer_B: Cyclic Sense & Cyclic Interrupt Timer_C: watchdog LP & Forced Wake-up Watchdog Refresh Mode register TIM_A TIM_B TIM_C watchdog MODE Watchdog Refresh Commands 1) Write to register to select LP Mode, with optional “Inverted Random code” and select Wake-Up functionality 2) Read operations: Read back device “Current Mode” Read “Random Code”, Leave “Debug Mode” 1) Write “timing values” to register address. 2) Read back register “timing values” 0_1111 1_0000 1_0001 1_0010 1_0011 1_0100 Regulator Control CAN interface control Input Output control Interrupt Control LIN1 interface control LIN2 interface control REG CAN I/O Interrupt LIN1 LIN2 1) Write “device control bits” to register address, to select device operation. 2) Read back register “control bits”. 3) Read device flags from each of the register addresses. COMPLETE SPI OPERATION Table 12 is a compiled view of all the SPI capabilities and options. Both MOSI and MISO information are described. Table 12. SPI Capabilities with Options Type of Command Read back of “device control bits” (MOSI bit 7 = 0) OR Read specific device information (MOSI bit 7 = 1) MOSI/ MISO MOSI MISO MOSI MISO Write device control bit to address selected by bits (13-9). MISO return 16 bits device status Reserved MOSI MISO MOSI MISO Read device flags and Wake-Up flags, from register address (bit 13-9), and sub address (bit 7). MISO return fixed device status (bit 15-8) + flags from the selected address and sub-address. MISO MOSI MISO MOSI 11 address Reserved Control bits [15-14] 00 Address [13-9] address Parity/Next bits [8] 1 Bit 7 0 Bits [6-0] 000 0000 Register control bits content 1 000 0000 Device ID and I/Os state Control bits Device Extended Status (8 bits) Reserved Reserved 0 Read of device flags form a register address, and sub address LOW (bit 7) Flags 1 Read of device flags form a register address, and sub address HIGH (bit 7) Flags Device Fixed Status (8 bits) 00 address 1 Device Fixed Status (8 bits) 01 address (note) Device Fixed Status (8 bits) 10 Device Fixed Status (8 bits) 11 address 1 Device Fixed Status (8 bits) Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity is selected and parity = 1. PARITY BIT 8 Calculation The parity is used for the write-to-register command (bit 15,14 = 01). It is calculated based on the number of logic one contained in bits 15-9,7-0 sequence (this is the entire 16 bits of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1if the number of 1 is even. Examples 1: MOSI [bit 15-0] = 01 00 011 P 01101001, P should be 0, because the command contains 7 bits with logic 1. Thus the Exact command will then be: MOSI [bit 15-0] = 01 00 011 0 01101001 33903/4/5 64 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OPERATION Examples 2: MOSI [bit 15-0] = 01 00 011 P 0100 0000, P should be 1, because the command contains 4 bits with logic 1. Thus the Exact command will then be: MOSI [bit 15-0] = 01 00 011 1 0100 0000 Parity Function Selection All SPI commands and examples do not use parity functions. The parity function is optional. It is selected by bit 6 in INIT MISC register. If parity function is not selected (bit 6 of INIT MISC = 0), then Parity bits in all SPI commands (bit 8) must be “0”. 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 65 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING DETAIL OF CONTROL BITS AND REGISTER MAPPING The following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100 MUX AND RAM REGISTERS Table 13. MUX Register(32) MOSI First Byte [15-8] [b_15 b_14] 0_0000 [P/N] 01 00 _ 000 P Default state Condition for default Bits b7 b6 b5 000 001 010 011 100 101 110 111 b4 0 1 b3 0 1 MOSI Second Byte, bits 7-0 bit 7 MUX_2 0 bit 6 MUX_1 0 bit 5 MUX_0 0 bit 4 Int 2K 0 bit 3 I/O-att 0 bit 2 0 0 bit 1 0 0 bit 0 0 0 POR, 5 V-CAN off, any mode different from Normal Description MUX_2, MUX_1, MUX_0 - Selection of external input signal or internal signal to be measured at MUX-OUT pin All functions disable. No output voltage at MUX-OUT pin VDD regulator current recopy. Ratio is approx 1/97. Requires an external resistor or selection of Internal 2.0 K (bit 3) Device internal voltage reference (approx 2.5 V) Device internal temperature sensor voltage Voltage at I/O-0. Attenuation or gain is selected by bit 3. Voltage at I/O-1. Attenuation or gain is selected by bit 3. Voltage at VSUP/1 pin. Refer to electrical table for attenuation ratio (approx 5) Voltage at VSENSE pin. Refer to electrical table for attenuation ratio (approx 5) INT 2k - Select device internal 2.0 kohm resistor between AMUX and GND. This resistor allows the measurement of a voltage proportional to the VDD output current. Internal 2.0 kohm resistor disable. An external resistor must be connected between AMUX and GND. Internal 2.0 kohm resistor enable. I/O-att - When I/O-0 (or I/O-1) is selected with b7,b6,b5 = 100 (or 101), b3 selects attenuation or gain between I/O-0 (or I/O-1) and MUX-OUT pin Gain is approx 2 for device with VDD = 5.0 V (Ref. to electrical table for exact gain value) Gain is approx 1.3 for device with VDD = 3.3 V (Ref. to electrical table for exact gain value) Attenuation is approx 4 for device with VDD = 5.0 V (Ref. to electrical table for exact attenuation value) Attenuation is approx 6 for device with VDD = 3.3 V (Ref. to electrical table for exact attenuation value) Notes 32. The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while 5V-CAN is OFF, the command is ignored, and the MXU register content is reset to default state (all control bits = 0). 33903/4/5 66 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 14. Internal Memory Registers A, B, C and D, RAM_A, RAM_B, RAM_C and RAM_D MOSI First Byte [15-8] [b_15 b_14] 0_0xxx [P/N] 01 00 _ 001 P Default state Condition for default 01 00 _ 010 P Default state Condition for default 01 00 _ 011 P Default state Condition for default 01 00 _ 100 P Default state Condition for default Ram d7 0 Ram d6 0 Ram d5 0 Ram d4 0 POR Ram c7 0 Ram c6 0 Ram c5 0 Ram c4 0 POR Ram d3 0 Ram d2 0 Ram d1 0 Ram d0 0 Ram b7 0 Ram b6 0 Ram b5 0 Ram b4 0 POR Ram c3 0 Ram c2 0 Ram c1 0 Ram c0 0 MOSI Second Byte, bits 7-0 Bit 7 Ram a7 0 Bit 6 Ram a6 0 Bit 5 Ram a5 0 Bit 4 Ram a4 0 POR Ram b3 0 Ram b2 0 Ram b1 0 Ram b0 0 Bit 3 Ram a3 0 Bit 2 Ram a2 0 Bit 1 Ram a1 0 Bit 0 Ram a0 0 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 67 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING INIT REGISTERS Note: these registers can be written only in INIT Mode Table 15. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT Mode) MOSI First Byte [15-8] [b_15 b_14] 0_0101 [P/N] 01 00 _ 101 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 I/O-x sync 1 bit 6 VDDL rst[1] 0 bit 5 VDDL rst[0] 0 bit 4 VDD rstD[1] 0 POR bit 3 VDD rstD[0] 0 bit 2 VAUX5/3 0 bit 1 Cyclic on[1] 0 bit 0 Cyclic on[0] 0 Bit b7 0 1 b6, b5 00 01 10 11 b4, b3 00 01 10 11 Description I/O-x sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected I/O-1 sense anytime I/O-1 sense during I/O-0 activation VDDL RST[1] VDDL RST[0] - Select the VDD under-voltage threshold, to activate RESET pin and/or INT Reset at approx 0.9 VDD. INT at approx 0.9 VDD, Reset at approx 0.7 VDD Reset at approx 0.7 VDD Reset at approx 0.9 VDD. VDD RSTD[1] VDD RSTD[0] - Select the RESET pin low lev duration, after VDD rises above the VDD under-voltage threshold 1.0 ms 5.0 ms 10 ms 20 ms b2 0 1 [VAUX 5/3] - Select Vauxilary output voltage VAUX = 3.3 V VAUX = 5.0 V b1, b0 00 01 10 11 Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected 200 μs (typical value. Ref. to dynamic parameters for exact value) 400 μs (typical value. Ref. to dynamic parameters for exact value) 800 μs (typical value. Ref. to dynamic parameters for exact value) 1600 μs (typical value. Ref. to dynamic parameters for exact value) 33903/4/5 68 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 16. Initialization Watchdog Registers, INIT watchdog (note: register can be written only in INIT Mode) MOSI First Byte [15-8] [b_15 b_14] 0_0110 [P/N] 01 00 _ 110 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 WD2INT 0 bit 6 MCU_OC 1 bit 5 OC-TIM 0 POR bit 4 WD Safe bit 3 WD_spi[1] 0 bit 2 WD_spi[0] 0 bit 1 WD N/Win 1 bit 0 Crank 0 Bit b7 0 1 Description WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command Function disable. No constraint between INT occurrence and INT source read. INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods. b6, b5 MCU_OC, OC-TIM - In LP VDD ON, select watchdog refresh and VDD current monitoring functionality. VDD_OC_LP threshold is defined in device electrical parameters (approx 1.5 mA) In LP Mode, when watchdog is not selected no watchdog + 00 no watchdog + 01 no watchdog + 10 In LP VDD ON Mode, VDD over-current has no effect In LP VDD ON Mode, VDD over-current has no effect In LP VDD ON Mode, VDD current > VDD_OC_LP threshold for a time > 100 μs (typically) is a Wake-Up event no watchdog In LP VDD ON Mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a Wake-Up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms) + 11 In LP Mode when watchdog is selected watchdog + 00 watchdog + 01 watchdog + 10 watchdog + 11 In LP VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. In LP VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. In LP VDD ON Mode, VDD over-current for a time > 100 μs (typically) is a Wake-Up event. In LP VDD ON Mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a watchdog refresh condition. VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is Wake-Up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms) b4 0 1 WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse SAFE pin is set low at the time of the RESET pin low activation SAFE pin is set low at the second consecutive time RESET pulse b3, b2 00 01 10 11 WD_spi[1] WD_spi[0] - Select the Watchdog (watchdog) Operation Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits. Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command. Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command. b1 0 1 WD N/Win - Select the Watchdog (watchdog) Window or Timeout operation Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period) 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 69 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Bit b0 0 1 Description Crank - Select the VSUP/1 threshold to disable VDD, while VSUP1 is falling toward GND VDD disable when VSUP/1 is below typically 4.0 V (parameter VSUP-TH1), and device in Reset Mode VDD kept ON when VSUP/1 is below typically 4.0 V (parameter VSUP_TH1) Table 17. Initialization LIN and I/O Registers, INIT LIN I/O (note: register can be written only in INIT Mode) MOSI First Byte [15-8] [b_15 b_14] 0_0111 [P/N] 01 00 _ 111 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 I/O-1 ovoff 0 bit 6 LIN_T2[1] 0 bit 5 LIN_T2[0] 0 POR bit 4 LIN_T/1[1] bit 3 LIN_T/1[0] 0 bit 2 I/O-1 out-en 0 bit 1 I/O-0 out-en 0 bit 0 Cyc_Inv 0 Bit b7 0 1 Description I/O-1 ovoff - Select the deactivation of I/O-1 when VDD or VAUX over-voltage condition is detected Disable I/O-1 turn off. Enable I/O-1 turn off, when VDD or VAUX over-voltage condition is detected. b6, b5 00 01 10 11 LIN_T2[1], LIN_T2[0] - Select pin operation as LIN Master pin switch or I/O pin is OFF pin operation as LIN Master pin switch pin operation as I/O: HS switch and Wake-Up input N/A b4, b3 00 01 10 11 LIN_T/1[1], LIN_T/1[0] - Select pin operation as LIN Master pin switch or I/O pin is OFF pin operation as LIN Master pin switch pin operation as I/O: HS switch and Wake-Up input N/A b2 0 1 I/O-1 out-en- Select the operation of the I/O-1 as output driver (HS, LS) Disable HS and LS drivers of pin I/O-1. I/O-1 can only be used as input. Enable HS and LS drivers of pin I/O-1. Pin can be used as input and output driver. b1 0 1 I/O-0 out-en - Select the operation of the I/O-0 as output driver (HS, LS) Disable HS and LS drivers of I/O-0 can only be used as input. Enable HS and LS drivers of the I/O-0 pin. Pin can be used as input and output drivers. b0 0 1 Cyc_Inv - Select I/O-0 operation in device LP Mode, when cyclic sense is selected During cyclic sense active time, I/O is set to the same state prior to entering in to LP Mode. During cyclic sense off time, I/O-0 is disable (HS and LS drivers OFF). During cyclic sense active time, I/O is set to the same state prior to entering in to LP Mode. During cyclic sense off time, the opposite driver of I/ O_0 is actively set. Example: If I/0_0 HS is ON during active time, then I/O_O LS is turned ON at expiration of the active time, for the duration of the cyclic sense period. 33903/4/5 70 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 18. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT Mode) MOSI First Byte [15-8] [b_15 b_14] 0_1000 [P/N] 01 01_ 000 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 LPM w RNDM 0 bit 6 SPI parity 0 bit 5 INT pulse 0 POR bit 4 INT width bit 3 INT flash 0 bit 2 Dbg Res[2] 0 bit 1 Dbg Res[1] 0 bit 0 Dbg Res[0] 0 Bit b7 0 1 Description LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into LP VDD OFF or LP VDD ON. Function disable: the LP Mode can be entered without usage of Random Code Function enabled: the LP Mode is entered using the Random Code b6 0 1 SPI parity - Select usage of the parity bit in SPI write operation Function disable: the parity is not used. The parity bit must always set to logic 0. Function enable: the parity is used, and parity must be calculated. b5 0 1 INT pulse -Select INT pin operation: low level pulse or low level INT pin will assert a low level pulse, duration selected by bit [b4] INT pin assert a permanent low level (no pulse) b4 0 1 INT width - Select the INT pulse duration INT pulse duration is typically 100 μs. Ref. to dynamic parameter table for exact value. INT pulse duration is typically 25 μs. Ref. to dynamic parameter table for exact value. b3 INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash Mode Function disable Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash Mode. b2, b1, b0 0xx 100 101 110 111 Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG pin. Ref. to parametric table for resistor range value.(33) Function disable 100 verification enable: resistor at DBG pin is typically 68 kohm (RB3) - Selection of SAFE Mode B3 101 verification enable: resistor at DBG pin is typically 33 kohm (RB2 - Selection of SAFE Mode B2 110 verification enable: resistor at DBG pin is typically 15 kohm (RB1) - Selection of SAFE Mode B1 111 verification enable: resistor at DBG pin is typically 0 kohm (RA) - Selection of SAFE Mode A Notes 33. Bits b2,1 and 0 allow the following operation: First, check the resistor device has detected at the DEBUG pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt register (Ref. to device flag table). Second, over write the resistor decoded by device, to set the SAFE Mode operation by SPI. Once this function is selected by bit 2 = 1, this selection has higher priority than “hardware”, and device will behave according to b2,b1 and b0 setting 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 71 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING SPECIFIC MODE REGISTER Table 19. Specific Mode Register, SPE_MODE MOSI First Byte [15-8] [b_15 b_14] 01_001 [P/N] 01 01_ 001 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 Sel_Mod[1] 0 bit 6 Sel_Mod[0] 0 bit 5 Rnd_C5b 0 POR bit 4 Rnd_C4b bit 3 Rnd_C3b 0 bit 2 Rnd_C2b 0 bit 1 Rnd_C1b 0 bit 0 Rnd_C0b 0 Bit b7, b6 00 01 10 11 Description Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI command. RESET Mode INIT Mode FLASH Mode N/A b5....b0 [Rnd_C4b... Rnd_C0b] - Random Code inverted, these six bits are the inverted bits obtained from the SPE-MODE Register read command. The SPE MODE Register is used for the Following Operation - Set the device in RESET Mode, to exercise or test the RESET functions. - Go to INIT Mode, using the Secure SPi command. - Go to FLASH Mode (in this mode the watchdog timer can be extended up to 32 s). - Activate the SAFE pin by S/W. This mode (called Special Mode) is accessible from the secured SPI command, which consist of 2 commands: 1) reading a random code and 2) then write the inverted random code plus mode selection or SAFE pin activation: Return to INIT Mode is done as follow (this is done from Normal Mode only): 1) Read random code: MOSI : 0001 0011 0000 0000 [Hex:0x 13 00] MISO report 16 bits, random code are bits (5-0) miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits random code) 2) Write INIT Mode + random code inverted MOSI : 0101 0010 01 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (RIX = random code inverted) MISO : xxxx xxxx xxxx xxxx (don’t care) SAFE pin activation: SAFE pin can be set low, only in INIT Mode, with following commands: 1) Read random code: MOSI : 0001 0011 0000 0000 [Hex:0x 13 00] MISO report 16 bits, random code are bits (5-0) miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits random code) 2) Write INIT Mode + random code bits 5:4 not inverted and random code bits 3:0 inverted MOSI : 0101 0010 01 R5 R4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (RIX = random code inverted) MISO : xxxx xxxx xxxx xxxx (don’t care) Return to Reset or Flash Mode is done similarly to the go to INIT Mode, except that the b7 and b6 are set according to the table above (b7, b6 = 00 - go to reset, b7, b6 = 10 - go to Flash). 33903/4/5 72 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING TIMER REGISTERS Table 20. Timer Register A, LP VDD Over-current & Watchdog Period Normal Mode, TIM_A MOSI First Byte [15-8] [b_15 b_14] 01_010 [P/N] 01 01_ 010 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 I_mcu[2] 0 bit 6 I_mcu[1] 0 bit 5 I_mcu[1] 0 bit 4 watchdog Nor[4] 1 POR bit 3 W/D_N[4] 1 bit 2 W/D_Nor[3] 1 bit 1 W/D_N[2] 1 bit 0 W/D_Nor[0] 0 LP VDD Over-current (ms) b7 00 0 1 3 (def) 4 01 6 8 b6, b5 10 12 16 11 24 32 Watchdog Period in Device Normal Mode (ms) b4, b3 000 00 01 10 11 2.5 3 3.5 4 001 5 6 7 8 010 10 12 14 16 011 20 24 28 32 b2, b1, b0 100 40 48 56 64 101 80 96 112 128 110 160 192 224 256 (def) 111 320 384 448 512 Table 21. Timer Register B, Cyclic Sense and Cyclic INT, in Device LP Mode, TIM_B MOSI First Byte [15-8] [b_15 b_14] 01_011 [P/N] 01 01_ 011 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 Cyc-sen[3] 0 bit 6 Cyc-sen[2] 0 bit 5 Cyc-sen[1] 0 bit 4 Cyc-sen[0] 0 POR bit 3 Cyc-int[3] 0 bit 2 Cyc-int[2] 0 bit 1 Cyc-int[1] 0 bit 0 Cyc-int[0] 0 Cyclic Sense (ms) b7 000 0 1 3 4 001 6 8 010 12 16 011 24 32 b6, b5, b4 100 48 64 101 96 128 110 192 256 111 384 512 Cyclic Interrupt (ms) b3 000 0 1 6 (def) 8 001 12 16 010 24 32 011 48 64 b2, b1, b0 100 96 128 101 192 258 110 384 512 111 768 1024 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 73 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 22. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C MOSI First Byte [15-8] [b_15 b_14] 01_100 [P/N] 01 01_ 100 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 WD-LP-F[3] 0 bit 6 WD-LP-F[2] 0 bit 5 WD-LP-F[1] 0 bit 4 WD-LP-F[0] 0 POR bit 3 FWU[3] 0 bit 2 FWU[2] 0 bit 1 FWU[1] 0 bit 0 FWU[0] 0 Table 23. Typical Timing Values Watchdog in LP VDD ON Mode (ms) b7 000 0 1 12 16 001 24 32 010 48 64 011 96 128 b6, b5, b4 100 192 256 101 384 512 110 768 1024 111 1536 2048 Watchdog in Flash Mode (ms) b7 000 0 1 48 (def) 256 001 96 512 010 192 1024 011 384 2048 b6, b5, b4 100 768 4096 101 1536 8192 110 3072 16384 111 6144 32768 Forced Wake-up (ms) b3 000 0 1 48 (def) 64 001 96 128 010 192 258 011 384 512 b2, b1, b0 100 768 1024 101 1536 2048 110 3072 4096 111 6144 8192 33903/4/5 74 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING WATCHDOG AND MODE REGISTERS Table 24. Watchdog Refresh Register, watchdog(34) MOSI First Byte [15-8] [b_15 b_14] 01_101 [P/N] 01 01_ 101 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 0 0 bit 6 0 0 bit 5 0 0 bit 4 0 0 POR bit 3 0 0 bit 2 0 0 bit 1 0 0 bit 0 0 0 Notes 34. The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the watchdog and also to transition from INIT Mode to Normal Mode, and from Normal Request Mode to Normal Mode (after a Wake-Up of a reset) . Table 25. MODE Register, MODE MOSI First Byte [15-8] [b_15 b_14] 01_110 [P/N] 01 01_ 110 P Default state MOSI Second Byte, bits 7-0 bit 7 mode[4] N/A bit 6 mode[3] N/A bit 5 mode[2] N/A bit 4 mode[1] N/A bit 3 mode[0] N/A bit 2 Rnd_b[2] N/A bit 1 Rnd_b[1] N/A bit 0 Rnd_b[0] N/A Table 26. LP VDD OFF Selection and FWU / Cyclic Sense Selection b7, b6, b5, b4, b3 0 1100 0 1101 0 1110 0 1111 FWU OFF OFF ON ON Cyclic Sense OFF ON OFF ON Table 27. LP VDD ON selection and operation mode b7, b6, b5, b4, b3 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111 b2, b1, b0 FWU OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON Cyclic Sense OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON ON Cyclic INT OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON Watchdog OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON Random Code inverted, these 3bits are the inverted bits obtained from the previous SPI command. The usage of these bits are optional and must be previously selected in the INIT MISC register [See bit 7 (LPM w RNDM) in Table 18] 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 75 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Prior to enter in LP VDD ON or LP VDD OFF, the Wake-Up flags must be cleared or read. This is done by the following SPI commands (See Table 37, Device Flag, I/O Real Time and Device Identification): 0xE100 for CAN Wake-Up clear 0xE380 for I/O Wake-Up clear 0xE700 for LIN1 Wake-Up clear 0xE900 for LIN2 Wake-Up clear If Wake-Up flags are not cleared, the device will enter into the selected LP Mode and immediately Wake-Up. In addition, the CAN failure flags (i.e. CAN_F and CAN_UF) must be cleared in order to meet the low power current consumption specification. This is done by the following SPI command: 0xE180 (read CAN failure flags) When the device is in LP VDD ON Mode, the Wake-Up by a SPI command uses a write to “Normal Request Mode”, 0x5C10. Mode Register Features The mode register includes specific functions and a “global SPI command” that allow the following: - read device current mode - read device Debug status - read state of SAFE pin - leave Debug state Table 28. Device Modes Global commands and effects Read device current mode, Leave debug mode. Keep SAFE pin as is. MOSI in hexadecimal: 1D 00 MOSI bits 15-14 00 MISO - release or turn off SAFE pin - read a 3 bit Random Code to enter in LP Mode These global commands are built using the MODE register address bit [13-9], along with several combinations of bit [1514] and bit [7]. Note, bit [8] is always set to 1. Entering into LP Mode using Random Code - LP Mode using Random Code must be selected in INIT Mode via bit 7 of the INIT MISC register. - In Normal Mode, read the Random Code using 0x1D00 or 0x1D80 command. The 3 Random Code bits are available on MISO bits 2,1 and 0. - Write LP Mode by inverting the 3 random bits. Example - Select LP VDD OFF without cyclic sense and FWU: 1. in hex: 0x5C60 to enter in LP VDD OFF Mode without using the 3 random code bits. 2. if Random Code is selected, the commands are: - Read Random Code: 0x1D00 or 0x1D80, MISO report in binary: bits 15-8, bits 7-3, Rnd_[2], Rnd_[1], Rnd_[0]. - Write LP VDD OFF Mode, using Random Code inverted: in binary: 0101 1100 0110 0 Rnd_b[2], Rnd_b[1], Rnd_b[0]. Table 28 summarizes these commands bits 13-9 01 110 bit 8 1 bit 7-3 bit 7 0 bits 6-0 000 0000 bit 2-0 Random code bits 6-0 000 0000 bit 2-0 Random code bits 6-0 000 0000 bit 2 X bit 1 SAFE bits 6-0 000 0000 bit 2 X bit 1 SAFE bit 0 DEBUG bit 0 DEBUG bit 15-8 Fix Status device current mode bit 8 1 bit 7-3 device current mode bit 8 1 bit 7-3 device current mode bit 8 1 bit 7-3 device current mode bit 7 1 bit 7 0 bit 7 1 Read device current mode Release SAFE pin (turn OFF). MOSI in hexadecimal: 1D 80 MOSI bits 15-14 00 bits 13-9 01 110 MISO bit 15-8 Fix Status Read device current mode, Leave debug mode. Keep SAFE pin as is. MOSI in hexadecimal: DD 00 MISO reports Debug and SAFE state (bits 1,0) MOSI bits 15-14 11 bits 13-9 01 110 MISO bit 15-8 Fix Status Read device current mode, Keep DEBUG mode Release SAFE pin (turn OFF). MOSI in hexadecimal: DD 80 MISO reports Debug and SAFE state (bits 1,0) MOSI bits 15-14 11 bits 13-9 01 110 MISO bit 15-8 Fix Status 33903/4/5 76 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING The Tables below describes MISO bits 7-0, used to decode the device’s current mode. Table 29. MISO bits 7-3 Device current mode, any of the above command b7, b6, b5, b4, b3 0 0000 0 0001 0 0010 0 0011 MODE INIT FLASH Normal Request Normal Mode The Table below describes the SAFE and DEBUG bit decoding. Table 30. SAFE and DEBUG status SAFE and DEBUG bits b1 0 1 b0 0 1 description SAFE pin OFF, not activated SAFE pin ON, driver activated. description Debug Mode OFF Debug Mode Active REGULATOR, CAN, I/O, INT AND LIN REGISTERS Table 31. Regulator Register MOSI First Byte [15-8] [b_15 b_14] 01_111 [P/N] 01 01_ 111 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 VAUX[1] 0 POR bit 6 VAUX[0] 0 bit 5 N/A bit 4 5V-can[1] 0 POR bit 3 5V-can[0] 0 bit 2 VDD bal en N/A bit 1 VDD bal auto N/A bit 0 VDD OFF en N/A Bits b7 b6 00 01 10 11 b4 b3 00 01 10 11 b2 0 1 b1 0 1 b0 0 1 Description VAUX[1], VAUX[0] - Vauxilary regulator control Regulator OFF Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags not reported. VAUX is disabled when UV or OC detected after 1.0 ms blanking time. Regulator ON. Under-voltage (UV) and over-current (OC) monitoring flags active. VAUX is disabled when UV or OC detected after 1.0 ms blanking time. Regulator ON. Under-voltage (UV) and over-current (OC) monitoring flags active. VAUX is disabled when UV or OC detected after 25 μs blanking time. 5 V-can[1], 5 V-can[0] - 5V-CAN regulator control Regulator OFF Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags not reported. 1.0 ms blanking time for UV and OC detection. Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags active. 1.0 ms blanking time for UV and OC detection. Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags active. 5 V-CAN disable when UV or OC detected after 25 μs blanking time. VDD bal en - Control bit to Enable the VDD external ballast transistor External VDD ballast disable External VDD ballast Enable VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typically 60 mA Disable the automatic activation of the external ballast Enable the automatic activation of the external ballast, if VDD > typically 60 mA VDD OFF en - Control bit to allow transition into LP VDD OFF Mode (to prevent VDD turn OFF) Disable Usage of LP VDD OFF Mode Enable Usage of LP VDD OFF Mode 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 77 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 32. CAN Register(35) MOSI First byte [15-8] [b_15 b_14] 10_000 [P/N] 01 10_ 000P Default state Condition for default Bits b7 b6 00 01 10 MOSI Second Byte, bits 7-0 bit 7 CAN mod[1] 1 note bit 6 CAN mod[0] 0 bit 5 Slew[1] 0 POR Description bit 4 Slew[0] 0 bit 3 Wake-Up 1/3 0 POR bit 2 bit 1 bit 0 CAN int 0 POR CAN mod[1], CAN mod[0] - CAN interface mode control, Wake-Up enable / disable CAN interface in Sleep Mode, CAN Wake-Up disable. CAN interface in receive only mode, CAN driver disable. CAN interface is in Sleep Mode, CAN Wake-Up enable. In device LP Mode, CAN Wake-Up is reported by device Wake-Up. In device Normal Mode, CAN Wake-Up reported by INT. CAN interface in transmit and receive mode. Slew[1] Slew[0] - CAN driver slew rate selection FAST MEDIUM SLOW SLOW Wake-up 1/3 - Selection of CAN Wake-Up mechanism 3 dominant pulses Wake-Up mechanism Single dominant pulse Wake-Up mechanism CAN INT - Select the CAN failure detection reporting Select INT generation when a bus failure is fully identified and decoded (i.e. after 5 dominant pulses on TxCAN) Select INT generation as soon as a bus failure is detected, event if not fully identified 11 b5 b4 00 01 10 11 b3 0 1 b0 0 1 Notes 35. The first time the device is set to Normal Mode, the CAN is in Sleep Wake-Up enabled (bit7 = 1, bit 6 =0). The next time the device is set in Normal Mode, the CAN state is controlled by bits 7 and 6. 33903/4/5 78 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 33. I/O Register MOSI First byte [15-8] [b_15 b_14] 10_001 [P/N] 01 10_ 001P Default state Condition for default Bits b7 b6 00 01 10 11 b5 b4 00 01 10 11 b3 b2 00 01 10 11 b1 b0 00 01 10 11 Description MOSI Second Byte, bits 7-0 bit 7 I/O-3 [1] 0 bit 6 I/O-3 [0] 0 bit 5 I/O-2 [1] 0 bit 4 I/O-2 [0] 0 POR bit 3 I/O-1 [1] 0 bit 2 I/O-1 [0] 0 bit 1 I/O-0 [1] 0 bit 0 I/O-0 [0] 0 I/O-3 [1], I/O-3 [0] - I/O-3 pin operation I/O-3 driver disable, Wake-up capability disable I/O-3 driver disable, Wake-up capability enable. I/O-3 HS driver enable. I/O-3 HS driver enable. I/O-2 [1], I/O-2 [0] - I/O-2 pin operation I/O-2 driver disable, Wake-up capability disable I/O-2 driver disable, Wake-up capability enable. I/O-2 HS driver enable. I/O-2 HS driver enable. I/O-1 [1], I/O-1 [0] - I/O-1 pin operation I/O-1 driver disable, Wake-up capability disable I/O-1 driver disable, Wake-up capability enable. I/O-1 LS driver enable. I/O-1 HS driver enable. I/O-0 [1], I/O-0 [0] - I/O-0 pin operation I/O-0 driver disable, Wake-up capability disable I/O-0 driver disable, Wake-up capability enable. I/O-0 LS driver enable. I/O-0 HS driver enable. 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 79 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 34. INT Register MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] 01 10_ 010P Default state Condition for default Bits b7 0 1 b6 0 1 b5 0 1 b4 0 1 b3 0 1 b2 Description MOSI Second Byte, bits 7-0 bit 7 CAN failure 0 bit 6 MCU req 0 bit 5 LIN2 fail 0 bit 4 LIN1fail 0 POR bit 3 I/O 0 bit 2 SAFE 0 bit 1 0 bit 0 Vmon 0 CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN over-current, Driver Over Temp, TXD-PD, RXD-PR, RX2HIGH, and CANBUS Dominate clamp) INT disable INT enable. MCU req - Control bit to request an INT. INT will occur once when the bit is enable INT disable INT enable. LIN2 fail - Control bit to enable INT when of failure on LIN2 interface INT disable INT enable. LIN/1 fail - Control bit to enable INT when of failure on LIN1 interface INT disable INT enable. I/O - Bit to control I/O interruption: I/O failure INT disable INT enable. SAFE - Bit to enable INT when of: Vaux over-voltage, VDD over-voltage, VDD Temp pre warning, VDD under-voltage(36), SAFE resistor mismatch, RST terminal short to VDD, MCU request INT.(37) INT disable INT enable. VMON - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5 V-CAN, VDD (IDD Over-current, VSUV, VSOV, VSENSELOW, 5V-CAN low or thermal shutdown, VAUX low or VAUX over-current INT disable INT enable. 0 1 b0 0 1 Notes 36. If VDD under-voltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 68. 37. Bit 2 is used in conjunction with bit 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request. 33903/4/5 80 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 35. LIN/1 Register(39) MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] 01 10_ 011P Default state Condition for default Bits b7 b6 00 01 10 11 Description MOSI Second Byte, bits 7-0 bit 7 LIN mode[1] 0 bit 6 LIN mode[0] 0 bit 5 Slew rate[1] 0 bit 4 Slew rate[0] 0 POR bit 3 0 bit 2 LIN T/1 on 0 bit 1 0 bit 0 Vsup ext 0 LIN Mode [1], LIN Mode [0] - LIN/1 interface mode control, Wake-Up enable / disable LIN/1 disable, Wake-Up capability disable not used LIN/1 disable, Wake-Up capability enable LIN/1 Transmit Receive Mode(38) b5 b4 00 01 10 11 Slew rate[1], Slew rate[0] LIN/1 slew rate selection Slew rate for 20 kbit/s baud rate Slew rate for 10 kbit/s baud rate Slew rate for fast baud rate Slew rate for fast baud rate b2 0 1 LIN T/1 on LIN/1 termination OFF LIN/1 termination ON b0 0 1 VSUP ext LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled. Notes 38. The LIN interface can be set in TXD/RXD Mode only when the TXD-L input signal is in recessive state. An attempt to set TXD/RXD Mode, while TXD-L is low, will be ignored and the LIN interface remains disabled. 39. In order to use the LIN interface, the 5V-CAN regulator must be set to ON. 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 81 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 36. LIN2 Register(41) MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] 01 10_ 100P Default state Condition for default Bits b7 b6 00 01 10 11 Description MOSI Second Byte, bits 7-0 bit 7 LIN mode[1] 0 bit 6 LIN mode[0] 0 bit 5 Slew rate[1] 0 bit 4 Slew rate[0] 0 POR bit 3 0 bit 2 LIN T2 on 0 bit 1 0 bit 0 Vsup ext 0 LIN mode [1], LIN mode [0] - LIN 2 interface mode control, Wake-Up enable / disable LIN2 disable, Wake-Up capability disable not used LIN2 disable, Wake-Up capability enable LIN2 Transmit Receive Mode(40) b5 b4 00 01 10 11 b2 0 1 b0 0 1 Slew rate[1], Slew rate[0] LIN 2slew rate selection Slew rate for 20 kbit/s baud rate Slew rate for 10 kbit/s baud rate Slew rate for fast baud rate Slew rate for fast baud rate LIN T2 on LIN 2 termination OFF LIN 2 termination ON VSUP ext LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled. Notes 40. The LIN interface can be set in TXD/RXD Mode only when the TXD-L input signal is in a recessive state. An attempt to set TXD/RXD Mode while TXD-L is low, will be ignored and the LIN interface will remain disabled. 41. In order to use the LIN interface, the 5V-CAN regulator must be set to ON. 33903/4/5 82 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS FLAGS AND DEVICE STATUS DESCRIPTION The table below is a summary of the device flags, I/O real time level, device Identification, and includes examples of SPI commands (SPI commands do not use parity functions). They are obtained using the following commands. This command is composed of the following: bits 15 and 14: • [1 1] for failure flags • - [0 0] for I/O real time status, device identification and CAN LIN driver receiver real time state. • bit 13 to 9 are the register address from which the flags is to be read. • bit 8 = 1 (this is not parity bit function, as this is a read command). When a failure event occurs, the respective flag is set and remains latched until it is cleared by a read command (provided the failure event has recovered). Table 37. Device Flag, I/O Real Time and Device Identification Bits 15-14 13-9 8 7 6 5 4 3 2 1 0 MOSI bits 15-7 MOSI bits [15, 14] Address [13-9] bit 8 bit 7 Next 7 MOSI bits (bits 6.0) should be “000_0000” MISO REG 8 Bits Device Fixed Status (bits 15...8) 11 0_1111 REG 1 0 MISO bits [7-0], device response on MISO pin bit 7 VAUX_LOW bit 6 VAUX_OVERCURRENT bit 5 5V-CAN_ THERMAL SHUTDOWN bit 4 5V-CAN_ UV bit 3 5V-CAN_ OVERCURRENT bit 2 VSENSE_ LOW bit 1 VSUP_ UNDERVOLTAGE bit 0 IDD-OCNORMAL MODE IDD-OC-LP VDDON MODE 11 1 - - - VDD_ THERMAL SHUTDOWN RST_LOW (2ms FWU VSUP/2-UV VSUP/1-OV I/O_O thermal watchdog flash mode 50% 1 INT service LP VDD OFF Reset request Hardware Timeout Leave Debug Hexa SPI commands to get I/O Flags and I/O Wake-Up: MOSI 0x E3 00, and MOSI 0x E3 80 00 1_0001 I/O 1 1 I/O_3 state I/O_2 state I/O_1 state I/O_0 state Hexa SPI commands to get I/O real time level: MOSI 0x 23 80 INT 11 1_0010 Interrupt 1 0 1 INT request RST high DBG resistor VDD temp Pre-warning VDD low >100 ms VDD UV VDD low RST VDD Overvoltage RST low >100 ms VAUX_OVERVOLTAGE watchdog refresh failure multiple Resets Hexa SPI commands to get INT Flags: MOSI 0x E5 00, and MOSI 0x E5 80 00 1_0010 Interrupt 1 1 VDD (5.0 V or 3.3 V) device p/n 1 device p/n 0 id4 id3 id2 id1 id0 Hexa SPI commands to get device Identification: MOSI 0x 25 10 example: MISO bit [7-0] = 1011 0010: MC33904, 5.0 V version, silicon pass 3.1 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 83 SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS Table 37. Device Flag, I/O Real Time and Device Identification LIN/1 11 1_0011 LIN 1 1 0 LIN1 Wake-Up LIN1 Term short to GND LIN 1 Over-temp RXD1 low RXD1 high TXD1 dom LIN1 bus dom clamp Hexa SPI commands to get LIN 2 Flags: MOSI 0x E7 00 00 1_0011 LIN 1 1 1 LIN1 State LIN1 WU en/dis - Hexa SPI commands to get LIN1 real time status: MOSI 0x 27 80 LIN2 11 1_0100 LIN 2 1 0 LIN2 Wake-Up LIN2 Term short to GND LIN 2 Over-temp RXD2 low RXD2 high TXD2 dom LIN2 bus dom clamp Hexa SPI commands to get LIN 2 Flags: MOSI 0x E9 00 00 1_0100 LIN 2 1 1 LIN2 State LIN2 WU en/dis - Hexa SPI commands to get LIN2 real time status: MOSI 0x 29 80 Table 38. Flag Descriptions Flag Description REG VAUX_LOW VAUX_OVERCURRENT Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Reports that VAUX regulator output voltage is lower than the VAUX_UV threshold. Set: VAUX below threshold for t >100 μs typically. Reset: VAUX above threshold and flag read (SPI) Report that current out of VAUX regulator is above VAUX_OC threshold. Set: Current above threshold for t >100 μs. Reset: Current below threshold and flag read by SPI. Report that the 5 V-CAN regulator has reached over-temperature threshold. Set: 5 V-CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) Reports that 5 V-CAN regulator output voltage is lower than the 5 V-CAN UV threshold. Set: 5V-CAN below 5V-CAN UV for t >100 μs typically. Reset: 5V-CAN > threshold and flag read (SPI) Report that the CAN driver output current is above threshold. Set: 5V-CAN current above threshold for t>100 μs. Reset: 5V-CAN current below threshold and flag read (SPI) Reports that VSENSE pin is lower than the VSENSE LOW threshold. Set: VSENSE below threshold for t >100 μs typically. Reset: VSENSE above threshold and flag read (SPI) Reports that VSUP/1 pin is lower than the VSUP/1 LOW threshold. Set: VSUP/1 below threshold for t >100 μs typically. Reset: VSUP/1 above threshold and flag read (SPI) Report that current out of VDD pin is higher that IDD-OC threshold, while device is in Normal Mode. Set: current above threshold for t>100 μs typically. Reset; current below threshold and flag read (SPI) Report that the VDD has reached over-temperature threshold, and was turned off. Set: VDD OFF due to thermal condition. Reset: VDD recover and flag read (SPI) Report that the RESET pin has detected a low level, shorter than 100 ms Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI) Report that the device voltage at VSUP/1 pin was below BATFAIL threshold. Set: VSUP/1 below BATFAIL. Reset: VSUP/1 above threshold, and flag read (SPI) Report that current out of VDD pin is higher that IDD-OC threshold LP, while device is in LP VDD ON Mode. Set: current above threshold for t>100 μs typically. Reset; current below threshold and flag read (SPI) 5 V-CAN_ THERMAL SHUTDOWN 5V-CAN_UV 5V-can_ over-current VSENSE_ LOW VSUP_ UNDERVOLTAGE IDD-OCNORMAL MODE VDD_ THERMAL SHUTDOWN RST_LOW (2.0 ms VSUP/2-UV Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Report I/O-3 HS switch short to GND failure Set: failure detected. Reset failure recovered and flag read (SPI) Report I/O-2 HS switch short to GND failure Set: failure detected. Reset failure recovered and flag read (SPI) Report SPI parity error was detected. Set: failure detected. Reset: flag read (SPI) Report SPI CSB was low for a time longer than typically 2.0 ms Set: failure detected. Reset: flag read (SPI) Report that VSUP/2 is below VSUP/2-UV threshold. Set VSUP/2 below VSUP/2-UV thresh. Reset VSUP/2 > VSUPUV thresh and flag read (SPI) Report that VSUP/1 is above VSUP/1-OV threshold. Set VSUP/1 above VSUP/1-OV threshold. Reset VSUP/1 < VSUPOV thresh and flag read (SPI) Report that the I/O-0 HS switch has reach over-temperature threshold. Set: I/O-0 HS switch thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) Report that the watchdog period has reach 50% of its value, while device is in Flash Mode. Set: watchdog period > 50%. Reset: flag read Report that Wake-Up source is I/O-1 or I/O-3 Set: after I/O-1 or I/O-3 wake detected. Reset: Flag read (SPI) Report that Wake-Up source is I/O-0 or I/O-2 Set: after I/O-0 or I/O-2 wake detected. Reset: Flag read (SPI) Report that Wake-Up source is SPI command, in LP VDD ON Mode. Set: after SPI Wake-Up detected. Reset: Flag read (SPI) Report that Wake-Up source is forced Wake-Up Set: after Forced Wake-Up detected. Reset: Flag read (SPI) Report that INT timeout error detected. Set: INT service timeout expired. Reset: flag read. Report that LP VDD OFF Mode was selected, prior Wake-Up occurred. Set: LP VDD OFF selected. Reset: Flag read (SPI) Report that RST source is an request from a SPI command (go to RST Mode). Set: After reset occurred due to SPI request. Reset: flag read (SPI) Report that the device left the Debug Mode due to hardware cause (voltage at DBG pin lower than typically 8.0 V). Set: device leave debug mode due to hardware cause. Reset: flag read. VSUP/1-OV I/O-0 thermal watchdog flash mode 50% Description Set / Reset condition I/O-1-3 Wake- Description Up Set / Reset condition I/O-0-2 Wake- Description Up Set / Reset condition SPI Wake-Up FWU INT service Timeout LP VDD OFF Reset request Hardware Leave Debug Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition 33903/4/5 86 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS Table 38. Flag Descriptions Flag Description INT INT request RST high DBG resistor Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition VDD TEMP PRE- Description WARNING Report that INT source is an INT request from a SPI command. Set: INT occurred. Reset: flag read (SPI) Report that RST pin is shorted to high voltage. Set: RST failure detection. Reset: flag read. Report that the resistor at DBG pin is different from expected (different from SPI register content). Set: failure detected. Reset: correct resistor and flag read (SPI). Report that the VDD has reached over-temperature pre-warning threshold. Set: VDD thermal sensor above threshold. Reset: VDD thermal sensor below threshold and flag read (SPI) Reports that VDD pin is lower than the VDDUV threshold. Set: VDD below threshold for t >100 μs typically. Reset: VDD above threshold and flag read (SPI) Reports that VDD pin is higher than the typically VDD + 0.6 V threshold. I/O-1 can be turned OFF if this function is selected in INIT register. Set: VDD above threshold for t >100 μs typically. Reset: VDD below threshold and flag read (SPI) Reports that VAUX pin is higher than the typically VAUX + 0.6 V threshold. I/O-1 can be turned OFF if this function is selected in INIT register. Set: VAUX above threshold for t >100 μs typically. Reset: VAUX below threshold and flag read (SPI) Reports that VDD pin is lower than the VDDUV threshold for a time longer than 100 ms Set: VDD below threshold for t >100 ms typically. Reset: VDD above threshold and flag read (SPI) Report that VDD is below VDD under-voltage threshold. Set: VDD below threshold. Reset: fag read (SPI) 0: mean 3.3V VDD version 1: mean 5V VDD version N/A Describe the device part number: 00: MC33903 01: MC33904 10: MC33905S 11: MC333905D Set / Reset condition Description Set / Reset condition Description Set / Reset condition VDD UV VDD OVERVOLTAGE VAUX_OVERVOLTAGE Description Set / Reset condition VDD LOW >100 ms VDD LOW VDD (5.0 V or 3.3 V) Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Device P/N1 and 0 Description Set / Reset condition Device id 4 to 0 Description N/A Describe the silicon revision number 10001: silicon revision 3.0 10010: silicon revision 3.1 10011: silicon revision 3.2 Set / Reset condition RST low >100 ms Multiple Resets watchdog refresh failure Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition N/A Report that the RESET pin has detected a low level, longer than 100 ms (Reset permanent low) Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI) Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong watchdog refresh. Set: after detection of multiple reset pulses. Reset: flag read (SPI) Report that a wrong or missing watchdog failure occurred. Set: failure detected. reset: flag read (SPI) 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 87 SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS Table 38. Flag Descriptions Flag Description LIN/1/2 LIN/1/2 bus dom clamp LIN/1/2 State Description Set / Reset condition Description Set / Reset condition Report that the LIN/1/2 bus is dominant for a time longer than tDOM Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI) Report real time LIN interface TXD/RXD Mode. 1 if LIN is in TXD/RXD Mode. 0 is LIN is not in TXD/ RXD Mode. Set: LIN in TXD RXD Mode. Reset: LIN not in TXD/RXD Mode. LIN not in TXD/RXD Mode by SPI command (ex LIN set in Sleep Mode) or following a failure event (ex: TxL Dominant). Flag read SPI command (0x2780 or 0x2980) do not clear it, as it is “real time” flag. Report real time LIN Wake-Up receiver state. 1 if LIN Wake-Up is enable, 0 if LIN Wake-Up is disable (means LIN signal will not be detected and will not Wake-Up the device). Set: LIN WU enable (LIN interface set in Sleep Mode Wake-Up enable). Reset: LIN Wake-Up disable (LIN interface set in Sleep Mode Wake-Up disable). Flag read SPI command (0x2780 or 0x2980) do not clear the flag, as it is “real time” information. Report that Wake-Up source is LIN/1/2 Set: after LIN/1/2 wake detected. Reset: Flag read (SPI) Report LIN/1/2 short to GND failure Set: failure detected. Reset failure recovered and flag read (SPI) Report that the LIN/1/2 interface has reach over-temperature threshold. Set: LIN/1/2 thermal sensor above threshold. Reset: sensor below threshold and flag read (SPI) Report that RXD/1/2 pin is shorted to GND. Set: RXD low failure detected. Reset: failure recovered and flag read (SPI) Report that RXD/1/2pin is shorted to recessive voltage. Set: RXD high failure detected. Reset: failure recovered and flag read (SPI) Report that TXD/1/2 pin is shorted to GND. Set: TXD low failure detected. Reset: failure recovered and flag read (SPI) LIN/1/2 WU Description Set / Reset condition LIN/1/2 Wake-Up LIN/1/2 Term short to GND LIN/1/2 Over-temp RXD-L/1/2 low RXD-L/1/2 high TXD-L/1/2 dom Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition 33903/4/5 88 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS FIX AND EXTENDED DEVICE STATUS For every SPI command, the device response on MISO is fixed status information. This information is either: Two Bytes Fix Status + Extended Status: when a device write command is used (MOSI bits 15-14, bits C1 C0 = 01) Table 39. Status Bits Description Bits MISO 15 INT 14 WU 13 RST 12 CAN-G 11 LIN-G 10 I/O-G 9 8 One Byte Fix Status: when a device read operation is performed (MOSI bits 15-14, bits C1 C0 = 00 or 11). 7 6 CAN-LOC 5 LIN2 4 LIN1 3 I/O-1 2 1 0 VREG-0 SAFE-G VREG-G CAN-BUS I/O-0 VREG-1 Bits INT WU RST CAN-G Description Indicates that an INT has occurred and that INT flags are pending to be read. Indicates that a Wake-Up has occurred and that Wake-Up flags are pending to be read. Indicates that a reset has occurred and that the flags that report the reset source are pending to be read. The INT, WU or RST source is CAN interface. CAN local or CAN bus source. The INT, WU or RST source is LIN2 or LIN1 interface The INT, WU or RST source is I/O interfaces. The INT, WU or RST source is from a SAFE condition The INT, WU or RST source is from a Regulator event, or voltage monitoring event The INT, WU or RST source is CAN interface. CAN local source. The INT, WU or RST source is CAN interface. CAN bus source. The INT, WU or RST source is LIN2 interface The INT, WU or RST source is LIN1 interface The INT, WU or RST source is I/O interface, flag from I/O sub adress Low (bit 7 = 0) The INT, WU or RST source is I/O interface, flag from I/O sub adress High (bit 7 = 1) The INT, WU or RST source is from a Regulator event, flag from REG register sub adress high (bit 7 = 1) The INT, WU or RST source is from a Regulator event, flag from REG register sub adress low (bit 7 = 0) LIN-G I/O-G SAFE-G VREG-G CAN-LOC CAN-BUS LIN2 LIN/LIN1 I/O-0 I/O-1 VREG-1 VREG-0 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 89 TYPICAL APPLICATIONS TYPICAL APPLICATIONS * Optional Q2 2.2 μF VBAUX VCAUX VAUX VSUP2 VE VB VDD RST INT MUX MOSI SCLK MISO CS Q1* RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr 100 nF >1.0 μF VSUP1 DBG 5V-CAN VSENSE I/O-0 I/O-1 >4.7 μF VDD RST INT A/D VBAT 1.0 k 22 k 100 nF 100 nF VSUP 4.7 k * SPI MCU CANH 60 CAN BUS VSUP1/2 1.0 k LIN BUS 1 option 1 60 4.7 nF SPLIT CANL LIN TERM1 TXD RXD TXD-L1 RXD-L1 TXD-L2 RXD-L2 CAN LIN1 LIN2 1.0 k option 2 LIN1 VSUP1/2 1.0 k LIN BUS 1 option 1 LIN TERM2 1.0 k option 2 LIN2 GND SAFE VSUP VSUP Safe Circuitry Notes 42. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP1/VSUP2 pins Figure 44. 33905D Typical Application Schematic 33903/4/5 90 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS Q2 2.2 μF VBAUX VCAUX VAUX VSUP2 100 nF >1.0 μF VSUP1 DBG 5V-CAN VSENSE I/O-0 100 nF I/O-1 VE VB VDD RST INT MUX MOSI SCLK MISO CS TXD RXD Q1* RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr >4.7 μF VDD RST INT A/D VBAT 1.0 k 22 k 100 nF VSUP 4.7 k * SPI MCU VSUP I/O-3 CANH 60 60 4.7 nF SPLIT CANL LIN TERM1 1.0 k LIN BUS 1 option 1 CAN LIN1 TXD-L1 RXD-L1 CAN BUS VSUP1/2 1.0 k option 2 LIN1 GND SAFE VSUP VSUP Safe Circuitry Notes 43. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP1/VSUP2 pins Figure 45. 33905S Typical Application Schematic 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 91 TYPICAL APPLICATIONS * Optional Q2 2.2 μF Q1* VBAUX VCAUX VAUX VE VSUP2 VB VDD RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr 100 nF >1.0 μF 1.0 k 100nF VSUP1 DBG 5V-CAN VSENSE I/O-0 >4.7 μF RST INT MUX MOSI SCLK MISO CS TXD RXD 4.7 k * VDD RST INT A/D VBAT VSUP 22 k 100 nF MCU SPI I/O-1 VBAT 22 k VSUP I/O-2 100 nF I/O-3 CANH 60 CAN BUS 60 4.7 nF SPLIT CANL GND CAN SAFE VSUP VSUP OR function Safe Circuitry Notes 44. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP1/VSUP2 pins Figure 46. 33904 Typical Application Schematic 33903/4/5 92 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS VBAT D1 VSUP 22 μF (45) VSUP1 100 nF >1.0 μF VSUP2 DBG 5V-CAN RST INT VDD >4.7 μF VDD RST INT VBAT I/O-0 22 k 100 nF MOSI SCLK MISO CS SPI MCU CANH 60 CAN BUS 60 4.7 nF SPLIT CANL GND SAFE VSUP VSUP OR function TXD RXD CAN Safe Circuitry Notes 45. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP1/VSUP2 pins Figure 47. 33903 Typical Application Schematic 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 93 TYPICAL APPLICATIONS VBAT D1 VSUP 22 μF 100 nF 1.0 k 22 k >1.0 μF 5V-CAN VSENSE IO-0 CANH 60 CAN BUS VSUP 1.0 k LIN BUS 1 option1 Q1* VSUP DBG VB VDD >4.7 μF RST INT MUX MOSI SCLK MISO CS TXD RXD TXD-L1 RXD-L1 TXD-L2 RXD-L2 4.7 k (optional) * = Optional VE VDD RST INT A/D VBAT 100 nF 100 nF SPI MCU 60 4.7 nF SPLIT CANL LIN-T1 CAN LIN1 LIN2 1.0 k option2 LIN1 VSUP 1.0 k LIN BUS 2 option1 LIN-T2 1.0 k option2 LIN2 GND SAFE VSUP VSUP Safe Circuitry Notes 46. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP pin Figure 48. 33903D Typical Application Schematic 33903/4/5 94 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS VBAT D1 VSUP 22 μF 100 nF 1.0 k 22 k VSUP >1.0 μF 5V-CAN VSENSE IO-0 IO-3 VSUP DBG VE VB VDD RST INT MUX MOSI SCLK MISO CS TXD RXD TXD-L RXD-L 4.7 k (optional) SPI >4.7 μF VDD RST INT A/D Q1* * = Optional VBAT 100 nF 100 nF MCU CANH 60 CAN BUS VSUP 1.0 k LIN BUS option1 CAN LIN 60 4.7 nF SPLIT CANL LIN-T 1.0 k option2 LIN GND SAFE VSUP VSUP Safe Circuitry Notes 47. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP pin Figure 49. 33903S Typical Application Schematic 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 95 TYPICAL APPLICATIONS The following figure illustrates the application case where two reverse battery diodes can be used for optimization of the filtering and buffering capacitor at the VDD pin. This allows using a minimum value capacitor at the VDD pin to guarantee reset-free operation of the MCU Q2 5.0 V/3.3 V VBAT D1 VBAUX VCAUX VSUP2 VSUP1 VAUX VE VB VDD during the cranking pulse and temporary (50 ms) loss of the VBAT supply. Applications without an external ballast on VDD and without using the VAUX regulator are illustrated as well. VBAT D2 C2 Q2 5.0 V/3.3 V VBAUX VCAUX VAUX VSUP2 VSUP1 VE VB VDD Q1 D1 C1 Q1 Partial View ex1: Single VSUP Supply Partial View ex2: Split VSUP Supply Optimized solution for cranking pulses. C1 is sized for MCU power supply buffer only. Q2 5.0 V/3.3 V VBAT D1 VBAUX VCAUX VAUX VSUP2 VSUP1 VE VB VDD VBAT D1 VBAUX VCAUX VAUX VSUP2 VSUP1 VE VB VDD Partial View ex 3: No External Transistor, VDD ~100 mA Capability delivered by internal path transistor. Partial View ex 4: No External Transistor - No VAUX Figure 50. Application Options 33903/4/5 96 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOIC 32 PACKAGE DIMENSIONS PACKAGING SOIC 32 PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 97 PACKAGING SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D 33903/4/5 98 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 99 PACKAGING SOIC 54 PACKAGE DIMENSIONS SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D 33903/4/5 100 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 101 PACKAGING SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D 33903/4/5 102 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION 4.0 DATE 9/2010 DESCRIPTION OF CHANGES • • • • • • • • • • • Initial Release - This document supersedes document MC33904_5. Initial release of document includes the MC33903 part number, the VDD 3.3 V version description, and the silicon revision rev. 3.2. Change details available upon request. Added Cyclic INT Operation During LP VDD ON Mode 47 Changed VSUP pin to VSUP1 and pin 2 (NC) to VSUP2 for the 33903 device Removed Drop voltage without external PNP pass transistor(13) 20 for VDD=3.3 V devices Added VSUP1-3.3 to VDD Voltage regulator, VDD pin 20. Added Pull-up Current, TXD, VIN = 0 V 24 for VDD=3.3 V devices Revised MUX and RAM registers 66 Revised Status Bits Description 89 Added Entering into LP Mode using Random Code 76. Removed part numbers MCZ33905S3EK/R2, MCZ33904A3EK/R2 and MCZ33905D3EK/R2, and added part numbers MCZ33903BD3EK/R2, MCZ33903BD5EK/R2, MCZ33903BS3EK/R2 and MCZ33903BS5EK/R2. Votalge Supply was improved from 27V to 28V. Changed Classification from Advance Information to Technical Data. Updated Notes in Tables 6. Revised Tables 6 ; Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: to reflect a Typical value. Corrected typographical errors throughout. Added Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) parameter to Tables 6. Updated I/O pins (I/O-0: I/O-3) on page 35. 5.0 12/2010 6.0 4/2011 • • • • • • • 33903/4/5 Analog Integrated Circuit Device Data Freescale Semiconductor 103 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2010 - 2011. All rights reserved. MC33903_4_5 Rev. 6.0 4/2011