33904

Freescale Semiconductor Advance Information Document Number: MC33904_5 Rev. 3.0, 2/2010 System Basis Chip Gen2 with High Speed CAN and LIN Interface The 33904/5 is the second generation family of System Basis Chips which combine several features and enhance present module designs. The device works as an advanced power management unit for the MCU and additional integrated circuits such as sensors, CAN transceivers. It has a built-in enhanced high speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostics, protection, and fail safe operation mode. The SBC may include one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to 4 wake-up input pins than can also be configured as output drivers for flexibility. This device implements multiple Low Power modes, with very lowcurrent consumption. In addition, the device is part of a family concept where pin compatibility, among the various devices with and without LIN interfaces, add versatility to module design. The 33904/5 also implements an innovative and advanced fail-safe state machine and concept solution. 33904 33904/5 33905 SBC CAN GEN2 EK SUFFIX (PB-FREE) 98ASA10556D 32-PIN SOIC EP EK SUFFIX (PB-FREE) 98ASA10506D 54-PIN SOIC EP Features • Protected 5.0V or 3.3V regulators for MCU (part number selectable) and additional ICs (SPI configurable) with optional external PNP usage to increase current capability for MCU. • Fully-protected embedded 5.0 V regulator for the CAN driver • Extremely low quiescent current in low power modes • Multiple under-voltage detections to address various MCU specifications and system operation modes (i.e. cranking) • Multiple wake-up sources in low power modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and VDD over-current detection. • Voltage, current and temperature protection with enhanced diagnostics that can be monitored by system via MUX output • ISO11898-5 high speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s. LIN 2.1 and J2602 LIN interface compatibility • Pb-free packaging designated by suffix code EK VBAT D1 ORDERING INFORMATION Device PCZ33905D3EK/R2 MCZ33905D5EK/R2 PCZ33905S3EK/R2 MCZ33905S5EK/R2 PCZ33904A3EK/R2 MCZ33904A5EK/R2 -40°C to 125°C 32 SOIC EP Temperature Range (TA) Package 54 SOIC EP 33905D (5.0 V/3.3 V) * = Optional Q2 Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE DBG GND VSENSE I/O-0 RST INT MOSI SCLK MISO CS MUX-OUT 5V-CAN TXD RXD TXD-L1 RXD-L1 TXD-L2 RXD-L2 VDD SPI A/D MCU I/O-1 CANH SPLIT CAN Bus LIN Bus LIN Bus CANL LIN-TERM 1 LIN-1 LIN-TERM 2 LIN-2 Figure 1. 33905D Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010. All rights reserved. VBAT D1 33905S (5.0 V/3.3 V) * = Optional Q2 Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE DBG GND VSENSE I/O-0 RST INT MOSI SCLK MISO CS MUX-OUT 5V-CAN TXD RXD TXD-L RXD-L VDD SPI A/D MCU I/O-1 CANH SPLIT CAN Bus VBAT CANL LIN-T LIN I/O-3 LIN Bus Figure 2. 33905S Simplified Application Diagram VBAT D1 33904A (5.0 V/3.3 V) * = Optional Q2 Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE DBG GND VSENSE I/O-0 RST INT MOSI SCLK MISO CS MUX-OUT 5V-CAN TXD RXD VDD SPI A/D MCU I/O-1 CANH VBAT SPLIT CAN Bus CANL I/O-2 I/O-3 Figure 3. 33904A Simplified Application Diagram 33904/5 2 Analog Integrated Circuit Device Data Freescale Semiconductor DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations Freescale Part No. PCZ33905D3EK/R2 MCZ33905D5EK/R2 Vdd output voltage 3.3V 5V 1 2 CAN interface LIN interface(s) Wake up input / LIN master termination 2 wake up + 2 LIN terms or 3 wake up + 1 LIN terms or 4 wake up + no LIN terms PCZ33905S3EK/R2 MCZ33905S5EK/R2 PCZ33904A3EK/R2 MCZ33904A5EK/R2 3.3V 5V 3.3V 1 5V no 4 wake up 1 1 3 wake up + 1 LIN terms or 4 wake up + no LIN terms SOIC 32pins exposed pad SOIC 32pins exposed pad SOIC 54 pins exposed pad Package 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 3 TABLE OF CONTENTS TABLE OF CONTENTS Internal Block Diagram .............................................................................................................................. 5 Pin Connections ........................................................................................................................................ 8 Electrical Characteristics ......................................................................................................................... 12 Maximum Ratings ................................................................................................................................. 12 Static Electrical Characteristics ............................................................................................................ 14 Dynamic Electrical Characteristics ....................................................................................................... 21 Timing Diagrams .................................................................................................................................. 24 Functional Description ............................................................................................................................. 28 Introduction ........................................................................................................................................... 28 Functional Pin Description .................................................................................................................... 28 Functional Device Operation ................................................................................................................... 32 Mode and State Description ................................................................................................................. 32 Low Power Modes ................................................................................................................................ 33 State Diagram ....................................................................................................................................... 34 Mode Change ....................................................................................................................................... 35 Watchdog Operation ............................................................................................................................. 35 Functional Block Operation Versus Mode ............................................................................................ 37 Illustration of Device Mode Transitions. ................................................................................................ 37 Cyclic Sense Operation During LP Modes ........................................................................................... 39 Behavior at Power Up and Power Down .............................................................................................. 40 Fail Safe Operation ................................................................................................................................. 42 CAN Interface ....................................................................................................................................... 46 CAN Interface Description .................................................................................................................... 46 CAN Bus Fault Diagnostic .................................................................................................................... 50 LIN Block ................................................................................................................................................. 53 LIN Interface Description ...................................................................................................................... 53 LIN Operational Modes ......................................................................................................................... 53 Serial Peripheral Interface ....................................................................................................................... 55 High Level Overview ............................................................................................................................. 55 Detail Operation .................................................................................................................................... 56 Detail of Control Bits And Register Mapping ........................................................................................ 59 Flags ..................................................................................................................................................... 75 Typical Applications ................................................................................................................................ 80 Packaging ............................................................................................................................................... 84 33904/5 4 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VBAUX VCAUX VAUX VSUP1 VE VB VSUP2 5 V Auxiliary Regulator VS2-INT VDD Regulator VDD SAFE RST Fail-safe DBG GND VSENSE INT MOSI Power Management Oscillator State Machine SPI SCLK MISO CS Analog Monitoring Signals Condition & Analog MUX MUX-OUT I/O-0 I/O-1 CANH SPLIT CANL VS2-INT VS2-INT Configurable Input-Output 5 V-CAN Regulator 5V-CAN Enhanced High-speed CAN Physical Interface TXD RXD TXD-L1 LIN-TERM1 LIN-1 LIN-TERM2 LIN-2 VS2-INT LIN 2.1 Interface - #1 RXD-L1 TXD-L2 LIN 2.1 Interface - #2 RXD-L2 Figure 4. 33905D Internal Block Diagram 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 5 INTERNAL BLOCK DIAGRAM VBAUX VCAUX VAUX VSUP1 VE VB VSUP2 5 V Auxiliary Regulator VS2-INT VDD Regulator VDD SAFE RST Fail-safe DBG GND VSENSE INT MOSI Power Management Oscillator State Machine SPI SCLK MISO CS Analog Monitoring Signals Condition & Analog MUX MUX-OUT I/O-0 I/O-1 I/O-3 CANH SPLIT CANL VS2-INT LIN-T LIN VS2-INT Configurable Input-Output 5 V-CAN Regulator 5V-CAN Enhanced High-speed CAN Physical Interface TXD RXD LIN Term #1 TXD-L LIN 2.1 Interface - #1 RXD-L Figure 5. 33905S Internal Block Diagram 33904/5 6 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM VBAUX VCAUX VAUX VSUP1 VE VB VSUP2 5 V Auxiliary Regulator VS2-INT VDD Regulator VDD SAFE RST Fail Safe DBG GND VSENSE INT MOSI Power Management Oscillator State Machine SPI SCLK MISO CS Analog Monitoring Signals Condition & Analog MUX MUX-OUT I/O-0 I/O-1 I/O-2 I/O-3 CANH SPLIT CANL Configurable Input-Output VS2-INT 5V-CAN Regulator 5V-CAN Enhanced High Speed CAN Physical Interface TxD RXD Figure 6. 33904A Internal Block Diagram 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 7 PIN CONNECTIONS PIN CONNECTIONS MC33905D NC NC NC VSUP1 VSUP2 LIN-T2 LIN-T1 SAFE 5V-CAN CANH CANL GND CAN SPLIT V-BAUX V-CAUX V-AUX MUX-OUT I/O-0 DBG NC NC NC TXDL2 GND RXDL2 LIN-2 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 MC33905S MC33904A GND SEE NOTE 1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 1 32 32 VB VB NC VSUP1 VSUP1 2 31 2 31 VE VE NC VSUP2 VSUP2 3 30 3 30 RXD RXD I/O-3 I/O-3 NC 4 29 4 29 LIN-T I/O-2 VB TXD TXD 5 28 5 28 SAFE SAFE VDD VDD VE 6 27 6 27 5V-CAN 5V-CAN RXD MISO MISO 7 26 7 26 CANH CANH TXD MOSI MOSI GND GND 8 25 8 25 CANL CANL SEE VDD SCLK SCLK SEE NOTE 1 24 NOTE 1 9 24 9 GND CAN GND CAN MISO CS CS 10 23 10 23 SPLIT SPLIT MOSI INT INT 11 22 11 22 V-BAUX V-BAUX SCLK RST RST V-CAUX V-CAUX 12 12 21 21 I/O-1 I/O-1 CS 13 20 13 20 V-AUX V-AUX INT VSENSE VSENSE 14 19 14 19 MUX-OUT RXD-L MUX-OUT NC RST 15 18 15 18 I/O-0 I/O-0 TXD-L NC I/O-1 16 17 16 17 DBG DBG LIN NC VSENSE RXD-L1 GND - LEAD FRAME GND - LEAD FRAME TXD-L1 LIN-1 32 pins exposed package 32 pins exposed package NC NC NC NC GND NC NC NC 54 pins exposed package Note 1: Exposed pad should be connected to electrical ground. Figure 7. 33904/5 Pin Connections Table 2. 33904/5 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 28. Pin # Pin # Pin # 33905D 33905S 33904A 1-3,2022,2730,3235,52-54 4 5 N/A 17, 18, 19 Pin Name N/C Pin Function No Connect Formal Name No Connection Definition 1 2 1 2 VSUP1 VSUP2 Power Power Battery Voltage Supply 1 Battery Voltage Supply 2 Supply input for the device internal supplies, power on reset circuitry and the VDD regulator. Supply input for 5 V-CAN regulator, VAUX regulator, I/O and LIN Terminals. 33904/5 8 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 2. 33904/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 28. Pin # Pin # Pin # 33905D 33905S 33904A 6 3 3 Pin Name LIN-T2 or I/O-3 Pin Function Output or Input/Output Formal Name LIN Termination 2 or Input/Output 3 Definition 33905D, Output pin for the LIN2 master node termination resistor. or 33904A/33905S, Configurable pin as an input or high side output, for connection to external circuitry (switched or small load). The input can be used as a programmable wake-up input in Low Power mode. When used as a high side, no overtemperature protection is implemented. A basic short to GND protection function, based on switch drain-source overvoltage detection, is available. 33905D, Output pin for the LIN1 master node termination resistor. or 33905S, 33905D, Configurable pin as an input or high side output, for connection to external circuitry (switched or small load). The input can be used as a programmable wake-up input in Low Power mode. When used as a high side, no overtemperature protection is implemented. A basic short to GND protection function, based on switch drain-source overvoltage detection, is available. 33904, Configurable terminal as input or high side output, for connection to external circuitry (switched or small load). Input can be used as a programmable wake-up input from Low Power Mode. When used as high side, no over-temperature protection is implemented. A basic short to GND protection function based on switch drain-source over-voltage detection is available. Output of the safe circuitry. The pin is asserted LOW in case of a safe condition is detected (e.g.: software watchdog is not triggered, VDD low, issue on reset pin etc.). Open drain structure. Output voltage for the embedded CAN interface. A capacitor must be connected to this pin. CAN high output. CAN low output. Power GND of the embedded CAN interface Output pin for connection to the middle point of the split CAN termination Output pin for external path PNP transistor base Output pin for external path PNP transistor collector Output pin for the auxiliary voltage. Multiplexed output to be connected to an MCU A/D input. Selection of the analog parameter available at MUX-OUT is done via the SPI. A switchable internal pull-down resistor is integrated for VDD current sense measurements. 7 4 4 LIN-T1 or LIN-T Output or Input/Output LIN Termination 1 or Input/Output 2 I/O-2 I/O-2 8 5 5 SAFE Output Safe Output (Active LOW) 9 10 11 12 13 14 15 16 17 6 7 8 9 10 11 12 13 14 6 7 8 9 10 11 12 13 14 5 V-CAN CANH CANL GND-CAN SPLIT VBAUX VCAUX VAUX MUX-OUT Output Output Output Ground Output Output Output Output Output 5V-CAN CAN High CAN Low GND-CAN SPLIT Output VB Auxiliary VCOLLECTOR Auxiliary VOUT Auxiliary Multiplex Output 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 9 PIN CONNECTIONS Table 2. 33904/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 28. Pin # Pin # Pin # 33905D 33905S 33904A 18 15 15 Pin Name I/O-0 Pin Function Input/Output Formal Name Input/Output 0 Definition Configurable pin as an input or output, for connection to external circuitry (switched or small load). The voltage level can be read by the SPI and via the MUX output pin. The input can be used as a programmable wake-up input in Low Power Mode. In low power, when used as an output, the high side or low side can be activated for a cyclic sense function. Input to activate the Debug Mode. In Debug Mode, no watchdog refresh is necessary. Outside of Debug Mode, connection of a resistor between DBG and GND allows the selection of Safe Mode functionality. LIN bus transmit data input. Includes an internal pull-up resistor to VDD. Ground of the IC. LIN bus receive data output. LIN bus input output connected to the LIN bus. LIN bus input output connected to the LIN bus. 19 16 16 DBG Input Debug 23 24,31 25 26 36 N/A N/A N/A N/A 17 N/A N/A N/A N/A 17 TXD-L2 GND RXD-L2 LIN2 33905D LIN-1 33905S LIN Input Ground Output Input/Output Input/Output LIN Transmit Data 2 Ground LIN Receive Data LIN bus LIN bus 37 18 18 33905D TXD-L1 33905S TXD-L Input LIN Transmit Data LIN Receive Data Sense input Input Output 1 LIN bus transmit data input. Includes an internal pull-up resistor to VDD. LIN bus receive data output. 38 19 19 33905D RXD-L1 33905S RXD-L Output 39 40 20 21 20 21 VSENSE I/O-1 Input Input/Output Direct battery voltage input sense. A serial resistor is required to limit the input current during high voltage transients. Configurable pin as an input or output, for connection to external circuitry (switched or small load). The voltage level can be read by the SPI and via the MUX output pin. The input can be used as a programmable wake-up input in Low Power Mode. Can be used in association with I/O-0 for a cyclic sense function in Low Power Mode. This is the device reset output whose main function is to reset the MCU. This pin has an internal pull-up to VDD. The reset input voltage is also monitored in order to detect external reset and safe conditions. This output is asserted low when an enabled interrupt condition occurs. The output is a push-pull structure. Chip select pin for the SPI. When the CS is low, the device is selected. In Low Power Mode with VDD ON, a transition on CS is a wake-up condition 41 22 22 RST Output Reset Output (Active LOW) 42 43 23 24 23 24 INT CS Output Input Interrupt Output (Active LOW) Chip Select (Active LOW) 44 45 46 47 25 26 27 28 25 26 27 28 SCLK MOSI MISO VDD Input Output Input Output Serial Data Clock Clock input for the Serial Peripheral Interface (SPI) of the device Master Out / Slave In Master In / Slave Out Voltage Digital Drain SPI data received by the device SPI data sent to the MCU. When the CS is high, MISO is highimpedance 5.0 V or 3.3 V output pin of the main regulator for the Microcontroller supply. 33904/5 10 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 2. 33904/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 28. Pin # Pin # Pin # 33905D 33905S 33904A 48 49 50 51 29 30 31 32 29 30 31 32 Pin Name TXD RXD VE VB GND Output Ground Pin Function Input Output Formal Name Transmit Data Receive Data Voltage Emitter Voltage Base Ground Definition CAN bus transmit data input. Internal pull-up to VDD CAN bus receive data output Connection to the external PNP path transistor. This is an intermediate current supply source for the VDD regulator Base output pin for connection to the external PNP pass transistor Ground EX PAD EX PAD EX PAD 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS(2) Supply Voltage at VSUP1and VSUP2 Normal Operation (DC) Transient Conditions (Load Dump) DC voltage on LIN, LIN1 and LIN2 Normal Operation (DC) Transient Conditions (Load Dump) DC voltage on CANL, CANH, SPLIT Normal Operation (DC) Transient Conditions (Load Dump) DC Voltage at SAFE Normal Operation (DC) Transient Conditions (Load Dump) DC Voltage at I/O-0, I/O-1, I/O-2, I/O-3 (LIN-Terminal Pins) Normal Operation (DC) Transient Conditions (Load Dump) DC voltage on TXDL1 TXDL2, RXDL2, RXDL2 DC voltage on TXD, RXD DC Voltage at INT DC Voltage at RST DC Voltage at MOSI, MSIO, SCLK and CS DC Voltage at MUXOUT DC Voltage at DBG Continuous current on CANH and CANL VI/O VI/OTR VDIGLIN VDIG VINT VRST VRST VMUX VDBG ILH -0.3 to 27 -0.3 to 40 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to 10 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to 10 200 V V V V V V V mA VSAFE VSAFETR -0.3 to 27 -0.3 to 40 V VBUS VBUSTR -32 to 27 -32 to 40 V VBUSLIN VBUSLINTR -27 to 27 -27 to 40 V VSUP1/2 VSUP1/2TR -0.3 to 27 -0.3 to 40 V V Symbol Value Unit 33904/5 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ESD Capability * AECQ100(1) Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 Ω) CANH and CANL. LIN1 and LIN2, Pins versus all GND pins all other Pins including CANH and CANL Charge Device Model - JESD22/C101 (CZAP = 4.0 pF) Corner Pins (Pins 1, 16, 17, and 32) All other Pins (Pins 2-15, 18-31) * According to IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 Ω) device unpowered, CANH and CANL pin without capacitor, versus GND device unpowered, LIN pin, versus GND device unpowered, VS1/VS2 (100 nF to GND), versus GND * According to “OEM_HW_Requirements_For_CAN_LIN_FR-Interfaces_V1 0_20081210.pdf” CANH, CANL without bus filter LIN with and without bus filter I/O with external components (22k - 10nF) THERMAL RATINGS Junction temperature Ambient temperature Storage temperature THERMAL RESISTANCE Thermal resistance junction to ambient Peak Package Reflow Temperature During Reflow (2), (3) Symbol Value Unit V VESD1-1 VESD1-2 VESD2-1 VESD2-2 VESD3-1 VESD3-2 VESD3-3 ±8000 ±2000 ±750 ±500 ±15000 ±15000 ±15000 VESD4-1 VESD4-2 VESD4-3 ±9000 ±12000 ±7000 TJ TA TST 150 -40 to 125 -55 to 165 °C °C °C RθJA TPPRT 50(4) Note 3 °C/W °C Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 2. The voltage on non-Vsup pins should never exceed the Vsup voltage at any time or permanent damage to the device may occur.Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. This parameter was measured according to Figure 8 below: 3. 4. PCB 100mm x 100mm Top side, 300 sq. mm (20mmx15mm) Bottom side 20mm x 40mm Bottom view Figure 8. PCB with Top and Bottom Layer Dissipation Area (Dual Layer) 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic POWER INPUT Nominal DC Voltage Range(5) Extended DC Low Voltage Range(6) Under-voltage Detector Thresholds, at VSUP1 pin, Low threshold (VSUP1 ramp down) High threshold (VSUP1 ramp up) Hysteresis Note: function not active in Low Power modes Under-voltage Detector Thresholds, at VSUP2 pin: Low threshold (VSUP2 ramp down) High threshold (VSUP2 ramp up) Hysteresis Note: function not active in Low Power modes VSUP Over-voltage Detector Thresholds, at VSUP1 pin: Not active in Low Power modes Battery loss detection threshold, at VSUP1 pin. Vsup 1 to turn Vdd ON, Vsup1 rising Vsup 1 to turn Vdd ON, hysteresis (guaranteed by design) Supply current(7) - from VSUP1 - from VSUP2, (5V-CAN Vaux, I/O OFF) Supply current, ISUP1 + ISUP2, Normal Mode, VDD ON - 5 V-CAN OFF, VAUX OFF - 5 V-CAN ON, CAN interface in Low Power VDD OFF Mode, VAUX OFF - 5 V-CAN OFF, Vaux ON - 5 V-CAN ON, CAN interface in TxRx Mode, VAUX OFF, I/O-x disable Low Power Mode VDD off. Wake-up from CAN, I/Ox inputs VSUP =< 18 V, -40 to 25°C VSUP =18 V, 125°C Low Power Mode VDD ON (5.0 V) with VDD under-voltage and VDD over-current monitoring, wake-up from CAN, I/Ox inputs VSUP =< 18 V, -40 to 25°C, IDD = 1.0μA VSUP =< 18 V, -40 to 25°C, IDD = 100 μA (20% of IDD load) VSUP =18 V, 125°C, IDD = 100 μA Low Power Mode, additional current for oscillator (used for: cyclic sense, forced wake-up, and in Low Power VDD ON Mode cyclic interruption and watchdog) VSUP = 8.0 V CANH to VBAT detection threshold, VSUP1 and VSUP2 > 8.0 V CANL to VDD detection threshold CANH to VDD detection threshold Notes 16. Guaranteed by design and device characterization. VLG VHG VLVB VHVB VL5 VH5 1.6 1.6 4.0 4.0 1.75 1.75 VSUP -2.0 VSUP -2.0 VDD -0.43 VDD -0.43 2.0 2.0 V V V V V V ICANH ICANL ICANL-OC ICANH-OC RINSLEEP VCANLP ICAN-UN_SUP1 VOH-VOL 1.5 -0.5 30 75 -195 5.0 -0.1 2.0 0.0 120 -120 0.0 3.0 3.0 0.05 -30 195 -75 50 0.1 10 mA mA mA mA kΩ V µA VCANL 0.5 2.0 1.5 2.5 2.25 3.0 V VCOM VCANH-VCANL VDIFF-HYST RIN RIN-DIFF RIN-MATCH VCANH 2.75 2.0 3.5 2.5 4.5 3.0 V -12 500 50 5.0 10 -3.0 0.0 12 900 50 100 3.0 V mV mV kΩ kΩ % V Symbol Min Typ Max Unit ICAN-UN_SUP2 - - 250 µA VDIFF-R-LP VDIFF-D-LP 1.15 - 0.4 - V V 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 19 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic SPLIT Output voltage Loaded condition ISPLIT = ± 500 µA Unloaded condition Rmeasure > 1.0 MΩ Leakage current -12 V < VSPLIT < +12 V -22 to -12 V < VSPLIT < +12 to +35 V LIN TERM1, LIN TERM2 LIN-T1, LIN-T2, high side switch drop @ I = -20 mA, VSUP > 10.5 V Operating Voltage Range Supply Voltage Range Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V Input Leakage Current at the receiver Driver off; VBUS = 0V; VBAT = 12 V Leakage Output Current to GND Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT Control unit disconnected from ground (Loss of local ground must not affect communication in the residual network) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V (guaranteed by design) VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V (Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition) Receiver Dominant State Receiver Recessive State Receiver Threshold Center (VTH_DOM + VTH_REC)/2 Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) LIN Wake-up threshold from Low Power VDD ON or Low Power VDD OFF Mode LIN Pull-up Resistor to VSUP Over-temperature Shutdown (guaranteed by design) Over-temperature Shutdown Hysteresis (guaranteed by design) VBUSWU RSLAVE TLINSD TLINSD_HYS VHYS 20 140 5.3 30 160 10 0.175 5.8 60 180 V kΩ °C °C IBUSNO_BAT VBUSDOM VBUSREC 0.6 VBUS_CNT 0.475 0.5 0.525 VSUP VSUP 0.4 VSUP 100 VSUP µA IBUS_NO_GND -1.0 1.0 IBUS_PAS_REC 20 mA IBUS_PAS_DOM -1.0 µA LT_HSDRP 1.0 1.4 V LIN1 AND LIN 2 MC33905D PIN - LIN1 MC33905S PIN (Parameters guaranteed for VSUP1, VSUP2 7 V ≤ VSUP ≤ 18 V) VBAT VSUP IBUS_LIM 40 90 200 mA 8.0 7.0 18 18 V V mA ILSPLIT 0.0 5.0 200 VSPLIT 0.3 x VDD 0.45 x VDD 0.5 x VDD 0.5 x VDD 0.7 x VDD 0.55 x VDD µA V Symbol Min Typ Max Unit 33904/5 20 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic SPI TIMING SPI operation frequency (MISO cap = 50 pF) SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Falling Edge of CS to Rising Edge of SCLK Falling Edge of SCLK to Rising Edge of CS MOSI to Falling Edge of SCLK Falling Edge of SCLK to MOSI MISO Rise Time (CL = 50 pF) MISO Fall Time (CL = 50 pF) Time from Falling to MISO Low-impedance Time from Rising to MISO High-impedance Time from Rising Edge of SCLK to MISO Data Valid Delay between rising and falling edge on CS CS low timeout detection SUPPLY, VOLTAGE REGULATOR, RESET VSUP under-voltage detector threshold deglitcher Rise time at turn ON. VDD from 1.0 to 4.5 μV. 2.2 μF at VDD pin. Deglitcher time to set reset pin low RESET PULSE DURATION VDD under-voltage (SPI selectable) short, default at power on when BATFAIL bit set medium medium long long Watchdog reset VSENSE INPUT Under-voltage deglitcher time INTERRUPT INT pulse duration (refer to SPI for selection. Guaranteed by design) short long INT-PULSE 20 90 25 100 35 130 μs BFT 30 100 μs RST-WD RST-PULSE 0.9 4.0 8.5 17 0.9 1.0 5.0 10 20 1.0 1.4 6 12 24 1.4 ms ms VS_LOW1/ 2_DGLT Symbol Min Typ Max Unit FREQ tPCLK tWSCLKH tWSCLKL tLEAD tLAG tSISU tSIH tRSO tFSO tSOEN tSODIS tVALID D2CS CS-TO 0.25 250 125 125 30 30 30 30 1.0 2.5 - 4.0 N/A N/A N/A N/A N/A N/A N/A 30 30 30 30 30 - MHz ns ns ns ns ns ns ns ns ns ns ns μs ms 30 50 20 50 250 30 100 800 40 μs μs μs tRISE-ON RST-DGLT 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 21 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic STATE DIGRAM TIMINGS Delay for SPI Timer A, Timer B or Timer C write command after entering Normal Mode (No command should occur within Td_nm. TD_NM delay definition: from CS rising edge of “Go to Normal Mode” command to CS falling edge of “Timer write” command) Tolerance for: W/D period in all modes, FWU delay, Cyclic sense period and active time, Cyclic Interrupt period, LP mode over current (unless otherwise noted)(20) CAN DYNAMIC CHARACTERISTICS TXD Dominant State Timeout Bus dominant clamping detection Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate) Propagation delay TXD to CAN, recessive to dominant Propagation delay CAN to RXD, recessive to dominant Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate) Propagation delay TXD to CAN, dominant to recessive Propagation delay CAN to RXD, dominant to recessive Loop time TXD to RXD, Medium Slew rate (Selected by SPI) Rec to Dom Dom to Rec Loop time TXD to RXD, Slow Slew rate (Selected by SPI) Rec to Dom Dom to Rec CAN wake up filter time, single dominant pulse (See Figure 29) CAN wake up filter time, 3 dominant pulses detection(18) CAN wake up filter time, 3 dominant pulses detection time (See Figure 30) Notes 17. No wake up for single pulse shorter than tCAN-WU1 min. Wake up for single pulse longer than tCAN-WU1 max. 18. 19. 20. Each pulse should be greater than tCAN-WU3-F min. Guaranteed by design, and device characterization. The 3 pulses should occur within tCAN-WU3-TO. Guaranteed by design, and device characterization. Guaranteed by design. out(19) tCAN-WU3-F tCAN-WU3-TO 300 120 ns μs detection(17) tCAN-WU1 tLOOP-SSL 0.5 300 300 2.0 5.0 μs tDOUT tDOM tLRD tTRD tRRD tLDR tTDR tRDR tLOOP-MSL 200 200 ns 300 300 60 100 600 600 120 70 45 120 75 50 1000 1000 210 110 140 200 150 140 µs µs ns ns ns ns ns ns ns tTIMING-ACC -10 10 % tD_NM 60 μs Symbol Min Typ Max Unit 33904/5 22 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit LIN 1 AND LIN 2 PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. See Figure 13, page 25. Duty Cycle 1: THREC(max) = 0.744 * VSUP THDOM(max) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V 0.581 0.396 - D1 D2 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds. See Figure 14, page 26. Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V Duty Cycle 4: THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) SRFAST 20 V / μs 0.590 0.417 - D3 D4 LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. See Figure 13, page 25. Propagation Delay and Symmetry (See Figure 13, page 25 and Figure 14, page 26) Propagation Delay of Receiver, tREC_PD=MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR Bus Wake-Up Deglitcher (Low Power VDD OFF and Low Power VDD ON Modes) (See Figure 15, page 25 for Low Power VDD OFF Mode and Figure 16, page 26 for Low Power Mode) Bus Wake-up Event Reported From Low Power VDD OFF Mode From Low Power VDD ON Mode μs μs t REC_PD t REC_SYM t PROPWL - 2.0 4.2 - 6.0 2.0 μs 42 70 95 t WAKE_LPVDD OFF 1.0 - 1500 12 t WAKE_LPVDD ON TXD Permanent Dominant State Delay (guaranteed by design) t TXDDOM 0.65 1.0 1.35 s 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 23 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS TPCLK CS TLEAD TWCLKH TLAG SCLK TWCLKL TSISU TSIH MOSI Undefined TVALID TSOEN Di 0 Don’t Care Di n Don’t Care TSODIS MISO Do 0 Do n Figure 9. SPI Timings TXD 0.3 x VDD RXD TLRD 0.7 x VDD TLDR 0.7 x VDD 0.3 x VDD Figure 10. CAN Signal Propagation Loop Delay TXD to RXD TXD 0.3 x VDD VDIFF TTRD 0.7 x VDD TTDR 0.9V TRRD 0.5V TRDR 0.7 x VDD 0.3 x VDD RXD Figure 11. CAN Signal Propagation Delays TXD to CAN and CAN to RXD 33904/5 24 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS . 12 V 10 µF VSUP VDD 100 nF 2.2 µF 33905 CANH Signal generator TXD CANL RXD 15 pF GND SPLIT RBUS 60 Ω CBus 100 pF All pins are not shown Figure 12. Test Circuit for CAN Timing Characteristics TXD tBIT tBIT VLIN_REC THREC(MAX) THDOM(MAX) 74.4% VSUP 58.1% VSUP tBUS_DOM(MAX) tBUS_REC(MIN) Thresholds of receiving node 1 LIN THREC(MIN) THDOM(MIN) 42.2% VSUP 28.4% VSUP Thresholds of receiving node 2 tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2) Figure 13. LIN Timing Measurements for Normal Slew Rate 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 25 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD tBIT tBIT VLIN_REC THREC(MAX) THDOM(MAX) 77.8% VSUP 61.6% VSUP tBUS_DOM(MAX) tBUS_REC(MIN) Thresholds of receiving node 1 LIN THREC(MIN) THDOM(MIN) 38.9% VSUP 25.1% VSUP Thresholds of receiving node 2 tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2) Figure 14. LIN Timing Measurements for Slow Slew Rate V REC LI N 0. V SU P 4 V BU S W U D om i nantl evel VD D 3V T PR O PW L T W AKE Figure 15. LIN Wake-up Low Power VDD OFF Mode Timing 33904/5 26 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS V LI _REC N LI N 0. V SU P 4 V BU S W U D om i nantl evel IQ R T PROPWL T W AKE I Q st l untlSPIr R ays ow i eadi com m and ng Figure 16. LIN Wake-up Low Power VDD ON Mode Timing 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The MC33904_5 is the second generation of System Basis Chip, combining: - Advanced power management unit for the MCU, the integrated CAN interface and for additional ICs such as sensors, CAN transceiver. - Built in enhanced high speed CAN interface (ISO118982 and -5), with local and bus failure diagnostic, protection and fail safe operation mode. - Built in LIN interface, compliant to LIN 2.1 and J2602-2 specification, with local and bus failure diagnostic and protection. - Innovative and hardware configurable fail safe state machine solution. - Multiple low power modes, with low current consumption. - Family concept; with and without LIN interface devices with pin compatibility. FUNCTIONAL PIN DESCRIPTION POWER SUPPLY (VSUP1 AND VSUP2) VSUP1 pin is the input pin for the device internal supply and the VDD regulator. VSUP2 is the input pin for the 5VCAN regulator, LINs interfaces and I/O functions. The VSUP block includes over and under-voltage detections which can generate interrupt. The device includes a loss of battery detector connected to VSUP1. Loss of battery is reported through a bit (called BATFAIL). This generates a POR (Power On Reset). EXTERNAL TRANSISTOR Q1 (VE AND VB) The device has a dedicated circuit to allow usage of an external P type transistor, with the objective to share the power dissipation between the internal transistor of the VDD regulator and the external transistor. The bipolar PNP recommended transistor are MJD42C or BCP52-16. When the external PNP is connected, the current is shared between the internal path transistor and the external PNP, with the following typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control is done by SPI. The device is able to operate without an external transistor. In this case the VEM and VB pins must remain open. VDD VOLTAGE REGULATOR (VDD) The regulator has two main modes of operation (Normal Mode and Low Power Mode). It can operate with or without an external PNP transistor. In Normal Mode, without external PNP, the max DC capability is 150mA. Current limitation, temperature pre warning flag and over temperature shutdown features are included. When VDD is turned ON, rise time from 0 to 5.0V is controlled. Output voltage is 5.0V. A 3.3V option is available via dedicated part number. If current higher than 150mA is required, an external PNP transistor must be connected to VEM (PNP emitter) and VB (PNP base) terminals, in order to increase total current capability and share the power dissipation between internal VDD transistor and the external transistor. See External Transistor Q1 (VE and VB). The PNP can be used even if current is less than 150mA, depending upon ambient temperature, maximum supply and thermal resistance. Typically, above 100-200mA, an external ballast transistor is recommended. VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY (5V-CAN) This regulator is supplied from the VSUP2 pin. A capacitor is required at 5V-CAN terminal. Analog MUX and part of the LIN interfaces are supplied from 5V-CAN. 5V-CAN regulator is OFF by default and must be turn ON by SPI. In Debug mode 5V-CAN is ON be default. V AUXILIARY OUTPUT, 5V AND 3.3V SELECTABLE (VB-AUX, VC-AUX, AND VCAUX) - Q2 The VAUX block is used to provide an auxiliary voltage output, 5 or 3.3V, selectable by the SPI. It uses an external PNP pass transistor for flexibility and power dissipation constraints. The external recommended bipolar transistors are MJD42C or BCP52-16. An over-current and under voltage detectors are provided. VAUX is controlled via the SPI, and can be turned ON or OFF. VAUX low threshold detection and over-current information will disable Vaux, and flags are reported in the SPI and can generate INT. Vaux is OFF by default and must be turned ON by SPI. VDD REGULATOR IN LOW POWER MODE When the device is set in Low Power VDD ON Mode, the VDD regulator is able to supply the MCU with a DC current below typ 1.5mA (LP-ITH). Transient current can also be supplied up to tenth of mA. Current in excess of 1.5mA is detected, and this event is managed by the device logic (wake-up detection, timer start for over current duration monitoring or watchdog refresh). 33904/5 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION UNDER-VOLTAGE RESET AND RESET FUNCTION (RST) The RESET pin is an open drain structure with an internal pull-up current source. The low side driver has limited current capability when asserted low, in order to tolerate a short to 5.0V.The Reset terminal voltage is monitored in order to detect failure (e.g. RESET pin shorted to 5.0V or GND). The RESET pin reports to the MCU under -voltage condition at the VDD pin, as well as failure in watchdog refresh operation. VDD under-voltage reset operate also in Low Power VDD ON Mode. Two VDD under-voltage threshold are included. The upper on (typ 4.65V, RST-TH1-5) can lead to a Reset or an Interrupt. This is selected by the SPI. When “RST-TH2-5“is selected, in Normal Mode, an INT is asserted when VDD falls below “RSTTH1-5“. This will allow the MCU to operate in a degraded mode, for example, with 4.0V VDD. capacitor to gnd. It incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX OUT pin. MUX OUTPUT (MUXOUT) The MUX-OUT terminal (Figures 17) delivers an analog voltage to the MCU A/D input. The voltage to be delivered to MUX-OUT is selected via the SPI, from one of the following functions: Vsup1, Vsense, I/O-0, I/O-1, Internal 2.5V reference, die temperature sensor, VDD current copy. Voltage divider or amplifier are inserted in the chain, as shown in Figures 17. For the VDD current copy, a resistor must be added to the MUX OUT pin, to convert current into voltage. Device includes an internal 2k resistor selectable by SPI. Voltage range at MUX_OUT is from gnd to VDD. It is automatically limited to VDD (max 3.3V for 3.3V part numbers). The MUX-OUT buffer is supplied from 5V-CAN regulator, so the 5V-CAN regulator must be ON in order to have: 1) MUX-OUT functionality and 2) SPI selection of the analog function. If 5V-CAN is OFF, MUX-OUT voltage is near gnd and the SPI command that selects one of the analog input is ignored. Delay must be respected between SPI commands for 5VCAN turn ON and SPI to select MUX-OUT function. The delay depends mainly upon the 5V-CAN capacitor and load on 5V-CAN. The delay can be estimated using the following formula: delay = C(5V-CAN) x U (5V) / I_lim 5V-CAN. C = cap at 5V-CAN regulator, U = 5V, I_lim 5V-CAN = min current limit of 5V-CAN regulator (parameter 5V-C ILIM). I/O PINS (I/O-1: I/O-3) I/O s are configurable input output pins. They can be used for small load or to drive external transistors. When used as output drivers, the I/Os are high side or low side type. They can also be set to high-impedance. I/Os are controlled by SPIn and at power on, the I/Os are set as inputs. They include over load protection by temperature or excess of drop voltage. In Low Power Mode, state of the I/O can be turned on or off, with extremely low extra consumption (except load). Protection is disabled in low power mode. When cyclic sense is used, I/O-0 is the high side/low side switch, I/O-1, 2 and 3 and the wake inputs. I/O-2 and I/O-3 terminals share also the LIN Master terminal function. VSENSE INPUT (VSENSE) This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION VBAT D1 VSUP_1 VSENSE RSENSE 1k S_in Multiplexer S_in S_iddc VDD-I_COPY 5V-CAN 5V-CAN MCU MUX-OUT A/D in RMI S_ir RM(*) (*)Optional I/O-0 S_in buffer S_g3.3 S-i/o_att I/O-1 S_g5 S_in Temp Vref: 2.5V S-i/o_att All swicthes and resistor are configured and controlled via the SPI. RM: internal resistor connected when VREG current monitor is used. S_g3.3 and S_g5 for 5.0V or 3.3V MCU. S_iddc to select VDD regulator current copy. S_in1 for Low Power Mode resistor bridge disconnection. S_ir to switch on/off of the internal RMI resistor. Figure 17. Analog Multiplexer Block Diagram DGB (DGB) AND DEBUG MODE The DBG pin has 2 functions: Primary function: It is an output used to set the device in Debug Mode. This is achieved by applying a voltage between 8V and 10V, at the debug terminal, and then powering up the device (ref to state diagram). When device leaves the INIT reset mode and enter in INIT mode, device detects that voltage at debug terminal is within the 8-10V range, and activate the debug mode. When debug mode is detected, no watchdog SPI refresh commands is necessary. This allow easy debug of the hardware and software routines (i.e SPI commands). Device is in debug mode is reported by SPI flag. While in de bug mode, when voltage at DBG terminal falls below the 8-10V range, the debug mode is left, and device start W/D operation, and expect proper W/D refresh.Debug mode can be left by SPI. Such command is recommended to avoid staying in debug mode in case of unwanted debug mode selection (pin FMEA). SPI command to leave debug has higher priority than providing 8-10V at debug pin. Secondary function: The resistor connected between DBG pin and gnd selects the Fail Safe Mode operation. DBG pin can also be connected directly to gnd (this prevent usage of debug mode). Flexibility is provided to the user to select SAFE output operation via a resistor at the DBG pin or via SPI command. The SPI command has higher priority than the hardware selection via Debug resistor. When the Debug mode is selected, the SAFE modes can not be configured via the resistor connected at DBG pin. SAFE Safe output terminal This pin is an output which is asserted low in case a fault event occurs. The objective is to drive electrical safe circuitry and set the ECU in a know sate independent of the MCU and SBC, once a failure has been detected. The SAFE output structure is an open drain, without a pullup. No current flow is allowed when SAFE is forced externally to a high-voltage (< 40V). INTERRUPT (INT) The INT output is asserted low or generate a low pulse when an interrupt condition occurs. The INT condition is enabled in the INT register. The selection of low level or pulse as well as pulse duration are selected by SPI. No current will flow inside the INT structure when VDD is low, in Low Power VDD OFF Mode. This allows the connection of an external pull resistor, and connection of an INT pin from other ICs without extra consumption in unpowered mode. 33904/5 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION INT has internal pull up structure to VDD. In Low Power VDD ON Mode, a diode is inserted in series with the pull up, so the high level is slightly lower than in other modes. CANH, CANL, SPLIT, RXD, TXD These are the terminals of the high speed CAN physical interface, between the CAN bus and the micro controller. A detail description is provided in the document. LIN, TXDL, RXDL AND LINTERM These are the terminals of the Local Interconnect Network physical interface. Device contains zero, one or two LIN interfaces. MC33904 has no LIN interface. MC33905S (S as Single) and MC33905D (D as Dual) contain respectively 1 and 2 LIN interfaces. LIN 1 and LIN 2 terminals are the connection to the LIN sub buses. LIN interfaces are connected to the MCU via the TxDL1 (TxDL2) and RxDL1 (RxDL2) terminals. The device also include one or two high side switches to Vsup2 terminal which can be used as a LIN master termination switch. Pins LINT-1 and LINT-2 are the same as I/O-2 and I/O-3. A detail description is provided in the document 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION The device has several operation modes. The transitions and conditions to enter or leave each modes are illustrated in the state diagram. 256ms when Normal Request mode is entered after RESET mode. Different duration can be selected by SPI for the case when normal request is entered from LP VDD ON mode. If the W/D refresh SPI command does not occur within the 256ms (or the shorter user defined time out), then the device will enter into RESET mode, for a duration of typ 1ms. note: in init reset, init, reset and normal request modes as well as in low power modes, the VDD external PNP is disabled. INIT RESET This mode is automatically entered after device “power on”. In this mode, the RSTb pin is asserted low, for a duration of typ 1ms. Control bits and flags are “set” to their default reset condition. The BATFAIL is set to indicated that the device is coming from an unpowered condition, and that all previous device configuration are lost and “reset” the default value. The duration of the INIT reset is typ 1ms. INIT reset mode is also entered from INIT mode in case the expected SPI command does not occur in due time (ref. INIT mode), and if device is not in debug mode. NORMAL In this mode, all device functions are available. This mode is entered by a SPI W/D refresh command from Normal Request mode, or from INIT mode. During Normal mode, the device Watchdog function is operating, and a periodic W/D refresh must occurs. In case of incorrect or missing W/D refresh command device will enter into Reset mode. From Normal mode, the device can be set by SPI command into Low Power modes (Low Power VDD ON or Low Power VDD OFF Modes). Dedicated secured SPI commands must be used to enter from Normal mode in RESET mode, INIT mode or FLASH mode. INIT This mode is automatically entered from “INIT reset” mode. In this mode, the device must be configured via SPI within a time of 256ms max. Four registers called INIT Wdog, INIT REG, INIT LIN I/O and INIT MISC must be and can only be configured during INIT mode. Other registers can be written in this mode, however they can be also written in other modes. Once the INIT registers configuration is done, a SPI Watchdog Refresh command must be send in order to set the device into Normal mode. If the SPI W/D refresh does not occur within the 256ms period, the device will return into INIT reset mode for typ 1ms, and then re enter into INIT mode. Register read operation is allowed in INIT mode to collect device status or to read back the INIT register configuration When INIT mode is left by a SPI W/D refresh command, it is only possible to re enter the INIT mode using a secured SPI command. FLASH In this mode, the software watchdog period is extended up to typ 32 seconds. This allow programming of the MCU flash memory while minimizing the software over head to refresh the W/D. The flash mode is entered by Secured SPI command and is left by SPI command. Device will enter into RESET mode. In case of incorrect or missing W/D refresh command device will enter into Reset mode. An INT can be generated at 50% of the W/D period. CAN interface operates in Flash mode to allow flash via CAN bus, inside the vehicle. RESET In this mode, the RSTb pin is asserted low. Reset mode is entered from Normal mode, Normal Request mode, LP VDD on mode and from Flash mode, when the W/D is not triggered, or if a VDD low condition is detected. The duration of reset is typ 1ms by default. The user can defined a longer Reset pulse activation only for the case the reset mode is entered following a VDD low condition. Reset pulse is always 1ms, in case Reset mode in entered due to wrong W/D refresh command. Reset mode can be entered via secured SPI command. DEBUG Debug is a special operation mode of the device which allows system easy software and hardware debugging. The debug operation is detected after power up if the DBG pin is set in the 8.0-10V range. When debug is detected, all the software watchdog operations are disabled: 256ms of INIT mode, W/D refresh of Normal mode and Flash mode, Normal Request time out (256ms or user defined value) are not operating and will not lead to transition into INIT reset or Reset mode. When device is in Debug, SPI command can be send without any time constraints with respect to W/D operation, MCU program can be “halted” or “paused” to verify proper operation. Debug can be left by removing 8-10V from debug pin, or by SPI command (ref to MODE register). 5V-CAN regulator is ON by default in debug mode. NORMAL REQUEST This mode is automatically entered after RESET mode, or after a wake up from Low Power VDD ON Mode. A W/D refresh SPI command is necessary to transition to NORMAL mode. The duration of the Normal request mode is 33904/5 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOW POWER MODES LOW POWER MODES The device has two main Low Power Modes: Low Power Mode with VDD off, and Low Power Mode with VDD on. note: Prior to enter in Low Power mode, I/O and CAN wake up flags must be cleared (ref to Mode register). The same wake-up events as in LP Vdd off mode (CAN, LIN, I/O, timer, cyclic sense) are available in LP Vdd on mode. In addition, two additional wake up conditions are available. • Dedicated SPI command. When device is in LP Vdd ON mode, the wake up by SPI command uses a write to “Normal Request Mode”, 0x5C10. • Output current from Vdd exceeding typ 1.5mA threshold. In Low Power VDD ON Mode, the device is able to source several tenth of mA DC. The current source capability can be time limited, by a selectable internal timer. Timer duration is up to 32ms, and is triggered when the output current exceed the output current threshold typ 1.5mA. This allow for instance a periodic activation of the MCU, while the device remains in LP VDD on mode. If the duration exceed the selected time (ex 32ms), the device will detect a wake up. Wake up event are reported to the MCU via a low level pulse at INT pulse. The MCU will detect the INT pulse and resume operation. Watchdog function in LP VDD ON mode It is possible to enable the W/D function in Low Power VDD ON Mode. In this case, the principle is time out. Refresh of the W/D is done either by: • a dedicated SPI command (different from any other SPI command or simple CSb activation which would wake up - ref to above paragraph) • or by a temporary (less than 32ms max) Vdd over current wake-up (Idd > 1.5mA typ). As long as the W/D refresh occurs, the device remains in LP Vdd on mode. MODE transition mode transition are either done automatically (i.e after time out expired or voltage conditions), or via SPI command, or by external event such as wake up. Some mode change are performed via “secured” SPI commands. LOW POWER - VDD OFF In this mode, VDD is turned off and the MCU connected to VDD is unsupplied. This mode is entered by the SPI. It can also be entered by automatic transition due to fail safe management. 5V-CAN and Vaux regulators are also turned OFF. When the device is in Low Power VDD OFF Mode, it monitors external events to wake up and leave the LP mode. The wake up events can occurs from: • CAN • LIN interface, depending upon device part number • Expiration of an internal timer • I/O-0, and I/O-inputs, and depending upon device part number and configuration, I/O-2 and/or 3 input • Cyclic sense of I/O-1 input, associated by I/O-0 activation, and depending upon device part number and configuration, cyclic sense of I/O-2 and 3 input, associated by I/O-0 activation When a wake up event is detected, the device enters into reset mode and then into Normal Request mode. The wake up source are reported into the device SPI registers. In summary, a wake up event from LP Vdd off, lead to Vdd regulator turn ON, and MCU operation restart. LOW POWER - VDD ON In this mode, the voltage at the VDD terminal remains at 5.0V (or 3.3V, depending upon device part number). The objective is to maintain the MCU powered, with reduced consumption. In such mode, the DC output current is expected to be limited to few 100uA or few mA, as the ECU is in reduced power operation mode. During this mode, the 5V-CAN and VAUX regulators are OFF. 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION STATE DIAGRAM STATE DIAGRAM VSUP fall VSUP1 rise > VSUP-TH1 & VDD > VDD_UVTH POWER DOWN T_INIT expired or VDD no wake up Cyclic sense active time I/O-1 I/O-1 deglitcher time (typ 30us) S1 closed S1 open Zoom Cyclic sense active time (ex 200us) NORMAL MODE LOW POWER MODE RESET or NORMAL REQUEST MODE Wake up event detected Wake up detected. R R R R R R I/O-0 I/O-1 S1 S1 I/O-0 I/O-1 I/O-2 S2 S2 I/O-2 S3 I/O-3 S3 I/O-3 Upon entering in LP mode, all 3 contact switches are closed. In LP mode, 1 contact switch is open. High level is detected on I/O-x, and device wakes up. Figure 21. Cyclic Sense operation - switch to gnd, wake up by open switch 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN BEHAVIOR AT POWER UP AND POWER DOWN DEVICE POWER UP: This section describe the device behavior during ramp up, and ramp down of Vsup1, and the flexibility offered mainly by the Crank bit and the 2 Vdd undervoltage reset thresholds. The figures below illustrate the device behavior during Vsup1 ramp up. As the Crank bit is by default set to 0, Vdd is enable when Vsup1 is above Vsup th 1 parameters. Vsup_nominal (ex 12V) Vsup slew rate Vdd nominal (ex 5V) VDD_UV TH (typ 4.65V) VBAT D1 VSUP1 MC33905 I_VDD VSUP1 VDD Vsup_th1 VDD_start up 90% VDD_start up Gnd VDD RESET 10% VDD_start up VDD_off 1ms Figure 22. Vdd start up versus Vsup1 tramp DEVICE POWER DOWN The figures below illustrate the device behavior during Vsup1 ramp down, based on Crank bit configuration, and Vdd undervoltage reset selection. Crank bit reset (INIT W/D register, bit 0 =0): Bit 0 = 0 is the default state for this bit. During Vsup ramp down, Vdd remain ON until device enters in Reset mode due to Vdd Under Voltage condition (Vdd < 4.6V or Vdd < 3.2V typ, threshold selected by SPI). When device is in Reset, if Vsup is below “Vsup_th1”, Vdd is turned OFF. Crank bit set (INIT W/D register, bit 0 =1): The bit 0 is set by SPI write. During Vsup ramp down, Vdd remains ON until device detects a POR and set BATfail. This occurs for a Vsup approx 3V. 33904/5 40 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN Vbat Vsup_nominal (ex 12V) VSUP1 Vbat Vsup_nominal (ex 12V) VSUP1 Vdd (5V) VDD_UV TH (typ 4.65V) Vsup_th1 (4.1V) Vdd (5V) VDD_UV TH (typ 4.65V) minVsup (3V) VDD VDD RESET RESET Case 1: “Vdd UV th 4.6V”, with bit Crank =0 (default value) Case 2: “Vdd UV 4.6V”, with bit Crank =1 Vbat Vsup_nominal (ex 12V) VSUP1 Vbat Vsup_nominal (ex 12V) VSUP1 Vsup_th1 (4.1V) Vdd (5V) VDD_UV TH (typ 4.65V) Vdd (5V) VDD_UV TH (typ 4.65V) minVsup (3V) VDD VDD_UV TH2 (typ 3.2V) (2) INT RESET (1) (1) reset then (2) Vdd turn OFF VDD VDD_UV TH2 (typ 3.2V) INT RESET Case 3: “Vdd UV th 3.2V”, with bit Crank =0 (default value) Case 2: “Vdd UV th 3.2V”, with bit Crank =1 Figure 23. Vdd Behavior During Vsup1 Ramp Down 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 41 FAIL SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN FAIL SAFE OPERATION OVERVIEW Fail safe mode is entered when specific fail conditions occur. The “Safe state” condition is defined by the resistor connected at the DGB pin. Safe Mode is entered after additional event or conditions are met: time out for CAN communication and state at I/O-1 pin. Exit of the safe state is always possible by a wake-up event: in the safe state the device is automatically wakeable CAN and I/O (if configured as inputs). Upon wake-up, the device operation is resumed: enter in Reset Mode. modes B1, B2 and B3: Upon SAFE activation, the system continues to monitor external event, and disable the MCU supply (turn Vdd off). The external events monitored are: CAN traffic, I/O-1 low level or both of them. 3 sub cases exist, B1, B2 and B3. Note: no CAN traffic indicates that the ECU of the vehicle are no longer active, thus that the car is being parked and stopped. The I/O low level detection can also indicate that the vehicle is being shutdown, if the I/O-1 terminal is connected for instance to a switched battery signal (ignition key on/off signal). The selection of the monitored events is done by hardware, via the resistor connected at DBG pin, but can be over write by software, via a specific SPI command. By default, after power up the device detect the resistor value at DBG pin (upon transition from INIT to Normal mode), and, if no specific SPI command related to Debug resistor change is send, operates according to the detected resistor. The INIT MISC register allow to verify and change the device behaviour, to either confirm or change the hardware selected behaviour. Device will then operate according to the SAFE mode configured by SPI. Table below (Table 7) illustrates the complete options available: FAIL SAFE FUNCTIONALITY Upon dedicated event or issue detected at a device pin (i.e RESET), the Safe mode can be entered. In this mode, the SAFE terminal is active low. Description Upon activation of the SAFE terminal, and if the failure condition that make the SAFE pin activated have not recovered, the device can help to reduce ECU consumption, assuming that the MCU is not able to set the whole ECU in low power mode. Two main cases are available: mode A: Upon SAFE activation, the MCU remains powered (Vdd stays ON), until the failure condition recovers (i.e S/W is able to properly control the device and properly refresh the W/D). Table 7. Fail Safe Options Resistor at DBG pin SPI coding - register INIT MISC bits [2,1,0] (higher priority that Resistor coding) Safe mode code A B1 B2 B3 Vdd status xte Vd rna d lc di o sa nd bl iti e on If Reset s/c gnd recovered Vdd OFF 100ms deglitcher time to activate SAFE and enter in SAFE mode to evaluate resistor at DBG pin and monitor ECU external events Figure 26. SAFE Modes B1, B2 or B3 Behavior Illustration 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor w ak e up 45 CAN INTERFACE CAN INTERFACE DESCRIPTION CAN INTERFACE CAN INTERFACE DESCRIPTION The figure below is a high level schematic of the CAN interface. It consist in a low side driver between CANL and gnd, and high side driver from CANH to 5V-CAN. Two differential receivers are connected between CANH and CANL, to detect bus state and to wake up from CAN Sleep Mode. An internal 2.5V reference provide the 2.5V recessive level via the matched Rin resistors. The resistors can be switched to gnd in CAN Sleep Mode. A dedicated split buffer provide a low impedance 2.5V to the Split terminal, for recessive level stabilization. VSUP SPI & State machine 5V-CAN Pattern Detection Wake-up Receiver Driver 2.5 V RIN QH CANH Differential Receiver RIN CANL RXD 5V-CAN Driver Thermal QL TXD SPI & State machine 5V-CAN Buffer SPLIT SPI & State machine Failure Detection & Management Figure 27. CAN Interface Block Diagram CAN INTERFACE SUPPLY The supply voltage for the CAN driver is the 5V-CAN pin. The CAN interface also has a supply pass from the battery line, through the VSUP pin. This pass is used in CAN Sleep Mode to allow wake-up detection. During CAN communication (transmission and reception), the CAN interface current is sourced from the 5V-CAN pin. During CAN Low Power Mode, the current is sourced from the Vsup2 pin. TX RX MODE In Tx/Rx Mode, both the CAN driver and the receiver are ON. In this mode, the CAN lines are controlled by the TXD pin level, and the CAN bus state is reported on the RXD pin. The 5V-CAN regulator must be ON. It supplies the CAN driver and receiver.The SPLIT pin is active and a 2.5V biasing is provided on the SPLIT output pin. RECEIVE ONLY MODE This mode is used to disable the CAN driver, but leave the CAN receiver active. In this mode, the device is only able to report the CAN state on the RXD pin. The TXD pin has no effect on CAN bus lines. The 5V-CAN regulator must be ON. The SPLIT pin is active and a 2.5V biasing is provided on the SPLIT output pin. OPERATION in TX/RX Mode The CAN driver will be enable as soon as the device is in Normal Mode and the TXD pin is recessive. 33904/5 46 Analog Integrated Circuit Device Data Freescale Semiconductor CAN INTERFACE CAN INTERFACE DESCRIPTION When the CAN interface is in Normal Mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD pin. The bus state is reported through the RXD pin. When TXD is high, the driver is set in the recessive state, and CANH and CANL lines are biased to the voltage set with 5V-CAN divided by 2, or approx. 2.5V. When TXD is low, the bus is set into the dominant state, and CANL and CANH drivers are active. CANL is pulled low and CANH is pulled high. The RXD pin reports the bus state: CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV). If “CANH minus CANL” is below the threshold, the bus is recessive and RXD is set high. If “CANH minus CANL” is above the threshold, the bus is dominant and RXD is set low. The SPLIT pin is active and provide a 2.5V biasing to the SPLIT output. Tx/Rx Mode and Slew Rate Selection The CAN signal slew rate selection is done via the SPI. By default and if no SPI is used, the device is in the fastest slew rate. Three slew rates are available. The slew rate controls the recessive to dominant, and dominant to recessive transitions. This also affects the delay time from the TXD pin . TXD to the bus, and from the bus to the RXD. The loop time is thus affected by the slew rate selection. Minimum Baud rate The minimum baud is determined by the shortest TXD permanent dominant timing detection. The maximum number of consecutive dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag). The shortest TXD dominant detection time of 300μs lead to a single bit time of: 300μs / 12 = 25μs. So the minimum Baud rate is 1 / 25μs = 40kBaud. SLEEP MODE Sleep Mode is a reduced current consumption mode. CANH and CANL driver are disabled and CANH and CANL lines are terminated to GND via the Rin resistor, the SPLIT pin is high-impedance. In order to monitor bus activities, the CAN wake-up receiver can be enabled. It is supplied internally from Vsup2. Wake-up events occurring on the CAN bus pin are reporting by dedicated flags in SPI and by INT pulse, and results in a device wake up if device was in Low Power Mode. When the device is set back into Normal Mode, CANH and CANL are set back into the recessive level. This is illustrated in Figure 28. Dominant state CANH-DOM Recessive state CANH 2.5V CANL CANL/CANH-REC CANH-CANL CANL-DOM High ohmic termination (50kohms) to GND RXD SPLIT 2.5V Bus Driver Receiver (bus dominant set by other IC) Normal or Listen Only Mode High- impedance Go to sleep, Sleep or Stand-by Mode Normal or Listen Only Mode Figure 28. Bus Signal in Tx/Rx and Low Power Mode Wake-up When the CAN interface is in Sleep Mode with wake-up enabled, the CAN bus traffic is detected. The CAN bus wakeup is a pattern wake-up. The wake-up by the CAN is enabled or disabled via the SPI. 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 47 CAN INTERFACE CAN INTERFACE DESCRIPTION CAN bus CANH Dominant Pulse # 1 CANL Internal differential wake-up receiver signal Dominant Pulse # 2 Internal wake-up signal Tcan wu1-f Can wake up detected Figure 29. Single Dominant Pulse Wake-up Pattern Wake-up In order to wake-up the CAN interface, the wake-up receiver must receive a series of 3 consecutive valid dominant pulses, by default when the CANWU bit is low. CANWU bit can be set high by SPI and the wake-up will occur after a single pulse duration of 2μs (typ). . CAN bus CANH Dominant Pulse # 1 CANL Dominant Pulse # 2 Dominant Pulse # 3 Dominant Pulse # 4 A valid dominant pulse should be longer than 500ns. The 3 pulses should occur in a time frame of 120μs, to be considered valid. When 3 pulses meet these conditions, the wake signal is detected. This is illustrated by the following figure. Internal differential wake-up receiver signal Internal wake-up signal Tcan wu3-f Tcan wu3-f Tcan wu3-to Tcan wu3-f Can wake up detected Dominant Pulse # n: duration 1 or multiple dominant bits Figure 30. Pattern Wake-up - Multiple Dominant Detection BUS TERMINATION The device supports the two main types of bus terminations: • Differential termination resistors between CANH and CANL lines. • SPLIT termination concept, with the mid point of the differential termination connected to GND through a capacitor and to the SPLIT pin. • In application, device can also be used without termination. 33904/5 48 Analog Integrated Circuit Device Data Freescale Semiconductor CAN INTERFACE CAN INTERFACE DESCRIPTION • The figure below illustrate some of the most common terminations. Supported CAN Terminations SPLIT termination CANH 60 SPLIT 60 CANL C5 ECU connector Termination outside ECU CANH C6 CANL C5 CAN bus SPLIT No connect 60 CAN bus SPLIT No connect CAN bus C4 Standard termination CANH C4 CANH No termination C4 CANL C5 C4 CAN bus 30 SPLIT C6 CANL C5 ECU connector Termination 30 Figure 31. Typical Application and Bus Termination Options 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 49 CAN INTERFACE CAN BUS FAULT DIAGNOSTIC CAN BUS FAULT DIAGNOSTIC The device includes diagnostic of bus short-circuit to GND, VBAT, and internal ECU 5.0 V. Several comparators are implemented on CANH and CANL lines. These comparators H5 Hb TX Diag Lg Vrg Lb L5 Vrvb Vr5 CANL Hg Vr5 VBAT (12-14V) Vrvb VDD VRVB (VSUP-2.0V) CANH VDD (5.0V) VR5 (VDD-.43V) CANH dominant level (3.6V) Recessive level (2.5V) VRG (1.75V) CANL dominant level (1.4V) GND (0.0V) monitor the bus level in the recessive and dominant states. The information is then managed by a logic circuitry to properly determine the failure and report it. Vrg Logic Figure 32. CAN Bus Simplified Structure Truth Table for Failure Detection The following table indicates the state of the comparators in case of a bus failure, and depending upon the driver state. Table 8. Failure Detection Truth Table Failure Description No failure CANL to GND CANH to GND No failure CANL to VBAT CANH to VBAT No failure CANL to 5.0V CANH to 5.0V Driver Recessive State Lg (threshold 1.75V) 1 0 0 Lb (threshold VSUP -2.0V) 0 1 1 L5 (threshold VDD -0.43V) 0 1 1 Hg (threshold 1.75V) 1 0 0 Hb (threshold VSUP -2.0V) 0 1 1 H5 (threshold VDD -0.43V) 0 1 1 0 0 0 Lb (threshold VSUP -2.0V) 0 1 0 L5 (threshold VDD -0.43V) 0 1 0 Driver Dominant State Lg (threshold 1.75V) Hg (threshold 1.75V) 1 1 0 Hb (threshold VSUP -2.0V) 0 1 1 H5 (threshold VDD -0.43V) 0 1 1 DETECTION PRINCIPLE In the recessive state, if one of the two bus lines are shorted to GND, VDD (5V), or VBAT, the voltage at the other line follows the shorted line, due to the bus termination resistance. For example: if CANL is shorted to GND, the CANL voltage is zero, the CANH voltage measured by the Hg comparator is also close to zero. In the recessive state, the failure detection to GND or VBAT is possible. However, it is not possible with the above implementation to distinguish which of the CANL or CANH lines are shorted to GND or VBAT. A complete diagnostic is possible once the driver is turned on, and in the dominant state. Number of Samples for Proper Failure Detection The failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. The error will be fully detected after 5 cycles of the recessive-dominant states. As long as the failure detection 33904/5 circuitry has not detected the same error for 5 recessivedominant cycles, the error is not reported. BUS CLAMPING DETECTION If the bus is detected to be in dominant for a time longer than (TDOM), the bus failure flag is set and the error is reported in the SPI. Such condition could occur in case the CANH line is shorted to a high-voltage. In this case current will flow from the high-voltage short circuit through the bus termination resistors (60Ω) and then in the SPLIT pin (if used) and in the device CANH and CANL input resistors, which are terminated to internal 2.5V biasing or to GND (Sleep Mode). Depending upon the high-voltage short-circuit, the number of nodes, usage of the SPLIT pin, RIN actual resistor and Mode state (Sleep or Active) the voltage across the bus termination can be sufficient to create a positive dominant voltage between CANH and CANL, and RXD pin will be low. This would prevent start of any CAN communication, and 50 Analog Integrated Circuit Device Data Freescale Semiconductor CAN INTERFACE CAN BUS FAULT DIAGNOSTIC thus a proper failure identification (requires 5 pulses on TXD). The bus dominant clamp circuit will help to determine such failure situation. RX PERMANENT RECESSIVE FAILURE The aim of this detection, is to diagnose an external hardware failure at the RX output pin and ensure that a TXD Diag Logic TX driver Diff output VDD/2 VDD RXD RX driver Diff CANL Rxsense VDD CANH 60 RX flag Prop delay RXD output CANL&H permanent failure at RX does not disturb the network communication. If RX is shorted to a logic high signal, the CAN protocol module within the MCU will not recognize any incoming message. In addition it will not be able to easily distinguish the bus idle state and can start communication at any time. In order to prevent this, an RX failure detection is necessary. Sampling Sampling RX short to VDD RX flag latched The RX flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 33. RX Path Simplified Schematic, RX Short to VDD Detection Implementation for Detection The implementation sense the RXD output voltage at each low to high transition of the differential receiver. Excluding the internal propagation delay, the RXD output should be low when the differential receiver is low. In case of an external short to VDD at the RXD output, RXD will be tied to a high level and can be detected at the next low to high transition of the differential receiver. CANL&H As soon as the RXD permanent recessive is detected, the RXD driver is deactivated. Once the error is detected the driver is disabled and the error is reported via SPI in CAN register. Recovery Condition The internal recovery is done by sampling a correct low level at TXD as shown in the following illustration. Diff output Sampling Sampling RXD output Rx short to VDD RX no longer shorted to VDD RX flag latched RX flag The RX flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 34. RX Path Simplified Schematic, Rx Short to VDD Detection TXD PERMANENT DOMINANT Principle If the TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible. The device has a TXD permanent time out detector. After the timeout, the bus driver is disabled and the bus is released into a recessive state. The TXD permanent flag is set. Recovery The TXD permanent dominant is used and activated also in case of a TXD short to RXD. The recovery condition for a TXD permanent dominant (recovery means the re-activation of the CAN drivers) is done by entering into a Normal Mode controlled by the MCU or when TXD is recessive while RXD change from recessive to dominant. 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 51 CAN INTERFACE CAN BUS FAULT DIAGNOSTIC TXD TO RXD SHORT CIRCUIT: Principle In case TXD is shorted to RXD during incoming dominant information, RXD is set low. Consequently, the TXD pin is low and drives CANH and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is possible. Detection and Recovery The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next incoming dominant bit, the bus will then be stuck in dominant again. The recovery condition is same as the TXD dominant failure IMPORTANT INFORMATION FOR BUS DRIVER REACTIVATION The driver stays disabled until the failure is/are removed (Tx and/or RX is no longer permanent dominant or recessive state or shorted) and the failure flags cleared (read). The CAN driver must be set by SPI in TxRx mode in order to re enable the CAN bus driver. 33904/5 52 Analog Integrated Circuit Device Data Freescale Semiconductor LIN BLOCK LIN INTERFACE DESCRIPTION LIN BLOCK LIN INTERFACE DESCRIPTION The physical interface is dedicated to automotive LIN subbus applications. The interface has 20kbps and 10kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has excellent ESD robustness and immunity against disturbance, and radiated emission performance. It has safe behavior in case of a LIN bus short-to-ground, or a LIN bus leakage during low power mode. Digital inputs are related to device Vdd terminal. The LIN pin exhibits no reverse current from the LIN bus line to VSUP, even in the event of a GND shift or VSUP disconnection. The transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by SPI. Receiver Characteristics The receiver thresholds are ratiometric with the device Vsup2 voltage. If the Vsup2 voltage goes below typ 6.1V, the LIN bus enters into a recessive state even if communication is sent on TXD. If LIN driver temperature reached over temperature threshold, the transceiver and receiver are disabled. When the temperature falls below the over temperature threshold, LIN driver and receiver will be automatically enabled. POWER SUPPLY PIN (VSUP) The VSUP-2 terminal is the supply pin for the LIN interface. To avoid a false bus message, an under-voltage on VSUP disables the transmission path (from TXD to LIN) when VSUP falls below 6.1 V. GROUND PIN (GND) In case of a ground disconnection at the module level, the LIN interface do not have significant current consumption on the LIN bus pin when in the recessive state. DATA INPUT PIN (TXDL1, TXDL2) The TXDl1 (TXDL2) input pin is the MCU interface to control the state of the LIN output. When TXDL is LOW (dominant), LIN output is LOW. When TXDL is HIGH (recessive), the LIN output transistor is turned OFF. This pin has an internal pull-up current source to Vdd to force the recessive state if the input pin is left floating. If the pin stays low (dominant sate) more than t TXDDOM, the LIN transmitter goes automatically in recessive state. This is reported by flag in LIN register. LIN BUS PIN (LIN1, LIN2) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN bus specification 2.1 and SAEJ2602-2. The LIN interface is only active during Normal mode. Driver Characteristics The LIN driver is a low side MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 kΩ must be added when the device is used in the master node. The 1.0 kΩ pull resistor can connected to LIN term or to ECU battery supply. DATA OUTPUT PIN (RXDL1, RXDL2) The RXDl output pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high voltage on RXD, LIN LOW (dominant) is reported by a low voltage on RXD. LIN OPERATIONAL MODES The LIN interface have two operational modes, Transmit receiver and LIN disable modes. When the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition. TRANSMIT RECEIVE In the TxRx mode, the LIN bus can transmit and receive information. When the 20kbps baud rate is selected, the slew rate and timing are compatible with LIN protocol specification 2.1. When the 10kbps baud rate is selected, the slew rate and timing are compatible with J2602-2. SLEEP MODE This mode is selected by SPI, and the transmission path is disabled. Supply current for LIN block from VSUP2 is very low (typ 3uA). LIN bus is monitor to detect wake-up event. In the Sleep Mode, the internal 725 kOhm pull-up resistor is connected and the 30 kOhm disconnected. 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 53 LIN BLOCK LIN OPERATIONAL MODES The LIN block can be awakened from Sleep Mode by detection of LIN bus activity. LIN Bus Activity Detection The LIN bus wake-up is recognized by a recessive to dominant transition, followed by a dominant level with a duration greater than 70 μs, followed by a dominant to recessive transition. This is illustrated in Figures 15 on page 26 and Figures 16 on page 27. Once the wake-up is Table 9. LIN Block Failure FAULT FUNCTIONNAL MODE CONDITION detected, the event is reported to the device state machine. An INT is generated if device is in LP Vdd ON mode, or Vdd will restart if device was in LP Vdd off mode. The wake up can be enable or disable by SPI. Fail-Safe Features The table below describes the LIN block behavior in case of failure. CONSEQUENCE LIN transmitter in recessive State LIN transmitter in recessive State LIN transmitter and receiver disabled High Side turned off RECOVERY LIN supply undervoltage Tx Rx TXD Pin Permanent Dominant Tx Rx LIN Thermal Shutdown LIN supply voltage < 6V (typ) TXD pin low for more than t TXDDOM Condition gone Condition gone LIN driver temperature > 160°C (typ) Condition gone 33904/5 54 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE HIGH LEVEL OVERVIEW SERIAL PERIPHERAL INTERFACE HIGH LEVEL OVERVIEW The device is using a 16 bits SPI, with the following arrangement: MOSI, Master Out Slave In bits: • bits 15 and 14 (called C1 and C0) are control bits to select the SPI operation mode (write control bit to device register, read back of the control bits, read of device flag). • bit 13 to 9 (A4 to A0) to select the register address. • bit 8 (P/N) has two functions: parity bit in write mode (optional, = 0 if not used), Next bit (=1) in read mode. • bit7 to 0 (D7 to D0): control bits MISO, Master IN Slave Out bits: • bits 15 to 8 (S15 to S8) are device status bits • bits 7 to 0(Do7 to Do0) are either extended device status bits, device internal control register content or device flags. Figure 35 is an overview of the SPI implementation. Bit 7 Bit 6 D7 D6 Bit 5 D5 Bit 4 Bit 3 D4 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 P/N MOSI C1 C0 A4 A3 A2 A1 A0 control bits register address Parity (optional) or Next bit =1 S9 S8 Do7 Do6 data MISO S15 S14 S13 S12 S11 S10 Do5 Do4 Do3 Do2 Do1 Do0 Device Status Extended Device Status, Register Control bits or Device Flags CSb active low. Must rise at end of 16 clocks, for write commands, MOSI bits [15, 14] = [0 1]. SCLK signal is low outside of CSB active CSb SCLK MOSI Don’t care MISO Tri state C1 S15 C0 S14 D0 Do0 Don’t care Tri state MOSI and MISO data changed at SCLK rising edge and sampled at falling edge. Msb first. MISO tri state outside of CSB active SPI wave form, and signals polarity Figure 35. Device SPI Overview 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 55 SERIAL PERIPHERAL INTERFACE DETAIL OPERATION DETAIL OPERATION BITS 15,14 AND 8 FUNCTIONS Table 10 summarizes the various SPI operation, depending upon bit 15, 14 and 8. Table 10. SPI Operations (bits 8, 14 & 15) Control bits MOSI[15-14], C1-C0 Type of Command Parity/Next MOSI[8] P/N Note for Bit 8 P/N 00 01 Read back of register content Write to register address, to control device operation Reserved Read of device flags form a register address 1 0 Bit 8 must be set to 1, independently of the parity function selected or not selected. If bit 8 is set to “0”: means parity not selected OR parity is selected AND parity = 0 1 10 11 if bit 8 is set to “1”: means parity is selected AND parity = 1 1 Bit 8 must be set to 1, independently of the parity function selected or not selected. BITS 13-9 FUNCTIONS The device contains several registers. Their address is coded on 5 bits (bits 13 to 9). Each register controls or reports part of the device function. Data can be written to the register, to control the device operation or set default value or behavior. Every register can also be read back in order to ensure that its content (default setting or value previously written) is correct. In addition some of the registers are used to report device flags. Device status on MISO When a write operation is performed to store data or control bit into the device, MISO pin reports a 16 bits fixed device status composed of 2 bytes: Device Fixed Status (bits 15 to 8) + extended Device Status (bits 7 to 0). In a read operation, MISO will report the Fixed device status (bits 15 to 8) and the next 8 bits will be the content of the selected register. 33904/5 56 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OPERATION REGISTER ADRESS TABLE Table 11 is the list of device registers and their associated address, coded with bits 13 to 9. Table 11. Device Registers with Corresponding Address Address MOSI[13-9] A4...A0 0_0000 Description Analog Multiplexer Quick Ref. Name MUX Functionality 1) Write “device control bits” to register address. 2) Read back register “control bits” 1) Write “data byte” to register address. 2) Read back “data byte” from register address 0_0001 0_0010 0_0011 0_0100 0_0101 0_0110 0_0111 0_1000 0_1001 Memory byte A Memory byte B Memory byte C Memory byte D Initialization Regulators Initialization Watchdog Initialization LIN and I/O Initialization Miscellaneous functions Specific Modes RAM_A RAM_B RAM_C RAM_D Init REG Init W/D Init LIN I/O Init MISC SPE_MODE 1) Write “device initialization control bits” to register address. 2) Read back “initialization control bits” from register address 1) Write to register to select device Specific Mode, using “Inverted Random Code”. 2) Read “Random Code” 1) Write “timing values” to register address. 2) Read back register “timing values” 0_1010 0_1011 0_1100 0_1101 0_1110 Timer_A: W/D & Low Power MCU consumption Timer_B: Cyclic Sense & Cyclic Interrupt Timer_C: W/D Low Power & Forced Wake-up Watchdog Refresh Mode register TIM_A TIM_B TIM_C W/D MODE Watchdog Refresh Commands 1) Write to register to select Low Power Mode, with optional “Inverted Random code” and select wake-up functionality 2) Read operations: Read back device “Current Mode” Read “Random Code”, Leave “Debug Mode” 1) Write “device control bits” to register address, to select device operation. 2) Read back register “control bits”. 3) Read device flags from each of the register addresses. 0_1111 1_0000 1_0001 1_0010 Regulator Control CAN interface control Input Output control Interrupt Control REG CAN I/O Interrupt 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 57 SERIAL PERIPHERAL INTERFACE DETAIL OPERATION COMPLETE SPI OPERATION Table 12 is a compiled view of all the SPI capabilities and options. Both MOSI and MISO information are described. Table 12. SPI Capabilities with Options Type of Command Read back of “device control bits” (MOSI bit 7 = 0) OR Read specific device information (MOSI bit 7 = 1) MOSI/ MISO MOSI MISO MOSI MISO Write device control bit to address selected by bits (13-9). MISO return 16 bits device status Reserved MOSI MISO MOSI MISO Read device flags and wake-up flags, from register address (bit 13-9), and sub address (bit 7). MISO return fixed device status (bit 15-8) + flags from the selected address and sub-address. MISO MOSI MISO MOSI 11 address Reserved Control bits [15-14] 00 Address [13-9] address Parity/Next bits [8] 1 Bit 7 0 Bits [6-0] 000 0000 Register control bits content 1 000 0000 Device ID and I/Os state Control bits Device Extended Status (8 bits) Reserved Reserved 0 Read of device flags form a register address, and sub address LOW (bit 7) Flags 1 Read of device flags form a register address, and sub address HIGH (bit 7) Flags Device Fixed Status (8 bits) 00 address 1 Device Fixed Status (8 bits) 01 address (note) Device Fixed Status (8 bits) 10 Device Fixed Status (8 bits) 11 address 1 Device Fixed Status (8 bits) Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity is selected and parity = 1. Thus the Exact command will then be: MOSI [bit 15-0]= 01 00 011 0 01101001 Examples 2: MOSI [bit 15-0]= 01 00 011 P 0100 0000, P should be 1, because the command contains 4 bits with logic 1. Thus the Exact command will then be: MOSI [bit 15-0]= 01 00 011 1 0100 0000 Parity function selection: The parity function is optional. It is selected by bit 6 in INIT MISC register. If parity function is not selected (bit 6 of INIT MISC =0), then Parity bits in all SPI commands (bit 8) must be “0”. PARITY BIT 8 Calculation The parity is used for write to register command (bit 15,14 = 01). It is calculated based on the number of logic one contained in bits 15-9,7-0 sequence (this is the whole 16 bits of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1if the number of 1 is even. Examples 1: MOSI [bit 15-0]= 01 00 011 P 01101001, P should be 0, because the command contains 7 bits with logic 1. 33904/5 58 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING DETAIL OF CONTROL BITS AND REGISTER MAPPING The following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100 MUX AND RAM REGISTERS Table 13. MUX Register MOSI First Byte [15-8] [b_15 b_14] 0_0000 [P/N] 01 00 _ 000 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 MUX_2 0 bit 6 MUX_1 0 bit 5 MUX_0 0 bit 4 Int 2K N/A bit 3 I/O-att 0 POR bit 2 X bit 1 X bit 0 X POR, 5V-CAN off, any mode different from Normal Description Bits b7 b6 b5 000 001 010 011 100 101 110 111 b4 0 1 b3 0 1 MUX_2, MUX_1, MUX_0 - Selection of external input signal or internal signal to be measured at MUX-OUT terminal All functions disable. No output voltage at MUX-OUT terminal VDD regulator current recopy. Ratio is approx 1/97. Requires an external resistor or selection of Internal 2K (bit 3) Device internal voltage reference (approx 2.5V) Device internal temperature sensor voltage Voltage at I/O-0. Attenuation or gain is selected by bit 3. Voltage at I/O-1. Attenuation or gain is selected by bit 3. Voltage at VSUP_1 terminal. Refer to electrical table for attenuation ratio (approx 5) Voltage at VSENSE terminal. Refer to electrical table for attenuation ratio (approx 5) INT 2k - Select device internal 2kohm resistor between AMUX and GND. This resistor allows the measurement of a voltage proportional to the VDD output current. Internal 2 kohm resistor disable. An external resistor must be connected between AMUX and GND. Internal 2 kohm resistor enable. I/O-att - When I/O-0 (or I/O-1) is selected with b7,b6,b5=100 (or 101), b3 selects attenuation or gain between I/O-0 (or I/O-1) and MUX-OUT terminal Gain is approx 2 for device with VDD =5V (Ref to electrical table for exact gain value) Gain is approx 1.3 for device with VDD =3.3V (Ref to electrical table for exact gain value) Attenuation is approx 6 for device with VDD =5V (Ref to electrical table for exact attenuation value) Attenuation is approx 4 for device with VDD =3.3V (Ref to electrical table for exact attenuation value) Table 14. Internal Memory Registers A, B, C and D, RAM_A, RAM_B, RAM_C and RAM_D MOSI First Byte [15-8] [b_15 b_14] 0_0xxx [P/N] 01 00 _ 001 P Default state Condition for default 01 00 _ 010 P Default state Condition for default 01 00 _ 011 P Default state Condition for default 01 00 _ 100 P Default state Condition for default Ram d7 0 Ram d6 0 Ram d5 0 Ram d4 0 POR Ram c7 0 Ram c6 0 Ram c5 0 Ram c4 0 POR Ram d3 0 Ram d2 0 Ram d1 0 Ram d0 0 Ram b7 0 Ram b6 0 Ram b5 0 Ram b4 0 POR Ram c3 0 Ram c2 0 Ram c1 0 Ram c0 0 MOSI Second Byte, bits 7-0 Bit 7 Ram a7 0 Bit 6 Ram a6 0 Bit 5 Ram a5 0 Bit 4 Ram a4 0 POR Ram b3 0 Ram b2 0 Ram b1 0 Ram b0 0 Bit 3 Ram a3 0 Bit 2 Ram a2 0 Bit 1 Ram a1 0 Bit 0 Ram a0 0 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 59 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING INIT REGISTERS Note: these registers can be written only in INIT mode Table 15. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_0101 [P/N] 01 00 _ 101 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 I/Ox sync 1 bit 6 VDDL rst[1] 0 bit 5 VDDL rst[0] 0 bit 4 VDD rstD[1] 0 POR bit 3 VDD rstD[0] 0 bit 2 VAUX5/3 0 bit 1 Cyclic on[1] 0 bit 0 Cyclic on[0] 0 Bit b7 0 1 b6, b5 00 01 10 11 b4, b3 00 01 10 11 Description I/Ox sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected I/O-1 sense anytime I/O-1 sense during I/O-0 activation VDDL rst[1] VddL rst[0] - Select the VDD Under-voltage threshold, to activate Reset terminal and/or INT Reset at approx 0.9 VDD. INT at approx 0.9 VDD, Reset at approx 0.7 VDD Reset at approx 0.7 VDD Reset at approx 0.9 VDD. VDD rstD[1] VDD rstD[0] - Select the Reset terminal low lev duration, after VDD rises above the VDD under-voltage threshold 1ms 5ms 10ms 20ms b2 0 1 [VAUX 5/3] - Select Vauxilary output voltage VAUX = 3.3V VAUX = 5 b1, b0 00 01 10 11 Cyclic on[1] Cyclic on[0] - Determine if I/O-1 activation time, when cyclic sense function is selected 200μs (typical value. ref to dynamic parameters for exact value) 400μs (typical value. ref to dynamic parameters for exact value) 800μs (typical value. ref to dynamic parameters for exact value) 1600μs (typical value. ref to dynamic parameters for exact value) 33904/5 60 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 16. Initialization Watchdog Registers, INIT W/D (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_0110 [P/N] 01 00 _ 110 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 WD2INT 0 bit 6 MCU_OC 1 bit 5 OC-TIM 0 POR bit 4 WD Safe bit 3 WD_spi[1] 0 bit 2 WD_spi[0] 0 bit 1 WD N/Win 1 bit 0 Crank 0 Bit b7 0 1 Description WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command Function disable. No constraint between INT occurrence and INT source read. INT source read must occur before the remaining of the current W/D period plus 2 complete W/D periods. b6, b5 MCU_OC, OC-TIM - In Low Power VDD ON, select watchdog refresh and VDD current monitoring functionality. VDD_OC_LP threshold is defined in device electrical parameters (approx 1.5mA) In low power mode, when W/D is not selected no W/D + 00 no W/D + 01 no W/D + 10 In Low Power VDD ON Mode, VDD over-current has no effect In Low Power VDD ON Mode, VDD over-current has no effect In Low Power VDD ON Mode, VDD current > VDD_OC_LP threshold for a time > 100μs (typ) is a wakeup event no W/D + 11 In Low Power VDD ON Mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register (selection range from 3 to 32ms) In low power mode when W/D is selected W/D + 00 W/D + 01 W/D + 10 W/D + 11 In Low Power VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command. In Low Power VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command. In Low Power VDD ON Mode, VDD over-current for a time > 100μs (typ) is a wake-up event. In Low Power VDD ON Mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a W/D refresh condition. VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is wake-up event. I_mcu_OC time is selected in Timer register (selection range from 3 to 32ms) b4 0 1 WD Safe - Select the activation of the SAFE terminal low, at first or second consecutive RESET pulse SAFE terminal is set low at the time of the RESET terminal low activation SAFE terminal is set low at the second consecutive time RESET pulse b3, b2 00 01 10 11 WD_spi[1] WD_spi[0] - Select the Watchdog (W/D) Operation Simple Watchdog selection: W/D refresh done by a 8bits or 16 bits SPI Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits. Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command. Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command. b1 0 1 b0 0 1 WD N/Win - Select the Watchdog (W/D) Window or Time out operation Watchdog operation is TIME OUT, W/D refresh can occur anytime in the period Watchdog operation is WINDOW, W/D refresh must occur in the open window (second half of period) Crank - Select the Vsup1 threshold to disable Vdd, while Vsup1 is falling toward gnd Vdd disable when Vsup1 is below typ 4V (parameter Vsup-th1), and device in Reset mode Vdd kept ON when Vsup1 is below typ4V (parameter Vsup_th1) 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 61 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 17. Initialization LIN and I/O registers, INIT LIN I/O (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_0111 [P/N] 01 00 _ 111 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 I/O-1 ovoff 0 bit 6 LIN_T1[1] 0 bit 5 LIN_T1[0] 0 POR bit 4 LIN_T0[1] bit 3 LIN_T0[0] 0 bit 2 I/O-1 out-en 0 bit 1 I/O-0 out-en 0 bit 0 Cyc_Inv 0 Bit b7 0 1 Description I/O-1 ovoff - Select the deactivation of I/O-1 in case VDD or VAUX over voltage condition is detected Disable I/O-1 turn off. Enable I/O-1 turn off, in case VDD or VAUX over-voltage condition is detected. b6, b5 00 01 10 11 LIN_T1[1], LIN_T1[1] - Select Terminal operation as LIN Master Terminal switch or I/O Terminal is OFF Terminal operation as LIN Master Terminal switch Terminal operation as I/O: high side switch and wake-up input N/A b4, b3 00 01 10 11 LIN_T0[1], LIN_T0[1] - Select Terminal operation as LIN Master Terminal switch or I/O Terminal is OFF Terminal operation as LIN Master Terminal switch Terminal operation as I/O: high side switch and wake-up input N/A b2 0 1 I/O-1 out-en- Select the operation of the I/O-1 as output driver (high side, low side) Disable high side and low side drivers of terminal I/O-1. I/O-1 can only be used as input. Enable high side and low side drivers of terminal I/O-1. Terminal can be used as input and output driver. b1 0 1 I/O-0 out-en - Select the operation of the I/O-0 as output driver (high side, low side) Disable high side and low side drivers of terminal I/O-0. I/O-0 can only be used as input. Enable high side and low side drivers of terminal I/O-0. Terminal can be used as input and output driver. b0 Cyc_Inv - Select I/O-0 operation in device Low Power mode, when cyclic sense is selected During cyclic sense active time, I/O is set to the same state prior to enter in low power mode. During cyclic sense off time, I/O-0 is disable (high side and low side drivers OFF). During cyclic sense active time, I/O is set to the same state prior to enter in low power mode. During cyclic sense on time, I/O-0 is actively set to the opposite (High side or low side driver is turned on). 33904/5 62 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 18. Initialization Miscellaneous Functions, INIT MISC (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_1000 [P/N] 01 01_ 000 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 LPM w RND 0 bit 6 SPI parity 0 bit 5 INT pulse 0 POR bit 4 INT width bit 3 INT flash 0 bit 2 Dbg Res[2] 0 bit 1 Dbg Res[1] 0 bit 0 Dbg Res[0] 0 Bit b7 0 1 Description LPM w RND - Select the functionality to change mode (enter in Low Power) using the device Random Code Function disable: the Low Power mode can be entered without usage of Random Code Function enabled: the Low Power mode is entered using the Random Code b6 0 1 SPI parity - Select usage of the parity bit in SPI write operation Function disable: the parity is not used. The parity bit must always set to logic 0. Function enable: the parity is used, and parity must be calculated. b5 0 1 INT pulse -Select INT terminal operation: low level pulse or low level INT terminal will assert a low level pulse, duration selected by bit [b4] INT terminal assert a permanent low level (no pulse) b4 0 1 INT width - Select the INT pulse duration INT pulse duration is typ 100μs. Ref to dynamic parameter table for exact value. INT pulse duration is typ 25μs. Ref to dynamic parameter table for exact value. b3 INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode Function disable Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in flash mode. b2, b1, b0 0xx 100 101 110 111 Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG terminal. Ref to parametric table for resistor range value. Function disable 100 verification enable: resistor at DBG terminal is typ 68kohms (RB3) - Selection of SAFE mode B3 101 verification enable: resistor at DBG terminal is typ 33kohms (RB2 - Selection of SAFE mode B2 110 verification enable: resistor at DBG terminal is typ 15kohms (RB1) - Selection of SAFE mode B1 111 verification enable: resistor at DBG terminal is typ 0kohms (RA) - Selection of SAFE mode A Notes 23. Bits b2,1 and 0 allow the following operation: First, check the resistor device has detected at the Debug pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt register (ref to device flag table). Second, over write the resistor decoded by device, to set the SAFE mode operation by SPI. Once this function is selected by bit 2 =1, this selection has higher priority than “hardware”, and device will behave according to b2,b1 and b0 setting 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 63 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING .SPECIFIC MODE REGISTER Table 19. Specific Mode Register, SPE_MODE MOSI First Byte [15-8] [b_15 b_14] 01_001 [P/N] 01 01_ 001 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 Sel_Mod[1] 0 bit 6 Sel_Mod[0] 0 bit 5 Rnd_C5b 0 POR bit 4 Rnd_C4b bit 3 Rnd_C3b 0 bit 2 Rnd_C2b 0 bit 1 Rnd_C1b 0 bit 0 Rnd_C0b 0 Bit b7, b6 00 01 10 11 Description Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI command. RESET mode INIT mode FLASH mode N/A b5....b0 [Rnd_C4b... Rnd_C0b] - Random Code inverted, these 6 bits are the inverted bits obtained from the SPE-MODE Register read command. The SPE MODE register is used for the following operation: - Set the device in RESET mode, to exercise or test the RESET functions. - Go to INIT mode, using the Secure SPi command. - Go to FLASH mode (in this mode the watchdog timer can be extended up to 32s). - Activate the SAFE terminal by S/W. These mode (called Special Mode) are accessible via secured SPI command, which consist in 2 commands: 1) reading a random code and 2) then write the inverted random code plus mode selection or SAFE pin activation: Return to INIT mode is done as follow (this is done from Normal mode only): 1) Read random code: MOSI : 0001 0011 0000 0000 [Hex:0x 13 00] MISO report 16 bits, random code are bits (5-0) miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (Rx= 6 bits random code) 2) Write INIT mode + random code inverted MOSI : 0101 0010 01 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (Rix= random code inverted) MISO : xxxx xxxx xxxx xxxx (don’t care) SAFE pin activation: SAFE pin can be set low, only in INIT mode, with following commands: 1) Read random code: MOSI : 0001 0011 0000 0000 [Hex:0x 13 00] MISO report 16 bits, random code are bits (5-0) miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (Rx= 6 bits random code) 2) Write INIT mode + random code bits 5:4 not inverted and random code bits 3:0 inverted MOSI : 0101 0010 01 R5 R4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (Rix= random code inverted) MISO : xxxx xxxx xxxx xxxx (don’t care) Return to RESET or FLASH mode is done similarly to the go to INIT mode, except that the b7, b6 are set according to table above (b7, b6 = 00 - go to reset, b7, b6 = 10 - go to FLASH). 33904/5 64 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING TIMER REGISTERS Table 20. Timer Register A, Low Power Vdd over current & Watchdog Period Normal mode, TIM_A MOSI First Byte [15-8] [b_15 b_14] 01_010 [P/N] 01 01_ 010 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 I_mcu[2] 0 bit 6 I_mcu[1] 0 bit 5 I_mcu[1] 0 bit 4 W/D Nor[4] 1 POR bit 3 W/D_N[4] 1 bit 2 W/D_Nor[3] 1 bit 1 W/D_N[2] 1 bit 0 W/D_Nor[0] 0 Low Power Vdd over current (ms) b6, b5 b7 00 0 1 3 (def) 4 01 6 8 10 12 16 11 24 32 Watchdog Period in Device Normal Mode (ms) b2, b1, b0 b4, b3 000 00 01 10 11 2.5 3 3.5 4 001 5 6 7 8 010 10 12 14 16 011 20 24 28 32 100 40 48 56 64 101 80 96 112 128 110 160 192 224 256 (def) 111 320 384 448 512 Table 21. Timer Register B, Cyclic Sense and Cyclic INT, in Device Low Power Mode, TIM_B MOSI First Byte [15-8] [b_15 b_14] 01_011 [P/N] 01 01_ 011 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 Cyc-sen[3] 0 bit 6 Cyc-sen[2] 0 bit 5 Cyc-sen[1] 0 bit 4 Cyc-sen[0] 0 POR bit 3 Cyc-int[3] 0 bit 2 Cyc-int[2] 0 bit 1 Cyc-int[1] 0 bit 0 Cyc-int[0] 0 Cyclic sense (ms) b6, b5, b4 b7 000 0 1 3 4 001 6 8 010 12 16 011 24 32 100 48 64 101 96 128 110 192 256 111 384 512 Cyclic Interrupt (ms) b2, b1, b0 b3 000 0 1 6 (def) 8 001 12 16 010 24 32 011 48 64 100 96 128 101 192 258 110 384 512 111 768 1024 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 65 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 22. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C MOSI First Byte [15-8] [b_15 b_14] 01_100 [P/N] 01 01_ 100 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 WD-LP-F[3] 0 bit 6 WD-LP-F[2] 0 bit 5 WD-LP-F[1] 0 bit 4 WD-LP-F[0] 0 POR bit 3 FWU[3] 0 bit 2 FWU[2] 0 bit 1 FWU[1] 0 bit 0 FWU[0] 0 Table 23. Typical Timing Values Watchdog in Low Power VDD ON Mode (in ms) b6, b5, b4 b7 000 0 1 12 16 001 24 32 010 48 64 011 96 128 100 192 256 101 384 512 110 768 1024 111 1536 2048 Watchdog in Flash Mode (in ms) b6, b5, b4 b7 000 0 1 48 (def) 256 001 96 512 010 192 1024 011 384 2048 100 768 4096 101 1536 8192 110 3072 16384 111 6144 32768 Forced Wake Up (in ms) b2, b1, b0 b3 000 0 1 48 (def) 64 001 96 128 010 192 258 011 384 512 100 768 1024 101 1536 2048 110 3072 4096 111 6144 8192 33904/5 66 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING WATCHDOG AND MODE REGISTERS Table 24. Watchdog refresh register, W/D MOSI First Byte [15-8] [b_15 b_14] 01_101 [P/N] 01 01_ 101 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 0 0 bit 6 0 0 bit 5 0 0 bit 4 0 0 POR bit 3 0 0 bit 2 0 0 bit 1 0 0 bit 0 0 0 Notes 24. The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the W/D and also to transition from INIT mode to Normal Mode, and from Normal Request Mode to Normal mode (after a wake up of a reset) . Table 25. MODE Register, MODE MOSI First Byte [15-8] [b_15 b_14] 01_110 [P/N] 01 01_ 110 P Default state MOSI Second Byte, bits 7-0 bit 7 Mode[4] N/A bit 6 Mode[3] N/A bit 5 Mode[2] N/A bit 4 Mode[1] N/A bit 3 Mode[0] N/A bit 2 Rnd_b[2] N/A bit 1 Rnd_b[1] N/A bit 0 Rnd_b[0] N/A Low Power Vdd OFF selection and FWU / Cyclic Sense selection b7, b6, b5, b4, b3 0 1100 0 1101 0 1110 0 1111 FWU off off ON ON Cyclic Sense off ON off ON Table 26. Low Power Vdd ON selection and operation mode b7, b6, b5, b4, b3 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111 b2, b1, b0 FWU off off off off off off off off ON ON ON ON ON ON ON ON Cyclic Sense off off off off ON ON ON ON off off off off ON ON ON ON Cyclic INT off off ON ON off off ON ON off off ON ON off off ON ON Watchdog off ON off ON off ON off ON off ON off ON off ON off ON Random Code inverted, these 3bits are the inverted bits obtained from the previous SPI command. 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 67 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Prior to enter in LP Vdd ON or LP Vdd OFF, the wake up flags must be cleared or read. This is done by the following SPI commands: 0xE100 and oxE380 for CAN and I/O wake up respectively. Ref to table “Device Flag, I/O real time and Device Identification” for details. If wake up flags are not cleared, device will enter in selected LP mode but will wake up immediately. When the device is in LP Vdd ON mode, the wake up by SPI command uses a write to “Normal Request Mode”, 0x5C10. Mode Register Features The mode register include specific function and “global SPI command” that allow the following: - read device current mode - read device Debug status - read state of SAFE terminal - leave Debug state - release or turn off SAFE terminal These global commands are built using the MODE register adress bit [13-9], along with several combinations of bit [1514] and bit [7]. Note that bit [8] is always set to 1. The table below summarize these commands Table 27. Device Modes Global commands and effects Read device current Mode, Leave debug mode. Keep SAFE terminal as is. MOSI in hexadecimal: 1D 00 MOSI bits 15-14 00 MISO bits 13-9 01 110 bit 15-8 bit 8 1 bit 7-3 device current mode bit 8 1 bit 7-3 device current mode bit 8 1 bit 7-3 device current mode bit 8 1 bit 7-3 device current mode bit 7 1 bit 2 X bit 7 0 bit 2 X bit 7 1 bit 7 0 bits 6-0 000 0000 bit 2-0 Random code bits 6-0 000 0000 bit 2-0 Random code bits 6-0 000 0000 bit 1 SAFE bits 6-0 000 0000 bit 1 SAFE bit 0 DEBUG bit 0 DEBUG Fix Status Read device current mode Release SAFE terminal (turn OFF). MOSI in hexadecimal: 1D 80 MOSI bits 15-14 00 MISO bits 13-9 01 110 bit 15-8 Fix Status Read device current Mode, Leave debug mode. Keep SAFE terminal as is. MOSI in hexadecimal: DD 00 MISO reports Debug and SAFE state (bits 1,0) MOSI bits 15-14 11 MISO bits 13-9 01 110 bit 15-8 Fix Status Read device current mode, Keep DEBUG mode Release SAFE terminal (turn OFF). MOSI in hexadecimal: DD 80 MISO reports Debug and SAFE state (bits 1,0) MOSI bits 15-14 11 MISO bits 13-9 01 110 bit 15-8 Fix Status Tables below describe the meaning of MISO bits 7-0, that allow to decode the device current mode. Table 28. MISO bits 7-0 Device current mode, any of the above command b7, b6, b5, b4, b3 0 0000 0 0001 0 0010 0 0011 MODE INIT FLASH Normal Request Normal mode Table below describes the SAFE and DEBUG bit decoding. Table 29. SAFE and DEBUG status SAFE and DEBUG bits b1 0 1 b0 0 1 DEBUG mode OFF DEBUG mode Active description SAFE terminal OFF, not activated FLASH 33904/5 68 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING .REGULATOR, CAN, I/O, INT AND LIN REGISTERS Table 30. (25)REGULATOR register, REG MOSI First Byte [15-8] [b_15 b_14] 01_111 [P/N] 01 01_ 111 P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 VAUX[1] 0 POR bit 6 VAUX[0] 0 bit 5 N/A bit 4 5V-can[1] 0 POR bit 3 5V-can[0] 0 bit 2 VDD bal en N/A bit 1 VDD bal auto N/A bit 0 VDD off en N/A Bits b7 b6 00 01 Description VAUX[1], VAUX[0] - Vauxilary regulator control Regulator OFF Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags not reported. VAUX disable in case UV or UV detected after 1.0ms blanking time. Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags active. VAUX disable in case UV or UV detected after 1.0ms blanking time. Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags active. VAUX disable in case UV or UV detected after 25μs blanking time. 5V-can[1], 5V-can[0] - 5V-CAN regulator control Regulator OFF Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags not reported. Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags active. Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags active. 5V-CAN disable in case UV or UV detected after 25μs blanking time. VDD bal en - Control bit to Enable the VDD external ballast transistor External VDD ballast disable External VDD ballast Enable VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typ 60mA Disable the automatic activation of the external ballast Enable the automatic activation of the external ballast, if VDD > typ 60mA VDD off en - Control bit to allow transition into Low Power VDD OFF Mode (to prevent VDD turn OFF) Disable Usage of Low Power VDD OFF Mode Enable Usage of Low Power VDD OFF Mode 10 11 b4 b3 00 01 10 11 b2 0 1 b1 0 1 b0 0 1 Notes 25. The first time the device is set in Normal mode, the CAN is in Sleep wake-up enable (10). The next time the device is set in Normal mode, the CAN state is controlled by the bit 7 and bit6 states. 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 69 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 31. CAN Register, CAN MOSI First byte [15-8] [b_15 b_14] 10_000 [P/N] 01 10_ 000P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 CAN mod[1] 1 note bit 6 CAN mod[0] 0 bit 5 Slew[1] 0 POR bit 4 Slew[0] 0 bit 3 Wake up 1/3 0 POR bit 2 bit 1 bit 0 CAN int 0 POR Bits b7 b6 00 01 10 Description CAN mod[1], CAN mod[0] - CAN interface mode control, wake-up enable / disable CAN interface in Sleep Mode, CAN wake-up disable. CAN interface in receive only mode, CAN driver disable. CAN interface is in Sleep Mode, CAN wake-up enable. In device low power mode, CAN wake-up is reported by device wake-up. In device normal mode, CAN wake-up reported by INT. CAN interface in transmit and receive mode. Slew[1] Slew[0] - CAN driver slew rate selection FAST MEDIUM SLOW SLOW Wake-up 1/3 - Selection of CAN wake-up mechanism 3 dominant pulses wake-up mechanism Single dominant pulse wake-up mechanism CAN INT - Select the CAN failure detection reporting Select INT generation when a bus failure is fully identified and decoded (i.e after 5 dominant pulses on TxCAN) Select INT generation as soon as a bus failure is detected, event if not fully identified 11 b5 b4 00 01 10 11 b3 0 1 b0 0 1 33904/5 70 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 32. I/O Register, I/O MOSI First byte [15-8] [b_15 b_14] 10_001 [P/N] 01 10_ 001P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 I/O-3 [1] 0 bit 6 I/O-3 [0] 0 bit 5 I/O-2 [1] 0 bit 4 I/O-2 [0] 0 POR bit 3 I/O-1 [1] 0 bit 2 I/O-1 [0] 0 bit 1 I/O-0 [1] 0 bit 0 I/O-0 [0] 0 Bits b7 b6 00 01 10 11 b5 b4 00 01 10 11 b3 b2 00 01 10 11 b1 b0 00 01 10 11 Description I/O-3 [1], I/O-3 [0] - I/O-3 terminal operation I/O-3 driver disable, Wake-up capability disable I/O-3 driver disable, Wake-up capability enable. I/O-3 High Side driver enable. I/O-3 High Side driver enable. I/O-2 [1], I/O-2 [0] - I/O-2 terminal operation I/O-2 driver disable, Wake-up capability disable I/O-2 driver disable, Wake-up capability enable. I/O-2 High Side driver enable. I/O-2 High Side driver enable. I/O-1 [1], I/O-1 [0] - I/O-1 terminal operation I/O-1 driver disable, Wake-up capability disable I/O-1 driver disable, Wake-up capability enable. I/O-1 Low Side driver enable. I/O-1 High Side driver enable. I/O-0 [1], I/O-0 [0] - I/O-0 terminal operation I/O-0 driver disable, Wake-up capability disable I/O-0 driver disable, Wake-up capability enable. I/O-0 Low Side driver enable. I/O-0 High Side driver enable. 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 71 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 33. INT Register, INT MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] 01 10_ 010P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 CAN failure 0 bit 6 MCU req 0 bit 5 LIN1 fail 0 bit 4 LIN0fail 0 POR bit 3 I/O 0 bit 2 SAFE 0 bit 1 0 bit 0 Vmon 0 Bits b7 0 1 b6 0 1 b5 0 1 b4 0 1 b3 0 1 b2 0 1 b0 Description CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN over-current, Driver Over Temp, TX-PD, RX-PR, RX2HIGH, and CANBUS Dominate clamp) INT disable INT enable. MCU req - Control bit to request an INT. INT will occur once when the bit is enable INT disable INT enable. not implemented in MC33904 INT disable INT enable. not implemented in MC33904 INT disable INT enable. I/O - Bit to control I/O interruption: I/O Wake-up INT disable INT enable. SAFE - description to be done INT disable INT enable. Vmon - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5V-CAN, VDD (IDD Over-current, VDD_Temp_prewarning), VSUV, VSOV, VSENSElow, 5V-CAN low or thermal shutdown, VAUX low or VAUX over-current INT disable INT enable. 0 1 33904/5 72 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 34. LIN 1 Register, LIN1 MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] 01 10_ 011P Default state Condition for default Bits b7 b6 00 01 10 11 Description MOSI Second Byte, bits 7-0 bit 7 LIN mode[1] 0 bit 6 LIN mode[0] 0 bit 5 Slew rate[1] 0 bit 4 Slew rate[0] 0 POR bit 3 0 bit 2 LIN T1 on 0 bit 1 0 bit 0 Vsup ext 0 LIN mode [1], LIN mode [0] - LIN 1 interface mode control, wake-up enable / disable LIN1 disable, wake-up capability disable not used LIN1 disable, wake-up capability enable LIN1 Transmit Receive mode b5 b4 00 01 10 11 Slew rate[1], Slew rate[0] LIN 1 slew rate selection Slew rate for 20kbit/s baud rate Slew rate for 10kbit/s baud rate Slew rate for fast baud rate Slew rate for fast baud rate b2 0 1 LIN T1 on LIN 1 termination OFF LIN 1 termination ON b0 0 1 Vsup ext LIN goes recessive when device Vsup2 is below typ 6V. This is to meet J2602 specification LIN continues operation below Vsup2 6V, until 5V-CAN is disabled. 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 73 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 35. LIN 2 Register, LIN2 MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] 01 10_ 100P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 LIN mode[1] 0 bit 6 LIN mode[0] 0 bit 5 Slew rate[1] 0 bit 4 Slew rate[0] 0 POR bit 3 0 bit 2 LIN T2 on 0 bit 1 0 bit 0 Vsup ext 0 Bits b7 b6 00 01 10 11 Description LIN mode [1], LIN mode [0] - LIN 2 interface mode control, wake-up enable / disable LIN2 disable, wake-up capability disable not used LIN2 disable, wake-up capability enable LIN2 Transmit Receive mode b5 b4 00 01 10 11 b2 0 1 b0 0 1 Slew rate[1], Slew rate[0] LIN 2slew rate selection Slew rate for 20kbit/s baud rate Slew rate for 10kbit/s baud rate Slew rate for fast baud rate Slew rate for fast baud rate LIN T2 on LIN 2 temination OFF LIN 2 temination ON Vsup ext LIN goes recessive when device Vsup2 is below typ 6V. This is to meet J2602 specification LIN continues operation below Vsup2 6V, until 5V-CAN is disabled. 33904/5 74 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE FLAGS FLAGS DESCRIPTION The table below is the summary of the device flags, I/O real time level and device Identification. They are obtained using the following commands. This command is composed of the following: Table 36. Device Flag, I/O real time and Device Identification Bits 15-14 13-9 8 7 6 5 4 3 2 1 0 bits 15 and 14: [1 1] for failure flags, or [0 0] for I/O real time status or device identification. • bit 13 to 9 are the register address from which the flags is to be read. • bit 8 = 1 (this is not parity bit function, as this is a read command). MOSI bits 15-7 MOSI bits [15, 14] Address bit 8 [13-9] bit 7 Next 6 MOSI bits (bits 6.0) should be “000_0000” MISO REG 8 Bits Device Fixed Status (bits 15...8) 11 0_1111 REG 1 0 MISO bits [7-0], device response on MISO terminal bit 7 VAUX_low bit 6 VAUX_overcurrent bit 5 5V-can_ Thermal shutdown bit 4 5V-can_ UV VDD_ Thermal shutdown bit 3 5V-can_ over-current bit 2 VSENSE_ low RST_low (2ms FWU VSUP2-UV INT service Timeout VSUP1-OV I/O-O thermal Low Power VDD OFF Reset request W/D flash mode 50% Hardware Leave Debug I/O-0-2 wake- SPI wake-up up Hexa SPI commands to get I/O Flags and I/O wake up: MOSI Ox E3 00, and MOSI Ox E3 80 00 1_0001 I/O 1 1 I/O-3 state I/O-2 state I/O-1 state I/O-0 state Hexa SPI commands to get I/O real time level: MOSI Ox 23 00 INT 11 1_0010 Interrupt 1 0 1 INT request RST high DBG resistor VDD temp Prewarning VDD low >100ms VDD UV VDD low RST VDD Overvoltage RST low >100ms VAUX_overvoltage multiple Resets W/D refresh failure Hexa SPI commands to get INT Flags: MOSI Ox E5 00, and MOSI Ox E5 80 00 1_0010 Interrupt 1 1 Vdd (5V or 3.3V) device p/n 1 device p/n 0 id4 id3 id2 id1 id0 Hexa SPI commands to get device Identification: MOSI Ox 25 10 MISO bit [7-0] = 1011 0001: MC33904, 5V version, silicon pass 3.0 MISO bit [7-0] = 1011 0010: MC33904, 5V version, silicon pass 3.1 LIN1 11 1_0011 LIN 1 1 0 LIN1 wake up LIN1 Term short to gnd LIN 1 Over-temp RxD1 low RxD1 high TxD1 dom LIN1 bus dom clamp Hexa SPI commands to get LIN 2 Flags: MOSI Ox E7 00 LIN2 11 1_0100 LIN 2 1 0 LIN2 wake up LIN2 Term short to gnd LIN 2 Over-temp RxD2 low RxD2 high TxD2 dom LIN2 bus dom clamp Hexa SPI commands to get LIN 2 Flags: MOSI Ox E9 00 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 75 SERIAL PERIPHERAL INTERFACE FLAGS Table 37. Flag Descriptions Flag Description Vaux_low Description Set / Reset condition Reports that VAUX regulator output voltage is lower than the VAUX_UV threshold. Set: VAUX below threshold for t >100μs typ. Reset: VAUX above threshold and flag read (SPI) Report that current out of VAUX regulator is above VAUX_OC threshold. Set: Current above threshold for t >100μs. Reset: Current below threshold and flag read by SPI. Report that the 5V-can regulator has reached over temperature threshold. Set: 5V-can thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) Reports that 5V-can regulator output voltage is lower than the 5V-can UV threshold. Set: 5V-can below 5V-can UV for t >100μs typ. Reset: 5V-can > threshold and flag read (SPI) Report that the CAN driver output current is above threshold. Set: 5V-can current above threshold for t>100us. Reset: 5V-can current below threshold and flag read (SPI) Reports that Vsense terminal is lower than the Vsense low threshold. Set: Vsense below threshold for t >100μs typ. Reset: Vsense above threshold and flag read (SPI) Reports that Vsup1 terminal is lower than the Vsup1 low resoled. Set: Vsup1 below threshold for t >100μs typ. Reset: Vsup1 above threshold and flag read (SPI) Report that current out of Vdd pin is higher that Idd-oc threshold, while device is in Normal mode. Set: current above threshold for t>100us typ. Reset; current below threshold and flag read (SPI) Report that the Vdd has reached over temperature threshold, and was turned off. Set: Vdd off due to thermal condition. Reset: Vdd recover and flag read (SPI) Report that the Reset pin has detected a low level, shorter than 100ms Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI) Report that the device voltage at Vsup1 pin was below BATFAIL threshold. Set: Vsup1 below BATFAIL. Reset: Vsup1 above threshold, and flag read (SPI) Report that current out of Vdd pin is higher that Idd-oc threshold LP, while device is in Low Power VDD ON Mode. Set: current above threshold for t>100us typ. Reset; current below threshold and flag read (SPI) Report that wake up source is CAN Set: after CAN wake detected. Reset: Flag read (SPI) Report that the CAN interface has reach over temperature threshold. Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) Report that Rx pin is shorted to gnd. Set: Rx low failure detected. Reset: failure recovered and flag read (SPI) Report that Rx pin is shorted to recessive voltage. Set: Rx high failure detected. Reset: failure recovered and flag read (SPI) Report that Tx pin is shorted to gnd. Set: Tx low failure detected. Reset: failure recovered and flag read (SPI) Report that the CAN bus is dominant for a time longer than tDOM Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI) Vaux_overcurrent 5V-can_ Thermal shutdown 5V-can_ UV 5V-can_ over-current VSENSE_ low VSUP_ Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Under-voltage Set / Reset condition IDD-OCNORMAL mode VDD_ Thermal shutdown RST_low ( VSUPUV thresh and flag read (SPI) Report that VSUP1 is above VSUP1-OV threshold. Set VSUP1 above VSUP1-OV thresh. Reset VSUP1 < VSUPOV thresh and flag read (SPI) Report that the I/O-0 high side switch has reach over temperature threshold. Set: I/O-0 high side switch thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) Report that the W/D period has reach 50% of its value, while device is in Flash mode. Set: W/D period > 50%. Reset: flag read Report that wake up source is I/O-1 or I/O-3 Set: after I/O-1 or I/O-3 wake detected. Reset: Flag read (SPI) Report that wake up source is I/O-0 or I/O-2 Set: after I/O-0 or I/O-2 wake detected. Reset: Flag read (SPI) Report that wake up source is SPI command, in Low Power VDD ON Mode. Set: after SPI Wake Up detected. Reset: Flag read (SPI) CAN_F Description Set / Reset condition CANL to VBAT Description Set / Reset condition CANL to GND Description Set / Reset condition CANL to GND Description Set / Reset condition CANH to VBAT Description Set / Reset condition CANH to GND Description Set / Reset condition CANH to GND Description Set / Reset condition HS3 short to GND HS2 short to GND SPI parity error Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition CSB low >2ms Description Set / Reset condition VSUP2-UV Description Set / Reset condition VSUP1-OV I/O-O thermal Description Set / Reset condition Description Set / Reset condition W/D flash mode 50% I/O-1-3 wakeup I/O-0-2 wakeup SPI wake-up Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 77 SERIAL PERIPHERAL INTERFACE FLAGS Table 37. Flag Descriptions Flag Description FWU Description Set / Reset condition Report that wake up source is Forced Wake Up Set: after Forced Wake Up detected. Reset: Flag read (SPI) Report that INT time out error detected. Set: INT service time out expired. Reset: flag read. Report that Low Power VDD OFF Mode was selected, prior wake up occurred. Set: Low Power VDD OFF selected. Reset: Flag read (SPI) Report that RST source is an request from a SPI command (go to RST mode). Set: After reset occurred due to SPI request. Reset: flag read (SPI) Report that the device left the Debug mode due to Hardware cause (voltage at DBG pin lower than typ 8V). Set: device leave debug mode due to Hardware cause. Reset: flag read. Report that INT source is an INT request from a SPI command. Set: INT occurred. Reset: flag read (SPI) Report that RST pin is shorted to high voltage. Set: RST failure detection. Reset: flag read. Report that the resistor at DBG pin is different from expected (different from SPI register content). Set: failure detected. Reset: correct resistor and flag read (SPI). Report that the Vdd has reached over temperature pre warning threshold. Set: Vdd thermal sensor above threshold. Reset: Vdd thermal sensor below threshold and flag read (SPI) Reports that VDD terminal is lower than the VDDUV threshold. Set: VDD below threshold for t >100μs typ. Reset: VDD above threshold and flag read (SPI) Reports that VDD terminal is higher than the typ Vdd + 0.6V threshold. I/O-1 can be turned OFF if this function is selected in INIT register. Set: VDD above threshold for t >100μs typ. Reset: VDD below threshold and flag read (SPI) Reports that Vaux terminal is higher than the typ Vaux + 0.6V threshold. I/O-1 can be turned OFF if this function is selected in INIT register. Set: Vaux above threshold for t >100μs typ. Reset: Vaux below threshold and flag read (SPI) Reports that VDD terminal is lower than the VDDUV threshold for a time longer than 100ms Set: VDD below threshold for t >100ms typ. Reset: VDD above threshold and flag read (SPI) Report that Vdd is below Vdd undervoltage threshold. Set: Vdd below threshold. Reset: fag read (SPI) Report that the Reset pin has detected a low level, longer than 100ms (Reset permanent low) Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI) Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong W/D refresh. Set: after detection of multiple reset pulses. Reset: flag read (SPI) Report that a wrong or missing W/D failure occurred. Set: failure detected. reset: flag read (SPI) Report that wake up source is LIN1 or LIN2 Set: after LIN1 or LIN 2 wake detected. Reset: Flag read (SPI) Report LIN term 1 or LIN term 2 short to gnd failure Set: failure detected. Reset failure recovered and flag read (SPI) INT service Timeout Low Power VDD OFF Reset request Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Hardware Leave Debug Description Set / Reset condition INT request Description Set / Reset condition RST high Description Set / Reset condition DBG resistor Description Set / Reset condition VDD temp Prewarning Description Set / Reset condition Description Set / Reset condition VDD UV VDD Overvoltage Description Set / Reset condition VAUX_overvoltage Description Set / Reset condition VDD low >100ms VDD low Description Set / Reset condition Description Set / Reset condition RST low >100ms multiple Resets W/D refresh failure LIN1/2 wake up LIN1/2 Term short to gnd Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition Description Set / Reset condition 33904/5 78 Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE FLAGS Table 37. Flag Descriptions Flag Description LIN 1 Over-temp RxD1 low Description Set / Reset condition Description Set / Reset condition Report that the LIN1 or LIN 2 interface has reach over temperature threshold. Set: LIN1 /LIN2 thermal sensor above threshold. Reset: sensor below threshold and flag read (SPI) Report that RxD1 / RxD2 pin is shorted to gnd. Set: Rx low failure detected. Reset: failure recovered and flag read (SPI) Report that RxD1 / RxD2 pin is shorted to recessive voltage. Set: Rx high failure detected. Reset: failure recovered and flag read (SPI) Report that TxD1 / RxD2 pin is shorted to gnd. Set: Tx low failure detected. Reset: failure recovered and flag read (SPI) Report that the LIN1 / LIN2 bus is dominant for a time longer than tDOM Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI) RxD1 high Description Set / Reset condition TxD1 dom Description Set / Reset condition LIN1 bus dom clamp Description Set / Reset condition FIX AND EXTENDED DEVICE STATUS For every SPi command the device response on MISO is a fix status information. This information is either: two bytes Fix Status + Extended Status: when a device write command is used (MOSI bits 15-14, bits C1 C0 = 01) Table 38. status bits description Bits MOSI 15 INT 14 WU 13 RST 12 CAN-G 11 LIN-G 10 I/O-G 9 8 one byte Fix Status: when a device read operation is performed (MOSI bits 15-14, bits C1 C0 = 00 or 11). 7 CANBUS 6 CANLOC 5 LIN1 4 LIN0 3 I/O-1 2 I/O-0 1 0 SAFE-G VREGG VREG-1 VREG0 Bits INT WU RST CAN-G I/O-G SAFE-G VREG-G CAN-LOC CAN-BUS I/O-1 I/I-0 VREG-1 VREG-0 Description Indicate that an INT has occurred and that INT flags are pending to be read. Indicate that an Wake Up has occurred and that Wake Up flags are pending to be read. Indicate that an Reset has occurred and that the flags that report the Reset source are pending to be read. The INT, or WU or RST source is CAN interface. CAN local or CAN bus source. The INT, or WU or RST source is I/O interfaces. The INT, or WU or RST source is from a SAFE condition The INT, or WU or RST source is from a Regulator event, or voltage monitoring event The INT, or WU or RST source is CAN interface. CAN local source. The INT, or WU or RST source is CAN interface. CAN bus source. The INT, or WU or RST source is I/O interface, flag from I/O sub adress Low (bit 7 =0) The INT, or WU or RST source is I/O interface, flag from I/O sub adress High (bit 7 =1) The INT, or WU or RST source is from a Regulator event, flag from REG register sub adress high (bit 7 =1) The INT, or WU or RST source is from a Regulator event, flag from REG register sub adress low (bit 7 =0) 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 79 TYPICAL APPLICATIONS TYPICAL APPLICATIONS * = Optional Q2 2.2uF VBAUX VCAUX VAUX VSUP2 VE Q1* RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr 100nF >1uF VSUP1 DBG VB VDD >4.7uF RST INT MUX MOSI SCLK MISO CS TXD RXD TXDL1 RXDL1 TXDL2 RXDL2 4.7k * VDD RST INT A/D VBAT 1k 22k 5V-CAN VSENSE I/O-0 100nF 100nF VSUP MCU SPI I/O-1 CANH 60 SPLIT CAN BUS VSUP1/2 1.0 k LIN BUS 1 option 1 option 2 CAN LIN1 60 4.7nF CANL LIN TERM1 LIN2 1.0 k LIN1 VSUP1/2 1.0 k LIN BUS 1 option 1 option 2 LIN TERM2 1.0 k LIN2 GND SAFE VSUP VSUP Safe Circuitry Notes 26. Cap > 10uF required to pass EMC requirement according to “OEM_HW_Requirement-For CAN_LIN_FR-interface_V10_20081210” or newer Figure 36. 33905D Typical Application Schematic 33904/5 80 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS * = Optional Q2 2.2uF VBAUX VCAUX VAUX VSUP2 100nF >1uF VSUP1 DBG Q1* VE VB RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr VDD >4.7uF RST INT MUX MOSI SCLK MISO CS TXD RXD TXDL1 RXDL1 4.7k * VDD RST INT A/D VBAT 1k 22k 5V-CAN VSENSE 100nF I/O-0 100nF I/O-1 VSUP MCU SPI VSUP I/O-3 CANH 60 SPLIT 60 CAN BUS 4.7nF CANL LIN TERM1 1.0 k LIN BUS 1 option 1 option 2 CAN LIN1 VSUP1/2 1.0 k LIN1 GND SAFE VSUP VSUP Safe Circuitry Notes 27. Cap > 10uF required to pass EMC requirement according to “OEM_HW_Requirement-For CAN_LIN_FR-interface_V10_20081210” or newer Figure 37. 33905S Typical Application Schematic 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 81 TYPICAL APPLICATIONS * = Optional Q2 2.2uF VBAUX VCAUX VAUX VE VSUP2 VB VDD Q1* RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr 100nF VSUP1 DBG 5V-CAN VSENSE I/O-0 VDD >4.7uF RST INT A/D 4.7k * SPI VBAT 1k 22k >1uF RST INT MUX MOSI SCLK MISO CS TXD RXD 100nF VSUP 1k 100nF MCU I/O-1 VBAT 22k VSUP 1k I/O-2 100nF I/O-3 CANH 60 60 CAN BUS 4.7nF SPLIT CANL GND CAN SAFE VSUP VSUP OR function Safe Circuitry Notes 28. Cap > 10uF required to pass EMC requirement according to “OEM_HW_Requirement-For CAN_LIN_FR-interface_V10_20081210” or newer Figure 38. 33904A Typical Application Schematic 33904/5 82 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS The following figure illustrates the application case where 2 reverse battery diodes can be used for optimization of the filtering and buffering capacitor at the VDD pin. This allows using a minimum value capacitor at the VDD pin to guarantee reset free operation of the MCU during the Q2 5 V/3.3 V VBAT D1 VBAUX VCAUX VSUP2 VSUP1 VAUX cranking pulse, and temporary (50 ms) loss of the VBAT supply. Applications without an external ballast on VDD and without using the VAUX regulator are illustrated as well. VBAT D2 C2 Q2 5 V/3.3 V VBAUX VCAUX VAUX VSUP2 VSUP1 Q1 VE VB VDD D1 C1 Q1 VE VB VDD Partial View ex1: Single VSUP Supply Partial View ex2: Split VSUP Supply Optimized solution for cranking pulses. C1 is sized for MCU power supply buffer only. Q2 5 V/3.3 V VBAT D1 VBAUX VCAUX VAUX VSUP2 VSUP1 VE VB VDD VBAT D1 VBAUX VCAUX VAUX VSUP2 VSUP1 VE VB VDD Partial View ex 3: No External Transistor, VDD ~100 mA Capability delivered by internal path transistor. Partial View ex 4: No External Transistor - No VAUX Figure 39. Application Options 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 83 PACKAGING SOIC 32 PACKAGE DIMENSIONS PACKAGING SOIC 32 PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D 33904/5 84 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 85 PACKAGING SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D 33904/5 86 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOIC 54 PACKAGE DIMENSIONS SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 87 PACKAGING SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D 33904/5 88 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D 33904/5 Analog Integrated Circuit Device Data Freescale Semiconductor 89 REVISION HISTORY REVISION HISTORY REVISION 1.0 2.0 DATE 11/2009 1/2010 DESCRIPTION OF CHANGES • • • • • • • • Initial Release Updated LIN 2.0 to LIN 2.1 throughout document Changed Pin VC to VE Changed Pin VBASE to VB Added note to Simplified Application and Typical Application drawings for Q1 to be optional. Updated Parameters Tables.; Timing accuracy added, CAN wake and CANL/CANH input current. Changed default setting of: INIT Reg register, bit7, I/Ox sync - INIT W/D register, bit 6 MCU_OC and bit 1 W/D N/Win Re-arranged the order of the devices. 3.0 2/2010 33904/5 90 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. All rights reserved. MC33904_5 Rev. 3.0 2/2010