33910

MC33910G5AC/MC3433910G5AC Freescale Semiconductor Advance Information Document Number: MC33910 Rev. 8.0, 3/2010 LIN System Basis Chip with High Side Drivers The 33910G5/BAC is a Serial Peripheral Interface (SPI) controlled System Basis Chip (SBC), combining many frequently used functions in an MCU based system, plus a Local Interconnect Network (LIN) transceiver. The 33910 has a 5.0 V, 50 mA/60 mA low dropout regulator with full protection and reporting features. The device provides full SPI readable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN Protocol Specification 2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry that can be disabled for higher data rates. Two 50 mA/60 mA high side switches with optional pulse-width modulated (PWM) are implemented to drive small loads. One high voltage input is available for use in contact monitoring, or as external wake-up input. This input can be used as high voltage Analog Input. The voltage on this pin is divided by a selectable ratio and available via an analog multiplexer. The 33910 has three main operating modes: Normal (all functions available), Sleep (VDD off, wake-up via LIN, wake-up inputs (L1), cyclic sense and forced wake-up), and Stop (VDD on with limited current capability, wake-up via CS, LIN bus, wake-up inputs, cyclic sense, forced wake-up and external reset). The 33910 is compatible with LIN Protocol Specification 2.0, 2.1, and SAEJ2602-2. Features • • • • • • Full-duplex SPI interface at frequencies up to 4.0 MHz LIN transceiver capable of up to 100 kbps with wave shaping Two 50 mA/60 mA high side switches One high voltage analog/logic Input Configurable window watchdog 5.0 V low drop regulator with fault detection and low voltage reset (LVR) circuitry • Switched/protected 5.0 V output (used for Hall sensors) • Pb-free packaging designated by suffix code AC 33910 VBAT VS1 VS2 VSENSE HS1 L1 33910 SYSTEM BASIS CHIP WITH LIN 2ND GENERATION AC SUFFIX (Pb-FREE) 98ASH70029A 32-PIN LQFP ORDERING INFORMATION Device MC33910G5AC/R2 MC34910G5AC/R2 MC33910BAC/R2 MC34910BAC/R2 Temperature Range (TA) - 40°C to 125°C -40°C to 85°C - 40°C to 125°C -40°C to 85°C 32-LQFP Package * See Page 2 for Device Variations VDD PWMIN ADOUT0 LIN LIN INTERFACE MCU MOSI MISO SCLK CS RXD TXD IRQ RST LGND PGND AGND HVDD HS2 WDCONF Figure 1. 33910 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2009 - 2010. All rights reserved. MC33910G5AC/MC3433910G5AC DEVICE VARIATIONS DEVICE VARIATIONS The 33910G5 data sheet is within MC33910G5 Product Specifications Pages 3 to 46 Table 1. This specification support the following products Device MC33910G5AC/R2 Temperature Generation Changes 1. Increase ESD GUN IEC61000-4-2 (gun test contact with 150 pF, 330 W test conditions) performance to achieve ±6.0 kV min on the LIN pin. 2. Immunity against ISO7637 pulse 3b 3. Reduce EMC emission level on LIN MC34910G5AC/R2 MC33910BAC/R2 MC34910BAC/R2 - 40 to 85°C - 40 to 125°C - 40 to 85°C 2.5 2.0 2.0 4. Improve EMC immunity against RF – target new specification including 3x68 pF 5. Comply with J2602 conformance test Initial release The 33910BAC data sheet is within MC33911BAC Product Specifications Pages 47 to 86 - 40 to 125°C 2.5 33910 2 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC MC33910G5 PRODUCT SPECIFICATIONS PAGES 3 TO 46 MC33910G5 PRODUCT SPECIFICATIONS PAGES 3 TO 46 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 3 MC33910G5AC/MC3433910G5AC INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM RST IRQ VS2 VS1 VDD INTERNAL BUS INTERRUPT CONTROL MODULE LVI, HVI, ALL OT (VDD, HS, LIN, SD) AGND VOLTAGE REGULATOR PGND RESET CONTROL MODULE LVR, WD, EXT µC 5.0 V OUTPUT MODULE HVDD WINDOW WATCHDOG MODULE PWMIN VS2 HIGH SIDE CONTROL MODULE HS1 VS2 MISO MOSI SCLK CS ADOUT0 HS2 SPI & CONTROL ANALOG MULTIPLEXER VBAT SENSE MODULE CHIP TEMPERATURE SENSE MODULE ANALOG INPUT MODULE L1 VSENSE WAKE-UP MODULE RXD TXD DIGITAL INPUT MODULE LIN PHYSICAL LAYER LIN LGND WDCONF Figure 2. 33910 Simplified Internal Block Diagram 33910 4 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC PIN CONNECTIONS PIN CONNECTIONS AGND HVDD VDD VSENSE VS1 NC* VS2 26 HS1 25 29 31 30 RXD TXD MISO MOSI SCLK CS ADOUT0 PWMIN 1 2 3 4 5 6 7 8 * See Recommendation in Table below 27 32 28 24 23 22 21 20 19 18 17 HS2 L1 NC* NC* NC* NC* PGND NC* 10 IRQ 11 12 13 14 15 16 RST NC* WDCONF LGND LIN NC* Figure 3. 33910 Pin Connections Table 2. 33910 Pin Definitions A functional description of each pin can be found in the Functional Pin Description. Pin 1 2 3 4 5 6 7 8 9 10 11 Pin Name RXD TXD MISO MOSI SCLK CS ADOUT0 PWMIN RST IRQ NC Formal Name Receiver Output Transmitter Input SPI Output SPI Input SPI Clock SPI Chip Select Analog Output Pin 0 PWM Input Internal Reset I/O Internal Interrupt Output Not Connected Definition This pin is the receiver output of the LIN interface which reports the state of the bus voltage to the MCU interface. This pin is the transmitter input of the LIN interface which controls the state of the bus output. SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the high-impedance state. SPI (Serial Peripheral Interface) data input. SPI (Serial Peripheral Interface) clock Input. SPI (Serial Peripheral Interface) chip select input pin. CS is active low. Analog Multiplexer Output. High Side Pulse Width Modulation Input. Bidirectional Reset I/O pin - driven low when any internal reset source is asserted. RST is active low. Interrupt output pin, indicating wake-up events from Stop modemode or events from Normal and Normal request modes. IRQ is active low. This pin must not be connected. NC* 9 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 5 MC33910G5AC/MC3433910G5AC PIN CONNECTIONS Table 2. 33910 Pin Definitions A functional description of each pin can be found in the Functional Pin Description. Pin 12 13 14 15, 16, 17, 19, 20, 21 & 22 18 23 24 25 26 27 28 29 30 31 32 Pin Name WDCONF LIN LGND NC PGND L1 HS2 HS1 VS2 VS1 NC VSENSE HVDD VDD AGND Formal Name Watchdog Configuration Pin LIN Bus LIN Ground Pin Not Connected Power Ground Pin Wake-up Input High Side Outputs Definition This input pin is for configuration of the watchdog period and allows the disabling of the watchdog. This pin represents the single-wire bus transmitter and receiver. This pin is the device LIN ground connection. It is internally connected to the PGND pin. This pin must not be connected or connected to ground. This pin is the device low side ground connection. It is internally connected to the LGND pin. This pin is the wake-up capable digital input(1). In addition, L1 input can be sensed analog via the analog multiplexer. High side switch outputs. These pins are device battery level power supply pins. VS2 is supplying the HSx drivers while VS1 supplies the remaining blocks.(2) This pin can be left opening or connected to any potential ground or power supply Battery voltage sense input.(3) +5.0 V switchable supply output pin.(4) +5.0 V main voltage regulator output pin.(5) This pin is the device analog ground connection. Power Supply Pin Not Connected Voltage Sense Pin Hall Sensor Supply Output Voltage Regulator Output Analog Ground Pin Notes 1. When used as digital input, a series 33 kΩ resistor must be used to protect against automotive transients. 2. Reverse battery protection series diodes must be used externally to protect the internal circuitry. 3. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery connections. It is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes. 4. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required. 5. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10 Ω) required. 33910 6 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Supply Voltage at VS1 and VS2 Normal Operation (DC) Transient Conditions (load dump) Supply Voltage at VDD Input / Output Pins Voltage Interrupt Pin (IRQ)(7) HS1 and HS2 Pin Voltage (DC) L1 Pin Voltage Normal Operation with a series 33k resistor (DC) Transient input voltage with external component (according to ISO7637-2) (See Figure ) VSENSE Pin Voltage (DC) LIN Pin Voltage Normal Operation (DC) Transient input voltage with external component (according to ISO7637-2) (See Figure ) VDD Output Current VBUSDC VBUSTR IVDD -18 to 40 -150 to 100 Internally Limited A VL1DC VL1TR VVSENSE -18 to 40 ±100 -27 to 40 V V (6) Symbol Value Unit V VSUP(SS) VSUP(PK) VDD VIN VIN(IRQ) VHS -0.3 to 27 -0.3 to 40 -0.3 to 5.5 -0.3 to VDD +0.3 -0.3 to 11 - 0.3 to VSUP +0.3 V V V V CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD, HVDD Notes 6. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device. 7. Extended voltage range for programming purpose only. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 7 MC33910G5AC/MC3433910G5AC ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ESD Capability AECQ100 Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 Ω) LIN Pin L1 all other Pins Charge Device Model - JESD22/C101 (CZAP = 4.0 pF) Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32) All other Pins (Pins 2-7, 10-15, 18-23, 26-31) According to LIN Conformance Test Specification / LIN EMC Test Specification, August 2004 (CZAP = 150 pF, RZAP = 330 Ω) Contact Discharge, Unpowered LIN pin with 220 pF LIN pin without capacitor VS1/VS2 (100 nF to ground) L1 input (33 kΩ serial resistor) According to IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 Ω) Unpowered LIN pin with 220 pF and without capacitor VS1/VS2 (100 nF to ground) L1 input (33 kΩ serial resistor) THERMAL RATINGS Operating Ambient Temperature (8) 33910 34910 Operating Junction Temperature Storage Temperature Thermal Resistance, Junction to Ambient Natural Convection, Single Layer board (1s)(8), (9) Natural Convection, Four Layer board (2s2p)(8), (10) Thermal Resistance, Junction to Case(11) Peak Package Reflow Temperature During Reflow(12), (13) Notes 8. 9. 10. 11. 12. 13. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. RθJC TPPRT TJ TSTG RθJA 85 56 23 Note 13 °C/W °C TA -40 to 125 -40 to 85 -40 to 150 -55 to 150 °C °C °C/W °C VESD4-1 VESD4-2 VESD4-3 ± 8000 ± 8000 ± 8000 VESD3-1 VESD3-2 VESD3-3 VESD3-4 ± 20k ± 11k >± 12k ±6000 VESD2-1 VESD2-2 ± 750 ± 500 VESD1-1 VESD1-2 VESD1-3 ± 8.0k ± 6.0k ±2000 Symbol Value Unit V 33910 8 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic SUPPLY VOLTAGE RANGE (VS1, VS2) Nominal Operating Voltage Functional Operating Voltage(14) Load Dump SUPPLY CURRENT RANGE (VSUP = 13.5 V) Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State(15) Stop Mode, VDD ON with IOUT = 100 µA, LIN Recessive State (17) (18) , 5.5 V < VSUP < 12 V VSUP = 13.5 V 13.5 V < VSUP < 18 V Sleep Mode, VDD OFF, LIN Recessive State(15), (17) 5.5 V < VSUP < 12 V VSUP = 13.5 V 13.5 V ≤ VSUP < 18 V Cyclic Sense Supply Current Adder(19) SUPPLY UNDER/OVER-VOLTAGE DETECTIONS Power-On Reset (BATFAIL)(20) Threshold (measured on VS1)(19) Hysteresis (measured on VS1)(19) VSUP under-voltage detection (VSUV Flag) (Normal and Normal Request Modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) VSUP over-voltage detection (VSOV Flag) (Normal and Normal Request Modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) VSOV_HYS VSOV 18 – 19.25 1.0 20.5 – VSUV_HYS VSUV 5.55 – 6.0 0.2 6.6 – VBATFAIL VBATFAIL_HYS 1.5 – 3.0 0.9 3.9 – V ICYCLIC ISLEEP – – – – 27 33 160 10 35 48 300 – µA (15), (16), Symbol Min Typ Max Unit VSUP VSUPOP VSUPLD 5.5 – – – – – 18 27 40 V V V IRUN ISTOP – 4.5 10 mA µA – – – 47 62 180 80 90 400 µA V V Notes 14. Device is fully functional. All features are operating. 15. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled. 16. 17. 18. 19. 20. Total IDD current (including loads) below 100 µA. Stop and Sleep modes current will increase if VSUP exceeds13.5 V. This parameter is guaranteed after 90 ms. This parameter is guaranteed by process monitoring but not production tested. The Flag is set during power up sequence. To clear the flag, a SPI read must be performed. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 9 MC33910G5AC/MC3433910G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic VOLTAGE REGULATOR (21) Symbol Min Typ Max Unit (VDD) VDDRUN 4.75 IVDDRUN VDDDROP – VDDSTOP 4.75 IVDDSTOP LRRUN LRSTOP 6.0 5.0 13 5.25 36 mA mV – – – – 25 25 mV LDRUN LDSTOP TPRE 90 TPRE_HYS TSD TSD_HYS – 150 – 115 13 170 13 140 – 190 – °C °C °C – – – – 80 50 °C 0.1 0.25 V 60 5.00 110 5.25 200 mA V V Normal Mode Output Voltage 1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V Normal Mode Output Current Limitation Dropout Voltage(22) IVDD = 50 mA Stop Mode Output Voltage IVDD < 5.0 mA Stop Mode Output Current Limitation Line Regulation Normal mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA Stop mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA Load Regulation Normal mode, 1.0 mA < IVDD < 50 mA Stop mode, 0.1 mA < IVDD < 5.0 mA Over-temperature Prewarning (Junction)(23) Interrupt generated, VDDOT Bit Set Over-temperature Prewarning Hysteresis(23) Over-temperature Shutdown Temperature Over-temperature Shutdown Hysteresis (Junction)(23) (23) HALL SENSOR SUPPLY OUTPUT(24) (HVDD) VDD Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100% IHVDD = 15 mA Current Limitation Dropout Voltage IHVDD = 15 mA; IVDD = 5.0 mA Line Regulation IHVDD = 5.0 mA; IVDD = 5.0 mA Load Regulation 1.0 mA > IHVDD > 15 mA; IVDD = 5.0 mA Notes 21. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω. 22. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V). 23. This parameter is guaranteed by process monitoring but not production tested. 24. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω. LDHVDD – – 20 LRHVDD – – 40 mV IHVDD HVDDDROP – 160 300 mV HVDDACC -2.0 20 – 35 2.0 50 mA mV % 33910 10 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic RST INPUT/OUTPUT PIN (RST) VDD Low Voltage Reset Threshold Low-state Output Voltage IOUT = 1.5 mA; 3.5 V ≤ VSUP ≤ 27 V High-state Output Current (0 V < VOUT < 3.5 V) Pull-down Current Limitation (internally limited) VOUT = VDD Low-state Input Voltage High-state Input Voltage MISO SPI OUTPUT PIN (MISO) Low-state Output Voltage IOUT = 1.5 mA High-state Output Voltage IOUT = -250 µA Tri-state Leakage Current 0 V ≤ VMISO ≤ VDD SPI INPUT PINS (MOSI, SCLK, CS) Low-state Input Voltage High-state Input Voltage MOSI, SCLK Input Current 0 V ≤ VIN ≤ VDD CS Pull-up Current 0 V < VIN < 3.5 V INTERRUPT OUTPUT PIN (IRQ) Low-state Output Voltage IOUT = 1.5 mA High-state Output Voltage IOUT = -250 µA Leakage Current VDD ≤ VOUT ≤ 10 V PULSE WIDTH MODULATION INPUT PIN (PWMIN) Low-state Input Voltage High-state Input Voltage Pull-up current 0 V < VIN < 3.5 V VIL VIH IPUPWMIN 10 20 30 -0.3 0.7 x VDD – – 0.3 x VDD VDD +0.3 V V µA IOUT – – 2.0 VOH VDD -0.8 – VDD mA VOL 0.0 – 0.8 V V IPUCS 10 20 30 VIL VIH IIN -10 – 10 µA -0.3 0.7 x VDD – – 0.3 x VDD VDD +0.3 V V µA ITRIMISO -10 – 10 VOH VDD -0.9 – VDD µA VOL 0.0 – 1.0 V V VIL VIH IOH IPD_MAX 1.5 -0.3 0.7 x VDD – – – 8.0 0.3 x VDD VDD +0.3 V V VRSTTH VOL 0.0 -150 – -250 0.9 -350 µA mA 4.3 4.5 4.7 V V Symbol Min Typ Max Unit 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 11 MC33910G5AC/MC3433910G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic HIGH SIDE OUTPUTS HS1 AND HS2 PINS (HS1, HS2) Output Drain-to-Source On Resistance TJ = 25°C, ILOAD = 50 mA; VSUP > 9.0 V TJ = 150°C, ILOAD = 50 mA; VSUP > 9.0 V(25) TJ = 150°C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(25) Output Current Limitation(26) 0 V < VOUT < VSUP - 2.0 V Open Load Current Detection(27) Leakage Current -0.2 V < VHSX < VS2 + 0.2 V Short-circuit Detection Threshold(28) 5.5 V < VSUP < 27 V Over-temperature Shutdown(29), (30) Hysteresis(30) THSSD THSSD_HYS VTHSC VSUP -2.0 140 – – 160 10 – 180 – °C °C IOLHSX ILEAK – – 10 V ILIMHSX 60 – 90 5.0 250 7.5 mA µA RDS(ON) – – – – – – 7.0 10 14 mA Ω Symbol Min Typ Max Unit Over-temperature Shutdown L1 INPUT PIN (L1) Low Detection Threshold(31) 5.5 V < VSUP < 27 V High Detection Threshold(31) 5.5 V < VSUP < 27 V Hysteresis(31) 5.5 V < VSUP < 27 V Input Current(32) VTHL 2.0 VTHH 3.0 VHYS 0.4 IIN -10 RL1IN RATIOL1 0.95 3.42 VRATIOL1OFFSET V 2.5 3.0 V 3.5 4.0 V 0.8 1.4 µA – 1300 10 2000 kΩ -0.2 V < VIN < VS1 Analog Input Impedance(33) Analog Input Divider Ratio (RATIOL1 = VL1 / VADOUT0) L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 Analog Output offset Ratio L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 Analog Inputs Matching L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 L1MATCHING 800 1.0 3.6 1.05 3.78 mV -80 -22 6.0 2.0 80 22 % 96 96 100 100 104 104 Notes 25. This parameter is production tested up to TA = 125°C, and guaranteed by process monitoring up to TJ = 150°C. 26. 27. 28. 29. 30. 31. 32. 33. 33910 When over-current occurs, the corresponding high side stays ON with limited current capability and the HSxCL flag is set in the HSSR. When open load occurs, the flag (HSxOP) is set in the HSSR. HS automatically shutdown if HSOT occurs or if the HVSE flag is enabled and an over-voltage occurs. When over-temperature shutdown occurs, both high sides are turned off. All flags in HSSR are set. Guaranteed by characterization but not production tested If L1 pin is unused it must be connected to ground. Analog multiplexer input disconnected from L1 input pin. Analog multiplexer input connected to L1 input pin. 12 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy)(35) ANALOG MULTIPLEXER Temperature Sense Analog Output Voltage TA = -40°C TA = 25°C TA = 125°C Temperature Sense Analog Output Voltage per characterization TA = 25°C Internal Chip Temperature Sense Gain Internal Chip Temperature Sense Gain per characterization at 3 temperatures(36) See Figure 16, Temperature Sense Gain VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0) 5.5 V < VSUP < 27 V VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization(36) 5.5 150 ms) with VSUV = 0. When in Reset mode, a VDD under-voltage condition with no VSUP under-voltage (VSUV = 0) will send the device to Sleep mode. All blocks are in their lowest power consumption condition. Only some wake-up sources (wake-up input with or without cyclic sense, forced wake-up and LIN receiver) are active. The 5.0 V regulator is OFF. The internal low-power oscillator may be active if the IC is configured for cyclic-sense. In this condition, one of the high side switches is turned on periodically and the wake-up input is sampled. Wake-up from Sleep mode is similar to a power-up. The device goes in Reset mode except that the SPI will report the wake-up source and the BATFAIL flag is not set. RESET MODE The 33910 enters the Reset mode after a power up. In this mode, the RST pin is low for 1.0 ms (typical value). After this delay, it enters the Normal Request mode and the RST pin is driven high. The Reset mode is entered if a reset condition occurs (VDD low, watchdog trigger fail, after wake-up from Sleep mode, Normal Request mode timeout occurs). NORMAL REQUEST MODE This is a temporary mode automatically accessed by the device after the Reset mode, or after a wake-up from Stop mode. In Normal Request mode, the VDD regulator is ON, the RESET pin is High, and the LIN is operating in RX Only mode. As soon as the device enters in the Normal Request mode an internal timer is started for 150 ms (typical value). During these 150 ms, the MCU must configure the Timing Control Register (TIMCR) and the Mode Control Register (MCR) with MOD2 and MOD1 bits set = 0, to enter the Normal mode. If within the 150 ms timeout, the MCU does not command the 33910 to Normal mode, it will enter in Reset mode. If the WDCONF pin is grounded in order to disable the watchdog function, it goes directly in Normal mode after the Reset mode. STOP MODE The Stop mode is the second low power mode, but in this case the 5.0 V regulator is ON with limited current drive capability. The application MCU is always supplied while the 33910 is operating in Stop mode. The device can enter into Stop mode only by sending the SPI command. When the application is in this mode, it can wake-up from the 33910 side (for example: cyclic sense, force wake-up, LIN bus, wake inputs) or the MCU side (CS, RST pins). Wake-up from Stop mode will transition the 33910 to Normal Request mode and generates an interrupt except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin. NORMAL MODE In Normal mode, all 33910 functions are active and can be controlled by the SPI interface and the PWMIN pin. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 27 MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Normal Request Timeout Expired(NRTOUT) ) Normal Request timeout expired (t NRTOUT VDD Low VDD Low VDD High and Power Down Power Up Reset Reset Delay (t RST) Expired VDD High and Reset Delay (tRST) expired Normal Request WDdisabled WD Disabled WD Trigger WD trigger VDDLLow V ow DD WD Failed WD failed VDDLLOW (>t NRTOUT) Expired VDD ow (>NRTOUT) expired and VSUV = 0 and VSUV = 0 Normal Stop Command STOP Command Sleep Command SLEEP Command Wake-up (Reset) Wake-Up (Reset) Sleep Stop VDD Low VDD L ow Legend WD: Watchdog Notes: WD Disabled: Watchdog disabled (WDCONF pin connected to GND) WD - means Watchdog WD Trigger: Watchdog is triggered by SPI command WD Failed:WD disabled - trigger or trigger occurs in closed window No watchdog means Watchdog disabled (WDCONF terminal connected to GND) WD trigger command sent via is triggered by SPI command Stop Command: Stop – means Watchdog SPI WD failed – means no Watchdog trigger or trigger occurs in closed window Sleep Command: Sleep command sent via SPI STOP Command - means STOP LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up. Wake-up from Stop mode: L1 state change, command sent via SPI SLEEP Command state change, LIN bus wake-up, via SPI Wake-up from Sleep mode: L1 - means SLEEP command send Periodic wake-up. Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge Figure 14. Operating Modes and Transitions 33910 28 Analog Integrated Circuit Device Data Freescale Semiconductor Wake-upInterrupt Wake-Up (Interrupt) MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Table 6. Operating Modes Overview Function VDD HVDD HSx Analog Mux L1 LIN Watchdog Voltage Monitoring Notes 58. 59. 60. 61. 62. Reset Mode Full VSUP/VDD Normal Request Mode Full SPI(58) SPI/PWM(59) SPI Input Rx-Only 150 ms (typ.) timeout VSUP/VDD Normal Mode Full SPI SPI/PWM SPI Input Full/Rx-Only On(62)/Off VSUP/VDD Stop Mode Stop Note(60) Wake-up Rx-Only/Wake-up VDD Sleep Mode Note(61) Wake-up Wake-up - Operation can be enabled/controlled by the SPI. Operation can be controlled by the PWMIN input. HSx switches can be configured for cyclic sense operation in Stop mode. HSx switches can be configured for cyclic sense operation in Sleep mode. Windowing operation when enabled by an external resistor. INTERRUPTS Interrupts are used to signal a microcontroller that a peripheral needs to be serviced. The interrupts which can be generated, change according to the operating mode. While in Normal and Normal Request modes, the 33910 signals through interrupts special conditions which may require a MCU software action. Interrupts are not generated until all pending wake-up sources are read in the Interrupt Source Register (ISR). While in Stop mode, interrupts are used to signal wake-up events. Sleep mode does not use interrupts. Wake-up is performed by powering-up the MCU. In Normal and Normal Request mode the wake-up source can be read by SPI. The interrupts are signaled to the MCU by a low logic level of the IRQ pin, which will remain low until the interrupt is acknowledged by a SPI read command of the ISR register. The IRQ pin will then be driven high. Interrupts are only asserted while in Normal, Normal Request and Stop mode. Interrupts are not generated while the RST pin is low. The following is a list of the interrupt sources in Normal and Normal Request modes. Some of these can be masked by writing to the SPI - Interrupt Mask Register (IMR). Low-voltage Interrupt: Signals when the supply line (VS1) voltage drops below the VSUV threshold (VSUV). High-voltage Interrupt: Signals when the supply line (VS1) voltage increases above the VSOV threshold (VSOV). Over-temperature Prewarning: Signals when the 33910 temperature has reached the preshutdown warning threshold. It is used to warn the MCU that an over-temperature shutdown in the main 5.0 V regulator is imminent. LIN Over-temperature Shutdown / TXD Stuck At Dominant / RXD Short-circuit: These signal fault conditions within the LIN interface will cause the LIN driver to be disabled. In order to restart the operation, the fault must be removed and TXD must go recessive. High Side Over-temperature Shutdown: Signals a shutdown in the high side outputs. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 29 MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES RESET To reset a MCU the 33910 drives the RST pin low for the time the reset condition lasts. After the reset source is removed, the state machine will drive the RST output low for at least 1.0 ms (typical value) before driving it high. In the 33910, four main reset sources exist: 5.0 V Regulator Low-voltage-Reset (VRSTTH) The 5.0 V regulator output VDD is continuously monitored against brown outs. If the supply monitor detects that the voltage at the VDD pin has dropped below the reset threshold VRSTTH the 33910 will issue a reset. In case of overtemperature, the voltage regulator will be disabled and the voltage monitoring will issue a VDDOT Flag independently of the VDD voltage. Window Watchdog Overflow If the watchdog counter is not properly serviced while its window is open, the 33910 will detect an MCU software runaway and will reset the microcontroller. Wake-up From Sleep Mode During Sleep mode, the 5.0 V regulator is not active, hence all wake-up requests from Sleep mode require a power-up/reset sequence. External Reset The 33910 has a bidirectional reset pin which drives the device to a safe state (same as Reset mode) for as long as this pin is held low. The RST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality is also active in Stop mode. After the RST pin is released, there is no extra t RST to be considered. In order to select and activate direct wake-up from L1 input, the Wake-up Control Register (WUCR) must be configured with appropriate L1WE input enabled or disabled. The wake-up input’s state is read through the Wake-up Status Register (WUSR). L1 input is also used to perform cyclic-sense wake-up. Note: Selecting an L1 input in the analog multiplexer before entering low power mode will disable the wake-up capability of the L1 input Wake-up from Wake-up input (L1) with cyclic sense timer enabled The SBCLIN can wake-up at the end of a cyclic sense period if on the wake-up input line (L1) a state change occurs. One or both HSx switch can be activated in Sleep or Stop modes from an internal timer. Cyclic sense and force wakeup are exclusive. If cyclic sense is enabled, the force wakeup can not be enabled. In order to select and activate the cyclic sense wake-up from the L1 input, before entering in low power modes (Stop or Sleep modes), the following SPI set-up has to be performed: In WUCR: select the L1 input to WU-enable. In HSCR: enable the desired HSx. • In TIMCR: select the CS/WD bit and determine the cyclic sense period with CYSTx bits. • Perform Goto Sleep/Stop command. Forced Wake-up The 33910 can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and Forced wake-up are exclusive. If Forced wake-up is enabled, the Cyclic Sense can not be enabled. To determine the wake-up period, the following SPI set-up has to be sent before entering in low power modes: • In TIMCR: select the CS/WD bit and determine the low power mode period with CYSTx bits. • In HSCR: all HSx bits must be disabled. CS Wake-up While in Stop mode, a rising edge on the CS will cause a wake-up. The CS wake-up does not generate an interrupt, and is not reported on SPI. LIN Wake-up While in the low-power mode, the 33910 monitors the activity on the LIN bus. A dominant pulse larger than t PROPWL followed by a dominant to recessive transition will cause a LIN wake-up. This behavior protects the system from a short to ground bus condition. The bit RXONLY = 1 from LINCR Register disables the LIN wake-up from Stop mode. WAKE-UP CAPABILITIES Once entered into one of the low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal mode operation. In Stop mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep mode the wake-up is performed by activating the 5.0 V regulator and resetting the MCU. In both cases the MCU can detect the wake-up source by accessing the SPI registers and reading the Interrupt Source Register. There is no specific SPI register bit to signal a CS wake-up or external reset. If necessary this condition is detected by excluding all other possible wake-up sources. Wake-up from Wake-up input (L1) with cyclic sense disabled The wake-up line is dedicated to sense state changes of external switch and wake-up the MCU (in Sleep or Stop mode). 33910 30 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES RST Wake-up While in Stop mode, the 33910 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. Then, the 33910 will change to Normal Request or Normal modes depending on the WDCONF pin configuration. The RST wake-up does not generate an interrupt and is not reported via SPI. From Stop mode, the following wake-up events can be configured: • Wake-up from L1 input without cyclic sense • Cyclic sense wake-up inputs • Force wake-up • CS wake-up • LIN wake-up • RST wake-up From Sleep mode, the following wake-up events can be configured: • Wake-up from L1 input without cyclic sense • Cyclic sense wake-up inputs • Force wake-up • LIN wake-up WINDOW CLOSED NO WATCHDOG CLEAR ALLOWED WINDOW OPEN FOR WATCHDOG CLEAR WD TIMING X 50% WD TIMING X 50% WD PERIOD (tPWD) WD TIMING SELECTED BY RESISTOR ON WDCONF PIN WINDOW WATCHDOG The 33910 includes a configurable window watchdog which is active in Normal mode. The watchdog can be configured by an external resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears are performed by writing through the SPI in the MOD bits of the Mode Control Register (MCR). During the first half of the SPI timeout, watchdog clears are not allowed, but after the first half of the SPI timeout window, the clear operation opens. If a clear operation is performed outside the window, the 33910 will reset the MCU, in the same way as when the watchdog overflows. Figure 15. Window Watchdog Operation To disable the watchdog function in Normal mode the user must connect the WDCONF pin to ground. This measure effectively disables Normal Request mode. The WDOFF bit in the Watchdog Status Register (WDSR) will be set. This condition is only detected during Reset mode. If neither a resistor nor a connection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150 ms (typ.) and signals the faulty condition through the Watchdog Status Register (WDSR). The watchdog timebase can be further divided by a prescaler which can be configured by the Timing Control Register (TIMCR). During Normal Request mode, the window watchdog is not active but there is a 150 ms (typ.) timeout for leaving the Normal Request mode. In case of a timeout, the 33910 will enter into Reset mode, resetting the microcontroller before entering again into Normal Request mode. FAULTS DETECTION MANAGEMENT The 33910 has the capability to detect faults like an over or under-voltage on VS1, TxD in permanent Dominant State, Over-temperature on HS, LIN. It is able to take corrective actions accordingly. Most of faults are monitoring through SPI and the Interrupt pin. The microcontroller can also take actions. The following table summarizes all fault sources the device is able to detect with associated conditions. The status for a device recovery and the SPI or pins monitoring are also described. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 31 MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Table 7. Fault Detection Management Conditions MONITORING(64) BLOCK FAULT MODE CONDITION FALLOUT RECOVERY REG (FLAG, BIT) VSR (BATFAIL, 0) INTERRUPT IRQ low + ISR (0101)(65) IRQ low + ISR (0101) IRQ low + ISR (0101) - BATTERY FAIL VSUP OVERVOLTAGE VSUP UNDERVOLTAGE VDD UNDERVOLTAGE VDD OVER-TEMP PREWARNING VDD OVERTEMPERATURE RXD PIN SHORT CIRCUIT LIN TXD PIN PERMANENT DOMINANT LIN DRIVER OVERTEMPERATURE HIGH SIDE DRIVERS OVERTEMPERATURE HS1 OPEN-LOAD DETECTION High Side HS2 OPEN-LOAD DETECTION HS1 OVERCURRENT HS2 OVERCURRENT All modes VSUP 19.25 V (typ) In Normal mode, HS shutdown if bit HVSE=1 (reg MCR) Reset (63) Condition gone Condition gone, to re-enable HS write to HSCR registers VSR (VSOV,3) Normal, Normal Request VSUP < 6.0 V (typ) All except Sleep VDD < 4.5 V (typ) Temperature > 115°C (typ) Temperature > 170°C (typ) RXD pin shorted to GND or 5 V Normal, Normal Request TXD pin low for more than 1s (typ) Temperature > 160°C (typ) Temperature > 160°C (typ) VSR (VSUV,2) Power Supply Condition gone VDD shutdown, Reset then Sleep LIN trans shutdown LIN transmitter reenabled once the condition is gone and TXD is high VSR (VDDOT,1) All except Low Power modes LINSR, (RXSHORT,3) LINSR (TXDOM,2) LIN transmitter shutdown IRQ low + ISR (0100)(65) LINSR (LINOT,1) Condition gone, to re-enable HS write to HSCR reg Both HS thermal shutdown All flags in HSSR are set IRQ low + ISR (0010) (65) HSSR (HS1OP,1) Normal, Normal Request Current through HSx < 5.0 mA (typ) HSSR (HS2OP,3) Condition gone Current through HSx tends to rise above the current limit 60 mA (min) The MCU did not command the device to Normal mode within the 150 ms timeout after reset WD timeout or WD clear within the window closed WDCONF pin is floating HSx on with limited current capability 60 mA (min) HSSR (HS1CL,0) - HSSR (HS2CL,2) NORMAL REQUEST TIME-OUT EXPIRED Normal Request Reset - - Watchdog WATCHDOG TIMEOUT Reset WD internal lower precision timebase 150 ms (typ) Connect WDCONF to a resistor or to GND WDSR (WDTO, 3) Normal WATCHDOG ERROR Notes 63. 64. 65. Normal WDSR (WDERR, 2) When in Reset mode a VDD under-voltage condition combined with no VSUP under-voltage (VSUV=0) will send the device to Sleep mode. Registers to be read when back in Normal Request or Normal mode depending on the fault. Interrupts only generated in Normal, Normal Request and Stop modes Unless masked, If masked IRQ remains high and the ISR flags are not set. 33910 32 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES TEMPERATURE SENSE GAIN The analog multiplexer can be configured via SPI to allow the ADOUT0 pin to deliver the internal junction temperature of the device. The graph below illustrates the internal chip temp sense obtained per characterization at 3 temperatures with 3 different lots and 30 samples. Temperature Sense Analog Output Voltage 5 4.5 4 Vadout0 (V) 3.5 3 2.5 2 -50 0 50 Temperature (°C) Figure 16. Temperature Sense Gain 100 150 HIGH SIDE OUTPUT PINS HS1 AND HS2 These outputs are two high side drivers intended to drive small resistive loads or LEDs incorporating the following features: • PWM capability (software maskable) • Open load detection • Current limitation • Over-temperature shutdown (with maskable interrupt) • High-voltage shutdown (software maskable) • Cyclic sense The high side switches are controlled by the bits HS1:2 in the High Side Control Register (HSCR). PWM Capability (direct access) Each high side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits HS1 and PWMHS1 are set in the High Side Control Register (HSCR), then the HS1 driver is turned on if the PWMIN pin is high and turned of if the PWMIN pin is low. This applies to HS2 configuring HS2 and PWMHS2 bits. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 33 MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES HVSE Interrupt Control Module High Voltage Shutdown High-Side Interrupt VDD VDD PWMIN PWMHSx VS2 MOD1:2 HSx HSxOP HSxCL on/off High Side Driver charge pump open load detection current limitation over-temperture shutdown (interrupt maskable) high voltage shutdown (maskable) HSx Control Status Wakeup Module Cyclic Sense Figure 17. High Side Drivers HS1 and HS2 Open Load Detection Each high side driver signals an open load condition if the current through the high side is below the open load current threshold. The open load condition is indicated with the bits HS1OP and HS2OP in the High Side Status Register (HSSR). Current Limitation Each high side driver has an output current limitation. In combination with the over-temperature shutdown the highside drivers are protected against over-current and shortcircuit failures. When the driver operates in the current limitation area, it is indicated with the bits HS1CL and HS2CL in the HSSR. Note: If the driver is operating in current limitation mode, excessive power might be dissipated. Over-temperature Protection (HS Interrupt) Both high side drivers are protected against overtemperature. In case of an over-temperature condition both high side drivers are shut down and the event is latched in the Interrupt Control Module. The shutdown is indicated as HS Interrupt in the Interrupt Source Register (ISR). A thermal shutdown of the high side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously. If the bit HSM is set in the Interrupt Mask Register (IMR), then an interrupt (IRQ) is generated. A write to the High Side Control Register (HSCR), when the over-temperature condition is gone, will re-enable the high side drivers. High-voltage Shutdown In case of a high voltage condition and if the high voltage shutdown is enabled (bit HVSE in the Mode Control Register (MCR) is set both high side drivers are shut down. A write to the High Side Control Register (HSCR), when the high voltage condition is gone, will re-enable the high side drivers. Sleep And Stop Mode The high side drivers can be enabled to operate in Sleep and Stop mode for cyclic sensing. Also see Table 6, Operating Modes Overview. LIN PHYSICAL LAYER The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification and has the following features: • LIN physical layer 2.0, 2.1 and SAEJ2602 compliant • Slew rate selection • Over-temperature shutdown • Advanced diagnostics The LIN driver is a low side MOSFET with thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are 33910 34 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed. LIN Pin The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. WAKE-UP MODULE LIN Wake-up MOD1:2 LSR0:1 J2602 RXONLY RXSHORT TXDOM LINOT VS1 LIN DRIVER Slope and Slew Rate Control Over-temperature Shutdown (interrupt maskable) 30 K LIN TXD SLOPE CONTROL WAKE-UP FILTER RXD RECEIVER LGND Figure 18. LIN Interface Slew Rate Selection The slew rate can be selected for optimized operation at 10.4 and 20 kBit/s as well as a fast baud rate for test and programming. The slew rate can be adapted with the bits LSR1:0 in the LIN Control Register (LINCR). The initial slew rate is optimized for 20 kBit/s. J2602 Conformance To be compliant with the SAE J2602-2 specification, the J2602 feature has to be enabled in the LINCR Register (bit DIS_J2602 sets to 0). The LIN transmitter is disabled in case of a VSUP under-voltage condition occurs and TXD is in Recessive State: the LIN bus goes in Recessive State and RXD goes high. The LIN transmitter is not disabled if TXD is in Dominant State. A deglitcher on VSUP (tJ2602_DEG) is implemented to avoid false switching. If the (DIS_J2602) bit is set to 1, the J2602 feature is disabled and the communication TXD-LIN-RXD works for VSUP down to 4.6 V (typical value) and then the communication is interrupted. The (DIS_J2602) bit is set per default to 0. Over-temperature Shutdown (LIN Interrupt) The output low side FET is protected against overtemperature conditions. In case of an over-temperature condition, the transmitter will be shut down and the LINOT bit in the LIN Status Register (LINSR) is set. If the LINM bit is set in the Interrupt Mask Register (IMR), an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone and TXD is high. RXD Short-circuit Detection (LIN Interrupt) The LIN transceiver has a short-circuit detection for the RXD output pin. If the device transmits and in case of a shortcircuit condition, either 5.0 V or Ground, the RXSHORT bit in 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 35 MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES the LIN Status Register (LINSR) is set and the transmitter is shut down. If the LINM bit is set in the Interrupt Mask Register (IMR), an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone (transition on RXD) and TXD is high. A read of the LIN Status Register (LINSR) without the RXD pin short-circuit condition will clear the bit RXSHORT. TXD Dominant Detection (LIN Interrupt) The LIN transceiver monitors the TXD input pin to detect a stuck in dominant (0 V) condition. In case of a stuck condition (TXD pin 0 V for more than 1 second (typ.)), the transmitter is shut down and the TXDOM bit in the LIN Status Register (LINSR) is set. If the LINM bit is set in the IMR, an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once TXD is high. A read of the LIN Status Register (LINSR) with the TXD pin at 5.0 V will clear the bit TXDOM. LIN Receiver Operation Only While in Normal mode, the activation of the RXONLY bit disables the LIN TXD driver. In case of a LIN error condition, this bit is automatically set. If Stop mode is selected with this bit set, the LIN wake-up functionality is disabled and the RXD pin will reflect the state of the LIN bus. STOP Mode And Wake-up Feature During Stop mode operation, the transmitter of the physical layer is disabled. The receiver is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than TPROPWL followed by a rising edge will generate a wake-up interrupt, and will be reported in the Interrupt Source Register (ISR). Also see Figure 11. SLEEP Mode And Wake-up Feature During Sleep mode operation, the transmitter of the physical layer is disabled. The receiver must be active to detect wake-up events on the LIN bus line. A dominant level longer than TPROPWL followed by a rising edge will generate a system wake-up (Reset), and will be reported in the Interrupt Source Register (ISR). Also see Figure 10. 33910 36 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS 33910 SPI INTERFACE AND CONFIGURATION The serial peripheral interface creates the communication link between a microcontroller (master) and the 33910. The interface consists of four pins (see Figure 19): • CS — Chip Select • MOSI — Master-out Slave-in • MISO — Master-in Slave-out • SCLK— Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0) and the slave replies with 4 system status bits (VMS,LINS,HSS,n.d.) + 4 bits of status information (S3:S0). CS Register Write Data MOSI A3 A2 A1 A0 C3 C2 C1 C0 Register Read Data MISO VMS LINS HSS S3 S2 S1 S0 SCLK Read Data Latch Write Data Latch Rising: 33910 changes MISO/ MCU changes MOSI Falling: 33910 samples MOSI/ MCU samples MISO Figure 19. SPI Protocol During the inactive phase of the CS (HIGH), the new data The rising edge of the Chip Select CS indicates the end of transfer is prepared. the transfer and latches the write data (MOSI) into the register. The CS high forces MISO to the high-impedance The falling edge of the CS indicates the start of a new data state. transfer and puts the MISO in the low-impedance state and Register reset values are described along with the reset latches the analog status data (Register read data). condition. Reset condition is the condition causing the bit to With the rising edge of the SPI clock (SCLK), the data is be set to its reset value. The main reset conditions are: moved to MISO/MOSI pins. With the falling edge of the SPI - Power-On Reset (POR): the level at which the logic is clock (SCLK), the data is sampled by the receiver. reset and BATFAIL flag sets. The data transfer is only valid if exactly 8 sample clock - Reset mode edges are present during the active (low) phase of CS. - Reset done by the RST pin (ext_reset) 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 37 MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS SPI REGISTER OVERVIEW Table 8. System Status Register Adress(A3:A0) $0 - $F Register Name / Read / Write Information SYSSR - System Status Register R BIT 7 VMS 6 LINS 5 HSS 4 - Table 9 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R. Table 9. SPI Register Overview Adress(A3:A0) Register Name / Read / Write Information MCR - Mode Control Register VSR - Voltage Status Register VSR - Voltage Status Register WUCR - Wake-up Control Register WUSR - Wake-up Status Register WUSR - Wake-up Status Register LINCR - LIN Control Register LINSR - LIN Status Register LINSR - LIN Status Register HSCR - High Side Control Register HSSR - High Side Status Register HSSR - High Side Status Register TIMCR - Timing Control Register WDSR - Watchdog Status Register $B $C $D $E $F WDSR - Watchdog Status Register AMUXCR - Analog Multiplexer Control Register CFR - Configuration Register IMR - Interrupt Mask Register ISR - Interrupt Source Register ISR - Interrupt Source Register W R R W R R W R R W R R W R R W W W R R BIT 3 HVSE VSOV VSOV 0 DIS_J2602 RXSHORT RXSHORT PWMHS2 HS2OP HS2OP CS/WD WDTO WDTO L1DS HVDD HSM ISR3 ISR3 2 0 VSUV VSUV 0 RXONLY TXDOM TXDOM PWMHS1 HS2CL HS2CL WD2 CYST2 WDERR WDERR MX2 CYSX8 0 ISR2 ISR2 1 MOD2 VDDOT VDDOT 0 LSR1 LINOT LINOT HS2 HS1OP HS1OP WD1 CYST1 WDOFF WDOFF MX1 0 LINM ISR1 ISR1 0 MOD1 BATFAIL BATFAIL L1WE L1 L1 LSR0 0 0 HS1 HS1CL HS1CL WD0 CYST0 WDWO WDWO MX0 0 VMM ISR0 ISR0 $0 $1 $2 $3 $4 $5 $6 $7 $A 33910 38 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS REGISTER DEFINITIONS System Status Register - SYSSR The System Status Register (SYSSR) is always transferred with every SPI transmission and gives a quick system status overview. It summarizes the status of the Voltage Monitor Status (VMS), LIN Status (LINS) and High Side Status (HSS). Table 10. System Status Register S7 Read VMS HS1CL HS1OP HS2CL HS2OP HSS Figure 22. High Side Status Mode Control Register - MCR S6 LINS S5 HSS S4 - The Mode Control Register (MCR) allows switching between the operation modes and to configure the 33910. Writing the MCR will return the VSR. Table 11. Mode Control Register - $0 C3 Write Reset Value Reset Condition HVSE 1 VMS - Voltage Monitor Status This read-only bit indicates that one or more bits in the VSR are set. 1 = Voltage Monitor bit set 0 = None C2 0 0 C1 MOD2 - C0 MOD1 - BATFAIL VDDOT VSUV VSOV Figure 20. Voltage Monitor Status LINS - LIN Status This read-only bit indicates that one or more bits in the LINSR are set. 1 = LIN Status bit set 0 = None VMS POR POR - - HVSE - High-Voltage Shutdown Enable This write-only bit enables/disables automatic shutdown of the high side drivers during a high-voltage VSOV condition. 1 = automatic shutdown enabled 0 = automatic shutdown disabled MOD2, MOD1 - Mode Control Bits These write-only bits select the operating mode and allow clearing the watchdog in accordance with Table 8, Mode Control Bits. Table 12. Mode Control Bits MOD2 MOD1 0 1 0 1 Description Normal Mode Stop Mode Sleep Mode Normal Mode + Watchdog Clear 0 LINOT TXDOM RXSHORT Figure 21. LIN Status HSS - High Side Switch Status This read-only bit indicates that one or more bits in the HSSR are set. 1 = High Side Status bit set 0 = None LINS 0 1 1 Voltage Status Register - VSR Returns the status of the several voltage monitors. This register is also returned when writing to the Mode Control Register (MCR). Table 13. Voltage Status Register - $0/$1 S3 Read VSOV S2 VSUV S1 VDDOT S0 BATFAIL 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 39 MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS VSOV - VSUP Over-voltage This read-only bit indicates an over-voltage condition on the VS1 pin. 1 = Over-voltage condition. 0 = Normal condition. VSUV - VSUP Under-voltage This read-only bit indicates an under-voltage condition on the VS1 pin. 1 = Under-voltage condition. 0 = Normal condition. VDDOT - Main Voltage Regulator Over-temperature Warning This read-only bit indicates that the main voltage regulator temperature reached the Over-temperature Prewarning Threshold. 1 = Over-temperature Prewarning 0 = Normal BATFAIL - Battery Fail Flag. This read-only bit is set during power-up and indicates that the 33910 had a Power-On-Reset (POR). Any access to the MCR or VSR will clear the BATFAIL flag. 1 = POR Reset has occurred 0 = POR Reset has not occurred Wake-up Control Register - WUCR This register is used to control the digital wake-up input. Writing the WUCR will return the Wake-Up Status Register (WUSR). Table 14. Wake-up Control Register - $2 C3 Write Reset Value Reset Condition 0 1 C2 0 1 C1 0 1 C0 L1WE 1 POR, Reset mode or ext_reset L1WE - Wake-up Input Enable This write-only bit enables/disables the L1 input. In Stop and Sleep mode the L1WE bit activates the L1 input for wakeup. If the L1 input is selected on the analog multiplexer, the L1WE is masked to 0. 1 = Wake-up Input enabled. 0 = Wake-up Input disabled. Wake-up Status Register - WUSR This register is used to monitor the digital wake-up input and is also returned when writing to the WUCR. Table 15. Wake-up Status Register - $2/$3 S3 Read - S2 - S1 - S0 L1 L1 - Wake-up input 1 This read-only bit indicates the status of the L1 input. If the L1 input is not enabled, then the Wake-up status will return 0. After a wake-up from Stop or Sleep mode this bit also allows to verify the L1 input has caused the wake-up, by first reading the Interrupt Status Register (ISR) and then reading the WUSR. The source of the wake-up is only reported on the first WUCR or WUSR access. 1 = L1 pin high, or L1 is the source of the wake-up. 0 = L1 pin low, disabled or selected as an analog input. 33910 40 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS LIN Control Register - LINCR This register controls the LIN physical interface block. Writing the LIN Control Register (LINCR) returns the LIN Status Register (LINSR). Table 16. LIN Control Register - $4 C3 Write Reset Value DIS_J2602 0 Table 17. LIN Slew Rate Control LSR1 0 0 1 1 LSR0 0 1 0 1 Description Normal Slew Rate (up to 20 kb/s) Slow Slew Rate (up to 10 kb/s) Fast Slew Rate (up to 100 kb/s) Reserved C2 RXONLY 0 POR, Reset mode, ext_reset or LIN failure gone* C1 LSR1 0 C0 LSR0 0 LIN Status Register - LINSR This register returns the status of the LIN physical interface block and is also returned when writing to the LINCR. Table 18. LIN Status Register - $4/$5 S3 Read RXSHORT Reset Condition POR POR * LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set, the flag resets automatically when the failure is gone. S2 TXDOM S1 LINOT S0 0 J2602 - LIN Dominant Voltage Select This write-only bit controls the J2602 circuitry. If the circuitry is enabled (bit sets to 0), the TXD-LIN-RXD communication works down to the battery under-voltage condition is detected. Below, the bus is in recessive state. If the circuitry is disabled (bit sets to 1), the communication TXD-LIN-RXD works down to 4.6 V (typical value). 0 = Enabled J2602 feature. 1 = Disabled J2602 feature. RXONLY - LIN Receiver Operation Only This write-only bit controls the behavior of the LIN transmitter. In Normal mode, the activation of the RXONLY bit disables the LIN transmitter. In case of a LIN error condition, this bit is automatically set. In Stop mode this bit disables the LIN wake-up functionality, and the RXD pin will reflect the state of the LIN bus. 1 = only LIN receiver active (Normal mode) or LIN wakeup disabled (Stop mode). 0 = LIN fully enabled. LSRx - LIN Slew-Rate This write-only bit controls the LIN driver slew-rate in accordance with Table 18. RXSHORT - RXD Pin Short-circuit This read-only bit indicates a short-circuit condition on the RXD pin (shorted either to 5.0 V or to Ground). The shortcircuit delay must be a worst case of 8.0 µs to be detected and to shut down the driver. To clear this bit, it must be read after the condition is gone (transition detected on RXD pin). The LIN driver is automatically re-enabled once the condition is gone and TXD is high. 1 = RXD short-circuit condition. 0 = None. TXDOM - TXD Permanent Dominant This read-only bit signals the detection of a TXD pin stuck at dominant (Ground) condition and the resultant shutdown in the LIN transmitter. This condition is detected after the TXD pin remains in dominant state for more than 1 second (typical value). To clear this bit, it must be read after TXD has gone high. The LIN driver is automatically re-enabled once TXD goes High. 1 = TXD stuck at dominant fault detected. 0 = None. LINOT - LIN Driver Over-temperature This read-only bit signals that the LIN transceiver was shutdown due to over-temperature. The transmitter is automatically re-enabled after the over-temperature condition is gone and TXD is high. The LINOT bit is cleared after SPI read once the condition is gone. 1 = LIN over-temperature shutdown 0 = None 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 41 MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS High Side Control Register - HSCR This register controls the operation of the high side drivers. Writing to this register returns the High Side Status Register (HSSR). Table 19. High Side Control Register - $6 C3 Write Reset Value Reset Condition PWMHS2 0 0 = Normal Timing Control Register - TIMCR This register allows to configure the watchdog, the cyclic sense and Forced Wake-up periods. Writing to the Timing Control Register (TIMCR) will also return the Watchdog Status Register (WDSR). Table 21. Timing Control Register - $A C3 C2 WD2 C2 PWMHS1 0 C1 HS2 0 C0 HS1 0 C1 WD1 CYST1 0 C0 WD0 CYST0 0 POR POR, Reset mode, ext_reset, HSx over-temp or (VSOV & HVSE) Write CS/WD CYST2 PWMHSx - PWM Input Control Enable. This write-only bit enables/disables the PWMIN input pin to control the respective high side switch. The corresponding high side switch must be enabled (HSx bit). 1 = PWMIN input controls HSx output. 0 = HSx is controlled only by SPI. HSx - HSx Switch Control. This write-only bit enables/disables the corresponding high side switch. 1 = HSx switch on. 0 = HSx switch off. High Side Status Register - HSSR This register returns the status of the high side switches and is also returned when writing to the HSCR. Table 20. High Side Status Register - $6/$7 S3 Read HS2OP Reset Value Reset Condition - 0 - POR CS/WD - Cyclic Sense or Watchdog prescaler select This write-only bit selects which prescaler is being written to, the Cyclic Sense/Forced Wake-up prescaler or the Watchdog prescaler. 1 = Cyclic Sense/Forced Wake-up Prescaler selected 0 = Watchdog Prescaler select WDx - Watchdog Prescaler This write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with Table 22. This configuration is valid only if windowing watchdog is active. Table 22. Watchdog Prescaler WD2 0 0 0 0 1 1 1 1 WD1 0 0 1 1 0 0 1 1 WD0 0 1 0 1 0 1 0 1 Prescaler Divider 1 2 4 6 8 10 12 14 S2 HS2CL S1 HS1OP S0 HS1CL High Side thermal shutdown A thermal shutdown of the high side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously. HSxOP - High Side Switch Open-Load Detection This read-only bit signals that the high side switches are conducting current below a certain threshold indicating possible load disconnection. 1 = HSx Open Load detected (or thermal shutdown) 0 = Normal HSxCL - High Side Current Limitation This read-only bit indicates that the respective high side switch is operating in current limitation mode. 1 = HSx in current limitation (or thermal shutdown) CYSTx - Cyclic Sense Period Prescaler Select This write-only bits selects the interval for the wake-up cyclic sensing together with the bit CYSX8 in the Configuration Register (CFR) (see page 44). This option is only active if one of the high side switches is enabled when entering in Stop or Sleep mode. Otherwise, a timed wake-up is performed after the period shown in Table 23. 33910 42 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS Table 23. Cyclic Sense and Force Wake-up Interval CYSX8(66) X 0 0 0 0 0 0 0 1 1 1 1 1 1 1 CYST2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 CYST1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 CYST0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 Interval No cyclic sense(67) 20 ms 40 ms 60 ms 80 ms 100 ms 120 ms 140 ms 160 ms 320 ms 480 ms 640 ms 800 ms 960 ms 1120 ms timeouts are disabled and the device automatically enters Normal mode out of Reset. This might be necessary for software debugging and for programming the Flash memory. 1 = Watchdog is disabled 0 = Watchdog is enabled WDWO - Watchdog Window Open This read-only bit signals when the watchdog window is open for clears. The purpose of this bit is for testing. Should be ignored in case WDERR is High. 1 = Watchdog window open 0 = Watchdog window closed Analog Multiplexer Control Register - MUXCR This register controls the analog multiplexer and selects the divider ration for the L1 input divider. Table 25. Analog Multiplexer Control Register -$C C3 Write Reset Value Reset Condition L1DS 1 C2 MX2 0 C1 MX1 0 C0 MX0 0 Notes 66. bit CYSX8 is located in Configuration Register (CFR) 67. No Cyclic Sense and no Force Wake-up available. Watchdog Status Register - WDSR This register returns the Watchdog status information and is also returned when writing to the TIMCR. Table 24. Watchdog Status Register - $A/$B S3 Read WDTO POR POR, Reset mode or ext_reset L1DS - L1 Analog Input Divider Select This write-only bit selects the resistor divider for the L1 analog input. Voltage is internally clamped to VDD. 0 = L1 Analog divider: 1 1 = L1 Analog divider: 3.6 (typ.) MXx - Analog Multiplexer Input Select These write-only bits selects which analog input is multiplexed to the ADOUT0 pin according to Table 26. When disabled or when in Stop or Sleep mode, the output buffer is not powered and the ADOUT0 output is left floating to achieve lower current consumption. Table 26. Analog Multiplexer Channel Select MX2 0 0 0 0 1 1 1 1 MX1 0 0 1 1 0 0 1 1 MX0 0 1 0 1 0 1 0 1 Meaning Disabled Reserved Die Temperature Sensor VSENSE input L1 input Reserved Reserved Reserved S2 WDERR S1 WDOFF S0 WDWO WDTO - Watchdog Timeout This read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the Watchdog within the window closed. Any access to this register or the Timing Control Register (TIMCR) will clear the WDTO bit. 1 = Last reset caused by watchdog timeout 0 = None WDERR - Watchdog Error This read-only bit signals the detection of a missing watchdog resistor. In this condition the watchdog is using the internal, lower precision timebase. The Windowing function is disabled. 1 = WDCONF pin resistor missing 0 = WDCONF pin resistor not floating WDOFF - Watchdog Off This read-only bit signals that the watchdog pin connected to Ground and therefore disabled. In this case watchdog 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 43 MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS Configuration Register - CFR This register controls the Hall Sensor Supply enable/ disable and the cyclic sense timing multiplier. Table 27. Configuration Register - $D C3 Write Reset Value Reset Condition HVDD 0 POR, Reset mode or ext_reset HSM - High Side Interrupt Mask This write-only bit enables/disables interrupts generated in the high side block. 1 = HS Interrupts Enabled 0 = HS Interrupts Disabled LINM - LIN Interrupts Mask C2 CYSX8 0 C1 0 0 C0 0 0 POR POR POR This write-only bit enables/disables interrupts generated in the LIN block. 1 = LIN Interrupts Enabled 0 = LIN Interrupts Disabled VMM - Voltage Monitor Interrupt Mask This write-only bit enables/disables interrupts generated in the Voltage Monitor block. The only maskable interrupt in the Voltage Monitor Block is the VSUP over-voltage interrupt. 1 = Interrupts Enabled 0 = Interrupts Disabled Interrupt Source Register - ISR This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges the interrupt and leads IRQ pin to high, in case there are no other pending interrupts. If there are pending interrupts, IRQ will be driven high for 10µs and then be driven low again. This register is also returned when writing to the Interrupt Mask Register (IMR). Table 29. Interrupt Source Register - $E/$F S3 Read ISR3 HVDD - Hall Sensor Supply Enable This write-only bit enables/disables the state of the hall sensor supply. 1 = HVDD on 0 = HVDD off CYSX8 - Cyclic Sense Timing x 8. This write-only bit influences the cyclic sense and Forced Wake-up period as shown in Table 23. 1 = Multiplier enabled 0 = None Interrupt Mask Register - IMR This register allows masking of some of the interrupt sources. No interrupt will be generated to the MCU and no flag will be set in the ISR register. The 5.0V Regulator overtemperature prewarning interrupt and Under-voltage (VSUV) interrupts can not be masked and will always cause an interrupt. Writing to the IMR will return the ISR. Table 28. Interrupt Mask Register - $E C3 Write Reset Value Reset Condition HSM 1 S2 ISR2 S1 ISR1 S0 ISR0 ISRx - Interrupt Source Register C2 0 1 C1 LINM 1 C0 VMM 1 These read-only bits indicate the interrupt source following Table 30. If no interrupt is pending then all bits are 0. In case more than one interrupt is pending, the interrupt sources are handled sequentially multiplex. POR 33910 44 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910G5AC/MC3433910G5AC FUNCTIONAL DEVICE OPERATIONS Table 30. Interrupt Sources Interrupt Source ISR3 ISR2 ISR1 ISR0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 none maskable no interrupt L1 Wake-up from Stop and Sleep mode LIN Wake-up Voltage Monitor Interrupt (Low Voltage and VDD over-temperature) Forced Wake-up maskable no interrupt HS Interrupt (Over-temperature) Reserved LIN Interrupt (RXSHORT, TXDOM, LIN OT) Voltage Monitor Interrupt (High Voltage) lowest none highest Priority 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 45 MC33910G5AC/MC3433910G5AC TYPICAL APPLICATION TYPICAL APPLICATION The 33910 can be configured in several applications. The figure below shows the 33910 in the typical Slave Node Application. V D1 BAT VS1 VS2 C2 C1 VDD Interrupt Control Module LVI, HVI, HTI, OCI C4 C3 IRQ Internal Bus Voltage Regulator C5 AGND 5V Output Module HVDD Hall Sensor Supply VDD IRQ RST Reset Control Module LVR, HVR, HTR, WD, RST TIMER PWMIN Window Watchdog Module High Side Control Module R1 HS1 HS2 MISO MOSI SPI SCLK CS SPI & CONTROL Chip Temp Sense Module Analog Multiplexer VBAT Sense Module VSENSE MCU L1 Analog Input Module R2 A/D ADOUT0 Wake Up Module Digital Input Module RXD SCI TXD C6 LIN Physical Layer LIN LIN A/D WDCONF R7 PGND AGND LGND Typical Component Values: C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 220 pF R1 = 10 kΩ; R2 = 20 kΩ-200 kΩ Recommended Configuration of the not Connected Pins (NC): Pin 15, 16, 17, 19, 20, 21, 22 = GND Pin 11 = open (floating) Pin 28 = this pin is not internally connected and may be used for PCB routing optimization. 33910 46 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC MC33911BAC PRODUCT SPECIFICATIONS PAGES 47 TO 86 MC33911BAC PRODUCT SPECIFICATIONS PAGES 47 TO 86 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 47 MC33910G5AC/MC3433910G5AC INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM RST IRQ VS2 VS1 VDD INTERNAL BUS INTERRUPT CONTROL MODULE LVI, HVI, HTI, OCI AGND VOLTAGE REGULATOR PGND RESET CONTROL MODULE LVR, HVR, HTR, WD 5V OUTPUT MODULE HVDD WINDOW WATCHDOG MODULE PWMIN VS2 HIGH SIDE CONTROL MODULE HS1 VS2 MISO MOSI SCLK CS ADOUT0 HS2 SPI & CONTROL ANALOG MULTIPLEXER VBAT SENSE MODULE CHIP TEMPERATURE SENSE MODULE ANALOG INPUT MODULE L1 VSENSE WAKE-UP MODULE RXD TXD DIGITAL INPUT MODULE LIN PHYSICAL LAYER LIN LGND WDCONF Figure 23. 33910 Simplified Internal Block Diagram 33910 48 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC PIN CONNECTIONS PIN CONNECTIONS AGND HVDD VSENSE VDD VS1 VS2 26 HS1 25 NC 28 31 30 29 RXD TXD MISO MOSI SCLK CS ADOUT0 PWMIN 1 2 3 4 5 6 7 8 * Special Configuration Recommended / Mandatory for Marked NC Pins 27 32 24 23 22 21 20 19 18 17 HS2 L1 NC* NC* NC* NC* PGND NC* 10 IRQ 11 12 13 14 15 16 RST NC* WDCONF LGND LIN NC* Figure 24. 33910 Pin Connections Table 31. 33910 Pin Definitions A functional description of each pin can be found in the Functional Pin Description. Pin 1 2 3 4 5 6 7 8 9 10 11, 15-17, 19-22, 28 Pin Name RXD TXD MISO MOSI SCLK CS ADOUT0 PWMIN RST IRQ NC Formal Name Receiver Output Transmitter Input SPI Output SPI Input SPI Clock SPI Chip Select Analog Output Pin 0 PWM Input Internal Reset I/O Internal Interrupt Output Definition This pin is the receiver output of the LIN interface which reports the state of the bus voltage to the MCU interface. This pin is the transmitter input of the LIN interface which controls the state of the bus output. SPI data output. When CS is high, the pin is in the high-impedance state. SPI data input. SPI clock Input. SPI chip select input pin. CS is active low. Analog multiplexer output. High side pulse width modulation input. Bidirectional reset I/O pin - driven low when any internal reset source is asserted. RST is active low. Interrupt output pin, indicating wake-up events from Stop mode or events from Normal and Normal Request modes. IRQ is active low. No connect 33910 NC* 9 49 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC PIN CONNECTIONS Table 31. 33910 Pin Definitions A functional description of each pin can be found in the Functional Pin Description. Pin 12 13 14 18 23 24, 25 26, 27 29 30 31 32 Pin Name WDCONF LIN LGND PGND L1 HS2, HS1 VS2, VS1 VSENSE HVDD VDD AGND Formal Name Watchdog Configuration Pin LIN Bus LIN Ground Pin Power Ground Pin Wake-up Input High Side Outputs Power Supply Pin Voltage Sense Pin Hall Sensor Supply Output Voltage Regulator Output Analog Ground Pin Definition This input pin is for configuration of the watchdog period and allows the disabling of the watchdog. This pin represents the single-wire bus transmitter and receiver. This pin is the device LIN ground connection. It is internally connected to the PGND pin. This pin is the device power ground connection. It is internally connected to the LGND pin. This pin is a wake-up capable digital input(68). In addition, L1 can be sensed analog via the analog multiplexer. High side switch outputs. These pins are device battery level power supply pins. VS2 is supplying the HS1 driver while VS1 supplies the remaining blocks.(69) Battery voltage sense input.(70) +5.0 V switchable supply output pin.(71) +5.0 V main voltage regulator output pin.(72) This pin is the device analog ground connection. Notes 68. When used as digital input, a series 33kΩ resistor must be used to protect against automotive transients. 69. Reverse battery protection series diodes must be used externally to protect the internal circuitry. 70. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery connections. It is strongly recommended to connect a 10kΩ resistor in series with this pin for protection purposes. 71. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required. 72. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10 Ω) required. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 50 MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 32. Maximum Ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Supply Voltage at VS1 and VS2 Normal Operation (DC) Transient Conditions (load dump) Supply Voltage at VDD Input / Output Pins Voltage Interrupt Pin (IRQ)(74) VIN(IRQ) HS1 Pin Voltage (DC) HS2 Pin Voltage (DC) L1 Pin Voltage Normal Operation with a series 33 kΩ resistor (DC) Transient input voltage with external component (according to ISO7637-2) (See Figure 26) VSENSE Pin Voltage (DC) LIN Pin Voltage Normal Operation (DC) Transient input voltage with external component (according to ISO7637-2) (See Figure ) VDD output current ESD Voltage (75) (73) Symbol Value Unit V VSUP(SS) VSUP(PK) VDD VIN -0.3 to 27 -0.3 to 40 -0.3 to 5.5 -0.3 to VDD+0.3 -0.3 to 11 - 0.3 to VSUP+0.3 - 0.3 to VSUP+0.3 -18 to 40 ±100 -27 to 40 -18 to 40 -150 to 100 Internally Limited ± 8000 ±2000 ± 150 ± 750 ± 500 Note 76 A V VESD1-1 VESD1-2 VESD2 VESD3-1 VESD3-2 VNC V V VBUSDC VBUSTR IVDD V V V VL1DC VL1TR VVSENSE V V CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD VHS1 VHS2 Human Body Model - LIN Pin Human Body Model - all other Pins Machine Model Charge Device Model Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32) All other Pins (Pins 2-7, 10-15, 18-23, 26-31) NC Pin Voltage (NC pins 11, 15, 16, 17, 19, 20, 21, 22, and 28)(76) Notes 73. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device. 74. Extended voltage range for programming purpose only. 75. Testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model, Robotic (CZAP = 4.0 pF). 76. Special configuration recommended / mandatory for marked NC pins. Please refer to the typical application. 33910 51 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 32. Maximum Ratings (continued) All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings THERMAL RATINGS Operating Ambient Temperature(77) 33910 34910 Operating Junction Temperature(77) Storage Temperature Thermal Resistance, Junction to Ambient Natural Convection, Single Layer board (1s)(78), (79) Natural Convection, Four Layer board (2s2p)(78), (80) Thermal Resistance, Junction to Case(81) Peak Package Reflow Temperature During Reflow(82), (83) RθJC TPPRT TJ TSTG RθJA 85 56 23 Note 83 °C/W °C TA -40 to 125 -40 to 85 -40 to 150 -55 to 150 °C °C °C/W °C Symbol Value Unit Notes 77. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking. 78. 79. 80. 81. 82. 83. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 52 MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 33. Static Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic SUPPLY VOLTAGE RANGE (VS1, VS2) Nominal Operating Voltage Functional Operating Voltage(84) Load Dump SUPPLY CURRENT RANGE (VSUP = 13.5 V) Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State(85) Stop Mode, VDD ON with IOUT = 100 µA, LIN Recessive State 5.5 V < VSUP < 12 V VSUP = 13.5 V Sleep Mode, VDD OFF, LIN Recessive State(85), (87) 5.5 V < VSUP < 12 V 12 V ≤ VSUP < 13.5 V Cyclic Sense Supply Current Adder(88) SUPPLY UNDER/OVER-VOLTAGE DETECTIONS Power-On Reset (BATFAIL)(89) Threshold (measured on VS1)(88) Hysteresis (measured on VS1)(88) VSUP under-voltage detection (VSUV Flag) (Normal and Normal Request modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) VSUP over-voltage detection (VSOV Flag) (Normal and Normal Request modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) VSOV_HYS VSOV 18 – 19.25 1.0 20.5 – VSUV_HYS VSUV 5.55 – 6.0 1.0 6.6 – VBATFAIL VBATFAIL_HYS 1.5 – 3.0 0.9 3.9 – V ICYCLIC ISLEEP – – – 27 37 10 35 48 – µA (85), (86), (87) Symbol Min Typ Max Unit VSUP VSUPOP VSUPLD 5.5 – – – – – 18 27 40 V V V IRUN ISTOP – 4.5 10 mA µA – – 48 58 80 90 µA V V Notes 84. Device is fully functional. All features are operating. 85. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, Cyclic Sense disabled. 86. 87. 88. 89. Total IDD current (including loads) below 100 µA. Stop and Sleep mode currents will increase if VSUP exceeds 13.5 V. This parameter is guaranteed by process monitoring but, not production tested. The flag is set during power up sequence. To clear the flag, a SPI read must be performed. 33910 53 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 33. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic VOLTAGE REGULATOR (90) Symbol Min Typ Max Unit (VDD) VDDRUN 4.75 IVDDRUN VDDDROP – VDDSTOP 4.75 IVDDSTOP LRRUN LRSTOP 6.0 5.0 12 5.25 36 mA mV – – 20 5.0 25 25 mV LDRUN LDSTOP TPRE 110 TPRE_HYS TSD TSD_HYS – 155 – 125 10 170 10 140 – 185 – °C °C °C – – 15 10 80 50 °C 0.1 0.25 V 60 5.00 110 5.25 200 mA V V Normal Mode Output Voltage 1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V Normal Mode Output Current Limitation Dropout Voltage(91) IVDD = 50 mA Stop Mode Output Voltage IVDD < 5.0 mA Stop Mode Output Current Limitation Line Regulation Normal mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA Stop mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA Load Regulation Normal mode, 1.0 mA < IVDD < 50 mA Stop mode, 0.1 mA < IVDD < 5.0 mA Over-temperature Prewarning (Junction)(92) Interrupt generated, Bit VDDOT Set Over-temperature Prewarning hysteresis(92) Over-temperature Shutdown Temperature Over-temperature Shutdown hysteresis (92) (Junction)(92) HALL SENSOR SUPPLY OUTPUT(93) (HVDD) VDD Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100% IHVDD = 15 mA Current Limitation Dropout Voltage IHVDD = 15 mA; IVDD = 5.0 mA Line Regulation IHVDD = 5.0 mA; IVDD = 5.0 mA Load Regulation 1.0 mA > IHVDD > 15 mA; IVDD = 5.0 mA Notes 90. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω. 91. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V). 92. This parameter is guaranteed by process monitoring but, not production tested. 93. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω. LDHVDD – 10 20 LRHVDD – 25 40 mV IHVDD HVDDDROP – 160 300 mV HVDDACC -2.0 20 – 30 2.0 50 mA mV % 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 54 MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 33. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic RST INPUT/OUTPUT PIN (RST) VDD Low Voltage Reset Threshold Low-State Output Voltage IOUT = 1.5 mA; 3.5 V ≤ VSUP ≤ 27 V High-state Output Current (0 < VOUT < 3.5 V) Pull-down Current Limitation (internally limited) VOUT = VDD Low-state Input Voltage High-state Input Voltage MISO SPI OUTPUT PIN (MISO) Low-state Output Voltage IOUT = 1.5 mA High-state Output Voltage IOUT = -250 µA Tri-state Leakage Current 0 V ≤ VMISO ≤ VDD SPI INPUT PINS (MOSI, SCLK, CS) Low-state Input Voltage High-state Input Voltage MOSI, SCLK Input Current 0 V ≤ VIN ≤ VDD CS Pull-up current 0 V < VIN < 3.5 V INTERRUPT OUTPUT PIN (IRQ) Low-state Output Voltage IOUT = 1.5 mA High-state Output Voltage IOUT = -250 µA Leakage current VDD ≤ VOUT ≤ 10 V PULSE WIDTH MODULATION INPUT PIN (PWMIN) Low-state Input Voltage High-state Input Voltage Pull-up current 0 V < VIN < 3.5 V VIL VIH IPUPWMIN 10 20 30 -0.3 0.7 x VDD – – 0.3 x VDD VDD + 0.3 V V µA VOH – – 2.0 VOH VDD - 0.8 – VDD mA VOL 0.0 – 0.8 V V IPUCS 10 20 30 VIL VIH IIN -10 – 10 µA -0.3 0.7 x VDD – – 0.3 x VDD VDD + 0.3 V V µA ITRIMISO -10 – 10 VOH VDD - 0.9 – VDD µA VOL 0.0 – 1.0 V V VIL VIH IOH IPD_MAX 1.5 -0.3 0.7 x VDD – – – 8.0 0.3 x VDD VDD + 0.3 V V VRSTTH VOL 0.0 -150 – -250 0.9 -350 µA mA 4.3 4.5 4.7 V V Symbol Min Typ Max Unit 33910 55 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 33. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic HIGH SIDE OUTPUT HS1 AND HS2 PINS (HS1, HS2) Output Drain-to-Source On Resistance TJ = 25°C, ILOAD = 50 mA; VSUP > 9.0 V TJ = 150°C, ILOAD = 50 mA; VSUP > 9.0 V(94) TJ = 150°C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(94) Output Current Limitation(95) 0 V < VOUT < VSUP - 2.0 V Open Load Current Detection (96) Symbol Min Typ Max Unit RDS(ON) – – – ILIMHS1 60 IOLHSx ILEAK VTHSC VSUP - 2 THSSD THSSD_HYS 150 – – 165 10 – 180 – – – 120 5.0 – 250 7.5 10 – – – 7.0 10 14 Ω mA mA µA V Leakage Current (-0.2 V < VHSx < VS2 + 0.2 V) Short Circuit Detection Threshold 5.5 V < VSUP < 27 V Over-temperature Shutdown(98), (99) Over-temperature Shutdown Hysteresis(99) L1 INPUT PIN (L1) Low Detection Threshold 5.5 V < VSUP < 27 V High Detection Threshold 5.5 V < VSUP < 27 V Hysteresis 5.5 V < VSUP < 27 V Input Current(100) -0.2 V < VIN < VS1 Analog Input Impedance(101) Analog Input Divider Ratio (RATIOL1 = VL1 / VADOUT0) L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 Analog Output Offset Ratio L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 Analog Inputs Matching L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 (97) °C °C VTHL 2.0 VTHH 3.0 VHYS 0.5 IIN -10 RL1IN RATIOL1 0.95 3.42 VRATIOL1OFFSET V 2.5 3.0 V 3.5 4.0 V 1.0 1.5 µA – 1550 10 – kΩ 800 1.0 3.6 1.05 3.78 mV -80 -22 0.0 0.0 80 22 % L1MATCHING 96 96 100 100 104 104 Notes 94. This parameter is production tested up to TA = 125°C and guaranteed by process monitoring up to TJ = 150°C. 95. 96. 97. 98. 99. 100. 101. When over-current occurs, the high side stays ON with limited current capability and the HS1CL flag is set in the HSSR. When open-load occurs, the flag (HS1OP) is set in the HSSR. When short circuit occurs and if HVSE flag is enabled, HS1 automatic shutdown. When over-temperature shutdown occurs, both high sides are turned off. All flags in HSSR are set. Guaranteed by characterization but, not production tested Analog multiplexer input disconnected from L1 input pin. Analog multiplexer input connected to L1 input pin. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 56 MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 33. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy)(102) ANALOG MULTIPLEXER Internal Chip Temperature Sense Gain VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0) 5.5 V < VSUP < 27 V VSENSE Output Related Offset -40°C < TA < -20°C ANALOG OUTPUT (ADOUT0) Maximum Output Voltage -5.0 mA < IO < 5.0 mA Minimum Output Voltage -5.0 mA < IO < 5.0 mA RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD) Low-state Output Voltage IOUT = 1.5 mA High-state Output Voltage IOUT = -250 µA TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD) Low-state Input Voltage High-state Input Voltage Pin Pull-up Current, 0 < VIN < 3.5 V VIL VIH IPUIN -0.3 0.7 x VDD 10 – – 20 0.3 x nVDD VDD + 0.3 30 V V µA VOH VOL V 0.0 – 0.8 V VDD-0.8 – VDD VOUT_MIN 0.0 – 0.35 VOUT_MAX VDD - 0.35 – VDD V V OFFSETVSENS E Symbol Min Typ Max Unit REXT WDACC 20 -15 – – 200 15 kΩ % STTOV RATIOVSENSE – 10.5 – mV/K 5.0 -30 -45 5.25 – – 5.5 30 45 mV Notes 102. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ) 33910 57 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 33. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic LIN PHYSICAL LAYER, TRANSCEIVER (LIN) Output Current Limitation Dominant State, VBUS = 18 V Leakage Output Current to GND Dominant State; VBUS = 0 V; VBAT = 12 V Recessive State; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT GND Disconnected; GNDDEVICE = VSUP; VBAT = 12V; 0 < VBUS < 18V VBAT disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18V Receiver Input Voltages Receiver Dominant State Receiver Recessive State Receiver Threshold Center (VTH_DOM + VTH_REC)/2 Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) LIN Transceiver Output Voltage Recessive State, TXD HIGH, IOUT = 1.0 µA Dominant State, TXD LOW, 500 Ω External Pull-up Resistor, LDVS = 0 Dominant State, TXD LOW, 500 Ω External Pull-up Resistor, LDVS = 1 LIN Pull-up Resistor to VSUP Over-temperature Shutdown(104) Over-temperature Shutdown Hysteresis Notes 103. Parameters guaranteed for 7.0 V ≤ VSUP ≤ 18 V. 104. When Over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set. VLIN_REC VLIN_DOM_0 VLIN_DOM_1 RSLAVE TLINSD TLINSD_HYS VSUP-1 – – 20 150 – – 1.1 1.7 30 165 10 – 1.4 2.0 60 180 – kΩ °C °C VBUSDOM VBUSREC VBUS_CNT VHYS – 0.6 0.475 – – – 0.5 – 0.4 – 0.525 0.175 V IBUS_PAS_DOM IBUS_PAS_REC IBUS_NO_GND IBUS -1.0 – -1.0 – – – – – – 20 1.0 100 mA µA mA µA VSUP (103) Symbol Min Typ Max Unit IBUSLIM 40 120 200 mA 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 58 MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 34. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic SPI INTERFACE TIMING (Figure 34) SPI Operating Frequency SCLK Clock Period SCLK Clock High Time(105) SCLK Clock Low Time(105) Falling Edge of CS to Rising Edge of SCLK(105) Falling Edge of SCLK to CS Rising Edge(105) MOSI to Falling Edge of SCLK(105) Falling Edge of SCLK to MOSI(105) MISO Rise Time(105) CL = 220 pF MISO Fall Time(105) CL = 220 pF Time from Falling or Rising Edges of - MISO Low-impedance - MISO High-impedance Time from Rising Edge of SCLK to MISO Data Valid(105) 0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100 pF RST OUTPUT PIN Reset Low-level Duration after VDD High (See Figure 33) Reset Deglitch Filter Time WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) Watchdog Time Period(106) External Resistor REXT = 20 kΩ (1%) External Resistor REXT = 200 kΩ (1%) Without External Resistor REXT (WDCONF Pin Open) t PWD 8.5 79 110 10 94 150 11.5 108 205 ms t RST t RSTDF 0.65 350 1.0 600 1.35 900 ms ns CS to:(105) Symbol Min Typ Max Unit f SPIOP tPSCLK tWSCLKH tWSCLKL tLEAD tLAG tSISU tSIH tRSO – 250 110 110 100 100 40 40 – – – – – – – – 4.0 N/A N/A N/A N/A N/A N/A N/A MHz ns ns ns ns ns ns ns ns – tFSO – 40 – ns 40 – ns tSOEN tSODIS tVALID 0.0 0.0 – – 50 50 ns 0.0 – 75 Notes 105. This parameter is guaranteed by process monitoring but, not production tested. 106. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ) 33910 59 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 34. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic L1 INPUT Wake-up Filter Time STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop Mode Activation(107) Normal Request Mode Timeout (see Figure 33) Delay Between SPI Command and HS Turn On(108) 9.0 V < VSUP < 27 V Delay Between SPI Command and HS Turn Off(108) 9.0 V < VSUP < 27 V Delay Between Normal Request and Normal Mode After a Watchdog Trigger Command (Normal Request mode)(107) Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and: Normal Request mode, VDD ON and RST HIGH First Accepted SPI Command Minimum Time Between Rising and Falling Edge on the CS t S-OFF – – 10 μs – – 15 — — 10 μs 80 N/A — μs t WUF 8.0 20 38 μs Symbol Min Typ Max Unit t STOP t NR TOUT t S-ON μs – 110 – 150 5.0 205 ms μs – – 10 μs t SNR2N t WUCS t WUSPI t 2CS 9.0 90 4.0 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC(109), (110) Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs 7.0 V ≤ VSUP ≤ 18 V Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs 7.6 V ≤ VSUP ≤ 18 V D1 0.396 D2 — — — KBIT/SEC(109),(111) — 0.581 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs 7.0 V ≤ VSUP ≤ 18 V Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs 7.6 V ≤ VSUP ≤ 18 V D3 μs 0.417 — — μs — — 0.590 D4 Notes 107. This parameter is guaranteed by process monitoring but, not production tested. 108. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load. 109. Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 27. 110. See Figure 28. 111. See Figure 29. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 60 MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 34. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming mode) LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS Propagation Delay and Symmetry(113) Propagation Delay Receiver, tREC_PD=max (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR Bus Wake-up Deglitcher (Sleep and Stop Bus Wake-up Event Reported From Sleep mode (115) (112) SRFAST — 20 — V / μs μs t REC_PD t REC_SYM t PROPWL t WAKE t WAKE t TXDDOM — - 2.0 42 3.0 — 70 6.0 2.0 95 μs μs modes)(114) — 9.0 0.65 — 13 1.0 1500 17 1.35 s From Stop mode(116) TXD Permanent Dominant State Delay PULSE WIDTH MODULATION INPUT PIN (PWMIN) PWMIN pin(117) Max. frequency to drive HS output pins fPWMIN — 10 — kHz Notes 112. VSUP from 7.0 V to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 6. 113. See Figure 9. 114. See Figure 10, for Sleep and Figure 11, for Stop mode. 115. The measurement is done with 1.0 µF capacitor and 0 mA current load on VDD. The value takes into account the delay to charge the capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0 V. See Figure 10. The delay depends of the load and capacitor on VDD. 116. 117. In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11. This parameter is guaranteed by process monitoring but, not production tested. 33910 61 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS 33910 1.0 nF TRANSIENT PULSE GENERATOR (NOTE) GND PGND LGND AGND LIN NOTE: Waveform Per ISO 7637-2. Test Pulses 1, 2, 3a, 3b. Figure 25. Test Circuit for Transient Test Pulses (LIN) 33910 1.0 nF TRANSIENT PULSE GENERATOR (NOTE) GND L1 10 kΩ PGND LGND AGND NOTE: Waveform Per ISO 7637-2. Test Pulses 1, 2, 3a, 3b. Figure 26. Test Circuit for Transient Test Pulses (L1) VSUP TXD RXD LIN R0 C0 R0 AND C0 COMBINATIONS: • 1.0 kΩ and 1.0 nF • 660 Ω and 6.8 nF • 500 Ω and 10 nF Figure 27. Test Circuit for LIN Timing Measurements 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 62 MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD tBIT tBIT VLIN_REC tBUS_DOM (MAX) tREC - MAX tDOM - MIN tBUS_REC (MIN) tDOM - MIN 74.4% VSUP 60.0% VSUP 58.1% VSUP 40.0% VSUP 28.4% VSUP 42.2% VSUP LIN 58.1% VSUP 40.0% VSUP 28.4% VSUP tREC - MIN tDOM - MAX RXD tBUS_DOM (MIN) tBUS_REC (MAX) tRDOM tRREC Figure 28. LIN Timing Measurements for Normal Slew Rate TXD tBIT tBIT VLIN_REC tBUS_DOM (MAX) tREC - MAX tDOM - MIN 61.6% VSUP 40.0% VSUP 25.1% VSUP tBUS_REC (MIN) tDOM - MIN 77.8% VSUP 60.0% VSUP 61.6% VSUP 40.0% VSUP 25.1% VSUP 38.9% VSUP LIN tDOM - MAX RXD tREC - MIN tBUS_DOM (MIN) tBUS_REC (MAX) tRDOM tRREC Figure 29. LIN Timing Measurements for Slow Slew Rate 33910 63 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VLIN_REC VBUSrec VBUSdom LIN BUS SIGNAL VSUP RXD tRX_PDF tRX_PDR Figure 30. LIN Receiver Timing VLIN_REC LIN 0.4 VSUP DOMINANT LEVEL VDD tPROPWL tWAKE Figure 31. LIN Wake-up Sleep Mode Timing VLIN_REC LIN 0.4 VSUP DOMINANT LEVEL IRQ tPROPWL tWAKE Figure 32. LIN Wake-up Stop Mode Timing 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 64 MC33910BAC / MC34910BAC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VSUP VDD RST tRST tNRTOUT Figure 33. Power On Reset and Normal Request Timeout Timing tPSCLK CS tLEAD SCLK tWSCLKL tSISU tSIH tWSCLKH tLAG MOSI UNDEFINED tVALID tSOEN D0 DON’T CARE D7 DON’T CARE tSODIS MISO D0 DON’T CARE D7 Figure 34. SPI Timing Characteristics 33910 65 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33910 is designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 33910 is well suited to perform keypad applications via the LIN bus. Two power switches are provided on the device configured as high side outputs. Other ports are also provided, which include a wake-up capable pin amd a Hall Sensor port supply. An internal voltage regulator provides power to a MCU device. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL PIN DESCRIPTION See Table 1, 33910 Simplified Application Diagram, for a graphic representation of the various pins referred to in the following paragraphs. Also, see the 33910 Pin Connections for a description of the pin locations in the package. microcontroller. Data on this output pin changes on the negative edge of the SCLK. When CS is High, this pin will remain in high-impedance state. RECEIVER OUTPUT (RXD) The RXD pin is a digital output. It is the receiver output of the LIN interface and reports the state of the bus voltage: RXD low when LIN bus is dominant, RXD high when LIN bus is recessive. CHIP SELECT (CS) CS is a active low digital input. It must remain low during a valid SPI communication and allow for several devices to be connected in the same SPI bus without contention. A rising edge on CS signals the end of the transmission and the moment the data shifted in is latched. A valid transmission must consist of 8 bits only. While in STOP mode a low-to-high level transition on this pin will generate a wake-up condition for the 33910. TRANSMITTER INPUT (TXD) The TXD pin is a digital input. It is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD is Low, recessive when TXD is High). This pin has an internal pull-up to force recessive state in case the input is left floating. ANALOG MULTIPLEXER (ADOUT0) The ADOUT0 pin can be configured via the SPI to allow the MCU A/D converter to read the several inputs of the Analog Multiplexer, including the L1 input voltage and the internal junction temperature. LIN BUS (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is compliant to the LIN bus specification 2.0. The LIN interface is only active during Normal and Normal Request modes. PWM INPUT CONTROL (PWMIN) This digital input can control the high sides in Normal Request and Normal mode. To enable PWM control, the MCU must perform a write operation to the high side control register (HSCR). This pin has an internal 20 μA current pull-up. SERIAL DATA CLOCK (SCLK) The SCLK pin is the SPI clock input pin. MISO data changes on the negative transition of the SCLK. MOSI is sampled on the positive edge of the SCLK. RESET (RST) This bidirectional pin is used to reset the MCU in case the 33910 detects a reset condition or to inform the 33910 that the MCU has just been reset. After release of the RST pin Normal Request mode is entered. The RST pin is an active low filtered input and output formed by a weak pull-up and a switchable pull-down structure which allows this pin to be shorted either to VDD or to GND during software development without the risk of destroying the driver. MASTER OUT SLAVE IN (MOSI) The MOSI digital pin receives SPI data from the MCU. This data input is sampled on the positive edge of SCLK. MASTER IN SLAVE OUT (MISO) The MISO pin sends data to an SPI-enabled MCU. It is a digital tri-state output used to shift serial data to the 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 66 MC33910BAC / MC34910BAC FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION INTERRUPT (IRQ) The IRQ pin is a digital output used to signal events or faults to the MCU while in Normal and Normal Request mode or to signal a wake-up from Stop mode. This active low output will transition to high, only after the interrupt is acknowledged by a SPI read of the respective status bits. HIGH SIDE OUTPUTS (HS1 AND HS2) These high side switches are able to drive loads such as relays or lamps. Their structure is connected to the VS2 supply pin. The pins are short-circuit protected and also protected against overheating. HS1and HS2 are controlled by SPI and can respond to a signal applied to the PWMIN input pin. The HS1 and HS2 outputs can also be used during Low Power mode for the cyclic-sense of the wake input. WATCHDOG CONFIGURATION (WDCONF) The WDCONF pin is the configuration pin for the internal watchdog. A resistor can be connected to this pin to configure the window watchdog period. When connected directly to ground, the watchdog will be disabled. When this pin is left open, the watchdog period is fixed to its lower precision internal default value (150 ms typical). POWER SUPPLY (VS1 AND VS2) Those are the battery level voltage supply pins. In an application, VS1 and VS2 pins must be protected against reverse battery connection and negative transient voltages, with external components. These pins sustain standard automotive voltage conditions such as load dump at 40 V. The high side switches (HS1 and HS2) are supplied by the VS2 pin, all other internal blocks are supplied by VS1 pin. GROUND CONNECTION (AGND, PGND, LGND) The AGND, PGND and LGND pins are the Analog and Power ground pins. The AGND pin is the ground reference of the voltage regulator. The PGND and LGND pins are used for high current load return as in the LIN interface pin. Note: PGND, AGND and LGND pins must be connected together. VOLTAGE SENSE PIN (VSENSE) This input can be connected directly to the battery line. It is protected against battery reverse connection. The voltage present in this input is scaled down by an internal voltage divider, and can be routed to the ADOUT0 output pin and used by the MCU to read the battery voltage. The ESD structure on this pin allows for excursion up to +40 V, and down to -27 V, allowing this pin to be connected directly to the battery line. It is strongly recommended to connect a 10kohm resistor in series with this pin for protection purposes. DIGITAL/ANALOG (L1) The L1 pin is a multi purpose input. It can be used as a digital input, which can be sampled by reading the SPI and used for wake-up when 33910 is in Low Power mode or used as analog inputs for the analog multiplexer. When used to sense voltage outside the module, a 33kohm series resistor must be used on each input. When used as a wake-up input L1 can be configured to operate in Cyclic-Sense mode. In this mode, one of the high side switches is configured to be periodically turned on and sample the wake-up input. If a state change is detected between two cycles a wake-up is initiated. The 33910 can also wake-up from Stop or Sleep by a simple state change on L1. When used as analog input, the voltage present on the L1 pins is scaled down by an selectable internal voltage divider and can be routed to the ADOUT0 output through the analog multiplexer. Note: If L1 input is selected in the analog multiplexer, it will be disabled as digital input and remains disabled in low Power mode. No wake-up feature is available in that condition. When the L1 input is not selected in the analog multiplexer, the voltage divider is disconnected from that input. HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD) This pin provides a switchable supply for external hall sensors. While in Normal mode, this current limited output can be controlled through the SPI. The HVDD pin needs to be connected to an external capacitor to stabilize the regulated output voltage. +5V MAIN REGULATOR OUTPUT (VDD) An external capacitor has to be placed on the VDD pin to stabilize the regulated output voltage. The VDD pin is intended to supply a microcontroller. The pin is current limited against shorts to GND and over-temperature protected. During Stop mode the voltage regulator does not operate with its full drive capabilities and the output current is limited. During Sleep mode the regulator output is completely shut down. 33910 67 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC33910 - Functional Block Diagram Integrated Supply Hall Sensor Supply Voltage Regulator VDD HVDD Analog Circuitry Window Watchdog Wake-Up High Side Drivers HS1 - HS2 LIN Physical Layer Interface Digital / Analog Input Voltage & Temperature Sense MCU Interface and Output Control SPI Interface Reset & IRQ Logic HS - PWM Control Analog Output 0 Integrated Supply Analog Circuitry MCU Interface and Output Control Drivers Figure 35. Functional Internal Block Diagram ANALOG CIRCUITRY The 33910 is designed to operate under automotive operating conditions. A fully configurable window watchdog circuit will reset the connected MCU in case of an overflow. Two low power modes are available with several different wake-up sources to reactivate the device. One analog / digital input can be sensed or used as the wake-up source. The device is capable of sensing the supply voltage (VSENSE) and the internal chip temperature (CTEMP). as over-current conditions in any of the driver stages can be reported to the connected MCU via IRQ or RST. The High Side driver outputs can be controlled via the SPI register as well as the PWMIN input. The integrated LIN physical layer interface can be configured via SPI register and its communication is driven through the RXD and TXD device pins. All internal analog sources are multiplexed to the ADOUT0 pin. VOLTAGE REGULATOR OUTPUTS Two independent voltage regulators are implemented on the 33910. The VDD main regulator output is designed to supply a MCU with a precise 5.0 V. The switchable HVDD output is dedicated to supply small peripherals as hall sensors. HIGH SIDE DRIVERS Two current and temperature protected High Side drivers with PWM capability are provided to drive small loads such as Status LED’s or small lamps. Both Drivers can be configured for periodic sense during low power modes. MCU INTERFACE The 33910 is providing its control and status information through a standard 8-Bit SPI interface. Critical system events such as Low- or High-voltage/Temperature conditions as well LIN PHYSICAL LAYER INTERFACE The 33910 provides a LIN 2.0 compatible LIN physical layer interface with selectable slew rate and various diagnostic features. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 68 MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES INTRODUCTION The 33910 offers three main operating modes: Normal (Run), Stop, and Sleep (Low Power). In Normal mode the device is active and is operating under normal application conditions. The Stop and Sleep modes are low power modes with wake-up capabilities. In Stop mode the voltage regulator still supplies the MCU with VDD (limited current capability) and in Sleep mode the voltage regulator is turned off (VDD = 0 V). Wake-up from Stop mode is initiated by a wake-up interrupt. Wake-up from Sleep mode is done by a reset and the voltage regulator is turned back on. The selection of the different modes is controlled by the MOD1:2 bits in the mode control register (MCR). Figure 36 describes how transitions are done between the different operating modes and Table 35, gives an overview of the Operating mode. NORMAL MODE In Normal mode, all 33910 functions are active and can be controlled by the SPI and the PWMIN pin. The VDD regulator is ON and delivers its full current capability. If an external resistor is connected between the WDCONF pin and the Ground, the window watchdog function will be enabled. The wake-up input (L1) can be read as a digital input or have its voltage routed through the analog-multiplexer. The LIN interface has slew rate and timing compatible with the LIN protocol specification 2.0. The LIN bus can transmit and receive information. The high side switches are active and have PWM capability according to the SPI configuration. The interrupts are generated to report failures 5 for VSUP over/under-voltage, thermal shutdown or thermal shutdown prewarning on the main regulator. RESET MODE The 33910 enters the Reset mode after a power up. In this mode, the RST pin is low for 1.0 ms (typical value). After this delay, the 33910 enters the Normal Request mode and the RST pin is driven high. The Reset mode is entered if a reset condition occurs (VDD low, watchdog trigger fail, after a wake-up from Sleep mode, Normal Request mode timeout occurs). SLEEP MODE The Sleep mode is a low power mode. From Normal mode, the device enters the Sleep mode by sending one SPI command through the MCR. All blocks are in their lowest power consumption condition. Only some wake-up sources (wake-up input with or without cyclic sense, forced wake-up and LIN receiver) are active. The 5.0 V regulator is OFF. The internal low-power oscillator may be active if the IC is configured for cyclic-sense. In this condition, one of the high side switches is turned on periodically and the wake-up inputs are sampled. Wake-up from Sleep mode is similar to a power-up. The device goes in Reset mode except that the SPI will report the wake-up source and the BATFAIL flag is not set. NORMAL REQUEST MODE This is a temporary mode automatically accessed by the device after the Reset mode or after a wake-up from Stop mode. In Normal Request mode, the VDD regulator is ON, the Reset pin is high and the LIN is operating in Rx Only mode. As soon as the device enters the Normal Request mode an internal timer is started for 150 ms (typical value). During these 150 ms, the MCU must configure the timing control register (TIMCR) and the MCR with MOD2 and MOD1 bits ste = 0 to enter in Normal mode. If within the 150 ms timeout the MCU does not command the 33910 to Normal mode, it will enter in Reset mode. If the WDCONF pin is grounded in order to disable the watchdog function, the 33910 goes directly in Normal mode after the Reset mode. If the WDCONF pin is open, the 33910 stays typically for 150 ms in Normal Request before entering in Normal mode. STOP MODE The Stop mode is the second low power mode, but in this case the 5.0 V regulator is ON with limited current drive capability. The application MCU is always supplied while the 33910 is operating in Stop mode. The device can enter in Stop mode only by sending the SPI command. When the application is in this mode, it can wake-up from the 33910 side (for example: cyclic sense, force wake-up, LIN bus, wake inputs) or the MCU side (CS, RST pins). Wake-up from Stop mode will transition the 33910 to Normal Request mode and generates an interrupt except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin. 33910 69 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Normal Request Timeout Expired (t NRTOUT) VDD LOW VDD HIGH AND RESET DELAY (t RST) EXPIRED POWER DOWN Power Up RESET NORMAL REQUEST WD DISABLED WD TRIGGER VDD LOW WD FAILED NORMAL VDD LOW (>t NRTOUT) EXPIRED AND VSUV = 0 SLEEP COMMAND WAKE-UP (RESET) SLEEP STOP VDD LOW Legend WD: Watchdog WD Disabled: Watchdog disabled (WDCONF pin connected to GND) WD Trigger: Watchdog is triggered by SPI command WD Failed: No watchdog trigger or trigger occurs in closed window Stop Command: Stop command sent via the SPI Sleep Command: Sleep command sent via the SPI Wake-up from Stop mode: L1 state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up. Wake-up from Sleep mode: L1 state change, LIN bus wake-up, Periodic wake-up. Figure 36. Operating Modes and Transitions STOP COMMAND WAKE-UP (INTERRUPT) 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 70 MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Table 35. Operating Modes Overview Function VDD HVDD HSx Analog Mux L1 LIN Watchdog VSENSE Notes 118. 119. 120. 121. 122. Reset Mode Normal Request Mode Normal Mode full On full SPI(118) SPI/PWM(119) SPI Input Rx-Only 150 ms (typ.) timeout On full SPI SPI/PWM SPI Input full/Rx-Only On(62)/Off On Stop Mode stop Note(120) Wake-up Rx-Only/Wake-up VDD Sleep Mode - Note(121) Wake-up Wake-up - Operation can be enabled/controlled by the SPI. Operation can be controlled by the PWMIN input. HSx switches can be configured for cyclic sense operation in Stop mode. HSx switches can be configured for cyclic sense operation in Sleep mode. Windowing operation when enabled by an external resistor. INTERRUPTS Interrupts are used to signal a microcontroller that a peripheral needs to be serviced. The interrupts which can be generated change according to the Operating mode. While in Normal and Normal Request modes the 33910 signals through interrupts special conditions which may require a MCU software action. Interrupts are not generated until all pending wake-up sources are read in the interrupt source register (ISR). While in Stop mode, interrupts are used to signal wake-up events. Sleep mode does not use interrupts, wake-up is performed by powering-up the MCU. In Normal and Normal Request mode the wake-up source can be read by SPI. The interrupts are signaled to the MCU by a low logic level of the IRQ pin, which will remain low until the interrupt is acknowledged by a SPI read. The IRQ pin will then be driven high. Interrupts are only asserted while in Normal-, Normal Request and Stop mode. Interrupts are not generated while the RST pin is low. Following is a list of the interrupt sources in Normal and Normal Request modes, some of those can be masked by writing to the SPI-interrupt mask register (IMR). Low Voltage Interrupt Signals when the supply line (VS1) voltage drops below the VSUV threshold (VSUV). High Voltage Interrupt Signals when the supply line (VS1) voltage increases above the VSOV threshold (VSOV). Over-temperature Prewarning Signals when the 33910 temperature has reached the preshutdown warning threshold. It is used to warn the MCU that an over-temperature shutdown in the main 5.0 V regulator is imminent. LIN Over-current Shutdown / Over-temperature Shutdown / TXD Stuck At Dominant / RXD Short-circuit These signal faulty conditions in the LIN interface (except the LIN over-current) that had led to disable the LIN driver. In order to restart operation, the fault must be removed and must be acknowledged by reading the SPI. The LINOC bit functionality in the LIN status register (LINSR) is to indicate that an LIN over-current occurred and the driver stays enabled. High Side Over-temperature Shutdown Signals a shutdown of the high side outputs. RESET To reset an MCU, the 33910 drives the RST pin low for the time the reset condition lasts. After the reset source has been removed the state machine will drive the RST output low for at least 1.0 ms typical value before driving it high. In the 33910 four main reset sources exist: 5V Regulator Low-Voltage-Reset (VRSTTH) The 5V regulator output VDD is continuously monitored against brown outs. If the supply monitor detects that the voltage at the VDD pin has dropped below the reset threshold VRSTTH the 33910 will issue a reset. In case of overtemperature, the voltage regulator will be disabled and the 33910 71 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES voltage monitoring will issue a VDDOT Flag independently of the VDD voltage. Window Watchdog Overflow If the watchdog counter is not properly serviced while its window is open, the 33910 will detect a MCU software runaway and will reset the microcontroller. Wake-up From Sleep Mode During Sleep mode, the 5.0 V regulator is not active, hence all wake-up requests from Sleep mode require a power-up/reset sequence. External Reset The 33910 has a bidirectional reset pin which drives the device to a safe state (same as Reset mode) for as long as this pin is held low. The RST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality is also active in Stop mode. After the RST pin is released, there is no extra t RST to be considered. In order to select and activate the cyclic sense wake-up from the L1 input, before entering in low power modes (Stop or Sleep modes), the following SPI set-up has to be performed: • In WUCR: select the L1 input to WU-enable. • In HSCR: enable HSx. • In TIMCR: select the CS/WD bit and determine the cyclic sense period with CYSTx bits. • Perform Goto Sleep/Stop command. Forced Wake-up The 33910 can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and forced wake-up are exclusive. If forced wake-up is enabled, the cyclic sense can not be enabled. To determine the wake-up period, the following SPI set-up has to be sent before entering in Low Power modes: • In TIMCR: select the CS/WD bit and determine the Low Power mode period with CYSTx bits. • In HSCR: the HSx bit must be disabled. CS Wake-up While in Stop mode, a rising edge on the CS will cause a wake-up. The CS wake-up does not generate an interrupt and is not reported on SPI. LIN Wake-up While in the low power modes the 33910 monitors the activity on the LIN bus. A dominant pulse larger than t PROPWL followed by a dominant to recessive transition will cause a LIN wake-up. This behavior protects the system from a shortto-ground bus condition. RST Wake-up While in Stop mode, the 33910 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. Then, the 33910 will change to Normal Request or Normal modes depending on the WDCONF pin configuration. The RST wake-up does not generate an interrupt and is not reported via SPI. From Stop mode, the following wake-up events can be configured: • Wake-up from L1 input without cyclic sense • Cyclic sense wake-up inputs • Force wake-up • CS wake-up • LIN wake-up • RST wake-up From Sleep mode, the following wake-up events can be configured: • Wake-up from L1 input without cyclic sense • Cyclic sense wake-up inputs • Force wake-up • LIN wake-up WAKE-UP CAPABILITIES Once entered in to one of the low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal mode operation. In Stop mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep mode the wake-up is performed by activating the 5.0 V regulator and resetting the MCU. In both cases the MCU can detect the wake-up source by accessing the SPI registers. There is no specific SPI register bit to signal a CS wake-up or external reset. If necessary this condition is detected by excluding all other possible wake-up sources. Wake-up From Wake-up Input (L1) With Cyclic Sense Disabled The wake-up line is dedicated to sense state changes of external switches and wake-up the MCU (in Sleep or Stop mode). In order to select and activate direct wake-up from the L1 input, the wake-up control register (WUCR) must be configured with L1WE input enabled. The wake-up input state is read through the wake-up status register (WUSR). L1 input is also used to perform cyclic-sense wake-up. Note: Selecting the L1 input in the analog multiplexer before entering Low Power mode will disable the wake-up capability of the L1 input. Wake-up From Wake-up Input (L1) With Cyclic Sense Timer Enabled The SBCLIN can wake-up at the end of a cyclic sense period if on the wake-up input lines (L1) a state change occurs. The HSx switch is activated in Sleep or Stop modes from an internal timer. Cyclic sense and force wake-up are exclusive. If cyclic sense is enabled, the force wake-up can not be enabled. Analog Integrated Circuit Device Data Freescale Semiconductor 33910 72 MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES WINDOW WATCHDOG The 33910 includes a configurable window watchdog which is active in Normal mode. The watchdog can be configured by an external resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears are performed by writing through the SPI in the MOD bits of the MCR. During the first half of the SPI timeout watchdog clears are not allowed; but after the first half of the PSPI-timeout window the clear operation opens. If a clear operation is performed outside the window, the 33910 will reset the MCU, in the same way as when the watchdog overflows. in the WDSR will be set. This condition is only detected during Reset mode. If neither a resistor nor a connection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150 ms (typ.) and signals the faulty condition through the WDSR. The watchdog timebase can be further divided by a prescaler which can be configured by the TIMCR. During Normal Request mode, the window watchdog is not active but there is a 150 ms (typ.) timeout for leaving the Normal Request mode. In case of a timeout, the 33910 will enter into Reset mode, resetting the microcontroller before entering again into Normal Request mode. HIGH SIDE OUTPUT PINS HS1 AND HS2 WINDOW CLOSED NO WATCHDOG CLEAR ALLOWED WINDOW OPEN FOR WATCHDOG CLEAR WD TIMING X 50% WD TIMING X 50% WD PERIOD (tPWD) WD TIMING SELECTED BY REGISTER ON WDCONF PIN These outputs are two high side drivers intended to drive small resistive loads or LEDs incorporating the following features: • PWM capability (software maskable) • Open load detection • Current limitation • Over-temperature shutdown (with maskable interrupt) • High-voltage shutdown (software maskable) • Cyclic sense The high side switches are controlled by the bits HS1:2 in the High Side Control Register (HSCR). PWM Capability (direct access) Each high side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits HS1 and PWMHS1 are set in the High Side Control Register (HSCR), then the HS1 driver is turned on if the PWMIN pin is high and turned of if the PWMIN pin is low. This applies to HS2 configuring HS2 and PWMHS2 bits. Figure 37. Window Watchdog Operation To disable the watchdog function in Normal mode the user must connect the WDCONF pin to ground. This measure effectively disables Normal Request mode. The WDOFF bit 33910 73 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES HVSE Interrupt Control Module High Voltage Shutdown High-Side Interrupt VDD VDD PWMIN PWMHSx VS2 MOD1:2 HSx HSxOP HSxCL on/off High Side - Driver charge pump open load detection current limitation overtemperture shutdown (interrupt maskable) high voltage shutdown (maskable) HSx Control Status Wakeup Module Cyclic Sense Figure 38. High Side Drivers HS1 and HS2 Open Load Detection Each high side driver signals an open load condition if the current through the high side is below the open load current threshold. The open load condition is indicated with the bits HS1OP and HS2OP in the High Side Status Register (HSSR). Current Limitation Each high side driver has an output current limitation. In combination with the over-temperature shutdown the highside drivers are protected against over-current and shortcircuit failures. When the driver operates in the current limitation area, it is indicated with the bits HS1CL and HS2CL in the HSSR. Note: If the driver is operating in current limitation mode, excessive power might be dissipated. Over-temperature Protection (HS Interrupt) Both high side drivers are protected against overtemperature. In case of an over-temperature condition both high side drivers are shut down and the event is latched in the Interrupt Control Module. The shutdown is indicated as HS Interrupt in the Interrupt Source Register (ISR). A thermal shutdown of the high side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously. If the bit HSM is set in the Interrupt Mask Register (IMR), then an interrupt (IRQ) is generated. A write to the High Side Control Register (HSCR), when the over-temperature condition is gone, will re-enable the high side drivers. High-voltage Shutdown In case of a high voltage condition and if the high voltage shutdown is enabled (bit HVSE in the Mode Control Register (MCR) is set) both high side drivers are shut down. A write to the High Side Control Register (HSCR), when the high voltage condition is gone, will re-enable the high side drivers. Sleep And Stop Mode The high side driver can be enabled to operate in Sleep and Stop mode for cyclic sensing. Also see Table 35, Operating Modes Overview. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 74 MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES LIN PHYSICAL LAYER The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification and has the following features: • LIN physical layer 2.0 compliant • Slew rate selection • Over-current shutdown • Over-temperature shutdown • LIN pull-up disable in Stop and Sleep modes • Advanced diagnostics • LIN dominant voltage level selection The LIN driver is a low side MOSFET with over-current and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a Slave mode. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed. LIN Pin The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication. INTERRUPT CONTROL MODULE WAKE-UP MODULE High-voltage Shutdown High Side Interrupt LIN Wake-up MOD1:2 LSR0:1 LINPE LDVS RXONLY RXSHORT TXDOM LINOT LINOC 30K LIN TXD SLOPE CONTROL WAKE-UP FILTER RXD RECEIVER LGND VS1 LIN – DRIVER Slope and Slew Rate Control Over-current Shutdown (interrupt maskable) Over-temperature Shutdown (interrupt maskable) Figure 39. LIN Interface Slew Rate Selection The slew rate can be selected for optimized operation at 10.4 and 20 kBit/s as well as a fast baud rate for test and programming. The slew rate can be adapted with the bits LSR1:0 in the LIN control register (LINCR). The initial slew rate is optimized for 20 kBit/s. LIN Pull-up Disable In Stop and Sleep Mode To improve performance and for safe behavior in case of LIN bus short to ground or LIN bus leakage during Low Power mode the internal pull-up resistor on the LIN pin can be disconnected by clearing the LINPE bit in the MCR. The bit LINPE also changes the bus wake-up threshold (VBUSWU). In case of a LIN bus short to GND, this feature will reduce the current consumption in Stop and Sleep modes. 33910 75 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Over-current Shutdown (LIN Interrupt) The output low side FET is protected against over-current conditions. In case of an over-current condition (e.g. LIN bus short to VBAT), the transmitter will not be shut down. The bit LINOC in the LIN status register (LINSR) is set. If the bit LINM is set in the interrupt mask register (IMR) an Interrupt IRQ will be generated. Over-temperature Shutdown (LIN Interrupt) The output low side FET is protected against overtemperature conditions. In case of an over-temperature condition, the transmitter will be shut down and the bit LINOT in the LIN status register (LINSR) is set. If the bit LINM is set in the interrupt mask register (IMR) an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone and TXD is high. A read of the LIN status register (LINSR) with the TXD pin will re-enable the transmitter. RXD Short-circuit Detection (LIN Interrupt) The LIN transceiver has a short-circuit detection for the RXD output pin. In case of an short-circuit condition, either 5.0 V or ground, the bit RXSHORT in the LIN status register (LINSR) is set and the transmitter is shutdown. If the bit LINM is set in the interrupt mask register (IMR) an interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone (transition on RXD) and TXD is high. A read of the LIN status register (LINSR) without the RXD pin short circuit condition will clear the bit RXSHORT. TXD Dominant Detection (LIN Interrupt) The LIN transceiver monitors the TXD input pin to detect stuck in dominant (0 V) condition. In case of a stuck condition (TXD pin 0V for more than 1 second (typ.)) the transmitter is shut down and the bit TXDOM in the LIN status register (LINSR) is set. If the bit LINM is set in the interrupt mask register (IMR) an interrupt IRQ will be generated. The transmitter is automatically re-enabled once TXD is high. A read of the LIN status register (LINSR) with the TXD pin is high will clear the bit TXDOM. LIN Dominant Voltage Level Selection The LIN dominant voltage level can be selected by the bit LDVS in the LIN control register (LINCR). LIN Receiver Operation Only While in Normal mode the activation of the RXONLY bit disables the LIN TX driver. In the case of a LIN error condition this bit is automatically set. In case a Low Power mode is selected with this bit set, the LIN wake-up functionality is disabled, then, in Stop mode, the RXD pin will reflect the state of the LIN bus. STOP Mode And Wake-up Feature During Stop mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Stop mode sequence the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in the recessive state. The receiver is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge will generate a wake-up interrupt and will be reported in the ISR. Also see Figure 32. SLEEP Mode And Wake-up Feature During Sleep mode operation the transmitter of the physical layer is disabled. In case the bit LIN-PU was set in the Sleep mode sequence the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in recessive state. The receiver is still active to be able to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge will generate a system wake-up (Reset) and will be reported in the ISR. Also see Figure 31. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 76 MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS SPI AND CONFIGURATION The SPI creates the communication link between a microcontroller (master) and the 33910. The interface consists of four pins (see Figure 40): • CS — Chip Select • MOSI — Master-Out Slave-In • MISO — Master-In Slave-Out • SCLK— Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0) and the slave replies with 3 system status bits and one not defined bit (VMS,LINS,HSS,n.d.) + 4 bits of status information (S3:S0). CS Register Write Data MOSI A3 A2 A1 A0 C3 C2 C1 C0 Register Read Data MISO VMS LINS HSS – S3 S2 S1 S0 SCLK Read Data Latch Write Data Latch Rising Edge of SCLK Change MISO/MISO Output Falling Edge of SCLK Sample MISO/MISO Input Figure 40. SPI Protocol During the inactive phase of the CS (HIGH), the new data The rising edge of the chip select CS indicates the end of transfer is prepared. the transfer and latches the write data (MOSI) into the register. The CS high forces MISO to the high-impedance The falling edge of the CS indicates the start of a new data state. transfer and puts the MISO in the low-impedance state and Register reset values are described along with the reset latches the analog status data (Register read data). condition. Reset condition is the condition causing the bit to With the rising edge of the SPI clock (SCLK), the data is be set to its reset value. The main reset conditions are: moved to MISO/MOSI pins. With the falling edge of the SPI - Power-On Reset (POR): level at which the logic is reset clock (SCLK) the data is sampled by the receiver. and BATFAIL flag sets. The data transfer is only valid if exactly 8 sample clock - Reset mode edges are present during the active (low) phase of CS. - Reset done by the RST pin (ext_reset) 33910 77 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS SPI REGISTER OVERVIEW . Table 36. System Status Register Adress(A3:A0) $0 - $F Register Name / Read / Write Information SYSSR - System Status Register R BIT 7 VMS 6 LINS 5 HSS 4 - Table 9 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R. Table 37. SPI Register Overview Adress(A3:A0) Register Name / Read / Write Information MCR - Mode Control Register VSR - Voltage Status Register VSR - Voltage Status Register WUCR - Wake-up Control Register WUSR - Wake-up Status Register WUSR - Wake-up Status Register LINCR - LIN Control Register LINSR - LIN Status Register LINSR - LIN Status Register HSCR - High Side Control Register HSSR - High Side Status Register HSSR - High Side Status Register TIMCR - Timing Control Register WDSR - Watchdog Status Register $B $C $D $E $F WDSR - Watchdog Status Register AMUXCR - Analog Multiplexer Control Register CFR - Configuration Register IMR - Interrupt Mask Register ISR - Interrupt Source Register ISR - Interrupt Source Register W R R W R R W R R W R R W R R W W W R R BIT 3 HVSE VSOV VSOV LDVS RXSHORT RXSHORT PWMHS2 HS2OP HS2OP CS/WD WDTO WDTO L1DS HVDD HSM ISR3 ISR3 2 LINPE VSUV VSUV RXONLY TXDOM TXDOM PWMHS1 HS2CL HS2CL WD2 CYST2 WDERR WDERR MX2 CYSX8 ISR2 ISR2 1 MOD2 VDDOT VDDOT LSR1 LINOT LINOT HS2 HS1OP HS1OP WD1 CYST1 WDOFF WDOFF MX1 LINM ISR1 ISR1 0 MOD1 BATFAIL BATFAIL L1WE L1 L1 LSR0 LINOC LINOC HS1 HS1CL HS1CL WD0 CYST0 WDWO WDWO MX0 VMM ISR0 ISR0 $0 $1 $2 $3 $4 $5 $6 $7 $A Note: Address $8 and $9 are reserved and must not be used. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 78 MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS REGISTER DEFINITIONS System Status Register - SYSSR The system status register (SYSSR) is always transferred with every SPI transmission and gives a quick system status overview. It summarizes the status of the voltage status register (VSR), LIN status register (LINSR) and the HSSR. Table 38. System Status Register S7 Read VMS HSS - High Side Switch Status This read-only bit indicates that one or more bits in the HSSR are set. 1 = High Side Status bit set 0 = None HS1CL S6 LINS S5 HSS S4 –. HS1OP HS2CL HS2OP HSS VMS - Voltage Monitor Status This read-only bit indicates that one or more bits in the voltage status register (VSR) are set. 1 = Voltage Monitor bit set 0 = None Figure 43. High Side Status Mode Control Register - MCR The MCR allows to switch between the operation modes and to configure the 33910. Writing the MCR will return the voltage status register (VSR). Table 39. Mode Control Register - $0 C3 C2 LINPE 1 BATFAIL VDDOT VSUV VSOV Figure 41. Voltage Monitor Status LINS - LIN Status This read-only bit indicates that one or more bits in the LIN status register (LINSR) are set. 1 = LIN Status bit set 0 = None VMS C1 MOD2 - C0 MOD1 - Write Reset Value Reset Condition HVSE 1 POR POR - - HVSE - High-voltage Shutdown Enable This write-only bit enables/disables automatic shutdown of the high side and the low side drivers during a high-voltage VSOV condition. 1 = automatic shutdown enabled 0 = automatic shutdown disabled LINPE - LIN pull-up enable. This write-only bit enables/disables the 30 kΩ LIN pull-up resistor in Stop and Sleep modes. This bit also controls the LIN bus wake-up threshold. 1 = LIN pull-up resistor enabled 0 = LIN pull-up resistor disabled LINOC LINOT TXDOM RXSHORT Figure 42. LIN Status LINS 33910 79 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS MOD2, MOD1 - Mode Control Bits These write-only bits select the Operating mode and allow to clear the watchdog in accordance with Table 38 Mode Control Bits. Table 40. Mode Control Bits MOD2 0 0 1 1 MOD1 0 1 0 1 Description Normal Mode Stop Mode Sleep Mode Normal Mode + watchdog Clear Any access to the MCR or voltage status register (VSR) will clear the BATFAIL flag. 1 = POR Reset has occurred 0 = POR Reset has not occurred Wake-up Control Register - WUCR This register is used to control the digital wake-up input. Writing the wake-up control register (WUCR) will return the wake-up status register (WUSR). Table 42. Wake-up Control Register - $2 C3 Write Reset Value Reset Condition 0 1 C2 0 1 C1 0 1 C0 L1WE 1 Voltage Status Register - VSR Returns the status of the several voltage monitors. This register is also returned when writing to the MCR. Table 41. Voltage Status Register - $0/$1 S3 Read VSOV POR, Reset mode or ext_reset S2 VSUV S1 VDDOT S0 BATFAIL L1WE - Wake-up Input Enable This write-only bit enables/disables the L1 input. In Stop and Sleep mode the L1WE bit activates the L1 input for wakeup. If the L1 input is selected on the analog multiplexer, the L1WE is masked to 0. 1 = Wake-up Input enabled. 0 = Wake-up Input disabled. Wake-up Status Register - WUSR This register is used to monitor the digital wake-up inputs and is also returned when writing to the wake-up control register (WUCR). Table 43. Wake-up Status Register - $2/$3 S3 Read - VSOV - VSUP Over-voltage This read-only bit indicates an over-voltage condition on the VS1 pin. 1 = Over-voltage condition. 0 = Normal condition. VSUV - VSUP Under-voltage This read-only bit indicates an under-voltage condition on the VS1 pin. 1 = Under-voltage condition. 0 = Normal condition. VDDOT - Main Voltage Regulator Over-temperature Warning This read-only bit indicates that the main voltage regulator temperature reached the Over-Temperature Prewarning Threshold. 1 = Over-temperature prewarning 0 = Normal BATFAIL - Battery Fail Flag. This read-only bit is set during power-up and indicates that the 33910 had a power on reset (POR). S2 - S1 - S0 L1 L1 - Wake-up input This read-only bit indicates the status of the L1 input. If the L1 input is not enabled then the wake-up status will return 0. After a wake-up form Stop or Sleep mode this bit also allows to verify the L1 input has caused the wake-up, by first reading the interrupt status register (ISR) and then reading the wake-up status register (WUSR). 1 = L1 Wake-up. 0 = L1 Wake-up disabled or selected as analog input. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 80 MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS LIN Control Register - LINCR This register controls the LIN physical interface block. Writing the LIN control register (LINCR) returns the LIN status register (LINSR). Table 44. LIN Control Register - $4 C3 Write Reset Value Reset Condition LDVS 0 POR, Reset mode or ext_reset LIN Status Register - LINSR This register returns the status of the LIN physical interface block and is also returned when writing to the LIN control register (LINCR). Table 46. LIN Status Register - $4/$5 C1 LSR1 0 C2 RXONLY 0 POR, Reset mode, ext_reset or LIN failure gone* C0 LSR0 0 Read S3 RXSHORT S2 TXDOM S1 LINOT S0 LINOC RXSHORT - RXD Pin Short Circuit This read-only bit indicates a short-circuit condition on the RXD pin (shorted either to 5.0 V or to Ground). The shortcircuit delay must be 8.0 µs worst case to be detected and to shutdown the driver. To clear this bit, it must be read after the condition is gone (transition detected on RXD pin). The LIN driver is automatically re-enabled once the condition is gone. 1 = RXD short circuit condition. 0 = None. TXDOM - TXD Permanent Dominant This read-only bit signals the detection of a TXD pin stuck at dominant (Ground) condition and the resultant shutdown in the LIN transmitter. This condition is detected after the TXD pin remains in dominant state for more than 1 second typical value. To clear this bit, it must be read after TXD has gone high. The LIN driver is automatically re-enabled once TXD goes High. 1 = TXD stuck at dominant fault detected. 0 = None. LINOT - LIN Driver Over-temperature Shutdown This read-only bit signals that the LIN transceiver was shutdown due to over-temperature. The transmitter is automatically re-enabled after the over-temperature condition is gone and TXD is high. The LINOT bit is cleared after SPI read once the condition is gone. 1 = LIN over-temperature shutdown 0 = None LINOC - LIN Driver Over-current Shutdown This read-only bit signals an over-current condition occurred on the LIN pin. The LIN driver is not shutdown but an IRQ is generated. To clear this bit, it must be read after the condition is gone. 1 = LIN over-current shutdown 0 = None POR * LIN failure gone: if LIN failure (over-temp, TXD/RXD short) was set, the flag resets automatically when the failure is gone. LDVS - LIN Dominant Voltage Select This write-only bit controls the LIN Dominant voltage: 1 = LIN Dominant Voltage = VLIN_DOM_1 (1.7 V typ) 0 = LIN Dominant Voltage = VLIN_DOM_0 (1.1 V typ) RXONLY - LIN Receiver Operation Only This write-only bit controls the behavior of the LIN transmitter. In Normal mode the activation of the RXONLY bit disables the LIN transmitter. In case of a LIN error condition this bit is automatically set. In Stop mode this bit disables the LIN wake-up functionality and the RXD pin will reflect the state of the LIN bus. 1 = only LIN receiver active (Normal mode) or LIN wakeup disabled (Stop mode). 0 = LIN fully enabled. LSRx - LIN Slew-Rate This write-only bit controls the LIN driver slew-rate in accordance with Table 45. Table 45. LIN Slew-Rate Control LSR1 0 0 1 1 LSR0 0 1 0 1 Description Normal Slew Rate (up to 20 kb/s) Slow Slew Rate (up to 10 kb/s) Fast Slew Rate (up to 100 kb/s) Reserved 33910 81 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS High Side Control Register - HSCR This register controls the operation of the high side drivers. Writing to this register returns the High Side Status Register (HSSR). Table 47. High Side Control Register - $6 C3 Write Reset Value Reset Condition PWMHS2 0 HSxCL - High Side Current Limitation This read-only bit indicates that the high side switch is operating in current Limitation mode. 1 = HSx in current limitation (or thermal shutdown) 0 = Normal Timing Control Register - TIMCR This register is a double purpose register which allows to configure the watchdog and the cyclic sense periods. Writing to the TIMCR will also return the WDSR. Table 49. Timing Control Register - $A C3 Write CS/WD CYST2 Reset Value Reset Condition 0 CYST1 0 CYST0 0 C2 PWMHS1 0 C1 HS2 0 C0 HS1 0 POR POR, Reset mode, ext_reset, HSx over-temp or (VSOV & HVSE) C2 WD2 C1 WD1 C0 WD0 PWMHSx - PWM Input Control Enable This write-only bit enables/disables the PWMIN input pin to control the high side switch. The high side switch must be enabled (HSx bit). 1 = PWMIN input controls HS1 output. 0 = HSx is controlled only by SPI. HSx - High Side Switch Control. This write-only bit enables/disables the high side switch. 1 = HSx switch on. 0 = HSx switch off. High Side Status Register - HSSR This register returns the status of the high side switch and is also returned when writing to the HSCR. Table 48. High Side Status Register - $6/$7 S3 Read HS2OP - POR CS/WD - Cyclic Sense or Watchdog Prescaler Select. This write-only bit selects which prescaler is being written to, the cyclic sense prescaler or the watchdog prescaler. 1 = Cyclic Sense Prescaler selected 0 = Watchdog Prescaler select WDx - Watchdog Prescaler This write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with Table 50. This configuration is valid only if windowing watchdog is active. Table 50. Watchdog Prescaler S2 HS2CL S1 HS1OP S0 HS1CL High Side thermal shutdown A thermal shutdown of the high side drivers is indicated by setting the HSxOP and HSxCL bits simultaneously. HSxOP - High Side Switch Open-Load Detection This read-only bit signals that the high side switch is conducting current below a certain threshold indicating possible load disconnection. 1 = HSx Open Load detected (or thermal shutdown) 0 = Normal WD2 0 0 0 0 1 1 1 1 WD1 0 0 1 1 0 0 1 1 WD0 0 1 0 1 0 1 0 1 Prescaler Divider 1 2 4 6 8 10 12 14 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 82 MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS CYSTx - Cyclic Sense Period Prescaler Select This write-only bits selects the interval for the wake-up cyclic sensing together with the bit CYSX8 in the configuration register (CFR) (see Configuration Register CFR). This option is only active if the high side switch is enabled when entering in Stop or Sleep mode. Otherwise a timed wake-up is performed after the period shown in Table 51. Table 51. Cyclic Sense Interval CYSX8(123) X 0 0 0 0 0 0 0 1 1 1 1 1 1 1 CYST2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 CYST1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 CYST0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 Interval No Cyclic Sense 20 ms 40 ms 60 ms 80 ms 100 ms 120 ms 140 ms 160 ms 320 ms 480 ms 640 ms 800 ms 960 ms 1120 ms 1 = Last reset caused by watchdog timeout 0 = None WDERR - Watchdog Error This read-only bit signals the detection of a missing watchdog resistor. In this condition the watchdog is using the internal, lower precision timebase. The windowing function is disabled. 1 = WDCONF pin resistor missing 0 = WDCONF pin resistor not floating WDOFF - Watchdog Off This read-only bit signals that the watchdog pin connected to GND and therefore disabled. In this case watchdog timeouts are disabled and the device automatically enters Normal mode out of Reset. This might be necessary for software debugging and for programming the Flash memory. 1 = Watchdog is disabled 0 = Watchdog is enabled WDWO - Watchdog Window Open This read-only bit signals when the watchdog window is open for clears. The purpose of this bit is for testing. Should be ignored in case WDERR is High. 1 = Watchdog window open 0 = Watchdog window closed Analog Multiplexer Control Register - MUXCR This register controls the analog multiplexer and selects the divider ration for the L1 input divider. Table 53. Analog Multiplexer Control Register -$C C3 Write Reset Value Reset Condition L1DS 1 POR Notes 123. bit CYSX8 is located in configuration register (CFR) Watchdog Status Register This register returns the watchdog status information and is also returned when writing to the TIMCR. Table 52. Watchdog Status Register - $A/$B S3 Read WDTO C2 MX2 0 C1 MX1 0 C0 MX0 0 S2 WDERR S1 WDOFF S0 WDWO POR, Reset mode or ext_reset L1DS - L1 Analog Input Divider Select WDTO - Watchdog Time Out This read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the watchdog within the window closed. Any access to this register or the TIMCR will clear the WDTO bit. This write-only bit selects the resistor divider for the L1 analog input. Voltage is internally clamped to VDD. 0 = L1 Analog divider: 1 1 = L1 Analog divider: 3.6 (typ.) 33910 83 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS MXx - Analog Multiplexer Input Select These write-only bits selects which analog input is multiplexed to the ADOUT0 pin according to Table 54. When disabled or when in Stop or Sleep mode, the output buffer is not powered and the ADOUT0 output is left floating to achieve lower current consumption. Table 54. Analog Multiplexer Channel Select MX2 0 0 0 0 1 1 1 1 MX1 0 0 1 1 0 0 1 1 MX0 0 1 0 1 0 1 0 1 Meaning Disabled Reserved Die Temperature Sensor VSENSE input L1 input Reserved Reserved Reserved Writing to the interrupt mask register (IMR) will return the ISR. Table 56. Interrupt Mask Register - $E C3 Write Reset Value Reset Condition HSM 1 C2 -. 1 POR C1 LINM 1 C0 VMM 1 HSM - High Side Interrupt Mask This write-only bit enables/disables interrupts generated in the high side block. 1 = HS Interrupts Enabled 0 = HS Interrupts Disabled LINM - LIN Interrupts Mask This write-only bit enables/disables interrupts generated in the LIN block. 1 = LIN Interrupts Enabled 0 = LIN Interrupts Disabled VMM - Voltage Monitor Interrupt Mask This write-only bit enables/disables interrupts generated in the voltage monitor block. The only maskable interrupt in the voltage monitor block is the VSUP over-voltage interrupt. 1 = Interrupts Enabled 0 = Interrupts Disabled Interrupt Source Register - ISR This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges the interrupt and leads IRQ pin to high, in case there are no other pending interrupts. If there are pending interrupts, IRQ will be driven high for 10µs and then be driven low again. This register is also returned when writing to the interrupt mask register (IMR). Table 57. Interrupt Source Register - $E/$F S3 Read ISR3 Configuration Register - CFR This register controls the cyclic sense timing multiplier. Table 55. Configuration Register - $D C3 Write Reset Value Reset Condition 0 0 POR, Reset mode or ext_reset C2 CYSX8 0 C1 0 0 C0 0 0 POR POR POR HVDD - Hall Sensor Supply Enable This write-only bit enables/disables the state of the hall sensor supply. 1 = HVDD on 0 = HVDD off CYSX8 - Cyclic Sense Timing x 8 This write-only bit influences the Cyclic Sense period as shown in Table 51. 1 = Multiplier enabled 0 = None Interrupt Mask Register - IMR This register allow to mask some of interrupt sources. The respective flags within the ISR will continue to work but will not generate interrupts to the MCU. The 5.0 V Regulator over-temperature prewarning interrupt and under-voltage (VSUV) interrupts can not be masked and will always cause an interrupt. S2 ISR2 S1 ISR1 S0 ISR0 ISRx - Interrupt Source Register These read-only bits indicate the interrupt source following Table 58. If no interrupt is pending than all bits are 0. In case more than one interrupt is pending, than the interrupt sources are handled sequentially multiplex. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 84 MC33910BAC / MC34910BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS Table 58. Interrupt Sources Interrupt Source ISR3 ISR2 ISR1 ISR0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Voltage monitor interrupt (Low-voltage and VDD over-temperature) none maskable no interrupt maskable no interrupt L1 wake-up from Stop modeHS interrupt (Over-temperature) Reserved LIN interrupt (RXSHORT, TXDOM, LIN OT, LIN OC) or LIN wake-up Voltage monitor interrupt (High-voltage) Forced wake-up lowest none highest Priority 33910 85 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC TYPICAL APPLICATIONS LOGIC COMMANDS AND REGISTERS TYPICAL APPLICATIONS The 33910 can be configured in several applications. The figure below shows the 33910 in the typical Slave Node Application. V D1 BAT VS1 VS2 C2 C1 VDD Interrupt Control Module LVI, HVI, HTI, OCI C4 C3 IRQ Internal Bus Voltage Regulator C5 AGND 5V Output Module HVDD Hall Sensor Supply VDD IRQ RST Reset Control Module LVR, HVR, HTR, WD, RST TIMER PWMIN Window Watchdog Module High Side Control Module R1 HS1 HS2 MISO MOSI SPI SCLK CS SPI & CONTROL Chip Temp Sense Module Analog Multiplexer VBAT Sense Module VSENSE MCU L1 Analog Input Module R2 A/D ADOUT0 Wake Up Module Digital Input Module RXD SCI TXD C6 LIN Physical Layer LIN LIN A/D R7 WDCONF PGND AGND LGND Typical Component Values: C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 220 pF R1 = 10 kΩ; R2 = 20 kΩ-200 kΩ Recommended Configuration of the not Connected Pins (NC): Pin 15, 16, 17, 19, 20, 21, 22 = GND Pin 11 = open (floating) Pin 28 = this pin is not internally connected and may be used for PCB routing optimization. 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 86 MC33910BAC / MC34910BAC PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under Available Documentation column select Packaging Information. AC SUFFIX (PB-FREE) 32-PIN LQFP 98ASH70029A REVISION D 33910 87 Analog Integrated Circuit Device Data Freescale Semiconductor MC33910BAC / MC34910BAC IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACKAGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTATION, PACKAGE DIMENSIONS (Continued) AC SUFFIX (PB-FREE) 32-PIN LQFP 98ASH70029A REVISION D 33910 Analog Integrated Circuit Device Data Freescale Semiconductor 88 MC33910BAC / MC34910BAC REVISION HISTORY REVISION HISTORY Revision 1.0 2.0 Date 5/2007 9/2007 Description of Changes • • • • • • • • • • • Initial Release Several textual corrections Page 11: “Analog Output offset Ratio” changed to “Analog Output offset” +/-22mV Page 11: VSENSE Input Divider Ratio adjusted to 5,0/5,25/5,5 Page 12: Common mode input impedance corrected to 75kΩ Page 13/15: LIN PHYSICAL LAYER parameters adjusted to final LIN specification release Revision number incremented at engineering request. Changed Functional Block Diagram on page 24. Datasheet updated according to the Pass1.2 silicon version electrical parameters Add Maximum Rating on IBUS_NO_GND parameter Added L1, Temperature Sense Analog Output Voltage per characterization(36), Internal Chip Temperature Sense Gain per characterization at 3 temperatures(36) See Figure 16, Temperature Sense Gain, VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization(36), and VSENSE Output Related Offset per characterization(36) parameters Added Temperature Sense Gain section Minor corrections to ESD Capability, (18), Cyclic Sense ON Time from Stop and Sleep Mode(45), Lin Bus Pin (LIN), Serial Data Clock Pin (SCLK), Master Out Slave In Pin (MOSI), Master In Slave Out Pin (MISO), Digital/ analog Pin (L1), Normal Request Mode, Sleep Mode, LIN Over-temperature Shutdown / TXD Stuck At Dominant / RXD Short-circuit:, Fault Detection Management Conditions, Lin Physical Layer, LIN Interface, Over-temperature Shutdown (LIN Interrupt), LIN Receiver Operation Only, SPI Protocol, L1 - Wake-up input 1, LIN Control Register - LINCR, and RXSHORT - RXD Pin Short-circuit Updated Freescale form and style Added explanation for pins Not Connected (NC). Changed VBAT_SHIFT and GND_SHIFT maximum from 10% to 11.5% for both parameters on page 13. Combined Complete Data sheet for Part Numbers MC33910BAC and MC34910BAC to the back of this data sheet. Changed ESD Voltage for Machine Model from ± 200 to ± 150 3.0 4.0 5.0 9/2007 2/2008 11/2008 • • • 6.0 7.0 8.0 2/2009 3/2009 3/2010 • • • • 33910 89 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. MC33910 Rev. 8.0 3/2010