33926_09

Freescale Semiconductor Advance Information Document Number: MC33926 Rev. 9.0, 12/2009 5.0 A Throttle Control H-Bridge The 33926 is a monolithic H-Bridge Power IC designed primarily for automotive electronic throttle control, but is applicable to any lowvoltage DC servo motor control application within the current and voltage limits stated in this specification. The 33926 is able to control inductive loads with currents up to 5.0 A peak. RMS current capability is subject to the degree of heatsinking provided to the device package. Internal peak-current limiting (regulation) is activated at load currents above 6.5 A ± 1.5 A. Output loads can be pulse width modulated (PWM’ed) at frequencies up to 20 kHz. A load current feedback feature provides a proportional (0.24% of the load current) current output suitable for monitoring by a microcontroller’s A/D input. A Status Flag output reports undervoltage, over-current, and over-temperature fault conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. Two independent disable inputs are provided to force the H-Bridge outputs to tri-state (high-impedance off-state). An inverted input changes the IN1 and IN2 inputs to LOW = true logic. Features 33926 AUTOMOTIVE THROTTLE H-BRIDGE ACTUATOR/ MOTOR EXCITER Bottom View SCALE 2:1 PNB SUFFIX (Pb-FREE) 98ARL10579D 32-PIN PQFN • 5.0 to 28 V continuous operation (transient operation from 5.0 to 40 V) • 225 mΩ maximum RDS(ON) @ 150°C (each H-Bridge MOSFET) ORDERING INFORMATION • 3.0 V and 5.0 V TTL / CMOS logic compatible inputs Temperature Device Package • Over-current limiting (Regulation) via an internal constant-off-time Range (TA) PWM MC33926PNB/R2 -40°C to 125°C 32 PQFN • Output short-circuit protection (short to VPWR or ground) • Temperature-dependent current-limit threshold reduction • All Inputs have an internal source/sink to define the default (floating input) states • Sleep mode with current draw < 50 µA (with inputs floating or set to match default logic states) • Pb-free packaging designated by suffix code PNB VDD VPWR 33926 SF FB IN1 IN2 VPWR CCP OUT1 MOTOR OUT2 PGND AGND MCU INV SLEW D1 D2 EN Figure 1. 33926 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VPWR LOGIC SUPPLY VDD CCP VCP CHARGE PUMP TO GATES HS1 HS2 OUT1 OUT2 EN IN1 IN2 D2 D1 INV SLEW SF FB AGND GATE DRIVE AND PROTECTION LOGIC HS1 LS1 HS2 LS2 VSENSE ILIM PWM LS1 LS2 PGND CURRENT MIRROR AND CONSTANT OFF-TIME PWM CURRENT REGULATOR PGND Figure 2. 33926 Simplified Internal Block Diagram 33926 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS VPWR OUT2 OUT2 OUT2 OUT2 CCP IN2 IN1 SLEW 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 D1 25 24 23 22 NC PGND PGND PGND SF PGND PGND PGND NC Transparent Top View of Package VPWR AGND VPWR INV FB NC AGND 21 20 19 18 10 11 12 13 14 15 16 OUT1 OUT1 OUT1 VPWR OUT1 EN D2 17 Figure 3. 33926 Pin Connections Table 1. 33926 Pin Definitions A functional description of each pin can be found in the Functional Description section beginning on page 12. Pin 1 Pin Name IN2 Pin Function Logic Input Formal Name Input 2 Definition Logic input control of OUT2; e.g., when IN2 is logic HIGH, OUT2 is set to VPWR, and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger input with ~ 80 μA source so default condition = OUT2 HIGH.) Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to VPWR, and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with ~ 80 μA source so default condition = OUT1 HIGH.) Logic input to select fast or slow slew rate. (Schmitt trigger input with ~ 80 μA sink so default condition = slow.) These pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the PCB. The low current analog signal ground must be connected to PGND via low impedance path (