33931

Freescale Semiconductor Advance Information Document Number: MC33931 Rev. 2.0, 12/2008 5.0 A Throttle Control H-bridge The 33931 is a monolithic H-bridge Power IC in a robust thermally enhanced package. It is designed primarily for automotive electronic throttle control, but is applicable to any low-voltage DC servo motor control application within the current and voltage limits stated in this specification. The 33931 H-bridge is able to control inductive loads with currents up to 5.0 A peak. RMS current capability is subject to the degree of heatsinking provided to the device package. Internal peak-current limiting (regulation) is activated at load currents above 6.5 A ±1.5 A. Output loads can be pulse width modulated (PWM-ed) at frequencies up to 11 kHz. A load current feedback feature provides a proportional (0.24% of the load current) current output suitable for monitoring by a microcontroller’s A/D input. A Status Flag output reports under-voltage, over-current, and over-temperature fault conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. The disable inputs are provided to force the Hbridge outputs to tri-state (high-impedance off-state). Features 33931 THROTTLE CONTROL H-BRIDGE VW SUFFIX (PB-FREE) 98ARH98330A 44-PIN HSOP WITH PROTRUDING HEAT SINK ORDERING INFORMATION Temperature Package 44 HSOP Device • 8.0 V to 28 V continuous operation (transient operation from Range (TA) 5.0 V to 40 V) MC33931VW/R2 -40°C to 125°C • 235 mΩ maximum RDS(ON) @ Tj=150°C (each H-bridge MOSFET) • 3.0 V and 5.0 V TTL / CMOS logic compatible inputs • Over-current limiting (regulation) via internal constant-off-time PWM • Output short-circuit protection (short to VPWR or GND) • Temperature-dependant current-limit threshold reduction • All inputs have an internal source/sink to define the default (floating input) states • Sleep mode with current draw < 50 µA (each half with inputs floating or set to match default logic states) VDD VPWR 33931 SF FB VPWR CCP OUT1 IN1 MOTOR OUT2 D1 EN/D2 PGND AGND MCU IN2 Figure 1. MC33931 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2008. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VPWR LOGIC SUPPLY VDD CCP VCP CHARGE PUMP TO GATES HS1 HS1 HS2 OUT1 OUT2 LS1 LS2 IN1 IN2 EN/D2 D1 SF FB AGND GATE DRIVE AND PROTECTION LOGIC LS1 HS2 LS2 VSENSE ILIM PWM PGND CURRENT MIRROR AND CONSTANT OFF-TIME PWM CURRENT REGULATOR PGND Figure 2. 33931 Simplified Internal Block Diagram 33931 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS AGND Tab D1 FB EN/D2 VPWR VPWR VPWR OUT1 OUT1 OUT1 PGND PGND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 SF IN1 IN2 CCP VPWR VPWR OUT2 OUT2 OUT2 PGND PGND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C Tab Figure 3. 33931 Pin Connections Table 1. 33931 Pin Definitions A functional description of each pin can be found in the Functional Description section beginning on page 11. Pin 1 Pin Name D1 Pin Function Logic Input Formal Name Disable Input 1 (Active High) Feedback Enable Input Definition When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger input with ~80 μA source so default condition = disabled. The load current feedback output provides ground referenced 0.24% of the high side output current. (Tie to GND through a resistor if not used.) When EN/D2 is logic HIGH the H-bridge is operational. When EN/D2 is logic LOW, the H-bridge outputs are tri-stated and placed in Sleep mode. (logic input with ~ 80 μA sink so default condition = Sleep mode.) These pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the PCB. Source of high side MOSFET1 and drain of low side MOSFET1. High-current power ground pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance ground plane on the PCB. Source of high side MOSFET2 and drain of low side MOSFET2. 2 3 FB EN/D2 Analog Output Logic Input 4-6,40,39 7-9 10,11,34,35 VPWR OUT1 PGND Power Input Power Output Power Ground Positive Power Supply H-bridge Output 1 Power Ground 36-38 OUT2 Power Output H-bridge Output 2 33931 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 33931 Pin Definitions (continued) A functional description of each pin can be found in the Functional Description section beginning on page 11. Pin 41 Pin Name CCP Pin Function Analog Output Logic Input Formal Name Charge Pump Capacitor Input 2 Definition External reservoir capacitor connection for the internal charge pump; connected to VPWR. Allowable values are 30 nF to 100 nF. Note: This capacitor is required for the proper performance of the device. Logic input control of OUT2;e.g., when IN2 is logic HIGH, OUT2 is set to VPWR, and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger Input with ~ 80 μA source so default condition = OUT2 HIGH.) Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to VPWR, and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with ~ 80 μA source so default condition = OUT1 HIGH.) Open drain active LOW Status Flag output (requires an external pull-up resistor to VDD. Maximum permissible load current < 0.5 mA. Maximum VCEsat < 0.4 V @ 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.) The low-current analog signal ground must be connected to PGND via lowimpedance path (