33932

Freescale Semiconductor Advance Information Document Number: MC33932 Rev. 3.0, 1/2009 5.0 A Throttle Control H-Bridge The 33932 is a monolithic H-Bridge Power IC in a robust thermally enhanced package. The 33932 has two independent monolithic HBridge Power ICs in the same package. They are designed primarily for automotive electronic throttle control, but are applicable to any lowvoltage DC servo motor control application within the current and voltage limits stated in this specification. Each H-bridge in the 33932 is able to control inductive loads with currents up to 5.0 A peak. RMS current capability is subject to the degree of heatsinking provided to the device package. Internal peakcurrent limiting (regulation) is activated at load currents above 6.5 A ±1.5 A. Output loads can be pulse width modulated (PWM-ed) at frequencies up to 11 kHz. A load current feedback feature provides a proportional (0.24% of the load current) current output suitable for monitoring by a microcontroller’s A/D input. A Status Flag output reports under-voltage, over-current, and over-temperature fault conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. Two independent disable inputs are provided to force the H-bridge outputs to tri-state (high-impedance off-state). Features 33932 THROTTLE CONTROL H-BRIDGE VW SUFFIX (PB-FREE) 98ARH98330A 44-PIN HSOP WITH PROTRUDING HEAT SINK ORDERING INFORMATION Device Temperature Range (TA) Package 44 HSOP MC33932VW/R2 -40°C to 125°C • 8.0 to 28 V continuous operation (transient operation from 5.0 to 40 V) • 235 mΩ maximum RDS(ON) @ 150°C (each H-Bridge MOSFET) • 3.0 V and 5.0 V TTL / CMOS logic compatible inputs • Over-current limiting (regulation) via internal constant-off-time PWM • Output short-circuit protection (short to VPWR or GND) • Temperature-dependant current-limit threshold reduction • All inputs have an internal source/sink to define the default (floating input) states • Sleep Mode with current draw < 50 µA (each half with inputs floating or set to match default logic states) VDD VPWR 33932 SFA FBA IN1 IN2 D1 EN/D2 VPWRA CCPA OUT1 MOTOR OUT2 PGNDA AGNDA IN3 IN4 D3 EN/D4 FBB SFB VDD PGNDB AGNDB VPWRB CCPB OUT3 MOTOR OUT4 VPWR MCU Figure 1. MC33932 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2009. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VPWRA LOGIC SUPPLY VDD CCPA VCP CHARGE PUMP TO GATES HS1 HS1 HS2 OUT1 OUT2 LS1 LS2 IN1 IN2 EN/D2 D1 SFA FBA AGNDA GATE DRIVE AND PROTECTION LOGIC LS1 HS2 LS2 VSENSE ILIM PWM PGND CURRENT MIRROR AND CONSTANT OFF-TIME PWM CURRENT REGULATOR H-Bridge A H-Bridge B LOGIC SUPPLY VDD PGNDA VPWRB CCPB VCP CHARGE PUMP TO GATES HS1 HS1 HS2 OUT3 OUT4 IN3 IN4 EN/D4 D3 SFB FBB GATE DRIVE AND PROTECTION LOGIC LS1 LS2 LS1 HS2 LS2 VSENSE ILIM PWM PGND CURRENT MIRROR AND CONSTANT OFF-TIME PWM CURRENT REGULATOR AGNDB PGNDB Figure 2. 33932 Simplified Internal Block Diagram 33932 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS AGNDA Tab D1 FBA EN/D2 VPWRA VPWRA VPWRA OUT1 OUT1 OUT1 PGNDA PGNDA PGNDB PGNDB OUT4 OUT4 OUT4 VPWRB VPWRB CCPB IN4 IN3 SFB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 H-BRIDGE A H-BRIDGE B 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 SFA IN1 IN2 CCPA VPWRA VPWRA OUT2 OUT2 OUT2 PGNDA PGNDA PGNDB PGNDB OUT3 OUT3 OUT3 VPWRB VPWRB VPWRB EN/D4 FBB D3 Tab AGNDB Figure 3. 33932 Pin Connections Table 1. 33932 Pin Definitions A functional description of each pin can be found in the Functional Description section beginning on page 11. Pin 1 2 3 Pin Name D1 FBA EN/D2 Pin Function Logic Input Analog Output Logic Input Formal Name Disable Input 1 (Active High) Feedback Enable Input Definition When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger input with ~80 μA source so default condition = disabled. H-Bridge A load current feedback output provides ground referenced 0.24% of the high side output current. (Tie to GND through a resistor if not used.) When EN/D2 is logic HIGH, H-Bridge A is operational. When EN/D2 is logic LOW, the H-Bridge A outputs are tri-stated and H-bridge A is placed in Sleep Mode. (logic input with ~ 80 μA sink so default condition = Sleep Mode.) These pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the PCB. H-bridge A source of high side MOSFET1 and drain of low side MOSFET1. High-current power ground pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance ground plane on the PCB. High-current power ground pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance ground plane on the PCB. 4-6,39,40 7-9 10,11,34,35 VPWRA VPWRB OUT1 PGNDA Power Input Power Output Power Ground Power Ground Positive Power Supply H-Bridge Output 1 Power Ground 12,13,32,33 PGNDB Power Ground 33932 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 33932 Pin Definitions (continued) A functional description of each pin can be found in the Functional Description section beginning on page 11. Pin 14-16 17,18,26-28 19 Pin Name OUT4 VPWRB CCPB Pin Function Power Output Power Input Analog Output Logic Input Logic Input Logic Output Open Drain Logic Input Analog Output Logic Input Formal Name H-Bridge Output 4 Positive Power Supply Charge Pump Capacitor Input 4 Input 3 Status Flag B (Active Low) Disable Input 3 (Active High) Feedback B Enable Input Definition H-bridge B Source of high side MOSFET2 and drain of low side MOSFET2. These pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the PCB. External reservoir capacitor connection for H-bridge B internal charge pump; connected to VPWRB. Allowable values are 30 to 100 nF. Note: This capacitor is required for the proper performance of the device. Logic input control of OUT4. Logic input control of OUT3. H-bridge B open drain active LOW Status Flag output (requires an external pullup resistor to VDD. Maximum permissible load current < 0.5 mA. Maximum VCEsat < 0.4 V @ 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.) When D3 is logic HIGH, both OUT3 and OUT4 are tri-stated. Schmitt trigger input with ~80 μA source so default condition = disabled. H-bridge B load current feedback output provides ground referenced 0.24% of the high side output current. (Tie to GND through a resistor if not used.) When EN/D4 is logic HIGH, H-bridge B is operational. When EN/D4 is logic LOW, the H-bridge B outputs are tri-stated and H-bridge B is placed in Sleep Mode. (logic input with ~ 80μA sink so default condition = Sleep Mode.) H-bridge B Source of high side MOSFET1 and drain of low side MOSFET1. H-Bridge A source of high side MOSFET2 and drain of low side MOSFET2. External reservoir capacitor connection for H-bridge A internal charge pump; connected to VPWRA. Allowable values are 30 to 100 nF. Note: This capacitor is required for the proper performance of the device. Logic input control of OUT2. Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to VPWRA, and when IN1 is logic LOW, OUT1 is set to PGNDA. (Schmitt trigger Input with ~ 80 μA source so default condition = OUT1 HIGH.) H-Bridge A open drain active LOW Status Flag output (requires an external pull-up resistor to VDD. Maximum permissible load current < 0.5 mA. Maximum VCEsat < 0.4 V @ 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.) The low-current analog signal ground must be connected to PGND via lowimpedance path (