33989

Freescale Semiconductor Technical Data Document Number: MC33989 Rev. 13.0, 3/2007 System Basis Chip with High-Speed CAN Transceiver The 33989 is a monolithic integrated circuit combining many functions used by microcontrollers (MCU) found in automotive Engine Control Units (ECUs). The device incorporates functions such as: two voltage regulators, four high voltage (wake up) inputs, a 1Mbaud capable CAN physical interface, an SPI interface to the MCU and VSUP monitoring and fault detection circuitry. The 33989 also provides reset control in conjunction with VSUP monitoring and the watchdog timer features. Also, an Interrupt can be generated, for the MCU, based on CAN bus activity as well as mode changes. Features • VDD1: Low Drop Voltage Regulator, Current Limitation, Overtemperature Detection, Monitoring, and Reset Function • VDD1: Total Current Capability 200 mA • V2: Tracking Function of VDD1 Regulator. Control Circuitry for External Bipolar Ballast Transistor for High Flexibility in Choice of Peripheral Voltage and Current Supply • Low Stand-By Current Consumption in Stop and Sleep Modes • High-Speed 1 MBaud CAN Physical Interface • Four External High Voltage Wake-up Inputs Associated with HS1 VBAT Switch • 150 mA Output Current Capability for HS1 VBAT Switch Allowing Drive of External Switches Pull-Up Resistors or Relays • VSUP Failure Detection • 40 V Maximum Transient Voltage • Pb Free designated by suffix code EG 33989 SYSTEM BASIS CHIP WITH HIGH-SPEED CAN DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42345B 28-PIN SOICW ORDERING INFORMATION Device MC33989DW/R2 - 40°C to 125°C MCZ33989EG/R2 28 SOICW Temperature Range (TA) Package 33989 5.0 V MCU VDD1 GND RST INT CS SCLK MOSI MISO CS SCLK MOSI MISO V2CTRL V2 HS1 L0 L1 L2 L3 WD CANH CANL VSUP VPWR V2 Local Module Supply Wake-Up Inputs Safe Circuits Twisted Pair CAN Bus SPI TX RX Figure 1. MC33989 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2007. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VSUP Monitor Dual Voltage Regulator VDD1 Monitor V2CTRL V2 VDD1 HS1 Control HS1 L0 L1 L2 L3 TX RX CAN H CAN L High Speed 1.0 MB/s CAN Physical Interface SPI Interface Programmable Wake-Up Inputs Oscillator Interrupt Watchdog Reset INT WD RST Mode Control CS SCLK MOSI MISO GND VSUP V2 Figure 2. 33989 Simplified Internal Block Diagram 33989 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS RX TX VDD1 RST INT GND GND GND GND V2 V2CTRL VSUP HS1 L0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 WD CS MOSI MISO SCLK GND GND GND GND CANL CANH L3 L2 L1 Figure 3. 33989 Pin Connections Table 1. 33989 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 18. Pin Number 1 2 3 Pin Name RX TX VDD1 Pin Function Output Input Power Output 4 5 6–9 20–23 10 11 RST INT GND V2 V2CTRL Output Output Ground Input Power Output 12 13 14–17 22 23 24 25 26 27 28 VSUP HS1 L0:L3 CANH CANL SCLK MISO MOSI CS WD Power Output Input Output Output Input Output Input Input Output Voltage Supply High Side One Level 0: 3 CAN High CAN Low System Clock Master In/Slave Out Master Out/Slave In Chip Select Watch Dog Formal Name Receive Data Transmit Data Voltage Digital Drain One Reset Interrupt Ground Voltage Source Two Voltage Control Definition CAN bus receive data output pin. CAN bus transmit data input pin. 5.0 V regulator output pin. Supply pin for the MCU. This is the device reset output pin whose main function is to reset the MCU. This pin has an internal pullup current source to VDD. This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. These device ground pins are internally connected to the package lead frame to provide a 33989-to-PCB thermal path. Sense input for the V2 regulator using an external series pass transistor. V2 is also the internal supply for the CAN transceiver. Output drive source for the V2 regulator connected to the external series pass transistor. Supply input pin for the 33989. Output of the internal high-side switch. The output current is internally limited to 150 mA. Inputs from external switches or from logic circuitry. CAN high output pin. CAN low output pin. Clock input pin for the Serial Peripheral Interface (SPI). SPI data sent to the MCU by the 33989. When CS is HIGH, the pin is in the high-impedance state. SPI data received by the 33989. The CS input pin is used with the SPI bus to select the 33989. The WD output pin is asserted LOW if the software watchdog is not correctly triggered. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Power Supply Voltage at VSUP Continuous (Steady-State) Transient Voltage (Load Dump) Logic Signals (RX, TX, MOSI, MISO, CS, SCLK, RST, WD, and INT) Output Current VDD1 HS1 Voltage Output Current ESD Voltage, Human Body Model HS1, L0, L1, L2, L3 All Other Pins ESD Voltage Machine Model All Pins Except CANH and CANL L0, L1, L2, L3 DC Input Voltage DC Input Current Transient Input Voltage with External Component (2) CANL and CANH Continuous Voltage CANL and CANH Continuous Current CANH and CANL Transient Voltage (Load Dump) (4) CANH and CANL Transient Voltage (5) Logic Inputs (TX and RX) ESD Voltage (HBM 100 pF, 1.5 k) CANL, CANH ESD Voltage Machine Model CANH and CANL VCANH/L ICANH/L VTRH/L VTRH/L V VESDCH VESDCM -200 to 200 VWUDC -0.3 to 40 -2.0 to 2.0 -100 to 100 -27 to 40 200 40 -40 to 40 -0.5 to 6.0 -4.0 to 4.0 V mA V V mA V V V KV V (1) Symbol Value Unit V VSUP VSUP VLOG I -0.3 to 27 -0.3 to 40 -0.3 to VDD1 + 0.3 Internally Limited V A V I -0.3 to VSUP + 0.3 Internally Limited V A kV VESDH VESDM - 4.0 to 4.0 -2.0 to 2.0 V ±200 Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, 1.5 k), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). 2. 3. 4. According to ISO 7637 specification. See Table 6, page 24. Load Dump test according to ISO 7637 part 1. Transient test according to ISO 7637 part 1, pulses 1, 2, 3a, and 3b according to schematic in Table 17, page 35. 33989 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings THERMAL RATINGS Operating Junction Temperature Storage Temperature Ambient Temperature Thermal Resistance Junction to GND Pins (5) (6) (7) Symbol Value Unit TJ TS TA RΘJ/P , TPPRT -40 to 150 -55 to 165 -40 to 125 20 Note 7. °C °C °C °C/W °C Peak Package Reflow Temperature During Reflow Notes 5. Ground pins 6, 7, 8, 9, 20, 21, 22, and 23 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standerd J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER INPUT (VSUP) Nominal DC Supply Voltage Range Extended DC Voltage Range 1 Reduced Functionality (8) Extended DC Voltage Range 2 (9) Input Voltage During Load Dump Load Dump Situation Input Voltage During Jump Start Jump Start Situation Supply Current in Standby Mode (10) (11) IOUT at VDD1 = 40 mA CAN recessive or Sleep-Disable State Supply Current in Normal Mode (10) Symbol Min Typ Max Unit VSUP VSUPEX1 5.5 — 18 V V 4.5 VSUPEX2 VSUPLD — VSUPJS — ISUP(STDBY) — ISUP(NORM) — ISUP(SLEEP1) (12) — — 5.5 27 V V 18 — 40 V — 27 mA 42 45 mA IOUT at VDD1 = 40 mA CAN recessive or Sleep-Disable State Supply Current in Sleep Mode (10) (11) VDD1 and V2 OFF, VSUP < 12 V, Oscillator Running Sleep-Disable State Supply Current in Sleep Mode (10) (11) VDD1 and V2 OFF, VSUP < 12 V, Oscillator Not Running (12) CAN in Sleep-Disable State Supply Current in Sleep Mode (10) (11) VDD1 and V2 OFF, VSUP > 12 V, Oscillator Running (12) CAN in Sleep-Disable State Supply Current in Stop Mode IOUT VDD1 < 2.0 mA (10) (11) VDD1 ON, VSUP < 12 V, Oscillator Running Sleep-Disable State (12) 42.5 45 µA CAN in ISUP(SLEEP2) — 72 105 µA — 57 90 ISUP(SLEEP3) — 100 150 µA ISUP(STOP1) — 135 210 µA CAN in ISUP(STOP2) CAN in ISUP(STOP3) Supply Current in Stop Mode IOUT VDD1 < 2.0 mA (11) VDD1 ON, VSUP < 12 V, Oscillator Not Running Sleep-Disable State (12) µA — 130 210 Supply Current in Stop Mode IOUT VDD1 < 2.0 mA (10) (11) VDD1 ON, VSUP > 12 V, Oscillator Running (12) CAN in Sleep-Disable State BATFAIL Flag Internal Threshold µA — 160 230 VBF 1.5 3.0 4.0 V Notes 8. VDD1 > 4.0 V, Reset high, Logic pin high level reduced, device is functional. 9. 10. 11. 12. Device is fully functional. All functions are operating. All modes available and operating. Watchdog, HS1 turn ON turn OFF, CAN cell operating, L0:L3 inputs operating, SPI read/write operation. Overtemperature may occur. Current measured at VSUP pin. With CAN cell in Sleep-Disable state. If CAN cell is Sleep-Enabled for wake-up, an additional 60 µA must be added to specified value. Oscillator running means Forced Wake-up or Cyclic Sense of Software Watchdog is Stop mode are not activated. 33989 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic BATFAIL Flag Hysteresis (13) Battery Fall Early Warning Threshold In Normal and Standby Mode Battery Fall Early Warning Hysteresis In Normal and Standby Mode POWER OUTPUT (VDD1) VDD1 Output Voltage IDD1 from 2.0 to 200 mA TAMB -40 to 125°C, 5.5 V < VSUP < 27 V (14) (13) Symbol VBF(HYS) BFEW Min — Typ 1.0 Max — Unit V V 5.3 BFEWH 0.1 5.8 6.3 V 0.2 0.3 VDD1OUT 4.9 VDD1OUT2 4.0 VDD1DRP — VDD1DRP2 — IDD1 200 TSD 160 — 200 285 350 0.1 0.25 0.2 0.5 — — 5.0 5.1 V VDD1 Output Voltage IDD1 from 2.0 to 200 mA, 4.5 V < VSUP < 5.5 V Dropout Voltage IDD1 = 200 mA Dropout Voltage, Limited Output Current IDD1 = 50 mA, 4.5 V < VSUP IDD1 Output Current Internally Limited Junction Thermal Shutdown Normal or Standby Modes Junction Over Temperature Pre-Warning VDDTEMP Bit Set Temperature Threshold Difference Reset Threshold 1 Selectable by SPI. Default Value After Reset. Reset Threshold 2 Selectable by SPI VDD1 Range for Reset Active Reset Delay Time Measured at 50% of Reset Signal Line Regulation (C at VDD1 = 47 µF Tantal) 9.0 V VSUP < 18, IDD = 10 mA Line Regulation (C at VDD1 = 47 µF Tantal) 5.5 < VSUP < 27 V, IDD = 10 mA Load Regulation (C at VDD1 = 47 µF Tantal) 1.0 mA < IIDD < 200 mA Thermal Stability VSUP = 13.5 V, 1 = -100 mA Not Tested (15) V V V mA °C TPW 125 — — 160 40 °C TSD - TPW RSTTH1 20 °C V 4.5 4.6 4.7 V RSTTH2 4.1 4.2 — — 4.0 30 4.3 — VDDR tD LR1 1.0 V µs — 5.0 25 mV LR2 — 10 25 mV LD — THERMS — 30 50 25 75 mV mV Notes 13. With CAN cell in Sleep-Disable state. If CAN cell is Sleep-Enabled for wake-up, an additional 60 µA must be added to specified value. 14. IDD1 is the total regulator output current. VDD specification with external capacitor. Stability requirement: C > 47 µF ESR < 1.3 Ω (tantalum capacitor). In reset, normal request, normal and standby modes. Measure with C = 47 µF Tantalum. 15. Guaranteed by design; however, it is not production tested. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER OUTPUT (VDD1) IN STOP MODE (16) VDD1 Output Voltage IDD1 < = 2.0 mA VDD1 Output Voltage IDD1 < = 10 mA IDD1 Stop Output Current to Wake-up SBC IDD1 Over Current to Wake-up Deglitcher Time Reset Threshold Reset Threshold Line Regulation (C at VDD1 = 47 µF Tantal) 5.5 V < VSUP < 27 V, IDD = 2.0 mA Load Regulation (C at VDD1 = 47 µF Tantal) 1 mA < IDD < 10 mA Max Decoupling Capacitor at VDD1 Pin, in Stop Mode(18) TRACKING VOLTAGE REGULATOR (V2) (19) (17) Symbol Min Typ Max Unit VDDSTOP 4.75 5.00 5.25 V VDDSTOP2 4.75 5.00 17 55 4.6 4.2 5.25 25 75 4.7 4.3 V IDD1SWU IDD1DGLT RSTSTOP1 RSTSTOP2 LRS 10 40 4.5 4.1 mA µs V V mV — LDS — 5.0 25 mV 15 — 75 200 µF VDDst-cap — V2 Output Voltage (C at V2 = 10 µF Tantal) I2 from 2.0 to 200 mA, 5.5 V < VSUP < 27 V I2 Output Current (for information only) Depending Upon External Ballast Transistor V2 Control Drive Current Capability Worst Case at TJ = 125°C V2LOW Flag Threshold LOGIC OUTPUT PIN (MISO) Low Level Output Voltage IOUT = 1.5 mA High Level Output Voltage IOUT = 250 µA Tri-Stated MISO Leakage Current 0 V < VMISO < VDD (20) V2 0.99 1.0 1.01 VDD1 I2 200 — — mA 12CTRL 0.0 — 4.0 10 4.25 mA V2LTH 3.75 V VOL 0.0 VOH VDD1-0.9 IHZ -2.0 — 2.0 — VDD1 — 1.0 V V µA Notes 16. If stop mode is used, the capacitor connected at VDD pin should not exceed the maximum specified by the “VDDst-cap” parameter. If capacitor value is exceeded, upon entering stop mode, VDD output current may exceed the IDDSWU and prevent the device to stay in stop mode. Guaranteed by design; however, it is not production tested. Guaranteed by design. V2 specification with external capacitor - Stability requirement: C > 42 µF and ESR < 1.3 Ω (Tantalum capacitor), external resistor between base and emitter required - Measurement conditions: Ballast transistor MJD32C, C = 10 µF Tantalum, 2.2 k resistor between base and emitter of ballast transistor Push/Pull structure with tri-state condition CS high. 17. 18. 19. 20. 33989 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic LOGIC INPUT PINS (MOSI, SCLK, CS) High Level Input Voltage Low Level Input Voltage High Level Input Current on CS Low Level Input Current on CS MOSI and SCLK Input Current RESET PIN (RST) (21) Symbol Min Typ Max Unit VIH VIL LIH LIL LN 0.7 VDD1 -0.3 -100 -100 -10 — — — — — VDD1 + 0.3 0.3 VDD1 -20 -20 10 V V µA µA µA High Level Output Current 0 < VOUT < 0.7 VDD Low Level Output Voltage (I0 = 1.5 mA) 5.5 V < VSUP < 27 V Low Level Output Voltage (I0 = 0 µA 1.0 V < VSUP < 5.5 V Reset Pull Down Current V > 0.9 V Reset Duration After VDD1 High WATCHDOG OUTPUT PIN (WD) (22) IOH -300 VOL 0.0 VOL 0.0 IPDW 2.3 RSTDUR 3.0 — 3.4 5.0 4.0 — 0.9 — 0.9 -250 -150 µA V V mA ms Low Level Output Voltage (I0 = 1.5 mA) 1.0 V < VSUP < 27 V High Level Output Voltage (I0 = 250 µA) INTERRUPT PIN (INT) (22) VOL 0.0 VOH VDD1-0.9 — — 0.9 VDD1 V V Low Level Output Voltage (I0 = 1.5 mA) High Level Output Voltage (I0 = 250 µA) HIGH SIDE OUTPUT PIN (HS1) RDSON at TJ = 25°C, and IOUT - 150 mA VSUP > 9.0 V RDSON at TA = 125°C, and IOUT - 150 mA VSUP > 9.0 V RDSON at TA = 125°C, and IOUT - 120 mA 5.5 < VSUP < 9.0 V Output Current Limitation HS1 Overtemperature Shutdown HS1 Leakage Current Output Clamp Voltage at IOUT = -10 mA No Inductive Load Drive Capability VOL VOH 0.0 VDD1-0.9 — — 0.9 VDD1 V V RON25 — RON125 — RON125-2 — LLIM OVT LLEAK VCL -1.5 — -0.3 160 155 — 3.5 — — — 5.5 500 190 10 — 4.5 2.0 2.5 Ω Ω Ω mA °C µA V Notes 21. Push/Pull structure with tri-state condition CS high. 22. Output pin only. Supply from VDD1. Structure switch to ground with pull-up current source. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic LOGIC INPUTS (L0:L3) Negative Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V Positive Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V Hysteresis 5.5 V < VSUP < 27 V Input Current -0.2 V < VIN < 40 V CAN SUPPLY (V2) Supply Current Cell Recessive State Supply Current Cell Dominant State without Bus Load Supply Current Cell, CAN in Sleep State Wake-up Enable V2 Regulator OFF Supply Current Cell, CAN in Sleep State Wake-up Disable V2 Regulator OFF (23) Notes 23. Push/Pull structure. IDIS — — 1.0 ISLEEP — 55 70 µA Symbol Min Typ Max Unit VTHN 2.0 2.5 2.7 VTHP 2.7 3.0 3.5 VHYS 0.6 LIN -10 — 10 — 1.3 3.3 4.0 4.2 3.8 4.6 4.7 2.5 3.0 3.2 3.0 3.6 3.7 V V V µA IRES — IDOM — 2.0 6.0 1.5 3.0 mA mA µA 33989 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic CANH AND CANL Bus Pins Common Mode Voltage Differential Input Voltage (Common Mode Between -3.0 and 7.0 V) Recessive State at RXD Dominant State at RXD Differential Input Hysteresis (RXD) Input Resistance Differential Input Resistance Unpowered Node Input Current CANH Output Voltage TXD Dominant State TXD Recessive State CANL Output Voltage TXD Dominant State TXD Recessive State Differential Output Voltage TXD Dominant State TXD Recessive State CANH AND CANL Output Current Capability (Dominant State) CANH CANL Overtemperature Shutdown CANL Over Current Detection Error Reported in CANR CANH Over Current Detection Error Reported in CANR TX AND RX TX Input High Voltage TX Input Low Voltage TX High Level Input Current, VTX = VDD TX Low Level Input Current, VTX = 0 V RX Output Voltage High, IRX = 250 µA RX Output Voltage Low, IRX = 1.0 mA VIH VILP LIH LIL VOH VOL 0.7 VDD -0.4 -10 -100 VDD-1 — — — — -50 — — VDD + 0.4 0.3 VDD 10 -20 — 0.5 V V µA µA V V ICANH/OC -200 — -60 ICANH ICANL TSHUT ICANL/OC 60 — 200 mA — 35 160 180°C — °C mA — -35 mA VDIFFD VDIFFR 1.5 — — — 3.0 100 V mV VCANLD VCANLR 0.5 2.0 — — 2.25 — VCANHD VCANHR 2.75 — — — 4.5 3.0 V VHYS RIN RIND ICANUP VCM VCANH-VCANL — 900 100 5.0 10 — — — — — — — 500 — — 100 100 1.5 mV KΩ KΩ mA V -27 — 40 V mV Symbol Min Typ Max Unit 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 7.0 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO) SPI Operation Frequency SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Falling Edge of CS to Rising Edge of SCLK Falling Edge of SCLK to Rising Edge of CS MOSI to Falling Edge of SCLK Falling Edge of SCLK to MOSI MISO Rise Time (CL = 220 pF) MISO Fall Time (CL = 220 pF) Time from Falling or Rising Edges of CS to: MISO Low Impedance MISO High Impedance Time from Rising Edge of SCLK to MISO Data Valid 0.2 V1 = = 0.8 V1, CL = 200 pF STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WD, INT) Delay Between CS Low to High Transition (End of SPI Stop Command) and Stop Mode Activation Detected by V2 OFF (24) Interrupt Low Level Duration SBC in Stop Mode Internal Oscillator Frequency All Modes Except Sleep and Stop (24) Symbol Min Typ Max Unit FREQ tPCLK tWSCLKH tWSCLKH tLEAD tLAG tSISU tSIH tRSO tFSO tSOEN tSODIS tVALID 0.25 250 125 125 100 100 40 40 — — — — — — — — — — 25 25 4.0 N/A N/A N/A N/A N/A N/A N/A 50 50 MHz ns ns ns ns ns ns ns ns ns ns — — — — 50 50 ns — — 50 tCSSTOP 18 tINT 7.0 OSCF1 — OSCF2 — WD1 8.58 WD2 39.6 WD3 88 WD4 308 f1ACC -12 — 12 350 392 100 112 45 50.4 9.75 10.92 100 — 100 — 10 13 — 34 µs µs kHz Internal Low Power Oscillator Frequency Sleep and Stop Modes (24) Watchdog Period 1 Normal and Standby Modes Watchdog Period 2 Normal and Standby Modes Watchdog Period 3 Normal and Standby Modes Watchdog Period 4 Normal and Standby Modes Watchdog Period Accuracy Normal and Standby Modes Notes 24. Guaranteed by design; however it is not production tested. kHz ms ms ms ms % 33989 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Normal Request Mode Timeout Normal Request Modes Watchdog Period 1 - Stop Stop Mode Watchdog Period 2 - Stop Stop Mode Watchdog Period 3 - Stop Stop Mode Watchdog Period 4 - Stop Stop Mode Stop Mode Watchdog Period Accuracy Stop Mode Cyclic Sense/FWU Timing 1 Sleep and Stop Modes Cyclic Sense/FWU Timing 2 Sleep and Stop Modes Cyclic Sense/FWU Timing 3 Sleep and Stop Modes Cyclic Sense/FWU Timing 4 Sleep and Stop Modes Cyclic Sense/FWU Timing 5 Sleep and Stop Modes Cyclic Sense/FWU Timing 6 Sleep and Stop Modes Cyclic Sense/FWU Timing 7 Sleep and Stop Modes Cyclic Sense/FWU Timing 8 Sleep and Stop Modes Cyclic Sense ON Time Sleep and Stop Modes Threshold and Condition to be Added Cyclic Sense/FWU Timing Accuracy Sleep and Stop Modes Delay Between SPI Command and HS1 Turn ON (25) Delay Between SPI Command and HS1 Turn OFF Delay Between SPI and V2 Turn ON Standby Mode Delay Between SPI and V2 Turn OFF (25) Normal Mode tSV2OFF 9.0 — 22 (25) (25) Symbol NRTOUT Min Typ Max Unit ms 308 WD1STOP 6.82 WD2STOP 31.5 WD3STOP 70 WD4STOP 245 f2ACC -30 CSFWU1 3.22 CSFWU2 6.47 CSFWU3 12.9 CSFWU4 25.9 CSFWU5 51.8 CSFWU6 66.8 CSFWU7 134 CSFWU8 271 350 392 ms 9.75 12.7 ms 45 58.5 ms 100 130 ms 350 455 % — 30 ms 4.6 5.98 ms 9.25 12 ms 18.5 24 ms 37 48.1 ms 74 96.2 ms 95.5 124 ms 191 248 ms 388 504 µs tON 200 350 500 tACC -30 — — — 30 22 22 % tSHSON tSHSOFF tSV2ON — — µs µs µs 9.0 — 22 µs Notes 25. Delay starts at falling edge of clock cycle #8 of the SPI command and start of Turn ON or Turn OFF of HS1 or V2. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Delay Between Normal Request and Normal Mode After WD Trigger Command Normal Request Mode Delay Between SPI and CAN Normal Mode SBC Normal Mode (26) Delay Between SPI and CAN Normal Mode SBC Normal Mode (26) Symbol tSNR2N Min Typ Max Unit µs 15 tSCANN — tSCANS — tWCS 15 tWSPI 90 tS1STSPI 20 35 70 µs — 10 µs — 10 µs Delay Between CS Wake-up (CS Low to High) and SBC Normal Request Mode (VDD1 on and Reset High) SBC in Stop Mode Delay Between CS Wake-up (CS Low to High) and First Accepted API Command SBC in Stop Mode Delay Between INT Pulse and First SPI Command Accepted In Stop Mode After Wake-up INPUT TERMINNALS (L0, L1, L2, AND L3) Wake-up Filter Time CAN MODULE-SIGNAL EDGE RISE AND FALL TIMES (CANH, CANL) Dominant State Timeout Propagation Loop Delay TX to RX, Recessive to Dominant Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Propagation Delay TX to CAN Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Propagation Delay CAN to RX, Recessive to Dominant Propagation Loop Delay TX to RX, Dominant to Recessive Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Propagation Delay TX to CAN Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Propagation Delay CAN to RX, Dominant to Recessive Notes 26. Guaranteed by design; however, it is not production tested. 40 90 µs — — N/A µs N/A tWUF 8.0 20 38 µs tDOUT tLRD 200 360 520 µs ns 70 80 100 110 tTRD 20 40 60 100 tRRD tLDR 70 90 100 130 tTDR 60 65 75 90 tRDR 20 30 140 155 180 220 210 225 255 310 ns 65 80 120 160 80 110 150 200 300 140 ns ns 120 135 160 200 170 180 220 260 ns 110 120 150 190 40 130 150 200 300 60 33989 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Non Differential Slew Rate (CANL or CANH) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 tSL3 tSL2 tSL1 tSL0 4.0 3.0 2.0 1.0 19 13.5 8.0 5.0 40 20 15 10 Symbol Min Typ Max Unit V/µs CANH CANL WU Receiver Pulse Width Filter Pulse OK Counter RST Latch RST WU OUT Narrow Pulse + Timeout Timeout Generator Standby Figure 4. Wake-Up Block Diagram The block diagram in Figure 4 illustrates how the wake-up signal is generated. First the CAN signal is detected by a low consumption receiver (WU receiver). Then the signal passes through a pulse width filter which discards the undesired pulses. The pulse must have a width bigger than 0.5 µs and smaller than 500 µs to be accepted. When a pulse is discarded the pulse counter is reset and no wake signal is generated, otherwise when a pulse is accepted the pulse counter is incremental and after three pulses the wake signal is asserted. Each one of the pulses must be spaced by no more than 500 µs. In that case the pulse counter is reset and no wake signal is generated. This is accomplished by the wake timeout generator. The wake-up cycle is completed (and the wake flag reset) when the CAN interface is brought to CAN Normal mode. The wake-up capability of the CAN can be disabled, refer to SPI interface and register section, CAN register. 1nF CANH Transient Pulse Generator (Note) 1nF GND GND 1nF LX 10 k Transient Pulse Generator (Note) GND CANL GND Note: Waveform in accordance to ISO 7637 part1, test pulses 1, 2, 3a and 3b. Note: Waveform in accordance to ISO 7637 part1, test pulses 1, 2, 3a and 3b. Figure 6. Transient Test Pulses for CANH/CANL Figure 5. Transient Test Pulse for L0:L3 Inputs 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS TX 0.8 V TTRD 2.0 V TTDR TLRD TX 0.8 V VDIFF 2.0 V 0.9 V 0.5 V VDIFF = VCANH - VCANL TLDR 2.0 V RX 0.8 V 0.9 V VDIFF TRRD TRDR 0.5 V 2.0 V RX 0.8 V Figure 7. Transceiver AC Characteristics 33989 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS tPCLK CS tLEAD tWCLKH tLAG SCLK tWCLKL tSISU tSIH MOSI Undefined tVALID tSOEN Di 0 Don’t Care Di 8 Don’t Care tSODIS MISO Do 0 Do 8 Notes: Incoming data at MOSI pin is sampled by the SBC at SCLK falling edge. Outgoing data at MISO pin is set by the SBC at SCLK rising edge (after tVALID delay time). Figure 8. SPI Timing Characteristics 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33989 is an integrated circuit dedicated to automotive applications. Its functions include: • One full protected voltage regulator with 200 mA total output current capability available at VDD1 external pin • Driver for an external path transistor for the V2 regulator function • Reset, programmable watchdog function, interrupt, and four operational modes • Programmable wake-up input and Cyclic Sense wake-up • CAN high-speed physical interface FUNCTIONAL PIN DESCRIPTION RECEIVE AND TRANSMIT DATA (RXD AND TXD) The RX and TX pins (receive data and transmit data pins, respectively) are connected to a microcontroller’s CAN protocol handler. TXD is an input and controls the CANH and CANL line state (dominant when TXD is LOW, recessive when TXD is HIGH). RXD is an output and reports the bus state (RXD LOW when CAN bus is dominant, HIGH when CAN bus is recessive). connect V2 to an external 5.0 V regulator or to the VDD1 output when no external series pass transistor is used. In this case, the V2CTRL pin must be left open. VOLTAGE SOURCE 2 CONTROL (V2CTRL) The V2CTRL pin is the output drive pin for the V2 regulator connected to the external series pass transistor. VOLTAGE SUPPLY (VSUP) VOLTAGE DIGITAL DRAIN ONE (VDD1) The VDD1 pin is the output pin of the 5.0 V internal regulator. It can deliver up to 200 mA. This output is protected against overcurrent and overtemperature. It includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130°C typical. When the temperature exceeds the overtemperature shutdown (170°C typical), the regulator is turned off. VDD1 includes an undervoltage reset circuitry, which sets the RST pin LOW when VDD1 is below the undervoltage reset threshold. The VSUP pin is the battery supply input of the device. HIGH-SIDE ONE (HS1) The HS1 pin is the internal high-side driver output. It is internally protected against overcurrent and overtemperature. LEVEL 0-3 INPUTS (L0:L3) The L0:L3 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be read by SPI. These inputs can be used as wake-up events for the SBC when operating in the Sleep or Stop mode. RESET (RST) The Reset pin RST is an output that is set LOW when the device is in reset mode. The RST pin is set HIGH when the device is not in reset mode. RST includes an internal pullup current source. When RST is LOW, the sink current capability is limited, allowing RST to be shorted to 5.0 V for software debug or software download purposes. CAN HIGH AND CAN LOW OUTPUTS (CANH AND CANL) The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TX input level, and the state of CANH and CANL is reported through RX output. A 60 Ω termination resistor is connected between CANH and CANL pins. INTERRUPT (INT) The Interrupt pin INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When an interrupt occurs, INT stays LOW until the interrupt source is cleared. INT output also reports a wake-up event by a 10 µs typical pulse when the device is in Stop mode. SYSTEM CLOCK (SCLK) SCLK is the System Clock input pin of the serial peripheral interface. MASTER IN SLAVE OUT (MISO) MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin. VOLTAGE SOURCE TWO (V2) The V2 pin is the input sense for the V2 regulator. It is connected to the external series pass transistor. V2 is also the 5.0 V supply of the internal CAN interface. It is possible to 33989 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION MASTER OUT SLAVE IN (MOSI) MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin. CHIP SELECT (CS) CS is the Chip Select pin of the serial peripheral interface. When this pin is LOW, the SPI port of the device is selected. WATCHDOG (WD) The Watchdog output pin is asserted LOW to flag that the software watchdog has not been properly triggered. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION DEVICE SUPPLY The device is supplied from the battery line through the VSUP pin. An external diode is required to protect against negative transients and reverse battery. It can operate from 4.5 V and under the jump start condition at 27 Vdc. This pin sustains standard automotive voltage conditions such as load dump at 40 V. When VSUP falls below 3.0 V typical the 33989 detects it and stores the information into the SPI register in a bit called BATFAIL. This detection is available in all operation modes. The device incorporates a battery early warning function, providing a maskable interrupt when the VSUP voltage is below 6.0 V typical. A hysteresis is included. Operation is only in Normal and Standby modes. VSUP low is reported in the Input/Output Register (IOR). however, depending upon the PNP gain an external resistorcapacitor network might be connected. The V2 is the supply input for the CAN cell. The state of V2 is reported in the IOR (bit V2LOW set to 1 if V2 is below 4.5 V typical). HS1 VBAT SWITCH OUTPUT The HS1 output is a 2.0 Ω typical switch from the VSUP pin. It allows the supply of external switches and their associated pull-up or pull down circuitry, in conjunction with the wake-up input pins, for example. Output current is limited to 200 mA and HS1 is protected against short-circuit and has an overtemperature shutdown (bit HS1OT in IOR and bit HS1OT-V2LOW in INT register). The HS1 output is controlled from the internal register and the SPI. Because of an internal timer, it can be activated at regular intervals in Sleep and Stop modes. It can also be permanently turned on in Normal or Standby modes to drive loads or supply peripheral components. No internal clamping protection circuit is implemented, thus a dedicated external protection circuit is required in case of inductive load drive. VDD1 VOLTAGE REGULATOR The VDD1 Regulator is a 5.0 V output voltage with output current capability up to 200 mA. It includes a voltage monitoring circuitry associated with a reset function. The VDD1 regulator is fully protected against overcurrent and short-circuit. It has over- temperature detection warning flags (bit VDDTEMP in MCR and interrupt registers), and overtemperature shutdown with hysteresis. BATTERY FALL EARLY WARNING Refer to the discussion under the heading: Device Supply. INTERNAL CLOCK V2 REGULATOR V2 Regulator circuitry is designed to drive an external path transistor increasing output current flexibility. Two pins are used to achieve the flexibility. Those pins are V2 and V2 control. The output voltage is 5.0 V and is realized by a tracking function of the VDD1 regulator. The recommended ballast transistor is MJD32C. Other transistors can be used; The device has an internal clock used to generate all timings (Reset, Watchdog, Cyclic Wake-up, Filtering Time, etc.). Two oscillators are implemented. A high accuracy (±12 percent) used in Normal Request, Normal and Standby modes, and a low accuracy (±30 percent) used in Sleep and Stop modes. OPERATIONAL MODES FUNCTIONAL MODES The device has four primary operation modes: 1. Standby mode 2. Normal mode 3. Stop mode 4. Sleep mode All modes are controlled by the SPI. An additional temporary mode called Normal Request mode is automatically accessed by the device after reset or wake-up from Stop mode. A Reset (RST) mode is also implemented. Special modes and configuration are possible for debug and program MCU flash memory. wake-up input reading through SPI and HS1 activation. The Watchdog is running. NORMAL MODE In this mode both regulators are ON. This corresponds to the normal application operation. All functions are available in this mode (Watchdog, wake-up input reading through SPI, HS1 activation, CAN communication). The software Watchdog is running and must be periodically cleared through SPI. STOP MODE Regulator 2 is turned OFF by disabling the V2 control pin. The regulator 1 is activated in a special low power mode, allowing to deliver few mA. The objective is to maintain the MCU of the application supplied while it is turned into power saving condition (i.e Stop or Wait modes). In Stop mode the device supply current from VBAT is very low. STANDBY MODE Only regulator 1 is ON. Regulator 2 is turned OFF by disabling the V2 control pin. Only the wake-up capability of the CAN interface is available. Other functions available are 33989 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES When the application is in Stop mode (both MCU and SBC), the application can wake-up from the SBC side (for example: cyclic sense, forced wake-up, CAN message, wake-up inputs and over current on VDD1), or the MCU side (key wake-up, etc.). Stop mode is always selected by the SPI. In Stop mode the software Watchdog can be running or idle depending upon selection by the SPI (RCR, bit WDSTOP). To clear the watchdog, the SBC must be awakened by a CS pin (SPI wake-up). In Stop mode, SBC wake-up capability are identical as in Sleep mode. Please refer to Table 5. the SBC is in Normal Request mode, the SBC goes back to Sleep mode. APPLICATION WAKE-UP FROM SBC SIDE When an application is in Stop mode, it can wake-up from the SBC side. When a wake-up is detected by the SBC (for example, CAN, Wake-up input, etc.) the SBC turns itself into Normal Request mode and generates an interrupt pulse at the INT pin. APPLICATION WAKE-UP FROM MCU SIDE When application is in Stop mode, the wake-up event may come from the MCU side. In this case the MCU signals to the SBC by a low to high transition on the CS pin. Then the SBC goes into Normal Request mode and generates an interrupt pulse at the INT pin. SLEEP MODE Regulators 1 and 2 are OFF. The current from VSUP pin is reduced. In this mode, the device can be awakened internally by cyclic sense via the wake-up inputs pins and HS1 output, from the forced wake-up function and from the CAN physical interface. When a wake-up occurs the SBC goes first into reset mode before entering Normal Request mode. STOP MODE CURRENT MONITOR If the VDD1 output current exceed an internal threshold (IDD1SWU), the SBC goes automatically into Normal Request mode and generates an interrupt at the INT pin. The interrupt is not maskable and the interrupt register will has no flag set. RESET MODE In this mode, the Reset (RST) pin is low and a timer is running for a time RSTDUR. After this time is elapsed, the SBC enters Normal Request mode. Reset mode is entered if a reset condition occurs (VDD1 low, watchdog timeout or watchdog trigger in a closed window). INTERRUPT GENERATION WHEN WAKE-UP FROM STOP MODE When the SBC wakes up from Stop mode, it first enters the Normal Request mode before generating a pulse (10 µs typical) on the INT pin. These interrupts are not maskable, and the wake-up event can be read through the SPI registers (CANWU bit in Reset Control Register (RCR) and LCTRx bit in Wake-Up Register (WUR). In case of wake-up from Stop mode over current or from forced wake-up, no bit is set. After the INT pulse the SBC accept SPI command after a time delay (tS1STSPI parameter). NORMAL REQUEST MODE This is a temporary mode automatically accessed by the device after the reset mode, or after the SBC wake-up from Stop mode. After wake-up from the Sleep mode or after the device power-up, the SBC enters the Reset mode before entering the Normal Request mode. After a wake-up from the Stop mode, the SBC enters Normal Request mode directly. In Normal Request mode the VDD1 regulator is ON, V2 is OFF, the reset pin is high. As soon as the device enters the Normal Request mode an internal 350 ms timer is started. During these 350 ms the microcontroller of the application must address the SBC via the SPI, configuring the Watchdog register. This is the condition for the SBC to stop the 350 ms timer and to go into the Normal or Standby mode and to set the watchdog timer according to configuration. SOFTWARE WATCHDOG IN STOP MODE If Watchdog is enabled, the MCU has to wake-up independently of the SBC before the end of the SBC watchdog time. In order to do this the MCU must signal the wake-up to the SBC through the SPI wake-up (CS activation). The SBC then wakes up and jumps into the Normal Request mode. MCU has to configured the SBC to go to either Normal or Standby mode. The MCU can then decide to go back again to Stop mode. When there is no MCU wake-up occurring within the watchdog timing, the SBC activates the Reset pin, jumping into the Normal Request mode. The MCU can then be initialized. NORMAL REQUEST ENTERED AND NO WD CONFIGURATION OCCURS In case the Normal Request mode is entered after SBC power-up, or after a wake-up from Stop mode, and if no WD configuration occurs while the SBC is in Normal Request mode, the SBC goes to Reset mode after the 350 ms time period is expired before again going into Normal Request mode. If no WD configuration is achieved, the SBC alternatively goes from Normal Request into reset, then Normal Request modes etc. In case the Normal Request mode is entered after a wakeup from Sleep mode, and if no WD configuration occurs while STOP MODE ENTER COMMAND Stop mode is entered at the end of the SPI message, and at the rising edge of the CS. Please refer to the t CSSTOP data in Dynamic Electrical Characteristics table on page 11. Once Stop mode is entered the SBC could wake-up from the V1 regulator over current detection. In order to allow time for the MCU to complete the last CPU instruction, allowing 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS the MCU to enter its low power mode, a deglitcher time of typical 40 µs is implemented. SPI Stop/ Sleep Command SPI CS Figure 9 indicates the operation to enter Stop mode. tCSSTOP IDD1DGLT SBC in Normal or Stand-by mode SBC in Stop mode no IDD1 over I wake-up SBC in Stop mode with IDD1over I wake-up Figure 9. Operation Entering Stop Mode RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS SOFTWARE WATCHDOG (SELECTABLE WINDOW OR TIMEOUT WATCHDOG) Software watchdog uses in the SBC Normal and Standby modes is to monitor MCU. The Watchdog can be either window or timeout. This is selectable by SPI (register TIM1, bit WDW). Default is window watchdog. The period for the watchdog is selectable from the SPI from 10 ms to 350 ms (register TIM1, bits WDT0 and WDT1). When the window watchdog is selected, the closed window is the first part of the selected period, and the open window is the second part of the period. Refer to the SPI TIM register description. Watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the closed window will generate a reset. Watchdog is cleared through SPI by addressing the TIM1 register. Table 5. Reset and Watchdog Output Operation Events Devices Power-up VDD1 Normal Watchdog Properly Triggered VDD1 < RSTTH Watchdog Timeout Reached VDD1 Normal Watchdog Properly Triggered VDD1 < RSTTH Watchdog Timeout Reached Mode 1 or 2 (Safe Mode) 1 1 1 2 (Safe Mode) 2 (Safe Mode) 2 (Safe Mode) WD Output Low to High High High Low (Note) High High Low (Note) Reset Output Low to High High Low Low High Low High RESET PIN DESCRIPTION A reset output is necessary and available to reset the microcontroller. Modes 1 and 2 are available for the reset pin (please refer to Table 5 for reset pin operation). Reset causes when SBC is in mode 1: • VDD1 falling out of range — If VDD1 falls below the reset threshold (parameter RSTTH), the ret pin is pulled low until VDD1 returns to the normal voltage. • Power-on reset — At device power-on or at device wakeup from Sleep mode, the reset is maintained low until VDD1 is within its operation range. Watchdog timeout — If watchdog is not cleared, the SBC will pull the reset pin low for the duration of the reset time (parameter RSTDUR). Notes 27. WD stays low until the Watchdog register is properly addressed through SPI. In Mode 2, the reset pin is not activated in case of Watchdog timeout. Please refer to Table 6 for more detail. For debug purposes at 25°C, the Reset pin can be shorted to 5.0 V because of its internal limited current drive capability. RESET AND WATCHDOG OPERATION: MODES1 AND 2 Watchdog and Reset functions have two modes of operation: 33989 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS 1. Mode 1 2. Mode 2 (also called Safe mode) These modes are independent of the SBC modes (Normal, Standby, Sleep, and Stop). Modes 1 and 2 selection is achieved through the SPI (register MCR, bit SAFE). Default mode after reset is Mode 1. Table 5 provides Reset and Watchdog output mode of operation. Two modes (modes 1 and 2) are available and can be selected through the SPI Safe bit. Default operation, after reset or power-up, is Mode 1. In both modes reset is active at device power-up and wake-up. • In mode 1–Reset is activated in case of VDD1 fall or watchdog not triggered. WD output is active low as soon as reset goes low. It remains low as long as the watchdog is not properly re-activated by the SPI. • In mode 2–(Safe mode) Reset is not activated in case of watchdog fault. WD output has the same behavior as in mode 1–The Watchdog output pin is a push-pull structure driving external components of the application for signal instance of an MCU wrong operation. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS Table 6. Table of Operation Mode Voltage Regulator HS1 Switch VDD1:ON V2:OFF HS1:OFF VDD1:ON V2:ON HS1:Controllable Wake-up Capabilities (if enabled) — Reset Pin INT Software Watchdog — CAN Cell Normal Request Normal Low for Reset-DUR Time, then High Normally High Active Low if WD or VDD1 under voltage occurs (and mode 1 selected) Same as Normal Mode Normally High Active Low if WD (29) — — — If Enabled, Signal Failure (VDD1 PreWarning Temp, CAN, HS1) Same as Normal Mode Signal SBC Wakeup and IDD > IDD1S/WU (Not Maskable) Running Tx/Rx Standby VDD1:ON V2:OFF HS1:Controllable VDD1:ON (Limited Current Capability) V2:OFF HS1:OFF or Cyclic — Running Low Power Stop CAN SPI L0:L3 Cyclic Sense Forced Wake-up IDD1 Over Current (28) Running if Enabled Low Power Not Running if Wake-up Capability Disabled if Enabled or VDD1 Under Voltage Occurs Sleep VDD1:OFF V2:OFF HS1:OFF or Cyclic CAN SPI L0:L3 Cyclic Sense Forced Wake-up — Low Not Active Not Running Low Power Wake-up Capability if Enabled Debug Normal Same as Normal Normally High Active Low if VDD1 Under Voltage Occurs Normally High Active Low if VDD1 Under Voltage Occurs Normally High Active Low if VDD1 Under Voltage Occurs Not Operating Same as Normal Not Running Same as Normal Debug Standby Same as Standby — Same as Standby Not Running Same as Standby Stop Debug Same as Stop Same as Stop Same as Stop Not Running Same as Stop Flash Programming Forced Externally — Not Operating Not Operating Not Operating Notes 28. Always enable. 29. If enabled. 33989 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS Watchdog Timeout VDD1 RST MODE 1 WD SPI WD Clear SPI CS Watchdog Period MODE 2 RST WD Figure 10. Reset and Watchdog Functions Diagram in Modes 1 and 2 Watchdog Register Addressed WAKE-UP CAPABILITIES Several wake-up capabilities are available for the device when it is in Sleep, or Stop modes. When a wake-up has occurred, the wake-up event is stored into the WUR or CAN registers. The MCU can then access to the wake-up source. The wake-up options are able to be selected through the SPI while the device is in Normal or Standby mode and prior to entering low power mode (Sleep or Stop mode). When a wake-up occurs from sleep mode the device activates VDD1. It generates an interrupt if wake-up occurs from Stop mode. internal timer. Cyclic Sense and Forced Wake-up are exclusive. If Cyclic Sense is enabled the forced wake-up can not be enabled. In order to select and activate the cyclic sense wake-up from the Lx inputs the WUR register must be configured with the appropriate level sensitivity, and the LPC register must be configured with 1xx1 data (bit LX2HS1 set at 1 and bit HS1AUTO set at 1). The wake-up mode selection (direct or cyclic sense) is valid for all 4 wake-up inputs. FORCED WAKE-UP WAKE-UP FROM WAKE-UP INPUTS (L0:L3) WITHOUT CYCLIC SENSE The wake-up lines are dedicated to sense external switch states and if changes occur to wake-up the MCU (in Sleep or Stop modes). The wake-up pins are able to handle 40 V DC. The internal threshold is 3.0 V typical and these inputs can be used as an input port expander. The wake-up inputs state are read through SPI (register WUR). In order to select and activate direct wake-up from the LX inputs, the WUR register must be configured with the appropriate level sensitivity. Additionally, the LPC register must be configured with 0x0 data (bits LX2HS1and HS1AUTO are set at 0). Level sensitivity is selected by WUR register. Level sensitivity is configured by a pair of Lx inputs: L0 and L1 level sensitivity are configured together while L2 and L3 are configured together. The SBC can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and Forced wake-up are exclusive. If Forced wake-up is enabled (FWU bit set to 1 in LPC register) the Cyclic Sense can not be enabled. CAN INTERFACE WAKE-UP The device incorporates a high-speed 1MBaud CAN physical interface. Its electrical parameters for the CANL, CANH, RX and TX pins are compatible with ISO 11898 specification (IS0 11898: 1993(E)). The control of the CAN physical interface operation is accomplished through the SPI. CAN modes are independent of the SBC operation modes. The device can wake-up from a CAN message if the CAN wake-up is enabled. Please refer to the CAN module description for detail of wake-up detection. SPI WAKE-UP CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND WAKE-UP INPUTS L0, L1, L2, L3) The SBC can wake-up upon state change of one of the four wake-up input lines (L0, L1, L2 and L3) while the external pull-up or pull down resistor of the switches associated to the wake-up input lines are biased with HS1 VSUP switch. The HS1 switch is activated in Sleep or Stop modes from an The device can wake-up by the CS pin in Sleep or Stop modes. Wake-up is detected by the CS pin transition from low to a high level. In Stop mode, this corresponds with the condition where the MCU and SBC are in Stop mode; and when the application wake-up event comes through the MCU. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS DEVICE POWER-UP, SBC WAKE-UP After device or system power-up, or after the SBC wakes up from Sleep mode, it enters into Reset mode prior to moving into Normal Request mode. DEBUG MODE: HARDWARE AND SOFTWARE DEBUG WITH THE SBC When the SBC is mounted on the same printed circuit board as the microcontroller it supplies, both application software and SBC dedicated routine must be debugged. The following features allow debug of the software by allowing the possibility of disabling the SBC internal software Watchdog timer. DEVICE POWER-UP, RESET PIN CONNECTED TO VDD1 At SBC power-up the VDD1 voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs every 350 ms. In order to allow software debug and avoid MCU reset, the Reset pin can be connected directly to VDD1 by a jumper. DEBUG MODES WITH SOFTWARE WATCHDOG DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY AND STOP DEBUG) The Watchdog software can be disabled through SPI. To avoid unwanted watchdog disable while limiting the risk of disabling Watchdog during SBC normal operation, the watchdog disable must be achieved the following sequence: • Step 1–Power down the SBC VSUP VDD1 Batfail TIM1(Step 3) SPI MCR(Step4) Debug Mode MCR (Step5) • Step 2–Power-up the SBC (The BATFAIL bit is set, allowing the SBC to enter Normal Request mode) • Step 3–Write to TIM1 register allowing SBC entering Normal mode • Step 4–Write to MCR register with data 0000, enabling the Debug mode. Complete SPI byte: 000 1 0000 • Step 5–Write to MCR register normal debug (0001x101) • Step 6–To leave the Debug mode, write 0000 to MCR register While in Debug mode, the SBC can be used without having to clear the WD on a regular basis to facilitate software and hardware debug. At Step 2, the SBC is in Normal Request. Steps 3, 4, and 5 should be completed consecutively and within the 350 ms time period of the Normal Request mode. If this step is not accomplished in a timely manner, the SBC will go into Reset mode, entering Normal Request again. When the SBC is in Debug mode, and set in Stop Debug or Sleep Debug, when a wake-up occurs the SBC enters Normal Request mode for a time period of 350 ms. To avoid the SBC generating a reset (enter Reset mode) the desired next Debug mode (Normal Debug or Standby Debug) should be configured within the 350 ms time period of the Normal Request mode. For details, please refer to State Machine in Debug mode, Figure 16. To avoid entering Debug mode after a power-up, first read BATFAIL bit (MCR read) and write 0000 into MCR. Figure 15 illustrates the Debug mode enter. MCR (Step6) SPI: Read Batfail SBC in Debug Mode, No WD Figure 11. Debug Mode Enter SBC Not in Debug Mode and WD ON MCU FLASH PROGRAMMING CONFIGURATION To download software into the application memory (MCU EEPROM or Flash) the SBC capabilities allows the VDD1 to be forced by an external power supply to 5.0 V; the reset and WD outputs by external signal sources are forced to zero or 5.0 V, both without damage. This allows, for example, supply of the complete application board by external power supply, applying the correct signal to reset pins. No function of the SBC is operating. Due to pass transistor from VDD1 to VSUP, supplying the device from VDD1 pin biases the VSUP pin. Therefore, VSUP should not be forced to a value above 5.0 V. The Reset pin is periodically pulled low for RSTDUR time (3.4 ms typical) before being pulled to VDD1 for 350 ms typical. During the time reset is low, the reset pin sinks 5.0 mA maximum (LPDW parameter). 33989 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS VDD1 VSUP (Open or > 5.0 V SBC RST WD MCU = Flash Programming Bus External supply and sources applied to VDD1, RST, and WD test points on application circuit board. Figure 12. Simplified Schematic for Flash Programming PACKAGE AND THERMAL CONSIDERATION The device is proposed in a standard surface mount SOIC28 package. In order to improve the thermal performances of the SOIC28 package, eight pins are internally connected to the lead frame and are used for heat transfer to the printed circuit board. Table 6, page 24, describes the SBC operation modes. Normal, Stand-by, and Stop Debug modes are entered through special sequence described in the Debug mode paragraph. WD: Timeout OR VDD1 Low W D: Reset Counter (3.4 ms) Expired 2 Timeout & Nostop 1 SPI: Stand-by & WD Trigger 3 Reset 1 Normal W D: Ti m Stand-by Nostop & SPI: Sleep & CS Low to High Nostop & SPI: Sleep & CS Low Power- SP to I: S H to ig p h& Tr C an S si L o tio w n Power Down V DD 1L ow (3 0) 1 Wake-up ut O R 2 Stop WD: Timeout OR VDD1 Low SPI: Stop & CS Low to High Transition Normal 1 Wake-up (VDD1 High Temperature OR (VDD11 Low > 100ms & VSUP >BFew)) & Nostop &!BATFAIL 1 2 3 4 denotes priority SPI: Normal eo SPI: Stand-by VDD1 Low OR WD: Timeout 350 ms &!Nostop 4 W SBC g rig :T D er Sleep STATE MACHINE DESCRIPTION: 28. Nostop = Nostop bit = 1 29. ! Nostop = Nostop bit = 0 30. BATFAIL = Batfail bit = 1 31. ! BATFAIL = Batfail bit = 0 32. VDD1 Over Temperature = VDD1 thermal shutdown occurs 33. 34. 35. VDD1 low = VDD1 below reset threshold VDD1 low >100 ms = VDD1 below reset threshold for more than 100 ms WD: Trigger = TIM1 register write operation. Figure 13. State Machine (Not Valid in Debug Modes) Notes These two SPI commands must be sent consecutively in this sequence. 30. If WD activated. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS Power-Up Behavior after power-up if no trigger appears Behavior after reset of BATFAIL if no trigger appears Reset Normal Request No Trigger Yes Normal Yes No Batfail No Yes No Stop Sleep Figure 14. Behavior at SBC Power-Up WD: Timeout 350 ms Normal Request WD: Trigger Reset Counter (3.4 ms) Expired Reset Power Down Normal SPI: MCR (0000) & Normal Debug Normal Debug SPI: MCR (0000) & Stand-by Debug Stand-by Debug Figure 15. Transitions to Enter Debug Modes 33989 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS WD: Time-out 350 ms Wake-up Stop (1) R W ak eu p Normal Request SPI: Stand-by & WD: Trigger Reset Counter (3.4 ms) Expired Reset Wake-up Sleep &!BATFAILNOSTOP & SPI: Sleep R WD : Tr R igg e r R R R SPI: Stop Stand-by SPI: Stop Debug & CS Low to High Transition eb E ug SP I: ma lD E SPI: SPI: Stand-by Debug Stand-by Debug SPI: Normal Debug Normal Debug R R (1) If Stop mode entered, it is entered without watchdog, no matter the WDSTOP bit. (E) Debug mode entry point (Step 5 of the Debug mode entering sequence). (R) Represents transitions to Reset mode due to VDD1 low. Figure 16. Simplified State Machine in Debug Modes LOGIC COMMANDS AND REGISTERS SPI INTERFACE AND REGISTER DESCRIPTION Table 7 illustrates a register, an 8-bit SPI. The first three bits are used to identify the internal SBC register address. Bit four is a read/write bit. The last four bits are Data Send from MCU to SBC, or read back from SBC to MCU. There is no significance during write operation state of MISO. During read operation only the final four bits of MISO have a meaning (content of the accessed register). The following tables describe the SPI register list, and register bit meaning. Registers reset value is also described along with the reset condition. Reset condition is the condition causing the bit to be set at the reset value. Table 7. Data Format Description Bit 7 A2 Bit 6 A1 Bit 5 A0 Bit 4 R/W Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 SBC Mode: Read operation: R/W Bit = 0 Write operation: R/W Bit = 1 Possible reset conditions include: SBC Reset: Power-On Reset POR SBC Mode Transition: NR2R - Normal Request to Reset Mode NR2N - Normal Request to Normal Mode NR2STB - Normal Request to Standby Mode N2R - Normal to Reset Mode STB2R - Standby to Reset Mode STO2R - Stop to Reset Mode STO2NR - Stop to Normal Request RESET - SBC in Reset Mode SPI: Normal Debug or St an d SP I: N -b y D eb ug Stop Debug Stand-by Normal 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 8. List of Registers Name MCR Address $000 Description Mode Control Register Comment and Use Write: Control of Normal, Standby, Sleep, Stop, Debug Modes Read: BATFAIL flag and other status bits and flags RCR $001 Reset Control Register Write: Configuration for reset voltage level, Safe bit, Stop mode Read: CAN wake-up and CAN failure status bits CAN $010 CAN Control Register Write: CAN module control: TX/RX and Sleep modes, slope control, wake enable/disable Read: CAN wake-up and CAN failure status bits IOR $011 I/O Control Register Write: HS1 (High Side switch) control in Normal and Standby mode Read: HS1 over temp bit, VSUP and V2 Low status WUR $100 Wake-up Input Register Timing Register Write: Control of wake-up input polarity Read: Wake-up input and real time LX input state Write: TIM1, Watchdog timing control, window, or Timeout mode Write: TIM2, Cyclic sense and force wake-up timing selection LPC $110 Low Power Mode Control Register Interrupt Register Write: Control HS1 periodic activation in Sleep and Stop modes, force wake-up Write: Interrupt source configuration Read: INT source TIM $101 INT $111 33989 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Mode Control Register (MCR) Table 9 provides Mode Control Register data. Table 9. MCR Register MCR $000B W R Reset Value Reset Condition D3 — BATFAIL (31) — — D2 MCTR2 VDDTEMP 0 POR, RESET D1 MCTR1 GFAIL 0 POR, RESET D0 MCTR0 WDRST 0 POR, RESET Notes 31. Bit BATFAIL cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0 V. Table 10. MCR Control Bits MCTR2 0 MCTR1 0 MCTR0 0 SBC Mode Enter/Exit Debug Mode Description To enter/exit Debug Mode, refer to detail Debug Mode: Hardware and Software Debug... 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 1 Normal Standby Stop, Watchdog OFF (32) — — — — — No watchdog running, Debug Mode Stop, Watchdog ON (32) Sleep (33) Normal Standby Stop Notes 32. Watchdog ON or OFF depends on RCR bit D3. 33. Before entering Sleep mode, bit BATFAIL in MCR must be previously cleared (MCR read operation), and bit NOSTOP in RCR must be previously set to 1. Table 11. MCR Status Bits Status Bits GFAIL Description Logic OR of CAN Failure (TXF Permanent Dominant, or CAN Over Current or CAN thermal), or HS1 Over Temperature, or V2 Low Battery Fail Flag (set when VSUP < 3.0 V) Temperature Pre-Warning on VDD (latched) Watchdog Reset Occurred BATFAIL VDDTEMP WDRST 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Reset Control Register (RCR) Table 12 provides Reset Control Register data while Table 13 outlines the RCR Control Bits, and Table 14 provides RCR Status Bits data. Table 12. RCR Register RCR $001B W R Reset Value Reset Condition 1 POR,RST, STO2NR 0 POR, NR2N NR2STB 0 POR 0 POR D3 WDSTOP D2 NOSTOP D1 SAFE D0 RSTTH Table 13. RCR Control Bits SAFE 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 1 WD Timeout V1 Drops Below RSTTH V1 Normal, WD Properly Triggered WD Pin 0 Reset Pin 0=>1 Device Power-Up Condition Table 14. RCR Status Bits Status Bits WDSTOP Bit Value 0 1 NOSTOP 0 1 RSTTH 0 1 No Watchdog in Stop Mode Watchdog Runs in Stop Mode Device Cannot Enter Sleep Mode Sleep Mode Allowed, Device Can Enter Sleep Mode Reset Threshold 1 Selected (typ 4.6 V) Reset Threshold 2 Selected (typ 4.2 V) Description CAN Register (CAN) Table 15 provides control of the high-speed CAN module, mode, slew rate, and wake-up. Table 15. CAN Register CAN $010B W R Reset Value Reset Condition D3 — CANWU — — D2 SC1 TXF 0 POR D1 SC0 CUR 0 POR D0 MODE THERM 0 POR 33989 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS High-Speed CAN Transceiver Modes The mode bit (D0) controls the state of the CAN module, Normal or Sleep modes. Please see Table 16. SC0 bit (D1) defines the slew rate when the CAN module is in Normal Table 16. CAN High-Speed Transceiver Modes SC1 0 0 1 1 x x SC0 0 1 0 1 1 0 MODE 0 0 0 0 1 1 mode, and controls the wake-up option (wake-up enable or disable) when the CAN module is in Sleep mode. CAN module modes (Normal and Sleep) are independent of the SBC modes. Please see Table 17. CAN Mode CAN Normal, Slew Rate 0 CAN Normal, Slew Rate 1 CAN Normal, Slew Rate 2 CAN Normal, Slew Rate 3 CAN Sleep and CAN Wake-up Disable CAN Sleep and CAN Wake-up Enable Table 17. CAN Status Bits Status Bits CANWU TXF CUR(1) THERM CAN Wake-up Occurred Permanent Dominant TX CAN Transceiver in Current Limitation CAN Transceiver in Thermal Shutdown Description • Return to CAN NORMAL Error bits are latched in the CAN registers. Bit (1) CUR is set to 1 when the CAN interface is programmed into CAN NORMAL for the first time after V2 turn ON. To clear the CUR bit, follow this procedure: • Turn V2 ON (SBC in Normal mode and V2 above V2 threshold) the CAN interface must be set into CAN Sleep Table 18. IOR Register IOR $011B W R Reset Value Reset Condition D3 — V2LOW — — D2 HS1ON HS1OT 0 POR D1 — VSUPLOW — — D0 — DEBUG — — Input/Output Control Register (IOR) Table 18 provides data about HS1 control in Normal and Standby modes, while Table 19 provides control bit data. Table 19. IOR Control Bits HS1ON 0 1 HS1 OFF, in Normal and Standby Modes HS1 ON, in Normal and Standby Modes HS1 State When HS1 is turned OFF due to an over temperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error bits are latched in the Input/ Output Registers (IOR). Please see Table 20. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 20. IOR Status Bits Status Bit V2LOW HS1OT VSUPLOW DEBUG V2 Below 4.0 V High Side 1 Over Temperature VSUP Below 6.1 V If Set, SBC Accepts Command to go to Debug Modes (No WD) Description Wake-up Input Register (WUR) The local wake-up inputs, L0, L1, L2, and L3 can be used in both Normal and Standby modes as port expander, as well Table 21. WUR Register WUR $100B W R Reset Value Reset Condition D3 LCTR3 L3WU 0 as and for waking up the SBC in Sleep or Stop modes. Please see Table 21. D2 LCTR2 L2WU 0 D1 LCTR1 L1WU 0 D0 LCTR0 L0WU 0 POR, NR2R, N2R, STB2R, STO2R The wake-up inputs can be configured separately, while L0 and L1 are configured together. Bits L2 and L3 are configured together. Please see Table 22. Table 22. WUR Control Bits LCTR3 x x x x 0 0 1 1 LCTR2 x x x x 0 1 0 1 LCTR1 0 0 1 1 x x x x LCTR0 0 1 0 1 x x x x L0/L1 Config Inputs Disabled High Level Sensitive Low Level Sensitive Both Level Sensitive — Inputs Disabled High Level Sensitive Low Level Sensitive Both Level Sensitive L2/L3 Config — Table 23 provides Status bits data. Table 23. WUR Status Bits Status Bit L3WU L2WU L1WU L0WU Notes: Status bits have two functions. After SBC wake-up, they indicate the wake-up source (Example: L2WU set at 1 if wake-up source is L2 input). After SBC wake and once the WUR has been read, status bits indicates the real time state of the LX inputs (1 mean LX is above threshold, 0 means that LX input is below threshold). If, after a wake-up from LX input, a WD timeout occurs before the first reading of the WUR register, the LXxWU bits are reset. This can occur only if SBC was in Stop mode. Description Wake-up Occurred (Sleep/Stop Modes), Logic State on Lx (Standby/Normal Modes) 33989 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Timing Register (TIM1/2) This register is composed of two registers: 1. TIM1–controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0. Please see Table 24. 2. TIM2–is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is read operation it is not allowed in either TIM1 or TIM2 registers. Please see Table 26. Table 24. TIM1 Register TMI1 $101B W R Reset Value Reset Condition D3 0 — — — D2 WDW — 0 POR, RST D1 WDT1 — 0 POR, RST D0 WDT0 — 0 POR, RST Table 25. TIM1 Control Bits WDW 0 0 0 0 1 1 1 1 WDT1 0 0 1 1 0 0 1 1 WDT0 0 1 0 1 0 1 0 1 Timing (ms) 10 45 100 350 10 45 100 350 Parameter Watchdog Period 1 Watchdog Period 2 Watchdog Period 3 Watchdog Period 4 Watchdog Period 1 Watchdog Period 2 Watchdog Period 3 Watchdog Period 4 Window Watchdog Enabled (Window Length is Half the Watchdog Timing) No Window Watchdog Window Open for Watchdog Clear WD Timing x 50% WD Timing x 50% Watchdog Period (WD Timing Selected by TIM1 Bit WDW=1) Watchdog Period (WD Timing Selected by TIM1 Bit WDW=1) Figure 17. Window Watchdog Table 26. TIM2 Register TMI2 $101B W R Reset Value Reset Condition D3 1 — — — D2 CSP2 — 0 POR, RST Figure 18. Timeout Watchdog D1 CSP1 — 0 POR, RST D0 CSP0 — 0 POR, RST 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 27. TIM1 Control Bits CSP2 0 0 0 0 1 1 1 1 CSP1 0 0 1 1 0 0 1 1 CSP0 0 1 0 1 0 1 0 1 Cyclic Sense Timing (ms) 5 10 20 40 75 100 200 400 Parameter Cyclic Sense/FWU Timing 1 Cyclic Sense/FWU Timing 2 Cyclic Sense/FWU Timing 3 Cyclic Sense/FWU Timing 4 Cyclic Sense/FWU Timing 5 Cyclic Sense/FWU Timing 6 Cyclic Sense/FWU Timing 7 Cyclic Sense/FWU Timing 8 Low Power Mode Control Register (LPC) Cyclic Sense on Time HS1 ON HS1 Cyclic Sense Timing, Off Time 10 µs HS1 OFF Lx Sampling Point Sample This register controls: • The state of HS1 in Stop and Sleep mode (HS1 permanently off or HS1 cyclic) • Enable or disable the forced wake-up function (SBC automatic wake-up after time spend in Sleep or Stop modes, time is defined by the TIM2 register) • Enable or disable the sense of the wake-up inputs (Lx) at sampling point of the Cyclic Sense period (LX2HS1 bit). t Figure 19. HS1 Operation when Cyclic Sense is Selected Table 28. LPC Register LPC $110B W R Reset Value Reset Condition D3 LX2HS1 — 0 POR, NR2R N2R,STB2RSTO2R D2 FWU — 0 POR, NR2R N2R,STB2RSTO2R D1 — — — — D0 HS1AUTO — 0 POR, NR2R N2R,STB2RSTO2R Please refer to the Cyclic Sense Wake-up discussion for details of the LPC register setup required for proper Cyclic Sense or direct wake-up operation. Table 29. LX2HS1 Control Bits LX2HS1 0 1 Wake-Up Inputs Supplied by HS1 No Yes, Lx Inputs Sensed at Sampling Point Table 30. HS1AUTO Control Bits HS1AUTO 0 1 Auto Timing HS1 in Sleep and Stop Modes OFF ON, HS1 Cyclic, Period Defined in TIM2 Register 33989 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Interrupt Register (INT) This register allows masking or enabling the interrupt source. A read operation informs about the interrupt source. Table 31. INT Register INT $111B W R Reset Value Reset Condition D3 VSUPLOW VSUPLOW 0 POR, RST D2 HS1OT-V2LOW HS1OT 0 POR, RST D1 VDDTEMP VDDTEMP 0 POR, RST D0 CANF CANF 0 POR, RST Table 32. INT Control Bits Control Bit CANF VDDTEMP HS1OT - V2LOW VSUPLOW Mask Bit for CAN Failures Mask Bit for VDD Medium Temperature (Pre-Warning) Mask Bit for HS1 Over Temperature AND V2 Below 4.0 V Mask Bit for VSUP Below 6.1 V Description When the mask bit is set, INT pin goes low if the appropriate condition occurs. Table 33. INT Status Bits Status Bit CANF VDDTEMP HS1OT VSUPLOW CAN Failure VDD Medium Temperature (pre-warning) HS1 Over Temperature VSUP Below 6.1 V Description 1. Bit D2 = 1: INT source is HS1OT 2. Bit D2 = 0: INT source is V2LOW HS1OT and V2LOW bits status are available in IOR. Upon a wake-up condition from Stop mode due to over current detection (IDD1SW-U1 or IDD1S-WU2), an INT pulse is generated; however, INT register content remains at 0000 (not bit set into the INT register). The status bit of the INT register content is a copy of the IOR and CAN registers status content. To clear the INT register bit the IOR and/or CAN register must be cleared (read register). Once this operation is done at IOR and CAN register the INT register is updated. Errors bits are latched in the CAN register and IOR. If HS1OT - V2LOW interrupt is only selected (only bit D2 set in INT register), reading INT register bit D2 leads to two possibilities: 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 37 TYPICAL APPLICATIONS TYPICAL APPLICATIONS MC33989, SBC High Speed Typical Application Schematic VBAT R6 D1 Rp R1 SW1 to L0 C6 HS1 L0 Q1 V2 VSUP C1 C2 Vsup monitor Dual Voltage Regulator Vdd1 Monitor V2CTRL 5V/200mA C10 Vdd1 C4 C5 V2 HS1 control Mode control Oscillator Int Watchdog Reset V2 C3 INT WD Rp R2 SW2 to L1 C7 L1 L2 L3 Programmable wake-up input RST MOSI SCLK MISO CS V2 MCU SPI Interface CANH CANL SW3 R3 to L2 Rd C8 Internal Module Supply Clamp(1) R4 to L3 Rd Connector C9 1Mbit/s CAN Physical Interface TX RX GND Safe Circuitry SW4 Detail of CAN standard termination schematic (not split termination) CANH (SBC) CANH CH L1 CANL CL R5 120 ohms CANL (SBC) Component values: D1: Q1: MJD32C R1,R2,R3,R4: 10k R5: 120 Rp, Rd: R6: 2.2k C1: 10uF C2: 100nF C3: 47uF C4: 100nF C5: 47uF tantal C6,C7,C8,C9,C10: 100nF CL, CH: 220 pF CAN Connector Detail of CAN split termination schematic CANH CH L1 CANL CL CANH (SBC) R6, 60 ohms R7, 60 ohms CANL (SBC) CS CAN Connector Figure 20. Typical Application Diagram 33989 38 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES SUPPLEMENTAL APPLICATION NOTES MC33989 - GENERAL INFORMATION MC33989 device supply on page 39 Voltage Regulator on page 40 Failure on VDD1, Watchdog, Reset, INT Pins on page 41 CAN Driver Overtemperature: on page 52 Overcurrent Detection: on page 52 Protection on page 52 Current in Case of Bus Short Conditions on page 52 WAKE-UP TIMINGS - SLEEP MODE LX Wakes up SBC from Sleep Mode on page 42 CAN Wake-Up on page 42 LX with Cyclic Sense on page 43 SOFTWARE ASPECTS Introduction on page 54 How to Enter in Normal Mode After a Power-Up on page 55 How to Change CAN Slew Rate on page 55 WAKE UP TIMING: STOP MODE LX Wake-Up on page 43 CAN Wake-Up on page 44 CS Wake-Up on page 44 Overcurrent Wake-Up on page 44 LX with Cyclic Sense on page 45 How to Set the CAN Interface in Sleep Mode on page 55 How to Control HS1 Output on page 55 How to Configure Wake-Up Before Going in Low Power Mode on page 56 Disable all Wake-Up on page 56 How to Enter in Sleep Mode on page 57 How to Enter in Stop Mode with Watchdog on page 57 How to Enter in Stop Mode without Watchdog on page 57 How to Recognize and Distinguish the Wake-Up Source on page 58 How to Use the Interrupt Function on page 59 Recognition and Recovery on page 59 How to Distinguish Between V2LOW and HS1 Overtemperature on page 59 MC33989 CAN INTERFACE Block Diagram on page 45 CAN Interface Supply on page 46 Main Operation Modes Description on page 46 CAN Driver Operation in Normal Mode on page 46 CAN Mode versus SBC Modes on page 48 How to Test the MC33989 CAN Interface on page 48 CAN LOW POWER MODE AND WAKE-UP Low Power Mode on page 49 Wake-Up on page 49 GENERAL INFORMATION The parameters given in the application section are for information only. Reference the electrical tables beginning on page 4 for actual operating parameters. MC33989 device supply FAILURE ON V2 SUPPLY, CAN BUS LINES, AND TX PIN V2LOW on page 51 TX Permanent Dominant on page 51 The MC33989 is supplied from the battery line. A serial diode is necessary to protect the device against negative transient pulses and from reverse battery situation. This is illustrated in the device typical application schematic. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 39 TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES Voltage Regulator The MC33989 contains two 5 V regulators: The V1 regulator, fully integrated and protected, and the V2 regulator Q1 R1 C5 which operates with an external ballast transistor. This is illustrated in the following device typical application schematic. Auxiliary 5V C6 Components list: C1: 22uF, C2: 100nF C3: >10uF C4: 100nF C5: >10uF C6: 100nF R1: 2.2k Rt: 60 - 120 Rp0 to Rp3: 22k Rs0 to Rs3: 22 k CL0 to CL3: 10nF Q1: MJD32C C1 V2CTRL V2 C2 VSUP HS1 WD VDD1 Safe circuitry C3 RST C4 VDD RST INT Rp0 S0 Rs0 CL0 L0 L1 L2 L3 CANH MC33989 INT CS MISO MOSI SCK TX RX GND SPI MCU CAN bus Rt CANL CAN GND Figure 21. Device Typical Application Schematic V1 Regulator The V1 regulator is 5 V output, 2% accuracy with current capability of 200 mA max. It requires external decoupling and stabilizing capacitors. The minimum recommended value are: • C4: 100 nF • C3: 10 µF < C3 < 22 µF, esr < 1 ohms. 22 µF < C3 < 47 µF, esr < 5 ohms. C3 > = 47 µF, esr < 10 ohms V2 Regulator: Operation with External Ballast Transistor The V2 regulator is a tracking regulator of the V1 output. Its accuracy relative to V1 is ±1%. It requires external decoupling and stabilizing capacitors. The recommended value are: 22 µF esr < 5 ohms, and 47 µF esr < 10 ohms. The V2 pin has two functions: sense input for the V2 regulator and 5 V power supply input to the CAN interface. Ballast transistor selection: PNP or PMOS transistors can be used. A resistor between base and emitter (or source and drain) is necessary to ensure proper operation and optimized performances. Recommended bipolar transistor is MJD32C. V2 Regulator: Operation without Ballast Transistor The external ballast transistor is optional. If the application does not requires more than the maximum output current capability of the V1 regulator, then the ballast transistor can be omitted. The thermal aspects must be analyzed as well. The electrical connections are shown in Figure 22. no connect V2CTRL VSUP V2 Components list: C1: 22uF, C2: 100nF C3: >10uF C4: 100nF C1 C2 MC33989 VDD1 Partial View RST C3 C4 VDD RST MCU partial view Figure 22. V2 Regulator Operation 33989 40 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES Failure on VDD1, Watchdog, Reset, INT Pins The paragraphs below describe the behavior of the device and of the INT, RST, and WD pins at power up and under failure of VDD1. Power Up and SBC Entering Normal Operation After a power-up the SBC enters in Normal request mode (CAN interface is in TX/RX mode): VDD1 is on, V2 is off. After 350 ms if no watchdog is written (no TIM1 register write) a reset occurs, and the SBC returns to normal request mode.During this sequence WD is active (low level). Once watchdog is written the SBC goes to normal mode: VDD1 is still on and V2 turns on, WD is no longer active and the reset pin is high. If the watchdog is not refreshed, the SBC generates a reset and returns to Normal request mode. VDD1 Write Watchdog each X ms No Watchdog is written SPI (CS) WD 350 ms RST INT SBC in RESET mode SBC in Normal request mode Reset every 350 ms SBC in Normal mode SBC in Normal request mode SBC in Normal mode Figure 23. Power Up and SBC Entering Normal Operation Power Up and VDD1 Going Low with Stop Mode as Default Low Power Mode Selected The first part of the following figure is identical to the above. If VDD1 is pulled below the VDD1 under voltage reset (typ 4.6 V) for instance by an overcurrent or short circuit (ex short to 4 V), and if a low power mode previously selected was stop mode, the SBC enters reset mode (reset pin is active). The pin WD stays high, but the high level (VOH) follows the VDD1 level. The interrupt pin goes low. When the VDD1 overload condition is removed, the SBC restarts in Normal request mode. VDD1 Write Watchdog each X ms No problem on Watchdog period SPI (CS) WD 350 ms 350 ms RST INT SBC in RESET mode SBC in Normal request mode Reset every 350 ms SBC in Normal mode SBC in Reset mode SBC in Normal Request mode Figure 24. Power Up and VDD1 Going Low with Stop Mode as Default Low Power Mode Selected 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 41 TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES Power Up and VDD1 Going Low with Sleep Mode as Default Low Power Mode Selected The first part of the graph is the same as the previous figure. If VDD1 is pulled below the VDD1 under voltage reset (typ 4.6 V) for instance by an over current or short circuit (ex short to 4 V), and if the low power mode previously selected was sleep mode and if the BATFAIL flag has been cleared, the SBC enters reset mode for a time period of 100 ms. The pin WD stays high, but the high level (VOH) follows the VDD1 level.The reset and interrupt pins are low. After the 100 ms, the SBC goes into sleep mode. VDD1 and V2 are off (The following figure is an example where VDD1 is shorted to 4 V, and after 100 ms the SBC enters sleep mode. VDD1 Write Watchdog each X ms No problem on Watchdog period SPI (CS) WD 350 ms 100 ms RST INT S B C in S le e p m o d e S B C in R e s e t m ode (B A T F A IL fla g m u s t b e c le a re d ) S B C in RESET m ode S B C in N o rm a l re q u e s t m ode Reset every 350 ms S B C in N o rm a l m ode Figure 25. Power up and VDD1 Going Low with Sleep Mode as Default Low Power Mode Selected WAKE-UP TIMINGS — SLEEP MODE The paragraphs below describe the wake-up events from sleep mode, and the sequence of the signals at the SBC level. The wake-up time described is the time from the wakeup event to the SBC reset pin release. The wake-up time is the sum of several timings: wake-up signal detection, VDD1 regulator start-up and decoupling capacitor charge, and reset time. At the end of the reset time, the reset pin goes from low to high and the MCU is ready to start software operations. LX Wakes up SBC from Sleep Mode Below is the case where the SBC is in sleep mode and is awaked by LX positive edge. LX VDD1 RST t1 t2 t3 Figure 26. • T1 (LX high level to VDD1 turn on): typ 100 µs. • T2: VDD1 rising time is dependent on the capacitor and the load connected to VDD1. It can be approximated by the capacitor charging time with the regulator output current limitation: T2 = (C x U)/I. With C = 100 mF, IDD1 = 200 mA min., U = 5 V so T2 = 2.5 ms). • T3 (VDD1>RST-TH (4.6 V by default) to reset high): parameter Rest dur: 4 ms max. • The total time is 6.6 ms in this example. CAN Wake-Up The following case describes the signal for CAN wake up. Refer to page 49 for more details on CAN wake up signals and the TCAN analysis. 33989 42 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES CAN VDD1 RESET RST tCAN t1 t2 t3 Figure 27. CAN Wake-Up LX with Cyclic Sense • T1(third valid CAN dominant pulse to VDD1 turn on): typ The case below is a description of the wake-up by LX input 80 µs. associated with the cyclic sense function. • T2 and T3 identical to page 39 above • The total time is 6.58 ms in this example. LX HS1 VDD1 RESET RST t1 t2 t3 t4 Figure 28. level. The wake-up time described is the time from the wakeup event to the SBC INT pin. The wake-up time is the sum of • T1: Is dependent on the selected cyclic sense timing in several timings: wake-up signal detection, the INT pulse, and the TIM2 register (5 ms to 400 ms). LX is sampled a minimum delay between INT and SBC ready to operate. At • 10 µs before the end of cyclic sense on time. If the LX the end of the wake-up time, the SBC is ready to operate, correct wake-up level happens just after the sample however the MCU might have already been in a restart • point, the wake-up will be detected at the next HS1 operation. activation and a complete period is lost. • T2: It is the same time as LX to VDD1 turn on: typ 100 µs • T3 & T4: same as page 39 • The total time is 11.5 ms (for a cyclic sense total time of 5 ms) in this example. LX Wake-Up Below is the case where the SBC is in stop mode and is awakened by an LX positive edge • T1(L0 high level to INT pulse): typ 100 µs. • The total time is 133 µs in this case. WAKE-UP TIMING: STOP MODE The following paragraphs describe the wake-up events from stop mode, and the sequence of the signals at the SBC 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 43 TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES L0 INT t1 tINT + tS-1STSPI (33µs max) Wake-up signalled to MCU. SBC ready to accept SPI command. Figure 29. Lx Wake-Up CAN Wake-Up The case below describes the signal for CAN wake-up. Refer to page 49 for more details on CAN wake-up signals and the TCAN analysis. CAN INT tCAN t1 tINT + tS-1STSPI (33µs max) Wake-up signalled to MCU. Figure 30. CAN Wake-Up CS Wake-Up • TCAN: refer to page 49 for more details. • T1: Third pulse on CAN to INT pulse: typ 80 µs. • The total time is 113 µs in this case. SBC ready to accept SPI command. The figure below describes the wake up from a CS signal transition, while the SBC is in stop mode. CS INT T1 tINT + tS-1STSPI (33µs max) Wake-up signalled to MCU. SBC ready to accept SPI command. Figure 31. CS Wake-Up Overcurrent Wake-Up • T1: CS rising edge to INT pulse: typ 60 µs. • The total time is 133 µs in this case. The following figure describes the signal when an overcurrent is detected at VDD1. A VDD1 overcurrent condition will lead to a wake-up from stop mode. 33989 44 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES IDD1S-WU (17 mA typ) IDD1 current INT t1 t2 tINT + tS-1STSPI (33µs max) Wake-up signalled to MCU. SBC ready to accept SPI command. Figure 32. Overcurrent Wake-Up • T2: Over current detected to SBC wake-up (INT pulse) = typ 60 µs • T1:VDD1 output current deglitcher time:IDD1-DGLT: typ • The total time is 148 µs in this case. 55 µs LX with Cyclic Sense LX HS1 INT t1 t2 tINT + tS-1STSPI (33µs max) Wake-up signalled to MCU. Figure 33. SBC ready to accept SPI command. MC33989 CAN INTERFACE • T1: Is dependent on the selected cyclic sense timing in the TIM2 register (5 ms to 400 ms). LX is sampled 10 µs before the end of cyclic sense on time. If the LX correct wake-up level happens just after sample point, the wake-up will be detected at the next HS1 activation and a complete period is lost. • T2: It is the same than Lx to INT pulse: typ 100 µs • The total time is around 5.13 ms (for a cyclic sense total time of 5 ms) in the above example. This section is a detailed description of the CAN interface of the MC33989. Block Diagram Figure 34 is a simplified block diagram of the CAN interface of the MC33989. 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 45 TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES V2 V2 SPI control TX V2 V2 Driver QH CANH CANH line RX Differential receiver 2.5V Bus termination (60 ohms) CAN L line V2 Driver SPI control VSUP Internal wake-up signal Wake-up pattern recognition SPI control QL CANL Wake-up receiver Figure 34. 33989 CAN Interface CAN Interface Supply The supply voltage for the CAN driver is the V2 pin. The CAN interface also has a supply path from the battery line, through the pin VSUP. This path is used in CAN sleep mode to allow wake-up detection. During CAN communication (transmission and reception) the CAN interface current is sourced from the V2 pin. During a CAN low power mode, the current is sourced from the VSUP pin. Main Operation Modes Description The CAN interface of the MC33989 has two main operation modes: Normal mode and sleep mode. The modes are controlled by the SPI command. In normal mode, used for communication, four different slew rates are available for the user. In sleep mode, the user has the option to enable or disable the remote CAN wake-up capability. TX CAN Driver Operation in Normal Mode When the CAN interface of the MC33989 is in Normal mode, the driver has two states: recessive or dominant. The driver state is controlled by the TX pin. The bus state is reported through the RX pin. When TX is high, the driver is set in a recessive state, CANH and CANL lines are biased to the voltage set at V2 divided by 2, approx. 2.5 V. When TX is low, the bus is set into dominant state: the CANL and CANH drivers are active. CANL is pulled to gnd, CANH is pulled high toward 5 V (the voltage at V2). The RX pin reports the bus state: the CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV). If “CANH minus CANL” is below the threshold, the bus is recessive and RX is set high. If “CANH minus CANL” is above the threshold, the bus is dominant and RX is set low. This is illustrated in the figure below. CANH-DOM CANH 2.5V CANH-CANL CANL-REC 2.5V CANL CANL-DOM CANH-REC RX Figure 35. CAN Driver Operation in Normal Mode 33989 46 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES TX and RX Pins The TX pin has an internal pull up to V2. The state of TX depends on the V2 status. RX is a push-pull structure, supplied by V2. When V2 is set at 5V, and CAN is in normal mode, RX reports the bus status. When V2 is off RX is low. Normal Mode and Slew Rate Selection The slew rate selection is done via the SPI. Four slew rates are available. The slew rate affects the recessive to dominant and dominant to recessive transitions. This affect is also the delay time from the TX pin to the bus, and from the bus to RX. The loop time is thus affected by the slew rate selection. The following figure is an illustration of the slew rate on CANH, CANL, TX and RX. CAN signal with slew rate 0 selected CAN signal with slew rate 3 selected R=60 ohms, CL = CH = 100pF Figure 36. Normal Mode and Slew Rate Selection Minimum Baud Rate As TX permanent dominant is detected after TDOUT (min 200 µs), a minimum Baud rate is required in order to get good behavior: once TX permanent dominant is detected the CAN driver is off. The maximum number of consecutive dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag). 200 µs/12 = 16.7 µs. The minimum Baud rate is 1/6.7 µs = 60 KBaud. Termination The MC33989 supports the two main types of bus termination: • Differential termination resistors between CANH and CANL lines. • Split termination concept, with mid point of the differential termination connected to gnd through a capacitor. CANH CANH CAN bus RT /2 RT /2 CAN bus RT MC33989 (partial drawing) CANL TX RX Gnd MC33989 (partial drawing) CANL Gnd TX RX Differential termination concept Split termination concept Figure 37. Bus Termination 33989 Analog Integrated Circuit Device Data Freescale Semiconductor 47 TYPICAL APPLICATIONS SUPPLEMENTAL APPLICATION NOTES CAN Mode versus SBC Modes The table below indicates the CAN interface modes versus the SBC modes as well as the status of TX, RX and the CAN bus pins. Table 34. CAN vs SBC Modes External ballast for V2 V2 voltage CANH/CANL (disconnected from other nodes) Floating to gnd Floating to gnd Floating to gnd Bus recessive CANH = CANL = 2.5 V SBC mode CAN mode TX RX Unpowered Reset (with ballast) Normal request (with ballast) Normal YES YES YES YES Unpowered 0V 0V 0V LOW LOW LOW Internal pull up to V2. LOW LOW LOW Report bus state High if bus recessive, Low if dominant 5V LOW Same as normal mode 5V Normal Slew rate 0,1,2,3 5V Normal Standby with external ballast Standby without external ballast, V2 connected to V1 Standby without external ballast, V2 connected to V1 Sleep Stop YES YES NO Sleep mode Normal or sleep Normal 5V 0V 5V 5V LOW Same as normal mode 5V Floating to gnd Floating to gnd Same as normal mode Floating to gnd NO Sleep 5V — — Sleep Sleep 0V 0V LOW LOW LOW LOW Floating to gnd Floating to gnd How to Test the MC33989 CAN Interface The CAN interface can be easily set up and tested. MC33989 can be connected as in the following figure. V2 is connected to V1. The device is supplied with nominal supply (12 V at VSUP input pin). After power on, reset the device, enter normal request mode, and the CAN interface is set in normal mode, slew rate 0. TX can be driven by a signal generator. RX will report the bus state. The figure below is a simple test schematic. V2CTRL V2 WD VSUP C1 C2 HS1 V1 RST RESET C3 C4 Components list: C1: 22uF, C2: 100nF C3: >10uF C4: 100nF Rt: 60 ohms MC33989 CANH CANL CANH CAN bus RT CANL GND RX Signal at RX output L0 L1 L2 L3 INT CS MISO MOSI SCK TX Signal generator F