34704

Freescale Semiconductor Technical Data Document Number: MC34704 Rev. 5.0, 2/2011 Multiple Channel DC-DC Power Management IC The 34704 is a multi-channel Power Management IC (PMIC) used to address power management needs for various multimedia application microprocessors. Its ability to provide either 5 or 8 independent output voltages with a single input power supply (2.7 and 5.5 V) together with its high efficiency, make it ideal for portable devices powered up by Li-Ion/polymer batteries or for USB powered devices as well. The 34704 is housed in a 7x7 mm, Pb-free, QFN56 and is capable of operating at a switching frequency of up to 2.0 MHz. This makes it possible to reduce external component size and to implement full space efficient power management solutions. 34704 MULTI-CHANNEL IC Features • 8 DC/DC (34704A) or 5 DC/DC (34704B) switching regulators with up to ±2% output voltage accuracy • Dynamic voltage scaling on all regulators. ORDERING INFORMATION • Selectable output voltage or current regulation on REG8 Temperature • I2C programmability Device Package Range (TA) • Output under-voltage and over-voltage detection for each MC34704AEP/R2 regulator -20°C to 85°C 56 QFN EP MC34704BEP/R2 • Over-current limit detection and short-circuit protection for each regulator • Thermal limit detection for each regulator, except REG7 • Integrated compensation for REG1, REG3, REG6, and REG8 • 5.0 µA maximum shutdown current (All regulators are off, 5.5 V VIN) • True cutoff on all of the boost and buck-boost regulators • Pb-free packaging designated by suffix code EP EP SUFFIX (PB-FREE) 98ASA10751D 56-PIN QFN 34704A/B REG 8 REG 4 2 VBKL VDDR I C COMM REG 3 REG 2 REG 5 PGND *REG 1 *REG 6 *REG 7 VCORE VIO1 VIO2 DDR MEMORY GND MPU GND LCD +5V VREF+ (5 to 16V) VREF- (-5 to -9V) * Available only in 34704A device Figure 1. 34704 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008 - 2011. All rights reserved. DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations Orderable Part Number MC34704AEP/R2 MC34704BEP/R2 No. of Regulators 8 5 Regulator Number Reg 1 - 8 Reg 2, 3, 4, 5, 8 34704 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM REG8 voltage data Control voltage data Control REG1/VG OUT8 L SW8 VG PreDrv Boot PWM Start-Up Ipeak-det and blanking SW control Error Amp Error Amp PWM P-skip PreDrv VOUT1 (34704A) VG SW1 VG Boot BT8 FB8 BT1 Error Amp Control Error Amp PWM PreDrv Control DRV7 FB7 PreDrv OUT7 voltage data voltage data Boot REG7 (34704A) REG2 VG BT2D PVIN2 SW2D VOUT2 Error Amp PWM P-skip PreDrv SW2U VG Amp VREF7 COMP7 Boot BT2U COMP2 FB2 REG6 (34704A) voltage data Control REG3 VG Control Boot voltage data VOUT6 L SW6 VG PreDrv Boot PWM Error Amp BT3 PVIN3 SW3 BT6 Error Amp Error Amp PWM P-skip PreDrv VOUT3 FB3 VG PreDrv Boot FB6 VG REG4 REG5 Boot PreDrv voltage data Control voltage data Control BT4D PVIN4 SW4D VOUT4 BT5D PVIN5 SW5D VOUT5 Error Amp Error Amp PreDrv PWM P-skip PreDrv SW4U VG Boot SW5U VG PWM P-skip BT4U FB4 COMP4 Boot BT5U COMP5 FB5 VDDI SCL SDA RST VIN AGND VIN VG VDDI (2.5V) VDDIMON (VDDIdet) I2C Registers To Reg 1-8 Reset Driver Sequencer OSC/Divider UVLO Detection Startup Control ONOFF LION FREQ SS PGND (EXPAD) mux Thermal Detection ADC Soft Start Figure 2. 34704 Internal Block Diagram 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS PIN CONNECTIONS COMP5 COMP5 COMP2 COMP2 VOUT5 VOUT2 VOUT5 VOUT2 SW5D SW5U SW2U SW2D PVIN5 PVIN5 PVIN2 SW5D SW5U SW2U SW2D PVIN2 BT5D BT5D BT2D BT2D FB5 FB5 FB2 BT5U BT4D PVIN4 SW4D VOUT4 SW4U BT4U FB4 COMP4 BT3 PVIN3 SW3 VOUT3 FB3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 42 2 3 4 5 6 7 8 9 10 11 12 13 Exposed Pad PGND 57 41 40 39 38 37 36 35 34 33 32 31 30 BT2U ONOFF LION VDDI VIN AGND VOUT6 SW6 BT6 FB6 VOUT7 DRV7 FB7 VREF7 BT5U BT4D PVIN4 SW4D VOUT4 SW4U BT4U FB4 COMP4 BT3 PVIN3 SW3 VOUT3 FB3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 42 2 3 4 5 6 7 8 9 10 11 12 13 Exposed Pad PGND 57 41 40 39 38 37 36 35 34 33 32 31 30 FB2 BT2U ONOFF LION VDDI VIN AGND PGND5 PGND4 NC4 AGND3 PGND2 NC3 AGND1 NC2 14 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SS FREQ VOUT8 SW8 SW1 SDA FB8 BT8 VG COMP7 VOUT1 SCL BT1 RST 14 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SS FREQ VOUT8 SW8 SW1 SDA FB8 BT8 VG SCL BT1 NC0 RST NC1 34704A Figure 3. 34704 Pin Connections Table 2. 34704 Pin Definitions 34704B A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number Device Pin Name Pin Function 1 A/B BT5U Passive Formal Name REG5 Boost Stage bootstrap capacitor input pin REG4 Buck Stage bootstrap capacitor input pin REG4 power supply input voltage REG4 Buck Stage switching node REG4 regulated output voltage pin REG4 Boost Stage switching node REG4 Boost Stage bootstrap capacitor input pin REG4 voltage feedback input for voltage regulation/programming REG4 compensation network connection REG3 bootstrap capacitor input pin Definition Connect a 1.0 μF capacitor between this pin and SW5U pin to enhance the gate of the Switch Power MOSFET. Connect a 0.01 μF capacitor between this pin and SW4D pin to enhance the gate of the Switch Power MOSFET. This is the connection to the drain of the high side switch FET. Input decoupling /filtering is required for proper REG4 operation. Use a 10uf decoupling capacitor for better performance. The inductor is connected between this pin and the SW4U pin. Connect this pin to the load and to the output filter as close to the pin as possible. The inductor is connected between this pin and the SW4D pin. Connect a 0.01 μF capacitor between this pin and SW4U pin to enhance the gate of the Switch Power MOSFET. Connect the feedback resistor divider to this pin. 2 A/B BT4D Passive 3 A/B PVIN4 Power 4 5 6 7 A/B A/B A/B A/B SW4D VOUT4 SW4U BT4U Input/Output Output Input/Output Passive 8 A/B FB4 Input 9 10 A/B A/B COMP4 BT3 Passive Passive REG4 compensation network connection. Connect a 0.01 μF capacitor between this pin and SW3 pin to enhance the gate of the Switch Power MOSFET. 34704 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 2. 34704 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number Device Pin Name Pin Function 11 A/B PVIN3 Power Formal Name REG3 power supply input voltage REG3 switching node REG3 output voltage return pin REG3 voltage feedback input for voltage regulation/programming Soft start time Definition This is the connection to the drain of the high side switch FET. Input decoupling /filtering is required for proper REG3 operation. Use a 10uf decoupling capacitor for better performance. The inductor is connected between this pin and the regulated REG3 output. This is the discharge path of REG3 output voltage. Connect the feedback resistor divider to this pin. 12 13 14 A/B A/B A/B SW3 VOUT3 FB3 Output Output Input 15 A/B SS Input The soft start time for all regulators can be adjusted by connecting this pin to an external resistor divider between VDDI and AGND pins. The oscillator frequency can be adjusted by connecting this pin to an external resistor divider between VDDI and AGND pins. This pin sets FSW1 value. Connect the feedback resistor divider to this pin. 16 A/B FREQ Input Oscillator frequency 17 A/B FB8 Input REG8 voltage feedback input for voltage regulation/programming REG8 bootstrap capacitor input pin REG8 regulated output voltage pin REG8 switching node REG1 switching node REG1 regulated output voltage before the cutoff switch REG1 regulated output voltage pin. REG1 bootstrap capacitor input pin I2C serial interface clock input I2C serial interface data input Power reset output signal (Microprocessor Reset) REG7 compensation network connection - 18 19 20 21 22 A/B A/B A/B A/B A/B BT8 VOUT8 SW8 SW1 VG Passive Output Output Output Passive Connect a 0.01 μF capacitor between this pin and SW8 pin to enhance the gate of the Synchronous Power MOSFET. Connect this pin directly to the load directly and to the output filter as close to the pin as possible. The inductor is connected between this pin and the VIN pin. The inductor is connected between this pin and the VIN Pin. REG1 regulated output voltage before the cut-off switch. This supplies the internal circuits and the gate drive Connect this pin directly to the load directly and to the output filter as close to the pin as possible. Pin 23 is not connected. Connect a 1.0 μF capacitor between this pin and SW1 pin to enhance the gate of the Switch Power MOSFET. I2C serial interface clock input. I2C serial interface data input. This is an open drain output and must be pulled up by an external resistor to a supply voltage like VIN. REG7 compensation network connection. Pin 28 is not connected 23(1) A B VOUT1 NC0 BT1 SCL SDA RST COMP7 NC1 VREF7 NC2 Output No Connect Passive Input/Output Input/Output Open Drain Passive No Connect Output No Connect 24 25 26 27 28 A/B A/B A/B A/B A B 29 A B REG7 resistor feedback Connect this pin to the bottom of the feedback resistor divider. network reference voltage Pin 29 is not connected 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 5 PIN CONNECTIONS Table 2. 34704 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number Device Pin Name Pin Function 30 A FB7 Input Formal Name REG7 voltage feedback input for voltage regulation/programming REG7 external Power MOSFET gate drive REG7 output voltage return pin. REG6 voltage feedback input for voltage regulation/programming REG6 bootstrap capacitor input pin. REG6 switching node REG6 regulated output voltage pin Analog ground of the IC Battery voltage connection Internal supply voltage Battery Detection Dual function IC turn On/ Off REG2 Boost Stage bootstrap capacitor input pin REG2 compensation network connection REG2 voltage feedback input for voltage regulation/programming REG2 Buck Stage bootstrap capacitor input pin REG2 power supply input voltage Definition Connect the feedback resistor divider to this pin. B 31 A B 32 A B 33 A AGND1 DRV7 NC3 VOUT7 PGND1 FB6 Output No Connect Output Input Pin 30 is connected to AGND REG7 external Power MOSFET gate drive. Pin 31 is not connected This is the discharge path of REG7 output voltage. Pin 32 is connected to PGND Connect the feedback resistor divider to this pin. B 34 A B 35 A B 36 A B 37 38 39 40 41 42 A/B A/B A/B A/B A/B A/B AGND2 BT6 NC4 SW6 PGND2 VOUT6 PGND3 AGND VIN VDDI LION ONOFF BT2U Passive No Connect Output Output Ground Power Output Input Input Passive Pin 33 is connected to AGND Connect a 0.01 μF capacitor between this pin and SW6 pin to enhance the gate of the Synchronous Power MOSFET. Pin 34 is not connected The inductor is connected between this pin and the VIN pin. Pin 35 is connected to PGND Connect this pin directly to the load directly and to the output filter as close to the pin as possible. Pin 36 is connected to PGND Analog ground of the IC. Input decoupling /filtering is required for the device to operate properly. Connect a 1.0 μF low ESR decoupling filter capacitor between this pin and GND. Always pull this pin High with a 470kohm Resistor to indicate Input power is present. This is a hardware enable/disable for the 34704A/B. It can be connected to a mechanical switch to turn the power On or Off. Connect a 1.0 μF capacitor between this pin and SW2U pin to enhance the gate of the Switch Power MOSFET. REG2 compensation network connection. Connect the feedback resistor divider to this pin. 43 44 A/B A/B COMP2 FB2 Passive Input 45 A/B BT2D Passive Connect a 1.0 μF capacitor between this pin and SW2D pin to enhance the gate of the Switch Power MOSFET. This is the connection to the drain of the high side switch FET. Input decoupling /filtering is required for proper REG2 operation. Use a 10uf decoupling capacitor for better performance 46 A/B PVIN2 Power 34704 6 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 2. 34704 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number Device Pin Name Pin Function 47 48 49 50 51 52 53 A/B A/B A/B A/B A/B A/B A/B SW2D VOUT2 SW2U SW5U VOUT5 SW5D PVIN5 Input/Output Output Input/Output Input/Output Output Input/Output Power Formal Name REG2 Buck Stage switching node REG2 regulated output voltage pin REG2 Boost Stage switching node REG5 Boost Stage switching node REG5 regulated output voltage pin REG5 Buck Stage switching node REG5 power supply input voltage REG5 Buck Stage bootstrap capacitor input pin REG5 voltage feedback input for voltage regulation/programming REG5 compensation network connection Power Ground Connection for all of the regulators except REG7 Definition The inductor is connected between this pin and the SW2U pin. Connect this pin to the load and to the output filter as close to the pin as possible. The inductor is connected between this pin and the SW2D pin. The inductor is connected between this pin and the SW5D pin. Connect this pin to the load and to the output filter as close to the pin as possible. The inductor is connected between this pin and the SW5U pin. This is the connection to the drain of the high side switch FET. Input decoupling /filtering is required for proper REG5 operation. Use a 10uf decoupling capacitor for better performance Connect a 1.0 μF capacitor between this pin and SW5D pin to enhance the gate of the Switch Power MOSFET. Connect the feedback resistor divider to this pin. 54 A/B BT5D Passive 55 A/B FB5 Input 56 Exposed Pad A/B A/B COMP5 PGND Passive Ground REG5 compensation network connection. Power Ground Connection for all of the regulators except REG7. This pad is provided to enhance thermal performance. Notes 1. If regulator 1 is not used, leave pin 23 Unconnected, All other components should be used to provide VG to the system 2. If regulators 5, 6, 7 and 8 are not used, connect the corresponding pins as follows: FB node: tied to GND, BT node: Not connected, VOUT node: Tied to GND, SW node: Tied to GND, DRV node: Tied to GND (REG7 only), COMP pin: Not connected, PVIN Pin: Not connected. 3. REG 2,3 and 4 should always be populated. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Battery Input Supply Voltage (VIN) Pin PVINx, RST, ONOFF, LION, DRV7(8), VG, SCL, SDA and VOUT1-5 Pins VDDI, COMPx, FBx, VREF7(8), FREQ, and SS Pins SW1-5 Pins SW8, SW6 (8) Symbol Value Unit VIN -0.3 to 6.0 -0.3 to 6.0 -0.3 to 3.0 V VSW-LOW Pins VSW-HIGH VBT-VSW VBT Pins VOUT-HIGH VOUT-NEG -1.0 to 6.0 -1.0 to 27 -0.3 to 6.0 -0.3 to 27 -0.3 to 27 -10.0 to 0.3 V V V V V V mA BTx Pins (Referenced to switch node) BTx Pins to GND VOUT8, VOUT6 VOUT7 Pin (8) (8) Continuous Output Current REG1 REG2,5 (8) 500 500 550 300 60 30 V VESD1 VESD2 ±1000 ±500 REG3 REG4 REG6,7(8) REG8 ESD Voltage Human Body Model Charge Device Model THERMAL RATINGS Maximum Junction Temperature Storage Temperature Maximum Power Dissipation (TA = 85°C) THERMAL RESISTANCE Thermal Resistance Junction to Ambient Junction to Board Peak Package Reflow Temperature During Reflow(5),(6) RΘJA RΘJB TPPRT (7) TJ(MAX) TSTG PD +150 -65 to +150 2.5 °C °C W °C/W 26 10 Note 6 °C Notes 4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 5. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Thermal Resistance is based on a four-layer board (2s2p) Available only on the 34704A 7. 8. 34704 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 2.7 V ≤ VIN ≤ 5.5 V, - 20°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic POWER INPUT Input Supply Voltage Typical Range Input DC Supply Current(9) VIN Pin Only All regulators are ON, no load; VIN = 3.6 V, FSW =1.0 Mhz Regulators 1 - 5 On, Reg 6, 7 and 8 Off; VIN = 3.6 V, FSW = 1.0 Mhz Input DC Shutdown Supply Current(9) (Shutdown, All regulators are OFF and VIN = 5.5V) This includes any pin connected to the battery Rising UVLO Threshold Falling UVLO Threshold RST RST Low Level Output Voltage IOL = 1.0 mA RST Leakage Current, Off-state @ 25°C Current Limit Monitoring Over and Short-circuit Current Limit Accuracy REGULATOR 1 & VG VG Output Voltage REG1 Output Voltage(10) Output Accuracy Line/Load Regulation(9) Dynamic Voltage Scaling Range Dynamic Voltage Scaling Step Size Continuous Output Current(9) Over-current Limit (Detected in Low Side FET) Short-circuit Current Limit (Detected in the Blocking FET) Over-current Limit Accuracy N-CH Switch Power MOSFET RDS(ON) N-CH Synch. Power MOSFET RDS(ON) N-CH Shutdown Power MOSFET RDS(ON) Discharge MOSFET RDS(ON) Thermal Shutdown Threshold(9) Thermal Shutdown Hysteresis(9) SW1 Leakage Current (Off State) @ 25°C Peak Current Detection Threshold at Power Up(9) Notes: 9. Guaranteed by Design 10. Available only on the 34704A VVG VOUT REGLN/LD VDYN VDYN_STEP IOUT ILIM_ION ISHORT_ION RDS(ON)-SW RDS(ON)-SY RDS(ON)-SH RDS(ON)-DIS TSD TSD-HYS ISW1_LKG IPEAK -4.0 -1.0 -10 -20 5.0 5.0 2.5 100 2.7 4.0 100 150 100 70 170 25 300 4.0 1.0 10 500 20 1.0 V V % % % % mA A A % mΩ mΩ mΩ Ω °C °C μA mA -20 20 % IRST-LKG VRST-OL 0.4 1.0 mA V UVLOR UVLOF 3.0 2.7 V V IOFF 5.0 VIN IIN 86 32 μA 2.7 5.5 V mA Symbol Min Typ Max Unit 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 2.7 V ≤ VIN ≤ 5.5 V, - 20°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic REGULATOR 2 Output Voltage Range Output Accuracy Line/Load Regulation(11) Feedback Reference Voltage Dynamic Voltage Scaling Range Dynamic Voltage Scaling Step Size Continuous Output Current (11) Symbol Min Typ Max Unit VOUT REGLN/LD VFB VDYN VDYN_STEP IOUT ILIM_ION ISHORT_ION RDS(ON)-SW RDS(ON)-SY RDS(ON)-SW RDS(ON)-SY RDS(ON)-DIS TSD TSD-HYS IPVIN2G_LKG ISW2D_LKG ISW2U_LKG VOUT REGLN/LD VFB VDYN VDYN_STEP IOUT ILIM_ION ISHORT_ION RDS(ON)-SW RDS(ON)-SY RDS(ON)-DIS TSD TSD-HYS IPVIN3_LKG ISW3_LKG 0.6 -2.0 -1.0 -17.5 -20 - 3.3 0.600(12) 2.5 200 1.4 2.1 120 1000 120 120 70 170 25 - 3.6 2.0 1.0 17.5 500 20 1.0 1.0 1.0 V % % V % % mA A A % mΩ mΩ mΩ mΩ Ω °C °C μA μA μA Over-current Limit (Detected in buck high side FET) Short-circuit Current Limit (Detected in buck high side FET) Battery Over-current Limit Accuracy N-CH Buck Switch Power MOSFET RDS(ON) N-CH Buck Synch. Power MOSFET RDS(ON) N-CH Boost Switch Power MOSFET RDS(ON) N-CH Boost Synch. Power MOSFET RDS(ON) Discharge MOSFET RDS(ON) Thermal Shutdown Threshold(11) Thermal Shutdown Hysteresis(11) PVIN2 Leakage Current (Off State) @25°C SW2D Leakage Current (Off State) @25°C SW2U Leakage Current (Off State) @25°C REGULATOR 3 Output Voltage Range Output Accuracy Line/Load Regulation(11) Feedback Reference Voltage Dynamic Voltage Scaling Range Dynamic Voltage Scaling Step Size Continuous Output Current(11) Over-current Limit (Detected in buck high side FET) Short-circuit Current Limit (Detected in buck high side FET) Over-current Limit Accuracy N-CH Switch Power MOSFET RDS(ON) N-CH Synch. Power MOSFET RDS(ON) Discharge MOSFET RDS(ON) Thermal Shutdown Threshold (11) Thermal Shutdown Hysteresis(11) PVIN3 Leakage Current (Off State) @25°C SW3 Leakage Current (Off State) @25°C 0.6 -4.0 -1.0 -17.5 -20 - 1.2 0.600(12) 2.5 150 1.0 1.5 500 500 70 170 25 - 1.8 4.0 1.0 17.5 550 20 1.0 1.0 V % % V % % mA A A % mΩ mΩ Ω °C °C μA μA Notes: 11. Guaranteed by Design 12. VFB is 0.6V when the part ist powered up and no DVS is changed. DVS is achieved by modifying VFB reference. 34704 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 2.7 V ≤ VIN ≤ 5.5 V, - 20°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic REGULATOR 4 Output Voltage Range Output Accuracy Line/Load Regulation(13) Feedback Reference Voltage Dynamic Voltage Scaling Range Dynamic Voltage Scaling Step Size Continuous Output Current (13) Symbol Min Typ Max Unit VOUT REGLN/LD VFB VDYN VDYN_STEP IOUT ILIM_ION ISHORT_ION RDS(ON)-SW RDS(ON)-SY RDS(ON)-SW RDS(ON)-SY RDS(ON)-DIS TSD TSD-HYS IPVIN4_LKG ISW4D_LKG ISW4U_LKG VOUT REGLN/LD VFB VDYN VDYN_STEP IOUT ILIM_ION ISHORT_ION RDS(ON)-SW RDS(ON)-SY RDS(ON)-SW RDS(ON)-SY RDS(ON)-DIS TSD TSD-HYS 0.6 -2.0 -1.0 -10 -20 - 1.8 0.600(14) 1.0 100 1.5 2.25 200 600 200 600 70 170 25 - 3.6 2.0 1.0 10 300 20 1.0 1.0 1.0 V % % V % % mA A A % mΩ mΩ mΩ mΩ Ω °C °C μA μA μA Over-current Limit (Detected in buck high side FET) Short-circuit Current Limit (Detected in buck high side FET) Over-current Limit Accuracy N-CH Buck Switch Power MOSFET RDS(ON) N-CH Buck Synch. Power MOSFET RDS(ON) N-CH Boost Switch Power MOSFET RDS(ON) N-CH Boost Synch. Power MOSFET RDS(ON) Discharge MOSFET RDS(ON) Thermal Shutdown Threshold(13) Thermal Shutdown Hysteresis(13) PVIN4 Leakage Current (Off State) @25°C SW4D Leakage Current (Off State) @25°C SW4U Leakage Current (Off State) @25°C REGULATOR 5 Output Voltage Range Output Accuracy Line/Load Regulation(13) Feedback Reference Voltage Dynamic Voltage Scaling Range Dynamic Voltage Scaling Step Size Continuous Output Current(13) Over-current Limit (Detected in buck high side FET) Short-circuit Current Limit (Detected in buck high side FET) Over-current Limit Accuracy N-CH Buck Switch Power MOSFET RDS(ON) N-CH Buck Synch. Power MOSFET RDS(ON) N-CH Boost Switch Power MOSFET RDS(ON) N-CH Boost Synch. Power MOSFET RDS(ON) Discharge MOSFET RDS(ON) Thermal Shutdown Threshold(13) Thermal Shutdown Hysteresis(13) 0.6 -2.0 -1.0 -17.5 -20 - 3.3 0.600(14) 2.5 150 1.4 2.1 120 1000 120 120 70 170 25 3.6 2.0 1.0 17.5 500 20 - V % % V % % mA A A % mΩ mΩ mΩ mΩ Ω °C °C Notes: 13. Guaranteed by Design 14. VFB is 0.6V when the part ist powered up and no DVS is changed. DVS is achieved by modifying VFB reference. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 2.7 V ≤ VIN ≤ 5.5 V, - 20°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic PVIN5 Leakage Current (Off State) @25°C SW5D Leakage Current (Off State) @25°C SW5U Leakage Current (Off State) @25°C REGULATOR 6 (16) Symbol IPVIN5_LKG ISW5D_LKG ISW5U_LKG VOUT REGLN/LD VFB VDYN VDYN_STEP IOUT ILIM_ION ISHORT_ION RDS(ON)-SW RDS(ON)-SY RDS(ON)-SH RDS(ON)-DIS TSD TSD-HYS ISW6_LKG VOUT REGLN/LD VFB IOUT RDS(ON)-DIS VIN-VOH VOL VREF7 REGLD Min - Typ - Max 1.0 1.0 1.0 Unit μA μA μA Output Voltage Range Output Accuracy Line/Load Regulation(15) Feedback Reference Voltage Dynamic Voltage Scaling Range Dynamic Voltage Scaling Step Size Continuous Output Current(15) Over-current Limit (Detected in low side FET) Short-circuit Current Limit (Detected in the Blocking FET) Over-current Limit Accuracy N-CH Switch Power MOSFET RDS(ON) N-CH Synch. Power MOSFET RDS(ON) N-CH Shutdown Power MOSFET RDS(ON) Discharge MOSFET RDS(ON) Thermal Shutdown Threshold(15) Thermal Shutdown Hysteresis(15) SW6 Leakage Current (Off State) @25°C REGULATOR 7(16) Output Voltage Range Output Accuracy Line/Load Regulation(15) Feedback Reference Voltage Continuous Output Current(15) Discharge MOSFET RDS(ON) Gate Drive Voltage High Level (@ -50 mA, VIN=3.6V) Gate Drive Voltage Low Level (@ 50 mA, VIN=3.6V) VREF7 Output Voltage VREF7 Voltage Accuracy VREF7 Output Load Regulation (10 μA to 1.0 mA) 5.0 -4.0 -1.0 -10 -20 - 15 0.600 2.5 50 3.0 4.5 200 600 200 70 170 25 (17) 15 4.0 1.0 10 60 20 1.0 V % % V % % mA A A % mΩ mΩ mΩ Ω °C °C μA -5.0 -2.0 -1.0 1.43 1.43 -7.0 0.600(17) 50 55 0.8 1.1 1.5 - -9.0 2.0 1.0 60 1.4 1.8 1.57 1.57 V % % V mA Ω V V V V V Notes 15. Guaranteed by Design 16. Available only on the 34704A 17. VFB is 0.6V when the part ist powered up and no DVS is changed. DVS is achieved by modifying VFB reference. 34704 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 2.7 V ≤ VIN ≤ 5.5 V, - 20°C ≤ TA ≤ 85°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic REGULATOR 8 Output Voltage Range Output Accuracy Feedback Reference Voltage Feedback Reference Voltage on current regulation mode Dynamic Voltage Scaling Range Dynamic Voltage Scaling Step Size Line/Load Regulation (18) Symbol Min Typ Max Unit VOUT VFB VFB VDYN VDYN_STEP REGLN/LD IOUT ILIM_ION ISHORT_ION RDS(ON)-SW RDS(ON)-SY RDS(ON)-SH RDS(ON)-DIS TSD TSD-HYS ISW8_LKG 5.0(19) -4.0 -10 -1.0 -20 - 15 0.600(20) 0.230(21) 2.5 15 1.0 1.5 450 1000 450 70 170 25 - 15 4.0 10 1.0 30 20 1.0 V % V V % % % mA A A % mΩ mΩ mΩ Ω °C °C μA Continuous Output Current(18) Over-current Limit (Detected in low side FET) Short-circuit Current Limit (Detected in the Blocking FET) Over-current Limit Accuracy N-CH Switch Power MOSFET RDS(ON) N-CH Synch. Power MOSFET RDS(ON) N-CH Shutdown Power MOSFET RDS(ON) Discharge MOSFET RDS(ON) Thermal Shutdown Threshold(18) Thermal Shutdown Hysteresis(18) SW8 Leakage Current (Off State) @25°C Notes 18. Guaranteed by Design 19. When Battery voltage is higher than 5.0V and VOUT8 is 5.0V, a polarization diode is necessary to achieve accurate output voltage. See Component Calculation on page 39 for further details. 20. VFB is 0.6V when the part ist powered up and no DVS is changed. DVS is achieved by modifying VFB reference. 21. When in Current regulation mode, the Voltage reference is set to 0.230mV to set the maximum current, and it is internally decreased to achieve a factor of the maximum current passing through the LED string 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 2.7V ≤ VIN ≤ 5.5V, -20°C ≤ TA ≤ 85°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic I2C COMMUNICATION Device Physical Address (7 bit Address) Maximum I2C Speed FREQ Selectable Switching Frequency 1 Selectable Switching Frequency 2 Selectable Switching Frequency Step Size Switching Frequency Accuracy Retry Timeout Period(23) tTIMEOUT fSW1 fSW2 fSTEP 750 250 -10 250 10 2000 1000 10 kHz kHz kHz % ms $54 400 kHz Symbol Min Typ Max Unit CURRENT LIMIT MONITORING Over-current Limit Timer(23) Retry Timeout Period(23) tLIMIT tRETRY 10 10 ms ms OUTPUT OVER-VOLTAGE/UNDER-VOLTAGE MONITORING Under-voltage Threshold (Response A) Over-voltage Threshold (Response A) Under-voltage Threshold (Response B) Over-voltage Threshold (Response B) Filter Delay Timer(23) RST RST Reset Delay(23) REGULATOR 1 & VG Operating Frequency(22), (23) Operating Frequency Selection Step Size Constant Time Off Value Low Side Timeout(23) (23) VUV-R VOV-R VUV-R VOV-R tFILTER - -20 20 -20 20 20 - % % % % μs tRST-DELAY - 10 ms fSW1 fSTEP tOFF tTIMEOUT 750 - 250 1.0 15 1500 - kHz kHz μs μs REGULATOR 2 Operating Frequency(23) Operating Frequency Selection Step Size fSW1 fSTEP 750 250 2000 kHz kHz Notes 22. When REG1 is used, the maximum fSW1 Frequency programed with external components should be 1500 kHz 23. Guaranteed by design. 34704 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 2.7V ≤ VIN ≤ 5.5V, -20°C ≤ TA ≤ 85°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic REGULATOR 3 Operating Frequency Operating Frequency Selection Step Size REGULATOR 4 Operating Frequency Operating Frequency Selection Step Size REGULATOR 5 Operating Frequency Operating Frequency Selection Step Size REGULATOR 6 Operating Frequency Operating Frequency Selection Step Size REGULATOR 7 Operating Frequency Selections Operating Frequency Selection Step Size REGULATOR 8 Operating Frequency Operating Frequency Selection Step Size fSW2 fSTEP 250 250 1000 kHz kHz fSW2 fSTEP 250 250 1000 kHz kHz fSW2 fSTEP 250 250 1000 kHz kHz fSW1 fSTEP 750 250 2000 kHz kHz fSW1 fSTEP 750 250 2000 kHz kHz fSW1 fSTEP 750 250 2000 kHz kHz Symbol Min Typ Max Unit 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 34704 is an multi-channel power management IC (PMIC) meant to address power management needs for various multimedia applications microprocessors in various configurations with a target overall efficiency of > 80% at typical loads. REGULATOR REG1 (25) The 34704 accepts an input voltage from various sources: •1 cell Li-Ion/Polymer (2.7 to 4.2 V) •5.0 V USB supply or AC wall adapter The different channels are: IOUT TYP (MA) 100 200 150 100 150 20 20 15 IOUT MAX (MA) 500 500 550 300 500 60 60 30 TARGET APPLICATION +5.0 V REF µP I/O µP Core DDR µP I/O REF+ REF Backlight Display REGULATOR TYPE Synchronous Boost Synchronous Buck-Boost Synchronous Buck Synchronous Buck-Boost Synchronous Buck-Boost Synchronous Boost Inverter Boost Synchronous Boost VOUT TYP (V) 5.0 2.8 / 3.3 1.2 / 1.5 / 1.8 1.8 / 2.5 3.3 15.0 -7.0 15.0 REG2 REG3 REG4 REG5 REG6 (25) REG7(25) REG8 Notes 24. Synchronous Buck-Boost: These regulators can work as pure BUCK regulator when the output voltage is lower than the input voltage; and work as pure BOOST regulator when the input voltage is lower than the output voltage. Compensation should be done for the worst case scenario, which is in most of the cases when the device is working as a boost converter, after compensating for this scenario it is recommended to verify the buck operation to assure stability in the whole operating range. 25. Available only on the 34704A REG1, REG3, REG6, and REG8 use internal compensation, while REG2, REG4, REG5, and REG7 use external compensation. The switching frequency of all regulators except REG6, 7, & 8 can be selected through the FREQ pin between 750 kHz and 2.0 MHz in 250 kHz steps. The high frequency operation is meant to minimize the size of external components while lower operating frequencies will allow for higher efficiency. REG7 is limited to operate at a lower frequency to minimize switching noise induced by driving the external switching MOSFET, but also can operate at the 1.0 MHz value with proper board layout. REG 6, 7, and 8 switching frequency can be selected between 250 kHz and 1.0 MHz in 250 kHz steps through I2C. For all regulators and at lower loads, a pulse skipping mode is implemented to maintain high efficiency. Note that pulse skipping occurs when the regulator enters into discontinuous conduction mode (DCM) at very light loads, however transitions between DCM and CCM may result in noisy switching nodes, therefore it is recommended to design the regulators to work in CCM all the time. Pulse skipping function is not guaranteed by circuit implementation. The 34704 uses 4 different phases of switching for all regulators except REG6, 7, and 8, to spread out the current draw by the individual converters from the input supply over time, to reduce the peak input current demand. This allows for better EMI performance and reduction in the input filter requirements. Each regulator except REG1 uses an external feedback resistor divider to set the output voltage. All output voltages can be adjusted dynamically (Dynamic Voltage Scaling) on the fly through an I²C serial interface. All converters, except REG1, utilize automatic soft-start by ramping the reference voltage to the error amplifier to prevent sudden change in duty cycle and output current/voltage at power up. REG1 (VG) will limit the inrush current by implementing a peak current detect and a constant off time. The 34704 is equipped with a dual function Power On/Off pin (ONOFF). This pin can be controlled by a mechanical switch to turn the device on or off. Pressing and releasing the mechanical switch turns the 34704 on while pressing and holding the switch for a time period (programmable through I2C) turns the 34704 off. Enable/disable control is also granted through I2C for groups of regulators and the whole IC. 34704 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL PIN DESCRIPTION REG5 BOOST STAGE BOOTSTRAP CAPACITOR INPUT PIN (BT5U) Connect a 1.0 μF capacitor between this pin and SW5U pin to enhance the gate of the Switch Power MOSFET. REG3 SWITCHING NODE (SW3) The inductor is connected between this pin and the regulated REG3 output. REG3 OUTPUT VOLTAGE RETURN PIN (VOUT3) REG4 BUCK STAGE BOOTSTRAP CAPACITOR INPUT PIN (BT4D) Connect a 0.01 μF capacitor between this pin and SW4D pin to enhance the gate of the Switch Power MOSFET. This is the discharge path of REG3 output voltage. REG3 VOLTAGE FEEDBACK INPUT FOR VOLTAGE REGULATION/PROGRAMMING (FB3) Connect the feedback resistor divider to this pin. REG4 POWER SUPPLY INPUT VOLTAGE (PVIN4) This is the connection to the drain of the high side switch FET. Input decoupling /filtering is required for proper REG4 operation. SOFT START TIME (SS) The soft start time for all regulators can be adjusted by connecting this pin to an external resistor divider between VDDI and AGND pins. REG4 BUCK STAGE SWITCHING NODE (SW4D) The inductor is connected between this pin and the SW4U pin. OSCILLATOR FREQUENCY (FREQ) The oscillator frequency can be adjusted by connecting this pin to an external resistor divider between VDDI and AGND pins. This pin sets FSW1 value. REG4 REGULATED OUTPUT VOLTAGE PIN (VOUT4) Connect this pin to the load and to the output filter as close to the pin as possible. REG8 VOLTAGE FEEDBACK INPUT FOR VOLTAGE REGULATION/PROGRAMMING (FB8) Connect the feedback resistor divider to this pin, when voltage mode control is used. When current mode control is used, connect this pin between the LED string and an ISET resistor to GND to force the operating current. Refer to Figure 10 and Figure 11. Exclude the components not used. REG4 BOOST STAGE SWITCHING NODE (SW4U) The inductor is connected between this pin and the SW4D pin. REG4 BOOST STAGE BOOTSTRAP CAPACITOR INPUT PIN (BT4U) Connect a 0.01 μF capacitor between this pin and SW4U pin to enhance the gate of the Switch Power MOSFET. REG8 BOOTSTRAP CAPACITOR INPUT PIN (BT8) Connect a 0.01 μF capacitor between this pin and SW8 pin to enhance the gate of the Synchronous Power MOSFET. REG4 VOLTAGE FEEDBACK INPUT FOR VOLTAGE REGULATION/PROGRAMMING (FB4) Connect the feedback resistor divider to this pin. REG8 REGULATED OUTPUT VOLTAGE PIN (VOUT8) Connect this pin directly to the load directly and to the output filter as close to the pin as possible. REG4 COMPENSATION NETWORK CONNECTION (COMP4) REG4 compensation network connection. REG8 SWITCHING NODE (SW8) The inductor is connected between this pin and VIN pin. REG3 BOOTSTRAP CAPACITOR INPUT PIN (BT3) Connect a 0.01 μF capacitor between this pin and SW3 pin to enhance the gate of the Switch Power MOSFET. REG1 SWITCHING NODE (SW1) The inductor is connected between this pin and VIN pin. REG3 POWER SUPPLY INPUT VOLTAGE (PVIN3) This is the connection to the drain of the high side switch FET. Input decoupling /filtering is required for proper REG3 operation. REG1 REGULATED OUTPUT VOLTAGE BEFORE THE CUT-OFF SWITCH (VG) REG1 regulated output voltage before the cutoff switch. This supplies the internal circuits and the gate drive. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION REG1 REGULATED OUTPUT VOLTAGE PIN (VOUT1) (34704A ONLY) Connect this pin directly to the load directly and to the output filter as close to the pin as possible. REG6 SWITCHING NODE (SW6) (34704A ONLY) The inductor is connected between this pin and the VIN pin. REG1 BOOTSTRAP CAPACITOR INPUT PIN (BT1) Connect a 1.0 μF capacitor between this pin and SW1 pin to enhance the gate of the Switch Power MOSFET. REG6 REGULATED OUTPUT VOLTAGE PIN (VOUT6) (34704A ONLY) Connect this pin directly to the load directly and to the output filter as close to the pin as possible. I2C SERIAL INTERFACE CLOCK INPUT (SCL) I C serial interface clock input. 2 ANALOG GROUND (AGND) Analog ground of the IC. I2C SERIAL INTERFACE DATA INPUT (SDA) I2C serial interface data input BATTERY VOLTAGE CONNECTION (VIN) Input decoupling /filtering is required for the device to operate properly. POWER RESET OUTPUT SIGNAL (MICROPROCESSOR RESET) (RST) This is an open drain output and must be pulled up by an external resistor to a supply voltage like VIN. INTERNAL SUPPLY VOLTAGE (VDDI) Connect a 1.0 μF low ESR decoupling filter capacitor between this pin and GND. REG7 COMPENSATION NETWORK CONNECTION (COMP7) REG7 compensation network connection. BATTERY DETECTION (LION) Pull this pin high to VIN to indicate a connection to a Li-Ion battery. REG7 RESISTOR FEEDBACK NETWORK REFERENCE VOLTAGE (VREF7) (34704A ONLY) Connect this pin to the bottom of the feedback resistor divider. DUAL FUNCTION IC TURN ON/OFF (ONOFF) This is a hardware enable/disable for the 34704. It can be connected to a mechanical switch to turn the power On or Off. REG7 VOLTAGE FEEDBACK INPUT FOR VOLTAGE REGULATION/PROGRAMMING (FB7) (34704A ONLY) Connect the feedback resistor divider to this pin. REG2 BOOST STAGE BOOTSTRAP CAPACITOR INPUT PIN (BT2U) Connect a 1.0 μF capacitor between this pin and SW2U pin to enhance the gate of the Switch Power MOSFET. REG7 EXTERNAL POWER MOSFET GATE DRIVE (DRV7) (34704A ONLY) REG7 external Power MOSFET gate drive. REG2 COMPENSATION NETWORK CONNECTION (COMP2) REG2 compensation network connection. REG7 OUTPUT VOLTAGE RETURN PIN (VOUT7) (34704A ONLY) This is the discharge path of REG7 output voltage. REG2 VOLTAGE FEEDBACK INPUT FOR VOLTAGE REGULATION/PROGRAMMING (FB2) Connect the feedback resistor divider to this pin. REG6 VOLTAGE FEEDBACK INPUT FOR VOLTAGE REGULATION/PROGRAMMING (FB6) (34704A ONLY) Connect the feedback resistor divider to this pin. REG2 BUCK STAGE BOOTSTRAP CAPACITOR INPUT PIN (BT2D) Connect a 1.0 μF capacitor between this pin and SW2D pin to enhance the gate of the Switch Power MOSFET. REG2 POWER SUPPLY INPUT VOLTAGE (PVIN2) This is the connection to the drain of the high side switch FET. Input decoupling /filtering is required for proper REG2 operation. REG6 BOOTSTRAP CAPACITOR INPUT PIN (BT6) (34704A ONLY) Connect a 0.01 μF capacitor between this pin and SW6 pin to enhance the gate of the Synchronous Power MOSFET. 34704 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION REG2 BUCK STAGE SWITCHING NODE (SW2D) The inductor is connected between this pin and the SW2U pin. REG5 POWER SUPPLY INPUT VOLTAGE (PVIN5) This is the connection to the drain of the high side switch FET. Input decoupling /filtering is required for proper REG5 operation. REG2 REGULATED OUTPUT VOLTAGE PIN (VOUT2) Connect this pin to the load and to the output filter as close to the pin as possible. REG5 BUCK STAGE BOOTSTRAP CAPACITOR INPUT PIN (BT5D) Connect a 1.0 μF capacitor between this pin and SW5D pin to enhance the gate of the Switch Power MOSFET. REG2 BOOST STAGE SWITCHING NODE (SW2U) The inductor is connected between this pin and the SW2D pin. REG5 VOLTAGE FEEDBACK INPUT FOR VOLTAGE REGULATION/PROGRAMMING (FB5) Connect the feedback resistor divider to this pin. REG5 BOOST STAGE SWITCHING NODE (SW5U) The inductor is connected between this pin and the SW5D pin. REG5 COMPENSATION NETWORK CONNECTION (COMP5) REG5 compensation network connection. REG5 REGULATED OUTPUT VOLTAGE PIN (VOUT5) Connect this pin to the load and to the output filter as close to the pin as possible. POWER GROUND CONNECTION FOR ALL OF THE REGULATORS EXCEPT REG7 (PGND) Power Ground Connection for all of the regulators except REG7. REG5 BUCK STAGE SWITCHING NODE (SW5D) The inductor is connected between this pin and the SW5U pin. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION * Figure 4. MC34704 Functional Internal Block Diagram INTERNAL BIAS CIRCUIT Gate Driver Voltage (VG) REG1/VG is the main regulator of the 34704 IC and will be used to supply internal circuitry and voltage biases through the VG output. It also provides the gate drive voltage for the rest of the regulators and itself. See Power-Up Sequence on page 28 for more details on how REG1 is a critical part of powering up the 34704. Based on this, REG1 will need extra circuitry to help it boot up until its output voltage is high enough that it can supply internal circuitry for the main control loop to take over. REG1 VG starts up in peak current detect PFM mode and REG1 VG output starts rising. When the appropriate internal circuitry is alive and the switching frequency FSW1 is selected, the PWM control of REG1 can take over. VREF Generator - Internal Reference Each one of the regulators in the 34704 uses a DAC which is controlled by the I2C interface to generate a dynamic VREF voltage for setting the output voltage on each regulator. VDDI Reference Voltage The 34704 uses the internal VG voltage to provide a precise low current 2.5 V voltage that is meant to serve as reference voltage to derive the FREQ and SS voltage needed to set the switching frequency 1 (FSW1) and the soft start, respectively. FAULT DETECTION AND PROTECTION Thermal Limit Detection There is a thermal sensor for each regulator except REG7. All regulators of the corresponding group will shutdown if at least one of them reaches the thermal limit. If either REG2, REG3 or REG4 reaches its thermal limit, the whole part will shutdown immediately. Over-Current & Short Circuit Monitoring The current limit circuitry has two levels of current limiting: • A soft over-current limit (over-current limit): If the peak current reaches the typical over-current limit, the switcher will start a cycle-by-cycle operation to limit the current and a 10 ms current limit timer starts. The switcher will stay in this mode of operation until the part regains normal 34704 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION operation, or shuts down after a failure to regain normal operation. • A hard over-current limit (short-circuit limit) that is higher than the cycle by cycle limit at which the device reacts by shutting down the output immediately. This is necessary to prevent damage in case of a short-circuit. After that, only GrpB will attempt a one time retry after a time-out period of 10 ms and will go through a new soft start cycle Output Over-voltage/Under-voltage Monitoring In the case of an output over-voltage/under-voltage, the user has two options that can be programmed through the I2C interface: Response A: The output will switch off automatically and the 34704 would alert the processor through I2C that such an event happened. Response B: The output will not switch off. Rather the 34704 communicates to the processor that an over-voltage/ under-voltage condition has occurred and waits for the processor decision to either shutoff or not; in the mean time the control loop will try to fix itself. NOTE: If Response A is set on any of the regulators from GrpB, and a OV/UV event occurs in the correspondig regulator, the complete device will shutdown and try to restart as long as the OV/UV is no longer present. This will also set the RST signal low until REG2, 3 and 4 are on regulation. changed via I2C at any time after power up has successfully completed. Phase Control REG1 to REG5 use the main Switching frequency FSW1, which is configured through the FREQ terminal at power up. FSW1 uses 4 different phases of switching (clock is 80 degrees out of phase) to spread out the current draw by the individual converters from the input supply over time to reduce the peak input current demand. The remaining regulators use FSW2 which can be programmed at any time via I2C after a successful power up sequence. Fault Register The 34704 has a dedicate fault register accessible via I2C which indicate which regulator is detecting a fault situation. In addition to this, each channel has its own fault register which indicates the type of fault detected in that regulator. I2C communication and Registers The 34704 can communicate using a standard I2C, communication protocol or an accurate I2C protocol. During the first one, the device processes the given command as soon as it has received it. During the accurate data communication, the device requires that each read/write command be sent twice to validate the data. The 34704 provides a user accessible register map that allows various general IC configurations as well as independent control of each regulator, including fault flag registers and all configurable features for each regulator. LOGIC AND CONTROL Startup Sequencing At power up, the VG regulator starts ramping up in peak detect mode. Meanwhile, VDDI is tracking VG until it reaches regulation and releases a POR signal that enables the internal circuitry and reads the FREQ and SS configuration to ramp up REG2, REG3 and REG4, that serve as the MPU main power supplies. Once the MPU is up, I2C communication is available to enable or disable GrpA, GrpC, GrpD and GrpE. An extra sequence can be configured for REG5, REG6 and REG7, changing the order in which they ramp up when enabled. See Power-Up Sequence on page 28. Soft Start Control During power up the 34704 reads the SS terminal to configure a default soft start timing for all regulators when these are enabled. Soft start for REG5 to REG8 can be OUTPUT GROUPS - REGULATORS The 34704 is divided in 5 different groups which are arranged as follows: • GrpA: Includes REG1(26) (VOUT1) • GrpB: Includes REG2, REG3, and REG4 • GrpC: Includes REG5, REG6(26), and REG7(26) • GrpD: Includes REG8 • GrpE: This is a special group. It includes REG5 when GrpC/E power sequencing option#1 is chosen Turning on/off each group would cause all contained regulators to turn on/off. Notes 26. Only on 34704A 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION REGUALATOR OVERVIEW WITH EFFICIENCY ANALYSIS REG1 (34704A Only) REG1 is a synchronous boost PWM voltage-mode control DC/DC regulator available only in the 34704A. Even though REG1 is a synchronous regulator, it is recommended to have a diode connected externally across its synchronous MOSFET. When the battery voltage is above REG1’s output (>5.0 V) as the case might be when connected to the USB supply or wall adaptor, the REG1 power MOSFETs will be tristated and the voltage on the output will be Battery minus the diode drop. This will help maintain REG1’s output to a maximum of 5.2 V and not allow it to drift all the way to 5.5 V. The switcher will operate in DCM at very light loads to allow pulse skipping. On the 34704A, when the appropriate command is received from the processor to turn on VOUT1, then the isolation FET of REG1 would turn on gradually to avoid any inrush current out of VG and to ramp the VOUT1 voltage in a controlled manner. REG1 VOUT1 will be discharged every time GrpA is shutting down and it will be held low by the discharge FET as long as possible. Characteristics • It powers up directly from the battery • Operates at a switching frequency equals to FSW1 • Drives integrated low RDS(ON) N-channel power MOSFETs (NHV_HC) as its output stage • It offers load disconnect from the input battery when the output is off (True Cutoff) • The output is ±4% accuracy • Output voltage is set to 5.0 V by means of an internal resistor divider • The output can be adjusted up or down at 2.5% for a total of 10% on each direction allowing Dynamic Voltage Scaling • Uses a bootstrap network with an internal diode to power its synchronous MOSFET • All gate drive circuits are supplied from REG1’s own VG output. • Uses integrated compensation • The output is monitored for under-voltage and overvoltage conditions • The output is monitored for over-current and short-circuit conditions • The regulator is monitored for over-temperature conditions Operation Modes The VG output is always active as long as: • The IC is not in an under-voltage lockout AND • No shutdown signal through the ONOFF pin is present AND • There is no ALLOFF shutdown command through the I2C interface AND • No faults exist that would cause the 34704 to shutdown The VOUT1 output will be active when: • VG output is available AND • There is no GrpA shutdown command through the I2C interface AND • No faults exist that would cause the VOUT1 to shut down REG2 This is a 4-switch synchronous buck-boost PWM voltagemode control DC/DC regulator. See Power-Up Sequence on page 28 for more details on when REG2 is powered up in the sequence. The switcher will operate in DCM at very light loads to allow pulse skipping. VOUT2 will be discharged every time the regulator is shutting down and it will be held low by the discharge FET as long as possible. Characteristics • It powers up directly from the battery • Operates at a switching frequency equals to FSW1 • Drives integrated low RDS(ON) N-channel power MOSFETs (NHV_HC) as its output stage • The output is ±2% accuracy • Output voltage is adjustable by means of an external resistor divider • The output can be adjusted up or down at 2.5% steps for a total of +17.5% to -20.0% on each direction allowing Dynamic Voltage Scaling • Uses bootstrap networks with an internal diode to power its high side MOSFETs • All gate drive circuits are supplied from VG • Uses external compensation • The output is monitored for under-voltage and overvoltage conditions • The output is monitored for over-current and short-circuit conditions • The regulator is monitored for over-temperature conditions Operation Modes The switcher will be active when: • VG is in regulation AND • There is no GrpB shutdown command through the I2C interface AND • No faults exist that would cause GrpB to shut down REG3 This is a synchronous buck PWM voltage-mode control DC/DC regulator. 34704 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION See Power-Up Sequence on page 28 for more details on when REG3 is powered up in the sequence. The switcher will operate in DCM at very light loads to allow pulse skipping. VOUT3 will be discharged every time the regulator is shutting down and it will be held low by the discharge FET as long as possible. Characteristics • It powers up directly from the battery • Operates at a switching frequency equals to FSW1 • Drives integrated low RDS(ON) N-channel power MOSFETs (NHV_HC) as its output stage • The output is ±4% accuracy • Output voltage is adjustable by means of an external resistor divider • The output can be adjusted up or down at 2.5% steps to achieve from +17.5% to -20.0% on each direction allowing Dynamic Voltage Scaling using the I2C DVS register. • An extra fine voltage scaling in 0.5% steps helps to adjust down the output voltage as low as 40%. • Uses a bootstrap network with an internal diode to power its switch MOSFET • All gate drive circuits are supplied from VG. • Uses integrated compensation. • The output is monitored for under-voltage and overvoltage conditions • The output is monitored for over-current and short-circuit conditions • The regulator is monitored for over-temperature conditions Operation Modes The switcher will be active when: • VG is in regulation AND • There is no GrpB shutdown command through the I2C interface AND • No faults exist that would cause GrpB to shut down REG4 This is a 4-switch synchronous buck-boost PWM voltagemode control DC/DC regulator. See Power-Up Sequence on page 28 for more details on when REG4 is powered up in the sequence. The switcher will operate in DCM at very light loads to allow pulse skipping. VOUT4 will be discharged every time the regulator is shutting down and it will be held low by the discharge FET as long as possible. Characteristics • It powers up directly from the battery • Operates at a switching frequency equals to FSW1 • Drives integrated low RDS(ON) N-channel power MOSFETs (NHV_HC) as its output stage • The output is ±2% accuracy • Output voltage is adjustable by means of an external resistor divider • The output can be adjusted up or down at 2.5% steps for a total of +17.5% to -20.0% on each direction allowing Dynamic Voltage Scaling. • Uses bootstrap networks with an internal diode to power its high side MOSFETs • All gate drive circuits are supplied from VG. • Uses external compensation • The output is monitored for under-voltage and overvoltage conditions • The output is monitored for over-current and short-circuit conditions • The regulator is monitored for over-temperature conditions Operation Modes The switcher will be active when: • VG is in regulation AND • There is no GrpB shutdown command through the I2C interface AND • No faults exist that would cause GrpB to shut down REG5 This is a 4-switch synchronous buck-boost PWM voltagemode control DC/DC regulator. See Power-Up Sequence on page 28 on for more details on when REG5 is powered up in the sequence. The switcher will operate in DCM at very light loads to allow pulse skipping. VOUT5 will be discharged every time the regulator is shutting down and it will be held low by the discharge FET as long as possible. Characteristics • It powers up directly from the battery • Operates at a switching frequency equals to FSW1 • Drives integrated low RDS(ON) N-channel power MOSFETs (NHV_HC) as its output stage • The output is ±2% accuracy • Output voltage is adjustable by means of an external resistor divider • The output can be adjusted up or down at 2.5% steps for a total of +17.5% to -20.0% on each direction allowing Dynamic Voltage Scaling. • Uses bootstrap networks with an internal diodes to power its high side MOSFETs • All gate drive circuits are supplied from VG. • Uses external compensation • The output is monitored for under-voltage and overvoltage conditions 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION • The output is monitored for over-current and short-circuit conditions • The regulator is monitored for over-temperature conditions Operation Modes The switcher will be active when: • VG is in regulation AND • There is no GrpC (OR GrpE) shutdown command through the I2C interface AND • No faults exist that would cause GrpC (OR GrpE) to shut down REG6 (Only 34704A) This is a synchronous boost PWM voltage-mode control DC/DC regulator. See Power-Up Sequence on page 28 for more details on when REG6 is powered up in the sequence. The switcher will operate in DCM at very light loads to allow pulse skipping. VOUT6 will be discharged every time the regulator is shutting down and it will be held low by the discharge FET as long as possible. Characteristics • It powers up directly from the battery • Operates at a switching frequency equals to FSW2 • Drives integrated low RDS(ON) N-channel power MOSFETs (NVHV_LC) as its output stage • It offers load disconnect from the input battery when the output is off (True Cut-Off) • The output is ±4% accuracy • Output voltage is adjustable by means of an internal resistor divider • The output can be adjusted up or down at 2.5% steps for a total of 10% on each direction allowing Dynamic Voltage Scaling • Uses a bootstrap network with an internal diode to power its synchronous MOSFET • All gate drive circuits are supplied from VG. • Uses integrated compensation. • The output is monitored for under-voltage and overvoltage conditions • The output is monitored for over-current and short-circuit conditions • The regulator is monitored for over-temperature conditions Operation Modes The switcher will be active when: • VG is in regulation AND • There is no GrpC shutdown command through the I2C interface AND • No faults exist that would cause GrpC to shut down REG7 (Only 34704A) This is a none-synchronous buck-boost inverting PWM voltage-mode control DC/DC regulator. See Power-Up Sequence on page 28 for more details on when REG7 is powered up in the sequence. The switcher will operate in DCM at very light loads to allow pulse skipping. VOUT7 will be discharged every time the regulator is shutting down and it will be held high to ground by the discharge FET as long as possible. Characteristics • • • • • • It powers up directly from the battery Operates at a switching frequency equals to FSW2 Drives an external P-channel power MOSFET The output is ±2% accuracy Output voltage is adjustable by means of an external resistor divider The output can be adjusted up or down at 2.5% steps for a total of 10% on each direction allowing Dynamic Voltage Scaling. All gate drive circuits are supplied from VG Uses external compensation, the type is up to the designer The output is monitored for under-voltage and overvoltage conditions • • • Operation Modes The switcher will be active when: • VG is in regulation AND • There is no GrpC shutdown command through the I2C interface AND • No faults exist that would cause GrpC to shut down REG8 This is a synchronous boost PWM voltage-mode control DC/DC regulator. See Power-Up Sequence on page 28 for more details on when REG8 is powered up in the sequence. VOUT8 will be discharged every time the regulator is shutting down and it will be held to ground by the discharge FET as long as possible. This regulator offers either voltage regulation for organic LEDs or current regulation for LCD backlighting LEDs. It provides either voltage or current feedback for these purposes through the same feedback pin. The regulator cannot drive only 1LED with a forward voltage drop of less than the battery input voltage. The processor would set the REG8 register through I2C before enabling REG8 to indicate if voltage regulation or current regulation will be used. Characteristics • It powers up directly from the battery 34704 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION • Operates at a switching frequency equals to FSW2 • Drives integrated low RDS(ON) N-channel power MOSFETs (NVHV_LC) as its output stage • It offers load disconnect from the input battery when the output is off (True Cut-Off) • The output is ±4% accuracy • Output voltage is adjustable by means of an external resistor divider when in voltage regulation mode • A 240 mV current limit comparator will be used to program/ sense the voltage drop across the current setting resistor at the bottom of the LED string connected to the REG8 output when the current regulation mode is selected. This will be used to program the maximum current flowing and will regulate it • The output can be adjusted up or down at 2.5% steps for a total of 10% on each direction allowing Dynamic Voltage Scaling • Maximum output current is adjustable by means of an external resistor connected to the FB8 pin and then the output current can be scaled down from the set maximum in 16 steps through I2C interface • Uses a bootstrap network with an internal diode to power its synchronous MOSFET • All gate drive circuits are supplied from VG. • Uses integrated compensation • The output is monitored for over-current and short-circuit conditions • The regulator is monitored for over-temperature conditions • The output is monitored for under-voltage and overvoltage conditions Operation Modes The switchers will be active when: • VG is in regulation AND • There is no GrpD shutdown command through the I2C interface AND • No faults exist that would cause GrpD to shut down OVERALL EFFICIENCY ANALYSIS In battery applications, it is highly recommended to power every single regulator directly from the battery to obtain full output capability: VBAT VBAT VBAT VBAT VBAT VBAT VBAT VBAT REG1 REG2 REG3 REG4 REG5 REG6 REG7 REG8 V1 (5.0 V) V2 (2.8 / 3.3 V) V3 (1.2 V / 1.5 V / 1.8 V) V4 (1.8 V / 2.5 V) V5 (3.3 V) V6 (15 V) V7 (-7.0 V) V8 (15 V) • • • • • • • • Figure 5. Overall Efficiency Analysis Efficiency analysis includes the following losses: MOSFET Conduction Losses MOSFET Switching Losses (Except for REG7 due to external MOSFET and board layout dependence) MOSFET Gate Charging Losses MOSFET Deadtime Losses External Diode Losses (Only for REG7) Inductor Winding DC Losses Inductor Core Losses (Assumed to be 20% of DC Losses as a rule of thumb) Output AC Losses Efficiency Analysis In this configuration, all of the regulators are supplied or powered directly with 3.6 V nominal, battery voltage. Efficiency was calculated using the maximum allowed frequency of 1.5 MHz and 1.0 MHz for FSW1 and FSW2, respectively, in this configuration. As a result, the following numbers are valid for worst case operation conditions. The following table shows the detailed analysis for each regulator with V2 at 3.3 V, V3 at 1.2 V, and V4 at 1.8 V. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 6. Regulator Analysis Table REG1 Vin (V) Vout (V) Iout_typ (A) Iout_max (A) DCR(mΩ) Cout (μF) ESR (mΩ) Fsw (kHz) Lout (μH) Iin_typ (A) Iin_max (A) ILout_peak (A) ICout_RMS (A) Pout (W) Ploss On Chip (W) Ploss Total (W) Pin (W) n (%) 3.60 5.00 0.100 0.500 230 22 9.00 1500 1.50 0.154 0.540 0.724 0.212 0.500 0.042 0.044 0.544 91.90% REG2 3.60 3.30 0.200 0.500 230 22 9.00 1500 1.50 0.201 0.502 0.510 0.005 0.660 0.047 0.049 0.709 93.12% REG3 3.60 1.20 0.150 0.550 230 22 9.00 1500 1.50 0.063 0.209 0.649 0.074 0.180 0.038 0.041 0.221 81.48% REG4 3.60 1.80 0.100 0.300 310 22 9.00 1500 1.50 0.059 0.178 0.444 0.076 0.180 0.028 0.030 0.210 85.91% REG5 3.60 3.30 0.150 0.500 230 22 9.00 1500 1.50 0.150 0.501 0.512 0.0006 0.495 0.034 0.035 0.530 93.33% REG6 3.60 15 0.050 0.060 230 22 9.00 1000 4.70 0.254 0.304 0.444 0.071 0.750 0.135 0.145 0.895 60.00% REG7 3.60 -7 0.050 0.060 230 22 9.00 1000 4.70 0.107 0.128 0.443 0.129 0.350 0.000 0.027 0.377 69.00% REG8 3.60 15 0.015 0.030 230 22 9.00 1000 4.70 0.077 0.154 0.297 0.043 0.225 0.045 0.047 0.272 64.00% Table 7. 34704A overall system efficiency 84% Overall System Pout (W) Ploss On Chip (W) Ploss Total (W) Pin (W) n (%) 3.340 0.369 0.41 3.75 84.00% Table 8. 34704B overall system efficiency 89% Overall System Pout (W) Ploss On Chip (W) Ploss Total (W) Pin (W) n (%) 1.74 0.192 0.202 1.942 89.6% 34704 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC34704 EFFICIENCY WAVEFORMS REG5 Efficiency 100% REG1 Efficiency 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 100 200 300 IOUT 400 500 600 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 100 200 300 IOUT 400 500 600 REG6 Efficiency 100% REG2 Efficiency 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 100 200 IOUT 300 400 500 600 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 10 20 30 IOUT 40 50 60 70 REG7 Efficiency 100% REG3 Efficiency 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 100 200 IOUT 300 400 500 600 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 10 20 30 IOUT 40 50 60 70 REG8 Efficiency 100% REG4 Efficiency 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 50 100 150 IOUT 200 250 300 350 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 IOUT 20 25 30 35 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES POWER-UP SEQUENCE Following is the power up sequence from a battery connection or a Power On signal through the ONOFF pin. 1. Battery initially connected to VIN. 2. LION pin is used to determine if a battery is being used (High for Li-Ion battery). 3. At initial power up from a cold start like the above with the battery first connected, the status of the ONOFF pin is ignored and 34704 moves forward to step (5). 4. After the cold start or battery insertion power up, activity on the ONOFF pin is used to determine if the device is enabled or disabled. If the device is disabled, then nothing happens. If the device is enabled then, 34704 moves forward to step (5). 5. The input battery UVLO signal de-asserts if the input voltage is above the UVLO rising threshold. 6. REG1 VG starts up in peak detect PFM and REG1 VG output starts rising. 7. VDDI output voltage will start tracking REG1 VG output. 8. When REG1 VG output rises high enough such that VDDI voltage is in regulation a POR signal is released and all internal circuitry can be enabled. I2C communication will remain disabled for normal power up sequence. The values of the FREQ and SS pins are read at this point. 9. REG1 PWM control loop can take over control of REG1 output once the VG voltage reaches a certain threshold set internally. 10. When REG1 is in regulation, it will be used to supply the Power MOSFET gate voltage for all of the other regulators except REG7. 11. REG3 is enabled, then when REG3 is in regulation. 12. REG2 is enabled, then when REG2 is in regulation. 13. REG4 is enabled, then when REG4 is in regulation. 14. I2C communication is enabled now since the processor supplies are up. 15. 34704 will de-assert the RST signal to indicate a “Power Good” after 10 ms of wait time. This output will be connected to the reset pin of the microprocessor. 16. The microprocessor then takes over and can enable REG1 VOUT1 and REG5 through REG8. The processor needs to send a command for REG8 mode of operation. The processor can also change REG5-8 soft start time before enabling them. The processor can also power down the system with an ALLOFF command. For power sequencing needs, the different regulators are grouped based on their function and how they relate to each other and the entire system. This makes power sequencing control a much easier task for the user where most of the group internal sequencing in now handled by the PMIC. All the processor has to do is to command the group and not each regulator. The regulators groups are as follows: • GrpA: Includes REG1 (VOUT1) • GrpB: Includes REG2, REG3, and REG4 • GrpC: Includes REG5, REG6, and REG7 • GrpD: Includes REG8 • GrpE: This is a special group. It includes REG5 when GrpC/E power sequencing option#1 is chosen SHUTDOWN SEQUENCES • Processor can disable VOUT1 (GrpA) at any point it desires • Processor can disable REG8 (GrpD) at any point it desires • Processor can disable REG5 (GrpE) at any point it desires if sequencing option#1 is picked • Processor can shutdown GrpC according to the power sequencing options 1, 2, 3, or 4 (see section “I2C User Interface”) • If any regulator in GrpC is shutting down due to a fault, the other regulators in GrpC will also shutdown by following the GrpC power sequencing options 1, 2, 3, or 4 (see section “I2C User Interface”) • If any regulator in GrpB is shutting down due to a fault, the other regulators in GrpB will also shutdown by following the processor supplies shutdown sequence. Then, GrpA, GrpC, GrpD, and GrpE (if applicable) will simultaneously shutdown keeping any sequencing within each group as necessary. VG will stay alive to perform a power up retry for GrpB but only for one time. If the power up cycle is successful, then normal operation is back. If the fault returns, then the shutdown sequence is repeated and then VG shuts down • Processor can shutdown the 34704 by sending an “ALLOFF” command, then GrpA, GrpC, GrpD, and GrpE (if applicable) will simultaneously shutdown keeping any sequencing within each group as necessary. Then, GrpB will shutdown according to the processor supply shutdown sequence. Then, VG will shut down. • The previous shutdown event can also happen through the ONOFF pin by pressing and holding the pin for a time period (programmable through I2C with a default of 1sec) • During battery depletion and when the input voltage passes the UVLO falling threshold, all of the outputs will be disabled without honouring the power down sequence This is to guarantee that the outputs are off and battery is not depleted further. 34704 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES • In any of the previous shutdown sequences, VG output will stay alive to maintain internal circuitry and logic until all other regulators are off, then it will shut off. POWER SUPPLY The battery voltage range is the following depending on the application: • 1-cell Li-Ion/Polymer: 2.7 to 4.2 V. Typ value is 3.6 V • USB supply or AC wall adapter: 4.5 to 5.5 V. Typ value is 5.0 V. This gives a total input voltage supply range of 2.7 to 5.5 V For the regulators, each one will be supplied separately through its own power input. LION PIN LION pin is always tied to VIN level. FREQUENCY SETTING PIN (FREQ PIN) There are two switching frequencies on board the 34704, one for REG6, 7 & 8, and the other for the rest of the regulators. To avoid any jitter or interference problems by having two oscillators on board, the switching frequency will be derived from the main oscillator using a frequency divider. 500 ns REG1/VG REG2 REG5, REG3 REG4 500 ns REG1/VG REG2 The switching frequency will be selectable for all of the regulators. REG6, 7 & 8 switching frequency (FSW2) will be selectable through I2C to be between 250 kHz and 1.0 MHz in 250 kHz steps. The rest of the regulators switching frequency (FSW1) will be selectable through the FREQ pin and can be selected between 750 kHz and 2.0 MHz, in 250 kHz steps. FSW1 default value is 2.0 MHz. This value is obtained by tying the FREQ pin to VDDI. FSW2 default value is 500 kHz. FSW1 will be selectable through programming the FREQ pin with an external resistor divider connected between VDDI and AGND pins. FSW2 will only be selectable through I2C. Please refer to the “I2C Programmability” section. The 34704 uses 4 different phases of switching (clock is 80 degrees out of phase) for FSW1 to spread out the current draw by the individual converters from the input supply over time to reduce the peak input current demand. This allows for better EMI performance and reduction in the input filter requirements. FSW1 has no phase relation with FSW2. The following distribution is shown for FSW1 of 2.0 MHz. The regulators grouping is based on their maximum current draw and attempts to reduce the effect on the input current draw. 500 ns REG1/VG REG2 REG5, REG3 REG4 REG4 500 ns REG1/VG REG2 REG5, REG3 SOFT START PIN (SS PIN) Initially at power up, the soft start time will be set for all of the regulators through programming the SS pin with an external resistor divider connected between VDDI and AGND pins (see the 34704A Typical Application Diagram). After power up, the soft start value for REG5 through REG8 can be changed and programmed through I2C. REG2 through REG4 soft start value is only set by the SS pin and cannot be programmed through I2C. See section “I2C Programmability” for more details. • If and only if the device is on and the ONOFF pin is pulled down for a time period (1s as a default and selectable to 2.0 sec, 1.5 sec, 1.0 sec or 0.5 sec via the I2C interface), then the device powers off after a second time period elapses unless it is masked by a command via the I2C interface: • The second period is the same amount of time as the first period so that the counter can be shared • When the first period elapses a shutdown flag is set to alert the processor that a shutdown signal has been activated. The ONOFF pin can be released after this flag is set without affecting what will happen next • A CPU can read out the shutdown flag to determine what to do • Power off the device immediately by a command via I2C interface (ALLOFF command) • Ignore the power off by sending a command via I2C interface to clear the shutdown flag ONOFF PIN This is a hardware enable/disable feature OR pin for the 34704: • It can be connected to a mechanical switch to turn the power On or Off • The device is power off by a command via the I2C interface as well • The power off by hardware can be masked by a command via the I2C interface • If the device is off and a falling edge is detected at the ONOFF pin, the device starts up 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES • Do nothing until the second time period expires and let the device power off by itself The ONOFF pin is edge sensitive and activates on a falling edge. It is normally pulled high. Shutdown if No Processor Communication Shutdown Flag Asserted 1 1st Period 2nd Period 0 Programmable Shutdown Delay 1st Period Turn On Programmable Shutdown Delay 2st Period During this time, the processor can abort the shutdown process or shutdown immediately before the 2nd period elapses with an I2C command ON/OFF Pin can be released during this period without affecting the device response process Figure 6. Hardware Power Up/Down Timing RST OUTPUT SIGNAL PIN This is a power reset output signal. It is an open drain output that should be connected to the reset input of the microprocessor. An external pull up resistor should be connected to this output and is recommended to be pulled up to V2 for best performance (If this pin is pulled up to the VIN pin, then the 1.0 µA shutdown current budget is not guaranteed) At power up, the RST pin is asserted (low) to keep the processor in “reset”. When VG, REG2, REG3, and REG4 are all in regulation (both OV and UV flags for each regulator are de-asserted) and no faults exist, the RST output is deasserted after a 10 ms delay to take the processor out of reset. Then the processor can go through its own internal power up sequence and can start communicating to the rest of the system. If ANY of the above four regulators has any of the following faults: over-temperature, short-circuit, over-current for more than 10 ms, over-voltage in response A, under-voltage in response A, or is shutting down normally, the RST output is asserted to put the processor back in reset. If ANY of the above four regulators has an over-voltage response B fault or an under-voltage response B fault, the RST output will not be asserted (only the OV and UV flags will be available for the microprocessor to read). a 10 ms current limit timer starts. The switcher will stay in this mode of operation until one of the following occurs: • The current is reduced back to the normal level inside the 10 ms timer and in this case normal operation is gained back • The output reaches the thermal shutdown limit and turns off • The current limit timer expires without gaining normal operation at which point the output turns off. Then only for GrpB, at the end of a timeout period of 10 ms, the output will attempt to restart again but for one time only. • The output current keeps increasing until it reaches the second over-current limit, see below for more details • A hard over-current limit (short circuit limit) that is higher than the cycle by cycle limit at which the device reacts by shutting down the output immediately. This is necessary to prevent damage in case of a short-circuit. After that, only GrpB will attempt a one time retry after a timeout period of 10ms and will go through a new soft start cycle OUTPUT OVER-VOLTAGE/UNDER-VOLTAGE MONITORING In the case of an output over-voltage/under-voltage, the user has two options that can be programmed through the I2C interface: Response A: The output will switch off automatically and the 34704 would alert the processor through I2C that such an event happened. Response B: The output will not switch off. Rather the 34704 communicates to the processor that an over-voltage/ under-voltage condition has occurred and wait for the THERMAL LIMIT DETECTION There is a thermal sensor for each regulator except REG7. It uses an external MOSFET. CURRENT LIMIT MONITORING The current limit circuitry has two levels of current limiting: • A soft over-current limit (over-current limit): If the peak current reaches the typical over-current limit, the switcher will start a cycle-by-cycle operation to limit the current and 34704 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS processor decision to either shutoff or not, in the mean time the control loop will try to fix itself. To avoid erroneous conditions, a 20 μs filter will be implemented. The OV/UV fault flag is masked during DVS until DVSSTAT flag is asserted “Done”. To keep the RST output low during ramp up and until the soft start is done, the OV/UV protection is masked from reporting that the output is in regulation. LOGIC COMMANDS AND REGISTERS I2C USER INTERFACE The 34704 communicates via I2C using a default device address $54 to access all user registers and program all regulators features independently. Physical address is in a 7bit format. The extra bit to complete the 8-bit indicates the reading or writing mode as shown in Figure 7 and Figure 8. After each byte read or sent, the MC34704 answers with an Acknowledge bit, indicating the bite was transferred successfully. 7 bit Physical Address + (w) bit 1010100 + 0 Start Bit ACK 0 ACK Sub-Address (MSB=0) 0XXXXXXX ACK 0 ACK Data XXXXXXXX ACK 0 ACK End Bit 10101 000 0000001 0 00001111 Figure 7. Writing sequence I2C bit stream   7 bit Physical ADD + ACK (w) bit 1010100 + 0 Start Bit 0 ACK Sub-address (MSB=1) 1XXXXXXX ACK 0 ACK RS 1 Physical ADD + ( r) bit 1010100 + 1 ACK 0 ACK Data Read XXXXXXX ACK 1 ACK End Bit 1010100 1000000 RS 1 0 1 0 1 0 0 00011111 Figure 8. Reading sequence I2C bit stream USER PROGRAMMABLE REGISTERS GrpC/E power sequencing setting (34704A Only) The microprocessor can choose one of several voltage sequence options for the GrpC/E supply (REG5), high voltage supply (REG6), and negative voltage supply (REG7). For 3 of the sequencing options, REG5 supply is controlled OPTION 1 (Default) MSB 0 LSB 0 GRPC/E ENABLED and tied with REG6 and REG7 in a preset power sequence. By default, only REG6 and REG7 are involved in the power sequence and REG5 is independently controlled with GrpE. 34704A assigns 2 bits to program the GrpC/E power sequencing options (CCDSEQ[1:0]). These bits value is latched in at GrpC power up and will not be allowed to change unless a power recycle happens. GRPC/E DISABLED REG5 is independently controlled REG6 and REG7 ramp down together REG5 is independently controlled REG6 and REG7 ramp up together. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS OPTION 2 MSB 0 LSB 1 GRPC/E ENABLED REG5 ramps up first Then REG6 and REG7 ramp up together GRPC/E DISABLED REG5, REG6 and REG7 ramp down together 3 4 1 1 0 1 REG5, REG6, and REG7 ramp up together REG5 and REG6 ramp up together first. Then ramp up REG7 REG5, REG6, and REG7 ramp down together REG7 ramps down first. Then REG5 and REG6 ramp down together Switching frequency for REG6, 7 & 8 FSW2 can be selected to be between 250 kHz and 1.0 MHz in 250 kHz steps. On the 34704B, FSW2 is just for REG8 since REG6 and 7 do not exist in this device. 34704 assigns 2 bits to program FSW2 (FSW2 [1:0]) FSW2 500kHz (Default) 250kHz 750kHz 1000kHz MSB 0 0 1 1 LSB 0 1 0 1 can decide whether to shutdown the output or not. In the mean time, the concerned output control loop will be attempting to correct the error. See Output Over-voltage/Under-voltage Monitoring on page 30 for more details. Response A and Response B share the same flag bit 34704 assigns 1 bit for this function (OVUVSETx) where x corresponds to each regulator. OV/UV Response A (Default) B bit 0 1 Shutdown Hold (Delay) Time The 34704 assigns 2 bits (SDDELAY[1:0]) for the processor to program the shutdown delay time period Shutdown Delay 1.0sec (Default) 0.5sec 1.5sec MSB 0 0 1 LSB 0 1 0 Dynamic Voltage Scaling for each regulator The customer can adjust each regulator’s output dynamically with 2.5% step size. The total range of adjustability will vary depending on each regulator to accommodate different operating environments. Some regulators will utilize the full range of -20.00% to +17.50% and some regulators will only use the range of ±10.00%. For details, see each regulator’s section. Each 2.5% step takes 50 μs before moving to the next step. REG8 only performs DVS when in voltage regulation mode. During DVS, the Over-voltage and Under-voltage monitoring will not be active. In addition to that, these faults will be masked and not active for a DVS settling time period equal to 1ms. This DVS settling time will start after the DVSSTAT register is flagged indicating that the DVS cycle is done. This is to ensure that during DVS and soft start alike the output will not be tripped due to a momentary overvoltage or under-voltage fault. This is the same for Response A and Response B of the over-voltage/under-voltage fault monitoring. 34704 assigns 4 bits register to program the Dynamic Voltage Scaling for each regulator (DVSSETx[3:0]) where x corresponds to each regulator. 2.0sec 1 1 Please refer to the /ONOFF pin description for more details Programming 34704 response to under-voltage/overvoltage conditions on each regulator There are two responses that can be programmed for an over-voltage/under-voltage condition: Response A: When an over-voltage (under-voltage) event is detected, the concerned output shuts down and a register is flagged to alert the processor. Response B: When an over-voltage/under-voltage event is detected, the concerned output will not shutdown, but the register is flagged to alert the processor. Then, the processor 34704 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Percentage Change 0.00% (Default) +2.50% +5.00% +7.50% +10.00% +12.50% +15.00% +17.50% -20.00% -17.50% -15.00% -12.50% -10.00% -7.50% -5.00% -2.50% MSB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Here is how the SSTIME bits interacts with the SSSETx register bits: 1. SSTIME is set by a value read through the SS pin. 2. SSTIME is copied into the bits SSSET5, SSSET6, SSSET7, and SSSET8. 3. The soft start time of REG2, REG3, and REG4 are only affected by the value of SSTIME bits. 4. The soft start time of REG5, REG6, REG7, and REG8 are affected by the value of bits SSSET5, SSSET6, SSSET7, and SSSET8 respectively. 34704 assigns 2 bits to store the value programmed by the SS pin. Bits SSTIME[1:0] can only be read by the user. Soft Start 0.5ms 2ms 8ms MSB 0 0 1 LSB 0 1 0 32ms 1 1 34704 assigns 2 bits for REG5 through REG8 to program the soft start times for these regulators (SSSETx[1:0]) where x corresponds to each regulator from REG5 through REG8. On/Off Control for each group of regulators as defined previously and for the whole IC 34704 assigns 1 bit per group to turn each group on/off (ONOFFA, C, D, or E bits). Please note that GrpB does not have a dedicated enable register which is enabled by default. GrpA, C, D, or E ONOFF OFF (Default) bit 0 Soft Start 0.5ms 2ms 8ms 32ms MSB 0 0 1 1 LSB 0 1 0 1 REG8 Regulation Mode The 34704 assigns 1 bit to indicate REG8’s regulation mode (REG8MODE). The processor assigns this bit to either regulation mode before enabling the REG8 output. REG8 Regulation Current (Default) Voltage bit 0 1 ON 1 Also, 34704 assigns 1 bit (ALLOFF) for disabling the whole IC through the I2C. (ALLOFF bit) ALL OFF False (Default) True bit 0 1 Soft Start Time There are two set of bits for setting the soft start value for all of the regulators except REG1. The SSTIME[1:0] bits reads the soft start value set by the SS pin and is used to initially set the soft start value for all of the regulators except REG1. Then, the SSSET bits for REG5 through REG8 can be used to change the soft start value for these regulators from the value set by the SSTIME. When REG8 is current regulated, LED backlight current can be reduced from the maximum in 16 steps through the I2C interface The maximum LED current can be set using the external resistor at the bottom of the LED string, then through I2C programming, this current value can be reduced in 16 steps. 34704 assigns 4 bits for this function (ILED[3:0]) The ILED setting is not a guaranteed characteristic from IMAX* (1/16) to IMAX* (9/16), due to an error amp common mode limitation. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Dynamic Voltage Scaling Status Flag LED Current IMAX * (1/16) IMAX * (2/16) IMAX * (3/16) IMAX * (4/16) IMAX * (5/16) IMAX * (6/16) IMAX * (7/16) IMAX * (8/16) IMAX * (9/16) IMAX * (10/16) IMAX * (11/16) IMAX * (12/16) IMAX * (13/16) IMAX * (14/16) IMAX * (15/16) IMAX (Default) MSB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DVS STATUS DVS Not Done DVS Done bit 0 1 In addition and for each regulator, 34704 assigns 1 bit (DVSSTATx) to flag to the processor that the desired output voltage level set with the DVSSETx bits has been reached. USER ACCESSIBLE FAULT REGISTERS Over-current Fault Register The 34704 assigns 1 bit for each regulator (ILIMFx) to indicate a fault due to over-current limit, where x corresponds to each regulator from REG1 to REG8, except REG7 ILIMF False True bit 0 1 Short-circuit Fault Register The 34704 assigns 1 bit for each regulator (SCFx) to indicate a fault due to short-circuit current limit, where x corresponds to each regulator from REG1 to REG8, except REG7 SCF False True bit 0 1 ACCURATE I2C COMMUNICATION MODE The 34704 assigns 1 bit to enable the Accurate I2C communication mode (ACCURATE). Setting this bit enables the Accurate mode in which each command and data should be sent 2 times to avoid false commands. USER ACCESSIBLE FLAG REGISTERS Cold Start Flag The 34704 assigns 1 bit (COLDF) to flag the processor that the power up was a result of battery insertion and not through ONOFF pin. This flag should be cleared after power up by the processor. Cold Start Flag /ONOFF (Default) Battery Insertion bit 0 1 Over-voltage Fault Register The 34704 assigns 1 bit for each regulator (OVFx) to indicate a fault due to over-voltage limit, where x corresponds to each regulator from REG1 to REG8 OVF False True bit 0 1 Shutdown Flag The 34704 assigns 1 bit (SHUTDOWN) to flag the processor if a shutdown signal is received through the ONOFF pin and a programmable time period with a default of 1sec has elapsed. /ONOFF Status Normal (Default) Shutdown bit 0 1 Under-voltage Fault Register The 34704 assigns 1 bit for each regulator (UVFx) to indicate a fault due to under-voltage limit, where x corresponds to each regulator from REG1 to REG8. UVF False True bit 0 1 Thermal Shutdown Fault Register 34704 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS The 34704 assigns 1 bit for each regulator (TSDFx) to indicate a fault due to thermal limit, where x corresponds to each regulator from REG1 to REG8, except REG7 TSDF False True bit 0 1 REG7 Independent ON/OFF Control (Only on 34704A) The 34704B provide two register to independently turn on REG7 when REG6 is not needed. Care must be taken when turning on REG7 to avoid inrush currents during regulator ramp-up. Following Process must be followed to assure successful turn on of REG7. 1. Set EN0 and clear DISCHR_B on REG7CR0 register 2. After 1ms or more, set EN1 on REG7CR0 register 3. Set REG7DAC register to $00 4. Gradually shift up REG7DAC register from $00 to $D9 to ramp-up the output voltage in a soft-start like wave. Soft start timing is dependant of I2C communication speed and number of bit you change per writing, for instance use 4,8 or 16 bits increase to ramp up the output voltage. Register Address 1 $58 $58 $59 $59 $59 $59 ... $59 2 3 4 5 6 ... 55 Code $50 $D0 $00 $04 $08 $0C ... $D9 Regulator Fault Register The 34704 assigns 1 bit for each regulator (FAULTx) to indicate that a fault had occurred on each regulator. The processor can just access this register periodically to determine system status. This reduces the access cycles. If a regulator fault register asserted, then the processor can access that regulator’s registers to see what kind of fault had occurred. FAULT F alse True bit 0 1 SPECIAL REGISTERS REG3 Fine Voltage Scaling Register Regulator 3 has an additional fine output voltage scaling that enables to lower the output voltage in 0.5% steps. The 34704 assigns an 8-bit register (REG3DAC) to the REG3 Digital to analog converter for the FB3 voltage generation. Output votlage must be reduced gradually to avoid a OV/UV fault to occur. REG7 independent start up example REGISTER DESCRIPTION SUMMARY TABLE Register GENERAL1 ADDR $01 R/W R/W Bit Name CCDSEQ SDDELAY R/W ONOFFx ALLOFF R GENERAL3 $03 R/W R/W VGSET1 $04 R/W R/W R R R/W R/W SSTIME COLDF SHTD OVUVSET1 DVSSET1 DVSSTAT1 OVUVSET2 DVSSET2 Bits 1:0 3:2 3:0 4 1:0 3 4 0 4:1 0 5:1 0 4:1 Description GrpC/E power sequence selection Hard shutdown delay timer selection GrpA,C,D,E On/off bits Soft shutdown bit (turn off all regulators) Soft start configuration latch Cold power up detection flag Hard Shutdown detection flag Set REG1/VG response type to OV/UV REG1 DVS value setting DVS voltage level status flag REG1 fault flags: Thermal SD, SC, ILim, UV and OV Set REG2 response type to OV/UV REG2 DVS value setting GENERAL2 $02 VGSET2 $05 REG2SET1 $06 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Register REG2SET2 ADDR $07 R/W R R R/W R/W R R R/W R/W R R R/W R/W R/W R R R/W R/W R/W R R R/W R/W R/W R/W R R R/W R/W R/W Bit Name DVSSTAT2 OVUVSET3 DVSSET3 DVSSTAT3 OVUVSET4 DVSSET4 DVSSTAT4 OVUVSET5 DVSSET5 SSSET5 DVSSTAT5 OVUVSET6 DVSSET6 SSSET6 DVSSTAT6 OVUVSET7 DVSSET7 SSSET7 FSW2 DVSSTAT7 OVUVSET8 DVSSET8 SSSET8 REG8MODE ILED DVSSTAT8 FLTx ACCURATE 3DACx DISCHG_B EN 7DACx Bits 0 5:1 0 4:1 0 5:1 0 4:1 0 5:1 0 4:1 1:0 0 5:1 0 4:1 1:0 0 5:1 0 4:1 1:0 3:2 0 2:1 0 4:1 1:0 3:2 6:4 0 5:1 7:0 0 7:0 4 7:6 7:0 Description DVS voltage level status flag REG2 fault flags: Thermal SD, SC, ILim, UV and OV Set REG3 response type to OV/UV REG3 DVS value setting DVS voltage level status flag REG3 fault flags: Thermal SD, SC, ILim, UV and OV Set REG4 response type to OV/UV REG4 DVS value setting DVS voltage level status flag REG4 fault flags: Thermal SD, SC, ILim, UV and OV Set REG5 response type to OV/UV REG5 DVS value setting REG5 Soft Start setting. DVS voltage level status flag REG5 fault flags: Thermal SD, SC, ILim, UV and OV Set REG6 response type to OV/UV REG6 DVS value setting REG6 Soft Start setting. DVS voltage level status flag REG6 fault flags: Thermal SD, SC, ILim, UV and OV Set REG7 response type to OV/UV REG7 DVS value setting REG7 Soft Start setting. REG6, 7 8, Frequency setting DVS voltage level status flag REG7 fault flags: UV and OV Set REG8 response type to OV/UV REG8 DVS value setting REG8 Soft Start setting. Voltage or Current Regulation mode on REG8 LED string current configuration during current regulation mode DVS voltage level status flag REG8 fault flags: Thermal SD, SC, ILim, UV and OV First Level fault register for REG1 through REG8 Accurate I2C communication mode enable REG3 DAC reference voltage configuration for Fine voltage Scaling Discharge enable for independent REG7 Control Output Enable bits for Independent REG7 Control REG7 DAC refence voltage configuration for REG7 Control REG3SET1 $08 REG3SET2 $09 REG4SET1 $0A REG4SET2 $0B REG5SET1 REG5SET2 REG5SET3 $0C $0D $0E REG6SET1 REG6SET2 REG6SET3 $0F $10 $11 REG7SET1 $12 REG7SET2 $13 REG7SET3 $14 REG8SET1 $15 REG8SET2 $16 R/W R/W REG8SET3 FAULTS I2CSET1 REG3DAC REG7CR0 REG7DAC $17 $18 $19 $49 $58 $59 R R R R/W R/W R/W R/W R/W 34704 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS I2C REGISTER DISTRIBUTION Each regulator has a fault register that records any fault that occurs in that regulator. Then there is a regulator fault reporting register that the processor can access at all times to see if any fault had occurred. There are also the IC general use registers. Those registers are also split between status reporting registers and processor programmable registers. This distribution keeps each regulator’s registers bundled together which makes it easier for the user to access one regulator at a time. D4 D3 D2 D1 D0 Addr $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $49 $58 $59 Name Reserved GENERAL1 GENERAL2 GENERAL3 VGSET1 VGSET2 REG2SET1 REG2SET2 REG3SET1 REG3SET2 REG4SET1 REG4SET2 REG5SET1 REG5SET2 REG5SET3 REG6SET1 REG6SET2 REG6SET3 REG7SET1 REG7SET2 REG7SET3 REG8SET1 REG8SET2 REG8SET3 FAULTS I2CSET1 REG3DAC REG7CR0 REG7DAC D7 D6 - D5 SDDELAY[1:0] ALLOFF SHTD ONOFFA COLDF ILIMF1 ILIMF2 ILIMF3 ILIMF4 ONOFFC UVF1 UVF2 UVF3 UVF4 CCDSEQ[1:0] ONOFFD ONOFFE OVUVSET1 OVF1 OVF2 OVF3 OVF4 DVSSTAT1 OVUVSET2 DVSSTAT2 OVUVSET3 DVSSTAT3 OVUVSET4 DVSSTAT4 OVUVSET5 SSSET5[1:0] OVF5 DVSSTAT5 OVUVSET6 SSSET6[1:0] OVF6 DVSSTAT6 OVUVSET7 SSSET7[1:0] OVF7 DVSSTAT7 OVUVSET8 SSSET8[1:0] OVF8 FLT2 3DAC1 7DAC1 DVSSTAT8 FLT1 ACCURATE 3DAC0 7DAC0 SSTIME[1:0] DVSSET1[3:0] TSDF1 TSDF2 TSDF3 TSDF4 SCF1 SCF2 SCF3 SCF4 DVSSET2[3:0] DVSSET3[3:0] DVSSET4[3:0] DVSSET5[3:0] TSDF5 SCF5 ILIMF5 UVF5 - DVSSET6[3:0] TSDF6 SCF6 ILIMF6 UVF6 DVSSET7[3:0] FSW2[1:0] UVF7 DVSSET8[3:0] ILED[3:0] REG8MODE ILIMF8 FLT4 3DAC3 7DAC3 UVF8 FLT3 3DAC2 7DAC2 TSDF8 SCF8 FLT5 3DAC4 DISCHG_B 7DAC4 FLT8 FLT7 FLT6 3DAC5 7DAC5 3DAC7 3DAC6 EN[1:0] 7DAC7 7DAC6 34704A Register Distribution Map 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Addr $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F$12 $13 $14 $15 $16 $17 $18 $19 $49 $58 $59 Name Reserved GENERAL1 GENERAL2 GENERAL3 Reserved VGSET2 REG2SET1 REG2SET2 REG3SET1 REG3SET2 REG4SET1 REG4SET2 REG5SET1 REG5SET2 REG5SET3 Reserved FSW2SET Reserved REG8SET1 REG8SET2 REG8SET3 FAULTS I2CSET1 REG3DAC REG7CR0 REG7DAC D7 D6 D5 D4 - D3 D2 D1 D0 ALLOFF SHTD TSDF5 SCF5 TSDF4 SCF4 TSDF3 SCF3 TSDF2 SCF2 - SDDELAY[1:0] ONOFFD COLDF ONOFFE SSTIME[1:0] UVF1 UVF2 UVF3 UVF4 OVF1 OVF2 OVF3 OVF4 OVUVSET2 DVSSTAT2 OVUVSET3 DVSSTAT3 OVUVSET4 DVSSTAT4 OVUVSET5 DVSSET2[3:0] ILIMF2 ILIMF3 ILIMF4 DVSSET3[3:0] DVSSET4[3:0] DVSSET5[3:0] ILIMF5 FSW2[1:2] DVSSET8[3:0] ILED[3:0] REG8MODE ILIMF8 FLT4 DAC3 7DAC3 UVF8 FLT3 DAC2 7DAC2 7DAC1 TSDF8 SCF8 FLT5 DAC4 DISCHG_B 7DAC4 OVF8 FLT2 DAC1 UVF5 OVF5 SSSET5[1:0] DVSSTAT5 FLT8 DAC7 7DAC7 DAC6 7DAC6 DAC5 7DAC5 OVUVSET8 SSSET8[1:0] DVSSTAT8 FLT1 ACCURATE DAC0 7DAC0 EN[1:0] 34704B Register Distribution Map 34704 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION COMPONENT CALCULATION FSW1 AND GENERAL SOFT START CONFIGURATION The 34704 uses FSW1 as the switching frequency for REG1(VG) thru REG5, and this can be changed by applying a voltage between 0 to 2.5 V to the FREQ pin. If the FREQ pin is left unconnected, the 34704 starts up with a default frequency of 750 KHz. To configure the FSW1, use a 2 resistors voltage divider from VDDI to ground to set the voltage on the FREQ pin as indicated bellow: Ratio 0 11/32 19/32 VDDI Soft Start timing [ms] 0.5 2.0 8.0 32.0 Ratio 0 9/32 13/32 17/32 21/32 VDDI FSW1 [KHz] 750 1000 1250 1500 1750 2000 IDD max = 100μΑ VDDI RSS1 RSS2 V SS = V DDI ⎛ ---------------------------------------⎞ ⎝ RSS1 + RSS2⎠ RSS1, RSS2 tolerance ±1.0% VSS RSS2 SS GND REGULATORS POWER STAGE AND COMPENSATION CALCULATION Regulator 1 and 6 (Synchronous Boost - internally compensated - REG1 is VG supply). REG1 is a Synchronous Boost converter set to 5.0 V and Maximum current of 500 mA while REG6 is set to 15 V at 60 mA (on the 34704B, REG1 does not exist but similar circuitry is used to provide the internal VG voltage). They do not need an external compensation network, thus, the only components that need to be calculated are: • R1 and RB (Only REG6): These two resistors help to set the output voltage to the desire value using a Vref=0.6 V, select R1 between 10 k and 100 K and then calculate RB as follows: R1 RB = --------------------Vo ----------- – 1 Vref Notes 27. If an external voltage is used, FSW1 can only be set during device startup. VDDI RF1 RF2 V FREQ = V DDI ⎛ ----------------------------- ⎞ ⎝ RF1 + RF2⎠ RF1, RF2 tolerance ±1.0% VFREQ RF2 FREQ GND Initially at power up, the soft start time will be set for all of the regulators through programming the SS pin with an external resistor divider connected between VDDI and AGND as follows: [Ω] • L: A boost power stage can be designed to operate in CCM for load currents above a certain level usually 5 to 15% of full load. The minimum value of inductor to maintain CCM can be determined by using the following procedure: 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION 1. Define IOB as the minimum current to maintain CCM as 15% of full load. Vo ( D ) ( 1 – D ) T L min ≥ -----------------------------------------2I OB where: D = Dutycycle Vo = Output Voltage T = Switching Period IOB = Boundary Current to achieve CCM 2 (H) regulators may work as a buck or a boost depending on the operating voltages, they need to be compensated in different ways for each situation. Since the 34704 is meant to work using a LiIon battery, the operating input voltage range is set from 2.7 - 4.2 V, then the following scenarios are possible: Input voltage range 3.0 - 4.2 2.7 - 3.0 3.5 - 4.2 2.7 - 4.2 2.7 - 4.2 2.7 - 3.0 3.5 - 4.2 Regulator 2 Vo 2.8 V 3.3 V 3.3 V Operation Buck Boost Buck Buck Buck Boost Buck 2. However the worst case condition for the boost power stage is when the input voltage is equal to one half of the output voltage, which results in the Maximum ΔIL, then: Vo ( T ) L min ≥ --------------16I OB (H) 4 1.8 V 2.5 V Note: On the 34704B Use the recommended 3.0uH inductor rated between 50 to 100 mA in order to have this regulator working in DCM. Rising the inductor value will make the regulator to begin working in CCM. • COUT: The three elements of output capacitor that contribute to its impedance and output voltage ripple are the ESR, the ESL and the capacitance C. The minimum capacitor value is approximately: 5 3.3 V 3.3 V Io max D max C OUT ≥ ---------------------------Fsw Δ Vo r where: Dmax = Maximum Dutycycle FSW = Switching Frequency • NOTE: Since these 3 regulators can work as a buck or a boost in a single application, a good practice to configure these regulators is to compensate for a boost scenario and then verify that the regulator is working in buck mode using that same compensation. Compensating for Buck operation: • L: A buck power stage can be designed to operate in CCM for load currents above a certain level usually 5 to 15% of full load. The minimum value of inductor to maintain CCM can be determined by using the following procedure: 1. Define IOB as the minimum current to maintain CCM as 15% of full load. ( Vo + Io max ( R DSONLSFET + R L ) D ′ min ) T Vo L min ≥ -------------------------------------------------------------------------------------------------------------------------- ≈ D ′ MAX T -------------2I OB 2I OB (F) • Where ΔVOr is the desired output voltage ripple. • Now calculate the maximum allowed ESR to reach the desired ΔVOr. Δ Vo r ESR ≤ -------------------------------------------Io max ⎛ ----------------------- + I ⎞ OB⎠ ⎝1 – D max [Ω] [H] where: RDSONLSFET = Body Resistance of the Lowside Fet RL = Inductor Winding Resistance D'Min = Minimum Off Percentage given by 1- (Vin_min/Vout_max) D'max = Maximum Off Percentage given by 1- (Vin_max/Vout_min) • 1CVG (Only Reg1): Use a 47uF capacitor from Ground to VG. • D1 (Only Reg1): Use a fast recovery schottky diode rated to 10V at 1A. Regulator 2, 4 and 5 (Synchronous Buck-Boost regulator with external compensation) These three regulators are 4-Switch synchronous buckboost voltage mode control DC-DC regulator that can operate at various output voltage levels. Since each of the • COUT: The three elements of output capacitor that contribute to its impedance and output voltage ripple are the ESR, the ESL and the capacitance C. A good approach to calculate the minimum real capacitance needed is to include the transient response analysis to control the maximum overshoot as desired. 34704 40 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION 1. First calculate the dt_I (inductor current rising time) given by: • R1 and RB: These two resistors help to set the output voltage to the desire value using a Vref=0.6 V, select R1 between 10 k and 100 K and then calculate RB as follows: Io max T dtI = --------------------Δ Iostep [s] Where the parameter ΔIo_step is the maximum current step during the current rising time and is define as: D max Vin min – Vo Δ Iostep = ⎛ -------------⎞ ⎛ -------------------------------⎞ ⎠ ⎝ Fsw ⎠ ⎝ L [A] R1 RB = --------------------Vo ----------- – 1 Vref [Ω] • Compensation network. (C1,C2,C3, R2, R3): For compensating a buck converter, 3 important frequencies referring to the plant are: 1. Output LC filter cutoff frequency (FLC): 2. Then the output capacitor can be chosen as follow: 1 F LC = ------------------------2 π LC OUT 2. Cutoff frequency due to capacitor ESR: [Hz] Io max dtI C OUT ≤ ---------------------Δ Vo max [A] • Where ΔVOmax is the maximum allowed transient overshoot expressed as a percentage of the output voltage, typically from 3 to 5% of Vo. 3. Finally find the maximum allowed ESR to allow the desired transient response: 1 F ESR = --------------------------------------2 π ( C OUT ) ESR 3. Crossover frequency (or bandwidth): [Hz] Δ Vo r ( Fsw ) ( L ) ESR max = -------------------------------------Vo ( 1 – D min ) F SW F BW = ---------10 [Ω] [Hz] NOTE: Do not use the parameters ΔVOr and ΔVOmax indistinctly, the first one indicates the output voltage ripple, while the second one is the maximum output voltage overshoot (transient response). The Type 3 external compensation network will be in charge of canceling some of these poles and zeros to achieve stability in the system. The following poles and zeroes frequencies are provided by the type 3 compensation. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 41 FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION F PO = F BW F Z1 = 0.9F LC F P1 = F ESR F 22 = 1.1F LC F SW F 2P = ---------2 The passive components associated to these frequencies are calculated with the following formulas. Vin min ⎛ 1 ⎞ 1 C1 = ------------------ ⎜ ---------------- ⎟ ⎛ ------------------------------ ⎞ V RAMP ⎝ D ′ 2⎠ ⎝ 2 π ( F PO R1 )⎠ min 1 C2 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F Z2 R1 )⎠ 1 R2 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F Z1 C1 )⎠ 1 R3 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F P1 C2 )⎠ 1 C3 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F P2 R2 )⎠ On the 34704 VRAMP is half of 1.2 V since each operation mode spends only half the ramp. 34704 42 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION Compensating for boost operation: • L: A boost power stage can be designed to operate in CCM for load currents above a certain level usually 5 to 15% of full load. The minimum value of inductor to maintain CCM can be determined by using the following procedure: 1. Define IOB as the minimum current to maintain CCM as 15% of full load: R1 RB = ----------------------Vo ------------- – 1 V REF [Ω] • Compensation network. (C1,C2,C3, R2, R3) For compensating a boost converter, 4 important frequencies referring to the plant are: 1. Output LC filter cutoff frequency (FLC): Vo ( D ) ( 1 – D ) T L min ≥ -----------------------------------------2I OB 2 [H] However the worst case condition for the boost power stage is when the input voltage is equal to one half of the output voltage, which results in the Maximum ΔIL, then: Vo ( T ) L min ≥ --------------16I OB D ′ min F LC = ------------------------2 π LC OUT [Hz] • Where D’min is the minimum off time percentage given by: [H] • COUT: The three elements of output capacitor that contribute to its impedance and output voltage ripple are the ESR, the ESL and the capacitance C. The minimum capacitor value is approximately: Vin min D ′ min = ---------------------Vout max 2. Cutoff frequency due to capacitor ESR: Io max D max C OUT ≥ ---------------------------Fsw Δ Vo r [F] 1 F ESR = --------------------------------------2 π ( C OUT ) ESR 3. The right plane zero frequency: [Hz] • Where ΔVOr is the desired output voltage ripple. • Now calculate the maximum allowed ESR to reach the desired ΔVOr: Δ Vo r ESR ≤ -------------------------------------------Io max ⎛ ---------------------- + I ⎞ - OB ⎝1 – D ⎠ max ( D ′ min ) R LOAD RHP Z = ---------------------------------------2πL 2 [Hz] [Ω] 4. Crossover frequency (or bandwidth): select this frequency as far away form the RHPZ as much as possible: • R1 and RB: These two resistors help to set the output voltage to the desire value using a Vref=0.6V, select R1 between 10k and 100K and then calculate RB as follows: RHP Z F BW « --------------6 [Hz] The Type 3 external compensation network will be in charge of canceling some of these poles and zeros to achieve stability in the system. The following poles and zeroes frequencies are provided by the type 3 compensation: F PO = F BW F P1 = F ESR F Z1 = 0.9F LC F SW F 2P = ---------2 F 22 = 1.1F LC 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 43 FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION The passive components associated to these frequencies are calculated with the following formulas Vin min ⎛ 1 ⎞ 1 C1 = ------------------ ⎜ ---------------- ⎟ ⎛ ------------------------------ ⎞ V RAMP ⎝ D ′ 2⎠ ⎝ 2 π ( F PO R1 )⎠ min 1 C2 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F Z2 R1 )⎠ 1 R2 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F Z1 C1 )⎠ 1 R3 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F P1 C2 )⎠ 1 C3 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F P2 R2 )⎠ On the 34704 VRAMP is half of 1.2 V since each operation mode spends only half the ramp. Regulator 3 (Synchronous Buck - internally compensated) • L: A buck power stage can be designed to operate in CCM for load currents above a certain level usually 5 to 15% of full load. The minimum value of inductor to maintain CCM can be determined by using the following procedure: 1. Define IOB as the minimum current to maintain CCM as 15% of full load. ( Vo + Io max ( R DSONLSFET + R L ) ( D ′ min ) T L min ≥ ------------------------------------------------------------------------------------------------------------2I OB Vo L min ≥ D ′ T ----------2IOB [H] • Then the output capacitor can be chosen as follow: [F] Io max dtI C OUT ≤ ---------------------ΔVo max Where ΔVOmax is the maximum allowed transient overshoot expressed as a percentage of the output voltage, typically from 3 to 5% of Vo. • Finally find the maximum allowed ESR to allow the desired transient response: • COUT: The three elements of output capacitor that contribute to its impedance and output voltage ripple are the ESR, the ESL and the capacitance C. A good approach to calculate the minimum real capacitance needed is to include the transient response analysis to control the maximum overshoot as desired. • First calculate the dt_I (inductor current rising time) given by: ΔVo r ( Fsw ) ( L ) ESR max = ------------------------------------Vo ( 1 – D min ) [Ω] NOTE: do not use the parameters ΔVOR and ΔVOmax indistinctly, the first one indicates the output voltage ripple, while the second one is the maximum output voltage overshoot (transient response). • R1 and RB: These two resistors help to set the output voltage to the desire value using a VREF=0.6 V, select R1 between 10 k and 100 K and then calculate RB as follows: [Ω] Io max T dtI = --------------------ΔIostep [s] Where the parameter ΔIO_step is the maximum current step during the current rising time and is define as: D max Vin min – Vo ΔIostep = ⎛ -------------⎞ ⎛ -------------------------------⎞ ⎠ ⎝ Fsw ⎠ ⎝ L [A] R1 RB = --------------------Vo----------- – 1 Vref Regulator 8 (Synchronous Boost - internally compensated -Voltage or current feedback) REG8 is a Synchronous Boost converter set to 15V with a maximum current of 30 mA and can be used with voltage 34704 44 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION feedback using the standard voltage divider configuration, or can be programmed to work with a current feedback configuration to control the current flowing through a LED string. It does not need external compensation network, thus the only components that need to be calculated are: • L: A boost power stage can be designed to operate in CCM for load currents above a certain level usually 5 to 15% of full load. The minimum value of inductor to maintain CCM can be determined by using the following procedure: • Define IOB as the minimum current to maintain CCM as 15% of full load: controls the amount of current flowing through it. To calculate this resistor, set the maximum current you want to flow though the string and use the following formula: V ref [Ω] RS = --------Io Where VREF=230 mV is the maximum internal reference voltage in current mode control that is reflected on the FB8 pin. When Input voltage is equal to or higher than VOUT8, a reverse bias diode is needed from the switching node to the output in order to cause a drop from the Input to the output, see Figure 9 below: Vo ( D ) ( 1 – D ) T L min ≥ -----------------------------------------2I OB 2 [H] BT8 VIN CBOOT L8 However the worst case condition for the boost power stage is when the input voltage is equal to one half of the output voltage, which results in the Maximum ÄIL, then: Vo ( T ) L min ≥ --------------16I OB SW8 D8 [H] VOUT8 R1 VOUT8 • COUT: The three elements of output capacitor that contribute to its impedance and output voltage ripple are the ESR, the ESL and the capacitance C. The minimum capacitor value is approximately: FB8 RB Figure 9. Reverse Bias Diode Io max D max C OUT ≥ ---------------------------Fsw ΔVo r [F] Regulator 7 (Inverter controller - external compensation needed) REG7 is a non-synchronous buck/boost inverting PWM voltage-mode control DC-DC regulator that drive an external P-MOSFET to supply a typical voltage of -7.0 V at a maximum current of 60 mA. • P-MOSFET: The peak current of the MOSFET is assumed to be ID, which is obtained by the following formula, define IOB from 5 to 15% of maximum current rating. – ( Io + I OB ) I Q ≥ I Lpeak = ---------------------------1–D And the voltage rating is given by: V Q = Vin – Vo • Diode D7: The peak value of the diode current is IFSM which should also be higher than ILpeak. The average current rating should be higher than the output current low and the repetition reverse voltage VRRM is given by: • Where ΔVOr is the desired output voltage ripple. • Now calculate ΔVOr the maximum allowed ESR to reach the desired. ΔVo r ESR ≤ -------------------------------------------Io max ⎛ ----------------------- + I ⎞ OB⎠ ⎝1 – D max [Ω] • R1 and RB (for Voltage feedback control): These two resistors help to set the output voltage to the desire value using a VREF=0.6 V, select R1 between 10k and 100K and then calculate RB as follows: R1 RB = --------------------Vo----------- – 1 Vref [Ω] • RS (For current feedback control with LED string): This resistor is attached at the end of the LED string and it 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 45 FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION V RRM ≥ Vin – Vo • L: The minimum value of inductor to maintain CCM can be determined by using the following procedure: • Output LC filter cutoff frequency (FLC): D ′ min F LC = ------------------------2 π LC OUT [Hz] 2 Vin min – VoT L min ≥ ------------------ ⎛ -------------------------------⎞ ⎝ Vo – Vin min⎠ 2Io max [H] Where D’min is the minimum off time percentage given by: Vin min D ′ min = ------------------------Vout max • COUT: The three elements of output capacitor that contribute to its impedance and output voltage ripple are the ESR, the ESL and the capacitance C. The minimum capacitor value is approximately: Io max D max C OUT ≥ ---------------------------F SW ΔVo r [F] • Cutoff frequency due to capacitor ESR: • Where ΔVOr is the desired output voltage ripple. • Now calculate the maximum allowed ESR to reach the desired. 1 F ESR = --------------------------------------2 π ( C OUT ) ESR • The right plane zero frequency: [Hz] ( D ′ min ) R LOAD RHP Z = ---------------------------------------D • 2πL ΔVo r ESR ≤ ------------------------------------------------Io max I OB ⎛ ----------------------- + -------------⎞ ⎝1 – D ⎠ max 1 – D [Ω] 2 [Hz] • Crossover frequency (or bandwidth): select this frequency as far away form the RHPZ as much as possible: • R1 and RB: These two resistors help to set the output voltage to the desire value using a VFB7=0.6V, select R1 between 10 k and 150 K and then calculate RB as follows: RHP Z F BW « --------------6 [Hz] 0.9 RB = ------------------------------------ R1 1.5 – Vo – 0.9 [Ω] The Type 3 external compensation network will be in charge of canceling some of these poles and zeros to achieve stability in the system. The following poles and zeroes frequencies are provided by the type 3 compensation: NOTE: RB is not grounded, instead is connected to VREF7 pin (VREF7=1.5 V) which provide a positive voltage to assure a positive voltage at the FB7 pin. • Compensation network. (C1,C2,C3, R2, R3) For compensating a buck converter, 4 important frequencies referring to the plant are: F PO = F BW F P1 = F ESR F Z1 = 0.9F LC F SW F 2P = ----------2 F 22 = 1.1F LC 34704 46 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION COMPONENT CALCULATION The passive components associated to these frequencies are calculated with the following formulas. Vin min ⎛ 1 ⎞ 1 C1 = ------------------ ⎜ ---------------- ⎟ ⎛ ------------------------------ ⎞ V RAMP ⎝ D ′ 2⎠ ⎝ 2 π ( F PO R1 )⎠ min 1 C2 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F Z2 R1 )⎠ 1 R2 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F Z1 C1 )⎠ 1 R3 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F P1 C2 )⎠ 1 C3 = ⎛ ----------------------------- ⎞ ⎝ 2 π ( F P2 R2 )⎠ On the 34704 VRAMP is half of 1.2 V since each operation mode spends only half the ramp. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 47 TYPICAL APPLICATIONS TYPICAL APPLICATIONS VIN VIN 34704A (19) V8 REG8 VOUT1 VG V1 SW8 BT8 VG REG8 SW1 BT1 BT2D VIN FB8 VIN VOUT7 DRV7 V7 PVIN2 SW2D VOUT2 V2 REG2 SW2U REG7 FB7 VREF7 COMP7 VIN V6 VOUT6 BT2U FB2 COMP2 BT3 PVIN3 SW3 VIN REG3 SW6 BT6 FB6 VIN BT5D PVIN5 SW5D REG6 VOUT3 FB3 BT4D PVIN4 SW4D VIN V3 V5 VOUT5 SW5U BT5U FB5 COMP5 VDDI VBUS SCL SDA V2 RST VIN AGND VOUT4 V4 REG4 REG5 SW4U BT4U FB4 COMP4 VIN ONOFF VIN VIN FREQ VDDI VIN SS PGND (EXPAD) Notes (18) 18. AGND(S) & PGND(S) SHOULD BE CONNECTED TOGETHER AS CLOSE TO THE IC AS POSSIBLE 19. REFER TO THE FB8 FUNCTIONAL PIN DESCRIPTION ON PAGE 17. 34704 48 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS Figure 10. 34704A Typical Application Diagram VIN VIN 34704B (21) REG8 VG SW8 BT8 VG REG8 SW1 BT1 FB8 VIN PVIN5 BT5D SW5D V5 VOUT5 VIN PVIN2 BT2D SW2D VOUT2 V2 REG2 SW2U REG5 SW5U BT5U FB5 COMP5 VIN PVIN4 BT4D SW4D V4 VOUT4 BT2U FB2 COMP2 PVIN3 BT3 SW3 VIN REG3 VOUT3 FB3 V3 REG4 SW4U BT4U FB4 COMP4 VDDI VBUS SCL SDA V2 RST VIN PGND (EXPAD) VIN ONOFF VIN VIN VIN FREQ SS AGND VIN Notes 20. AGND(S) & PGND(S) SHOULD BE CONNECTED TOGETHER AS CLOSE TO THE IC AS POSSIBLE 21. REFER TO THE FB8 FUNCTIONAL PIN DESCRIPTION ON PAGE 17. (20) Figure 11. 34704B Typical Application Diagram 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 49 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EP SUFFIX 56-PIN 98ASA10751D REVISION A 34704 50 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (CONTINUED) EP SUFFIX 56-PIN 98ASA10751D REVISION A 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 51 PACKAGING PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (CONTINUED) EP SUFFIX 56-PIN 98ASA10751D REVISION A 34704 52 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 2.0 3.0 4/2008 6/2008 • Initial Release • • • • Revised 34704 Simplified Application Diagram on page 1 Revised 34704 Internal Block Diagram on page 3 Revised 34704 Pin Definitions on page 4 Revised 34704A Typical Application Diagram on page 49 and 34704B Typical Application Diagram on page 49 4.0 5.0 6/2009 1/2010 • Updated category from Advance Information to Technical Data. • • • • • • • • • • • • • • • Added Max I2C Speed as 400kHz to dynamic electrical characteristics table Added Device Physical address to dynamic electrical characteristics table. Added register Definition summary table Changed REG7 name definition on Functional Description table to "Inverter boost" Added efficiency Plots Clarified GrpC and E Shutdown Sequence Clarified REG8 Voltage/Current Regulation Mode on feature list. Clarified Pulse Skipping operation. Added minimum Fine Scaling value at 40% Correted Register Vs Bit notation on I2C user interface section. Added I2C reading and writing Bit stream sequence example. Added ACCURATE Bit definition Revised Pin Definitions Table for Pins 3, 11, 35, 40, 46 and 53 Removed Li-ion battery references throughout document. Added Feedback Reference Voltage and Feedback Reference Voltage on Current Regulation Mode to Table 4. 34704 Analog Integrated Circuit Device Data Freescale Semiconductor 53 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008 - 2009. All rights reserved. MC34704 Rev. 5.0 2/2011