34844

Freescale Semiconductor Advance Information Document Number: 34844 Rev. 3.0, 11/2008 10 Channel LED Backlight Driver with Integrated Power Supply The 34844 is a high efficiency, LED driver for use in backlighting LCD displays from 10" to 20"+. Operating from supplies of 7V to 28V, the 34844 is capable of driving up to 160 LEDs in 10 parallel strings. Current in the 10 strings is matched to within ±2%, and can be programmed via the I2C/SM-Bus interface. The 34844 also includes a Pulse Width Monitor (PWM) generator for LED dimming. The LEDs can be dimmed to one of 256 levels, programmed through the I2C/SM-Bus interface. Up to 65,000:1 (256:1 PWM, 256:1 Current DAC) dimming ratio. The integrated boost converter generates the minimum output voltage required to keep all LEDs illuminated with the selected current, providing the highest efficiency possible. The integrated boost selfclocks at a default frequency of 600kHz, but may be programmed via I2C to 150/300/600/1200 kHz. The PWM frequency can be set from 100Hz to 25kHz, or can be synchronized to an external input. If not synchronized to another source, the internal PWM rate outputs on the CK pin. This enables multiple devices to be synchronized together. The 34844 also supports optical/temperature closed loop operation and also features LED over-temperature protection, LED short protection, and LED open circuit protection. The IC also includes overvoltage protection, over-current protection, and under-voltage lockout. Features • Input voltage of 7.0 to 28V • Boost output voltage up to 60V, with Dynamic Headroom Control (DHC) • 3.0A integrated boost FET • Up to 50mA LED current per channel • 90% efficiency (DC:DC) • 10-channel current mirror with ±2% current matching • I2C/SM-Bus interface • PWM frequency programmable or synchronizable from 100Hz to 25,000Hz • 32-Ld 5x5x1.0mm TQFN Package • Pb-free packaging designated by suffix code EP 7.0 to 28V 34844 LED DRIVER EP SUFFIX (PB-FREE) 98ASA10800D 32-PIN QFN-EP ORDERING INFORMATION Device MC34844EP/R2 Temperature Range (TA) -40°C to 105°C Package 32 QFN-EP Applications • • • • Monitors - up to 27 inch Personal Computer Notebooks GPS Screens Small screen Televisions 34844 VIN VDC1 VDC2 VDC3 COMP SLOPE SCK SDA PWM A0/SEN CK M/~S EN VDC1 ISET PIN NIN GND VOUT PGNDA PGNDB FAIL I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 VCC SWA SWB Control Unit VDC1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ VDC1 Figure 1. Simplified Application Diagram (SM-Bus Mode) * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2008. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VIN VDC1 VDC2 VDC3 COMP SLOPE VOUT CK EN M/~S PWM PWM GENERATOR I0 I1 I2 SCK SDA 10 CHANNEL 50mA CURRENT MIRROR I3 I4 I5 I6 I7 I8 ISET CURRENT DAC I9 CLOCK/PLL V SENSE FAIL BOOST CONTROLLER LDO OVP PGNDA PGNDB SWA SWB A0/SEN I2C INTERFACE PIN NIN TEMP/OPTO LOOP CONTROL OCP/OTP/UVLO GND Figure 2. 34844 Simplified Internal Block Diagram 34844 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS COMP VOUT VDC2 VDC1 PWM 25 24 CK 23 VDC3 TRANSPARENT TOP VIEW QFN - EP 5MM X 5MM 32 LEAD EP GND 22 SLOPE 21 NIN 20 PIN 19 ISET 18 FAIL 17 I9 9 I1 10 I2 11 I3 12 I4 13 I5 14 I6 15 I7 16 I8 M/~S SCK 27 SDA 26 32 VIN 1 PGNDB 2 SWB 3 SWA 4 PGNDA 5 A0/SEN 6 EN 7 IO 8 31 30 29 28 EP = Exposed Pad Figure 3. 34844 Pin Connections Table 1. 34844 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 11. Pin Number 1 2 3 4 5 6 7 8 - 17 18 Pin Name VIN PGNDB SWB SWA PGNDA A0/SEN EN I0-I9 FAIL Pin Function Power Power Input Input Power Input Input Input Open Drain Formal Name Input voltage Power Ground Switch node B Switch node A Power Ground Device Select Enable LED Channel Fault detection Input supply Power ground Boost switch connection B Boost switch connection A Power ground Address select, device select pin or OVP HW control Enable pin (active high, internal pull-up) LED string connections Fault detected pin (open drain): No Failure = Low impedance Failure = High Impedance LED current setting resistor Positive input analog current control Definition 19 20 21 22 23 24 25 ISET PIN NIN SLOPE VDC3 CK PWM Passive Input Input Passive Output Input/Output Input Current set Positive current scale Negative current scale Negative input analog current control Boost Slope Internal Regulator 3 Clock signal External PWM Boost slope compensation Setting resistor Decoupling capacitor for internal phase locked loop power Clock synchronization pin (input for M/~S = low - internal pull-up, output for M/~S = high) External PWM input (internal pull-down) 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 34844 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 11. Pin Number 26 27 28 29 30 31 32 EP Pin Name SDA SCK VDC1 COMP M/~S VDC2 VOUT GND Pin Function Bidirectional Bidirectional Output Passive Input Output Input Formal Name I2C data I2C clock Internal Regulator 1 Compensation pin Master/Slave selector Internal Regulator 2 Voltage Output Ground I2C data Line I2C clock line Decoupling capacitor for internal logic rail Boost converter Type compensation pin Selects Master Mode (1) or Slave Mode (0) Decoupling capacitor for internal regulator Boost Output voltage sense pin Ground Reference for all internal circuits other than Boost FET Definition 34844 4 Analog Integrated Circuit Device Data Freescale Semiconductor MAXIMUM RATINGS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Maximum Pin Voltages A0/SEN I0, I1, I2, I3, I4, I5, I6, I7, I8, I9,EN(4) VIN SWA, SWB, VOUT FAIL, PIN, NIN, ISET, M/~S, CK Maximum LED Current ESD Voltage(1) IMAX VESD +2000 +200 VMAX 7.0 45 30 65 6.0 55 mA V V Symbol Value Unit Human Body Model (HBM) Machine Model (MM) THERMAL RATINGS Ambient Temperature Range Junction to Ambient Junction to Case Temperature(2) TA TθJA TθJC TJ TSTO Reflow(3) TPPRT -40 to 105 32 3.5 150 -40 to 150 260 °C °C/W °C/W °C °C °C W Temperature(2) Maximum junction temperature Storage temperature range Peak Package Reflow Temperature During Power Dissipation TA = 25°C TA = 70°C TA = 85°C TA = 105°C 3.9 2.5 2.0 1.4 Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2), and the Machine Model (MM) (AEC-Q100003), RZAP = 0Ω 2. 3. 4. Per JEDEC51 Standard for Multilayer PCB Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 45V is the Maximum allowable voltage on all LED channels in off-state. 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS Table 3. Electrical Characteristics Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40°C ≤ TA ≤ 105°C, PGND = 0V, unless otherwise noted. Characteristic SUPPLY Supply Voltage Supply Current when Shutdown Mode Manual & SM-Bus: EN = Low, SCK & SDA=Low, PWM = Low I C: EN = Low, SETI C bit = 1, CLRI C bit = 0, PWM = Low Supply Current when Sleep Mode SM-Bus: EN = low, SCK & SDA= Active, SETI2C bit = 0, PWM=Low, EN bit = 0 I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 0, PWM=Low Supply Current when Operational Mode Boost=Pulse Skipping, Channels = 0% of Duty Cycle Manual: EN= High, SCK & SDA=Low, PWM=Low SM-Bus: EN= Low, SCK & SDA=Active, EN bit= 1, PWM=Low I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 1, PWM=Low Under-voltage Lockout VIN Rising Under-voltage Hysteresis VIN Falling VDC1 Voltage(5) CVDC1 = 2.2μF VDC2 Voltage(5) CVDC2 = 2.2μF VDC3 Voltage(5) CVDC3 = 2.2μF BOOST Output Voltage Range(6) VIN = 7.0V VIN = 28V Boost Switch Current Limit RDSON of Internal FET IDRAIN= 1.0A Boost Switch Off-state Leakage Current VSWA,SWB = 65V Peak Boost Efficiency(7) EFFBOOST 90 % IBOOST_LEAK 10 VOUT1 VOUT2 IFET RDSON 8.0 31 2.6 2.8 250 43 60 3.0 500 A mΩ V VDC3 2.4 2.5 2.6 V VDC2 5.5 6.0 6.5 V VDC1 2.4 2.5 2.6 V UVLOHYST 150 200 250 mV UVLO 5.4 6.0 6.4 V IOPERATIONAL 10.0 mA ISLEEP 2 2 2 Symbol Min Typ Max Unit VIN ISHUTDOWN 7.0 12 28 V - 2.0 17 3.0 - μA mA μA Notes 5. This output is for internal use only and not to be used for other purposes 6. Minimum and Maximum output voltages are dependent on Min/Max duty cycle condition. 7. Guaranteed by design 34844 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS Table 3. Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40°C ≤ TA ≤ 105°C, PGND = 0V, unless otherwise noted. Characteristic Line Regulation (8) VIN=7.0V to 28V Load Regulation (8) VLED = 8.0V to 65V (all Channels) Slope compensation voltage ramp RSLOPE = 68KΩ Current Sense Amplifier Gain Current Sense Resistor OTA Transconductance Transconductance Sink and Source Current Capability Output Voltage Precharge FAIL PIN Off-state Leakage Current VFAIL = 5.5V On-state Voltage Drop ISINK = 4.0mA LED CHANNELS Sink Current ICHx Register = 255, RISET=5.1kΩ 0.1%, PIN&NIN = Disabled, TA=25°C Regulated minimum voltage across drivers Pulse Width > 4μs Current Matching Accuracy ISET Pin Voltage RISET=5.1kΩ 0.1% LED Current Amplitude Resolution 1.0mA < ILED < 50mA Off-state Leakage Current, All channels (VCH = 45V) PIN INPUT Voltage to Disable PIN mode PIN Bias Current PIN = VSET Analog Dimming Current ICHx Register = 255, RISET=5.1kΩ 0.1% PIN = VSET/2 PIN = VSET Notes 8. Guaranteed by design 23.75 47.50 25 50 26.25 52.50 mA IDIM_PIN VPIN_DIS IPIN 2.2 -2.0 2.0 V μA ICH_LEAK 10 μA ILEDRES 1.5 % IMATCH VSET -2.0 2.017 2.048 2.0 2.079 % V VMIN 675 750 825 mV ISINK 49 50 51 mA VOL 0.4 V IFAIL_LEAK 5 μA ACSA RSENSE GM ISS VHOLD 0.45 9.0 22 200 100 0.5 0.55 mΩ μS μA V VSLOPE 0.49 V/μs IOUT/VLED -0.2 0.2 %/V Symbol IOUT/VIN Min -0.2 Typ Max 0.2 Unit %/V 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS Table 3. Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40°C ≤ TA ≤ 105°C, PGND = 0V, unless otherwise noted. Characteristic NIN INPUT Voltage to Disable NIN mode NIN Bias Current NIN = VSET Analog Dimming Current ICHx Register = 255, RISET=5.1kΩ 0.1% NIN = VSET/2 NIN = 0V OVER-TEMPERATURE PROTECTION Over-temperature Threshold(9) Rising Hysteresis I2C/SM-BUS PHYSICAL LAYER [SCK, SDA] I2C Address SM-Bus Address Input Low Voltage Input High Voltage Input Hysteresis Output Low Voltage Sink Current < 4.0mA Input Current Input Capacitance(9) LOGIC INPUTS / OUTPUTS (CK, M/~S, PWM, A0/SEN) Input Low Voltage Input High Voltage Input Hysteresis Input Current Output Low Voltage (CK) ISINK < 2.0mA Output High Voltage (CK) ISOURCE < 2.0mA Input Capacitance(9) Notes 9. Guaranteed by design CINI 5.0 ρF VOHL 2.2 5.5 V VILL VIHL VHYSL IIIL VOLL -0.3 1.5 -5.0 0.1 0.5 5.5 5.0 0.2 V V V μA V ADRI2C ADRSMB VILI VIHI VHYSI VOLI IINI CINI -0.3 2.1 0.3 -5.0 1110110 1110110 0.8 5.5 0.4 5.0 10 Binary Binary V V V V μA ρF OTT 150 165 25 175 °C 23.75 47.50 25 50 26.25 52.50 mA IDIM_NIN VNIN_DIS ININ 2.2 -2.0 2.0 V μA Symbol Min Typ Max Unit 34844 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS Table 3. Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40°C ≤ TA ≤ 105°C, PGND = 0V, unless otherwise noted. Characteristic OVER-VOLTAGE PROTECTION Over-voltage Clamp - OVP Register Table: OVP = Fh OVP = Eh OVP = Dh OVP = Ch OVP = Bh OVP = Ah OVP = 9h OVP = 8h OVP = 7h OVP = 6h OVP = 5h OVP = 4h OVP = 3h OVP = 2h Over-voltage threshold, Set by Hardware, Voltage at A0/SEN A0/SEN Sink Current BOOST Switching Frequency (BST [1:0]=0) Switching Frequency (BST [1:0]=1) Switching Frequency (BST [1:0]=2) Switching Frequency (BST [1:0]=3) Minimum Duty Cycle Maximum Duty Cycle Soft Start Period Boost Switch Rise Time(9) Boost Switch Fall Time(9) Notes 10. Guaranteed by design fSW0 fSW1 fSW2 fSW3 DMIN DMAX tSS tTR tF 0.14 0.27 0.54 1.08 80 0.15 0.30 0.60 1.2 10 85 6.5 15 25 0.17 0.33 0.66 1.32 15 MHz MHz MHz MHz % % ms ns ns ISINK_OVP 100 μA OVPFH OVPEH OVPDH OVPCH OVPBH OVPAH OVP9H OVP8H OVP7H OVP6H OVP5H OVP4H OVP3H OVP2H OVPHW 60.5 56.5 53 49 45 41 38 34 30.5 26 23 19 15 11 6.15 62.5 58 54 51 47 43 39 36 32 28 24 20 16 12 6.5 64.5 60 56 52.5 48.5 44.5 40.5 37.5 33.5 30 25 21 17 13 6.85 V V V V V V V V V V V V V V V Symbol Min Typ Max Unit 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS Table 3. Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40°C ≤ TA ≤ 105°C, PGND = 0V, unless otherwise noted. Characteristic PWM GENERATOR Input PWM Frequency Range (12) M/~S = Low (Slave Mode) PWM Frequency M/~S = High (Master Mode) FPWM Register = 768 FPWM Register = 192,000 PWM dimming resolution PWM PIN (DIRECT PWM CONTROL) Input PWM Pin Minimum Pulse(12) Input PWM Frequency Range PHASE LOCK LOOP CK Slave Mode Frequency Lock Range(11) M/~S = Low (Slave Mode) CK Slave Mode Input Jitter(12) M/~S = Low (Slave Mode) Slave Mode Acquisition Time M/~S = Low (Slave Mode) FPWMS=25KHz FPWMS=100Hz CK Frequency (Master Mode) FPWM Register = 768 FPWM Register = 192,000 I2C/SM-BUS PHYSICAL LAYER [SCK, SDA] Interface Frequency Range SM-Bus Power-on-Reset Time Output fall time 10ρF < CL < 400ρF Output rise time 10ρF