56800ERM

56855 Data Sheet Technical Data 56800E 16-bit Digital Signal Controllers DSP56855 Rev. 6 01/2007 freescale.com 56855 General Description • 120 MIPS at 120MHz • 24K x 16-bit Program SRAM • 24K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Access up to 2M words of program memory or 8M words of data memory • Chip Select Logic for glueless interface to ROM and SRAM • Six (6) independent channels of DMA • Enhanced Synchronous Serial Interface (ESSI) • Two (2) Serial Communication Interfaces (SCI) • General Purpose 16-bit Quad Timer with 1 external pin • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Computer Operating Properly (COP)/Watchdog Timer • Time-of-Day (TOD) • 100 LQFP package • Up to 18 GPIO 6 VDDIO 10 VDD 4 VSSIO 10 VSS VDDA 4 VSSA JTAG/ Enhanced OnCE Program Controller and Hardware Looping Unit Address Generation Unit 16-Bit DSP56800E Core Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit PAB PDB CDBR CDBW Memory Program Memory 24,576 x 16 SRAM Boot ROM 1024 x 16 ROM Data Memory 24,576 x 16 SRAM XDB2 XAB1 XAB2 PAB PDB CDBR CDBW System Bus Control DMA 6 channel Core CLK IPBus Bridge (IPBB) IPWDB Decoding Peripherals A0-20 [20:0] D0-D15 [15:0] RD Enable WR Enable CS0-CS3[3:0] or GPIOA0-GPIOA3[3:0] Bus Control External Address Bus Switch External Data Bus Switch External Bus Interface Unit 2 SCI ESSI0 or or GPIOE GPIOC IPRDB IPAB DMA Requests IPBus CLK POR 3 CLKO MODEA-C or (GPIOH0-H2) RSTO RESET System COP/TOD CLK Integration Module Quad Timer or GPIOG Interrupt Controller COP/ Watchdog Time of Day Clock Generator OSC PLL EXTAL XTAL 4 6 IRQA IRQB 56855 Block Diagram 56855 Technical Data, Rev. 6 Freescale Semiconductor 3 Part 1 Overview 1.1 56855 Features 1.1.1 • • • • • • • • • • • • • • • • Core Efficient 16-bit engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three (3) internal address buses and one (1) external address bus Four (4) internal data buses and one (1) external data bus Instruction set supports both DSP and controller functions Four (4) hardware interrupt levels Five (5) software interrupt levels Controller-style addressing modes and instructions for compact code Efficient C Compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced OnCE debug programming interface 1.1.2 • • Memory Harvard architecture permits up to three (3) simultaneous accesses to program and data memory On-Chip Memory — 24K × 16-bit Program SRAM — 24K × 16-bit Data SRAM — 1K × 16-bit Boot ROM • Off-Chip Memory Expansion (EMI) — Access up to 2M words of program memory or 8M words of data memory — Chip Select Logic for glue-less interface to ROM and SRAM 1.1.3 • • • • • Peripheral Circuits for 56855 General Purpose 16-bit Quad Timer with 1 external pin* Two (2) Serial Communication Interfaces (SCI)* Enhanced Synchronous Serial Interface (ESSI) module* Computer Operating Properly (COP)/Watchdog Timer JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging 56855 Technical Data, Rev. 6 4 Freescale Semiconductor 56855 Description • • • Six (6) independent channels of DMA Time-of-Day (TOD) Up to 18 GPIO * Each peripheral I/O can be used alternately as a General Purpose I/O if not needed 1.1.4 • • Energy Information Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs Wait and Stop modes available 1.2 56855 Description The 56855 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals, creating an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56855 is well-suited for many applications. The 56855 includes many peripherals that are especially useful for low-end Internet appliance applications and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices; remote metering; sonic alarms. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C Compilers, enabling rapid development of optimized control applications. The 56855 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56855 also provides two external dedicated interrupt lines, and up to 18 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56855 controller includes 24K words of Program RAM, 24K words of Data RAM and 1K of Boot ROM. It also supports program execution from external memory. This controller also provides a full set of standard programmable peripherals that include one Enhanced Synchronous Serial Interface (ESSI), two Serial Communications Interfaces (SCI), and one Quad Timer. The ESSI, SCIs, four chip selects and Quad Timer external output can be used as General Purpose Input/Outputs when its primary function is not required. 56855 Technical Data, Rev. 6 Freescale Semiconductor 5 1.3 State of the Art Development Environment • • Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Product Documentation The four documents listed in Table 1-1 are required for a complete description of and proper design with the 56855. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Table 1-1 56855 Chip Documentation Topic 56800E Reference Manual DSP56855 User’s Manual 56855 Technical Data Sheet DSP56855 Errata Description Detailed description of the 56800E architecture, and 16-bit core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the 56855 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Details any chip issues that might be present Order Number 56800ERM DSP5685xUM 56855 DSP56855E 56855 Technical Data, Rev. 6 6 Freescale Semiconductor Data Sheet Conventions 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR “asserted” “deasserted” Examples: This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56855 Technical Data, Rev. 6 Freescale Semiconductor 7 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56855 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals present. Table 2-1 56855 Functional Group Pin Allocations Functional Group Power (VDD, VDDIO, or VDDA) Ground (VSS, VSSIO,or VSSA) PLL and Clock External Bus Signals External Chip Select* Interrupt and Program Control Enhanced Synchronous Serial Interface (ESSI0) Port* Serial Communications Interface (SCI0) Ports* Serial Communications Interface (SCI1) Ports* Quad Timer Module Port* JTAG/Enhanced On-Chip Emulation (EOnCE) *Alternately, GPIO pins Number of Pins (4, 10, 1)1 (4, 10, 1)1 3 39 4 72 6 2 2 1 6 1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA 2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed. 56855 Technical Data, Rev. 6 8 Freescale Semiconductor Introduction Logic Power VDD VSS 4 4 1 1 RXDO (GPIOE0) TXDO (GPIOE1) RXD1 (GPIOE2) TXD1 (GPIOE3) SCI 0 1 I/O Power Analog Power1 VDDIO VSSIO VDDA VSSA 10 10 1 1 1 1 1 1 1 A0 - A20 External Bus D0 - D15 RD WR 1 SCI 2 STD0 (GPIOC0) SRD0 (GPIOC1) SCK0 (GPIOC2) SC00 (GPIOC3) SC01 (GPIOC4) SC02 (GPIOC5) ESSI 0 56855 21 16 1 1 1 Chip Select CS0 - CS3 (GPIOA0 - A3) 4 1 Timer Module TIO0 (GPIOG0) 1 1 1 XTAL EXTAL CLKO PLL/Clock IRQA IRQB Interrupt/ Program Control MODA, MODB, MODC (GPIOH0 - H2) RESET RSTO 1 1 3 1 1 1 1 1 1 1 1 TCK TDI TDO TMS TRST DE JTAG / Enhanced OnCE Figure 2-1 56855 Signals Identified by Functional Group2 1. Specifically for PLL, OSC, and POR. 2. Alternate pin functions are shown in parentheses. 56855 Technical Data, Rev. 6 Freescale Semiconductor 9 Part 3 Signals and Package Information All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions: 1. When a pin has GPIO functionality, the pull-up may be disabled under software control. 2. MODE A, MODE B and MODE C pins have no pull-up. 3. TCK has a weak pull-down circuit always active. 4. Bidirectional I/O pullups automatically disable when the output is enabled. This table is presented consistently with the Signals Identified by Functional Group figure. 1. BOLD entries in the Type column represents the state of the pin just out of reset. 2. Output(Z) means an output in a High-Z condition. Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP Pin No. 9 35 65 84 10 36 66 85 Signal Name VDD VDD VDD VDD VSS VSS VSS VSS VSS Ground (VSS)—These pins provide grounding for the internal structures of the chip and should all be attached to VSS. Type VDD Description Power (VDD)—These pins provide power to the internal structures of the chip, and should all be attached to VDD. 56855 Technical Data, Rev. 6 10 Freescale Semiconductor Introduction Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. 1 14 29 43 49 58 72 76 86 96 2 15 30 44 50 60 73 78 87 97 2 18 19 Signal Name VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VDDA VSSA VDDA VSSA Analog Power (VDDA)—These pins supply an analog power source. Analog Ground (VSSA)—This pin supplies an analog ground. VSSIO Ground (VSSIO)—These pins provide grounding for all I/O and ESD structures of the chip and should all be attached to VSS. Type VDDIO Description Power (VDDIO)—These pins provide power for all I/O and ESD structures of the chip, and should all be attached to VDDIO (3.3V). 56855 Technical Data, Rev. 6 Freescale Semiconductor 11 Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. 5 6 7 8 22 23 24 25 31 32 33 34 45 46 47 48 53 54 55 56 57 Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Type Output(Z) Description Address Bus (A0-A20)—These signals specify a word address for external program or data memory access. 56855 Technical Data, Rev. 6 12 Freescale Semiconductor Introduction Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. 59 67 68 69 70 71 79 80 81 82 83 94 95 98 99 3 Signal Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 RD Output Read Enable (RD)— is asserted during external memory read cycles. This signal is pulled high during reset. 4 WR Output Write Enable (WR) — is asserted during external memory write cycles. This signal is pulled high during reset. 61 CS0 GPIOA0 Output Input/Output External Chip Select (CS0)—This pin is used as a dedicated GPIO. Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. External Chip Select (CS1)—This pin is used as a dedicated GPIO. Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. External Chip Select (CS2)—This pin is used as a dedicated GPIO. Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Type Input/Output(Z) Description Data Bus (D0-D15)—These pins provide the bidirectional data for external program or data memory accesses. 62 CS1 GPIOA1 Output Input/Output 63 CS2 GPIOA2 Output Input/Output 56855 Technical Data, Rev. 6 Freescale Semiconductor 13 Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. 64 Signal Name CS3 GPIOA3 Type Output Input/Output Description External Chip Select (CS3)—This pin is used as a dedicated GPIO. Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Timer Input/Output (TIO0)—This pin can be independently configured to be either timer input source or output flag. Port G GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. External Interrupt Request A and B—The IRQA and IRQB inputs are asynchronized external interrupt requests that indicate that an external device is requesting service. A Schmitt trigger input is used for noise immunity. They can be programmed to be level-sensitive or negative-edgetriggered. If level-sensitive triggering is selected, an external pull-up resistor is required for Wired-OR operation. Mode Select (MODA)—During the bootstrap process MODA selects one of the eight bootstrap modes. Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed. Mode Select (MODB)—During the bootstrap process MODB selects one of the eight bootstrap modes. Port H GPIO (1)—This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed. Mode Select (MODC)—During the bootstrap process MODC selects one of the eight bootstrap modes. Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed. Reset (RESET)—This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the MODA, MODB, and MODC pins. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware reset is required and it is necessary not to reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but do not assert TRST. 27 RSTO Output Reset Output (RSTO)—This output is asserted on any reset condition (external reset, low voltage, software or COP). 77 TIO0 Input/Output GPIOG0 16 17 IRQA IRQB Input/Output Input 11 MODA Input GPIOH0 12 MODB Input/Output Input GPIOH1 13 MODC Input/Output Input GPIOH2 28 RESET Input/Output Input 56855 Technical Data, Rev. 6 14 Freescale Semiconductor Introduction Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. 51 Signal Name RXD0 Type Input Description Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial data and transfers it to the SCI 0 receive shift register. Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Serial Transmit Data 0 (TXD0)—This signal transmits data from the SCI 0 transmit data register. Port E GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Serial Receive Data 1 (RXD1)—This input receives byte-oriented serial data and transfers it to the SCI 1 receive shift register. Port E GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Serial Transmit Data 1 (TXD1)—This signal transmits data from the SCI 1 transmit data register. Port E GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. ESSI Transmit Data (STD0)—This output pin transmits serial data from the ESSI Transmitter Shift Register. Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Receive Data (SRD0)—This input pin receives serial data and transfers the data to the ESSI Receive Shift Register. Port C GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Clock (SCK0)—This bidirectional pin provides the serial bit rate clock for the transmit section of the ESSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. Port C GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. GPIOE0 52 TXD0 Input/Output Output(Z) GPIOE1 74 RXD1 Input/Output Input GPIOE2 75 TXD1 Input/Output Output(Z) GPIOE3 88 STD0 Input/Output Output GPIOC0 89 SRD0 Input/Output Input GPIOC1 90 SCK0 Input/Output Input/Output GPIOC2 Input/Output 56855 Technical Data, Rev. 6 Freescale Semiconductor 15 Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. 91 Signal Name SC00 Type Input/Output Description ESSI Serial Control Pin 0 (SC00)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin will be used for the receive clock I/O. For synchronous mode, this pin is used either for transmitter1 output or for serial I/O flag 0. Port C GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Control Pin 1 (SC01)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin is the receiver frame sync I/O. For synchronous mode, this pin is used either for transmitter2 output or for serial I/O flag 1. Port C GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. Crystal Oscillator Output (XTAL)—This output connects the internal crystal oscillator output to an external crystal. If an external clock source other than a crystal oscillator is used, XTAL must be used as the input. External Crystal Oscillator Input (EXTAL)—This input should be connected to an external crystal. If an external clock source other than a crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2 Clock Output (CLKO)—This pin outputs a buffered clock signal. When enabled, this signal is the system clock divided by four. Test Clock Input (TCK)—This input pin provides a gated clock to synchronize the test logic and to shift serial data to the JTAG/Enhanced OnCE port. The pin is connected internally to a pull-down resistor. Test Data Input (TDI)—This input pin provides a serial input data stream to the JTAG/Enhanced OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Test Data Output (TDO)—This tri-statable output pin provides a serial output data stream from the JTAG/Enhanced OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. GPIOC3 92 SC01 Input/Output Input/Output GPIOC4 93 SC02 Input/Output Input/Output GPIOC5 20 XTAL Input or Output Input/Output 21 EXTAL Input 26 42 CLKO TCK Output Input 40 TDI Input 39 TDO Output (Z) 56855 Technical Data, Rev. 6 16 Freescale Semiconductor General Characteristics Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. 41 Signal Name TMS Type Input Description Test Mode Select Input (TMS)—This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Note: 38 TRST Input Always tie the TMS pin to VDD through a 2.2K resistor. Test Reset (TRST)—As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment, since the Enhanced OnCE/JTAG module is under the control of the debugger. In this case it is not necessary to assert TRST when asserting RESET. Outside of a debugging environment RESET should be permanently asserted by grounding the signal, thus disabling the Enhanced OnCE/JTAG module on the device. Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. 37 DE Input/Output Debug Event (DE)—This is an open-drain, bidirectional, active low signal. As an input, it is a means of entering debug mode of operation from an external command controller. As an output, it is a means of acknowledging that the chip has entered debug mode. This pin is connected internally to a weak pull-up resistor. Part 4 Specifications 4.1 General Characteristics The 56855 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The 56855 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized 56855 Technical Data, Rev. 6 Freescale Semiconductor 17 specifications will be published after complete characterization and device qualifications have been completed. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Table 4-1 Absolute Maximum Ratings Characteristic Supply voltage, core Supply voltage, IO Supply voltage, analog Digital input voltages Analog input voltages (XTAL, EXTAL) Current drain per pin excluding VDD, GND Junction temperature Storage temperature range 1. VDD must not exceed VDDIO 2. VDDIO and VDDA must not differ by more that 0.5V Symbol VDD1 VDDIO2 VDDIO VIN VINA I TJ TSTG 2 Min VSS – 0.3 VSSIO – 0.3 VSSA – 0.3 VSSIO – 0.3 VSSA – 0.3 — -40 -55 Max VSS + 2.0 VSSIO + 4.0 VDDA + 4.0 VSSIO + 5.5 VDDA + 0.3 8 120 150 Unit V V V mA °C °C Table 4-2 Recommended Operating Conditions Characteristic Supply voltage for Logic Power Supply voltage for I/O Power Supply voltage for Analog Power Symbol VDD VDDIO VDDA Min 1.62 3.0 3.0 Max 1.98 3.6 3.6 Unit V V V 56855 Technical Data, Rev. 6 18 Freescale Semiconductor General Characteristics Table 4-2 Recommended Operating Conditions Characteristic Ambient operating temperature PLL clock frequency1 Operating Frequency2 Frequency of peripheral bus Frequency of external clock Frequency of oscillator Frequency of clock via XTAL Frequency of clock via EXTAL Symbol TA fpll fop fipb fclk fosc fxtal fextal Min -40 — — — — 2 — 2 Max 85 240 120 60 240 4 240 4 Unit °C MHz MHz MHz MHz MHz MHz MHz 1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and selected. The actual frequency depends on the source clock frequency and programming of the CGM module. 2. Master clock is derived from on of the following four sources: fclk = fxtal when the source clock is the direct clock to EXTAL fclk = fpll when PLL is selected fclk = fosc when the source clock is the crystal oscillator and PLL is not selected fclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected Table 4-3 Thermal Characteristics1 100-pin LQFP Characteristic Symbol Thermal resistance junction-to-ambient (estimated) I/O pin power dissipation Power dissipation Maximum allowed PD 1. See Section 6.1 for more detail. 2. TJ = Junction Temperature TA = Ambient Temperature Value 41.2 User Determined PD = (IDD × VDD) + PI/O (TJ – TA) / RθJA 2 Unit °C/W W W °C θJA PI/O PD PDMAX 56855 Technical Data, Rev. 6 Freescale Semiconductor 19 4.2 DC Electrical Characteristics Table 4-4 DC Electrical Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Input high voltage (XTAL/EXTAL) Input low voltage (XTAL/EXTAL) Input high voltage Input low voltage Input current low (pullups disabled) Input current high (pullups disabled) Output tri-state current low Output tri-state current high Output High Voltage Output Low Voltage Output High Current Output Low Current Input capacitance Output capacitance VDD supply current (Core logic, memories, peripherals) Run Deep Stop2 Light Stop3 VDDIO supply current (I/O circuity) Run5 Deep Stop2 VDDA supply current (analog circuity) Deep Stop2 Low Voltage Interrupt6 Low Voltage Interrupt Recovery Hysteresis Power on Reset7 Note: 1. 2. 3. 4. 1 Symbol VIHC VILC VIH VIL IIL IIH IOZL IOZH VOH VOL IOH IOL CIN COUT IDD4 Min VDDA – 0.8 -0.3 2.0 -0.3 -1 -1 -10 -10 VDDIO – 0.7 — 8 8 — — — — — Typ VDDA — — — — — — — — — — — 8 12 70 0.05 5 Max VDDA + 0.3 0.5 5.5 0.8 1 1 10 10 — 0.4 16 16 — — 110 10 14 Unit V V V V μA μA μA μA V V mA mA pF pF mA mA mA IDDIO — IDDA — VEI VEIH POR — — — 60 2.5 50 1.5 120 2.85 — 2.0 μA V mV V 40 0 50 1.5 mA mA Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry. 56855 Technical Data, Rev. 6 20 Freescale Semiconductor Supply Voltage Sequencing and Separation Cautions 5. 6. Running core and performing external memory access. Clock at 120 MHz. When VDD drops below VEI max value, an interrupt is generated. 7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates. 150 EMI Mode5 MAC Mode1 120 90 IDD (mA) 60 30 0 20 40 60 80 100 120 Figure 4-1 Maximum Run IDDTOTAL vs. Frequency (see Notes 1. and 5. in Table 4-4) 4.3 Supply Voltage Sequencing and Separation Cautions Figure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies. 56855 Technical Data, Rev. 6 Freescale Semiconductor 21 DC Power Supply Voltage 3.3V VDDIO, VDDA 2 Supplies Stable VDD 1.8V 1 0 Notes: 1. VDD rising before VDDIO, VDDA 2. VDDIO, VDDA rising much faster than VDD Time Figure 4-2 Supply Voltage Sequencing and Separation Cautions VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from rising faster than VDDIO. VDD should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reaches approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper operation, the difference between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially leakage current. During supply sequencing, the following general relationship should be adhered to: VDDIO > VDD > (VDDIO - 2.1V) In practice, VDDA is typically connected directly to VDDIO with some filtering. 56855 Technical Data, Rev. 6 22 Freescale Semiconductor AC Electrical Characteristics Supply 3.3V Regulator VDDIO, VDDA 1.8V Regulator VDD Figure 4-3 Example Circuit to Control Supply Sequencing 4.4 AC Electrical Characteristics Timing waveforms in Section 4.2 are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V for all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of VIH and VIL for an input signal are shown. VIH Input Signal Midpoint1 Fall Time Note: The midpoint is VIL + (VIH – VIL)/2. Low High 90% 50% 10% VIL Rise Time Figure 4-4 Input Signal Measurement References Figure 4-5 shows the definitions of the following signal states: • • • • Active state, when a bus or signal is driven, and enters a low impedance state. Tri-stated, when a bus or signal is placed in a high impedance state. Data Valid state, when a signal level has reached VOL or VOH. Data Invalid state, when a signal level is in transition between VOL and VOH. Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data Active Data3 Valid Data3 Figure 4-5 Signal State 56855 Technical Data, Rev. 6 Freescale Semiconductor 23 4.5 External Clock Operation The 56855 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 4.5.1 Crystal Oscillator The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 4-5. In Figure 4-6 a typical crystal oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal Frequency = 2–4 MHz (optimized for 4MHz) EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 10MΩ TOD_SEL bit in CGM must be set to 0 Figure 4-6 Crystal Oscillator 4.5.2 High Speed External Clock Source (> 4MHz) The recommended method of connecting an external clock is given in Figure 4-7. The external clock source is connected to XTAL and the EXTAL pin is held at ground, VDDA, or VDDA/2. The TOD_SEL bit in CGM must be set to 0. 56855 XTAL EXTAL GND,VDDA, External Clock or VDDA/2 (up to 240MHz) Figure 4-7 Connecting a High Speed External Clock Signal using XTAL 56855 Technical Data, Rev. 6 24 Freescale Semiconductor External Clock Operation 4.5.3 Low Speed External Clock Source (2-4MHz) The recommended method of connecting an external clock is given in Figure 4-8. The external clock source is connected to XTAL and the EXTAL pin is held at VDDA/2. The TOD_SEL bit in CGM must be set to 0. 56855 XTAL EXTAL External Clock (2-4MHz) VDDA/2 Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL Table 4-5 External Clock Operation Timing Requirements4 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Frequency of operation (external clock driver)1 Clock Pulse Width4 External clock input rise time2, 4 External clock input fall time3, 4 1. 2. 3. 4. Symbol fosc tPW trise tfall Min 0 6.25 — — Typ — — — — Max 240 — TBD TBD Unit MHz ns ns ns See Figure 4-7 for details on using the recommended connection of an external clock driver. External clock input rise time is measured from 10% to 90%. External clock input fall time is measured from 90% to 10%. Parameters listed are guaranteed by design. VIH External Clock 90% 50% 10% tPW tPW 90% 50% 10% tfall trise VIL Note: The midpoint is VIL + (VIH – VIL)/2. Figure 4-9 External Clock Timing 56855 Technical Data, Rev. 6 Freescale Semiconductor 25 Table 4-6 PLL Timing Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic External reference crystal frequency for the PLL1 PLL output frequency PLL stabilization time 2 Symbol fosc fclk tplls Min 2 40 — Typ 4 — 1 Max 4 240 10 Unit MHz MHz ms 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 4MHz input crystal. 2. This is the minimum time required after the PLL setup is changed to ensure reliable operation. 4.6 External Memory Interface Timing The External Memory Interface is designed to access static memory and peripheral devices. Figure 4-10 shows sample timing and parameters that are detailed in Table 4-7. The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user controlled wait states. The equation: t = D + P * (M + W) should be used to determine the actual time of each parameter. The terms in the above equation are defined as: t P parameter delay time the period of the system clock, which determines the execution rate of the part (i.e. when the device is operating at 120 MHz, P = 8.33 ns). D fixed portion of the delay, due to on-chip path delays. M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible clock duty cycle derating. W the sum of the applicable wait state controls. See the “Wait State Controls” column of Table 4-7 for the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for details of what each wait state field controls. Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change if the operating frequency of the part changes. The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain two sets of numbers to account for this difference. The “Wait States Configuration” column of Table 4-7 should be used to make the appropriate selection. 56855 Technical Data, Rev. 6 26 Freescale Semiconductor External Memory Interface Timing A0-Axx,CS tRD tARDD tRDA tRDRD tARDA RD tAWR tWRWR WR tWR tWAC tWRRD tRDWR tDWR D0-D15 tDOS tDOH tAD tRDD tDRD Data Out Data In Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 4-10 External Memory Interface Timing Table 4-7 External Memory Interface Timing Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0–3.6V, TA = –40× to +120×C, CL £ 50pF, P = 8.333ns Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Data Out Valid to WR Asserted Symbol tAWR tWR Wait States Configuration WWS=0 WWS>0 WWS=0 WWS>0 WWS=0 WWS=0 WWS>0 WWS>0 D -0.79 -1.98 -0.86 -0.01 -1.52 - 5.69 -2.10 -4.66 -1.47 -2.36 -4.67 -1.60 - 0.44 M 0.50 0.69 0.19 0.00 0.00 0.25 0.19 0.50 0.25 0.19 0.50 0.25 0.00 Wait States Controls WWSS WWS Unit ns ns tDWR WWSS ns Valid Data Out Hold Time after WR Deasserted Valid Data Out Set Up Time to WR Deasserted Valid Address after WR Deasserted RD Deasserted to Address Invalid tDOH tDOS tWAC tRDA WWSH WWS,WWSS WWSH RWSH ns ns ns 56855 Technical Data, Rev. 6 Freescale Semiconductor 27 Table 4-7 External Memory Interface Timing (Continued) Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0–3.6V, TA = –40× to +120×C, CL £ 50pF, P = 8.333ns Characteristic Address Valid to RD Deasserted Valid Input Data Hold after RD Deasserted RD Assertion Width Address Valid to Input Data Valid Address Valid to RD Asserted RD Asserted to Input Data Valid WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted Symbol tARDD tDRD tRD tAD tARDA tRDD tWRRD tRDRD tWRWR tRDWR Wait States Configuration D -2.07 0.00 -1.34 -10.27 -13.5 - 0.94 -9.53 -12.64 -0.75 -0.162 M 1.00 N/A1 1.00 1.00 1.19 0.00 1.00 1.19 0.25 0.00 0.75 1.00 0.50 0.69 Wait States Controls RWSS,RWS — RWS RWSS,RWS RWSS RWSS,RWS WWSH,RWSS RWSS,RWSH WWSS, WWSH MDAR, BMDAR, RWSH, WWSS Unit ns ns ns ns ns ns ns ns ns ns WWS=0 WWS>0 -0.44 -0.11 0.14 -0.57 1. N/A since device captures data before it deasserts RD 2. If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used. 4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 1. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration3 RESET Deassertion to First External Address Output Edge-sensitive Interrupt Request Width Symbol tRAZ tRA tRDA tIRW Min — 30 — 1T + 3 Max 11 — 120T — Unit ns ns ns ns See Figure 4-11 4-11 4-11 4-12 56855 Technical Data, Rev. 6 28 Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 1. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2 Characteristic IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State4 Delay from IRQA Assertion (exiting Stop) to External Data Memory5 Delay from IRQA Assertion (exiting Wait) to External Data Memory Fast6 Normal7 RSTO pulse width8 normal operation internal reset mode (Continued) Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Symbol tIDM tIDM -FAST tIG tIG -FAST tIRI tIRI -FAST tIW tIF Min 18T 14T 18T 14T 22T 18T 1.5T Max — — — — — — — Unit ns See Figure 4-13 ns 4-13 ns 4-14 ns 4-15 4-15 18T 22ET — — ns ns 4-16 128ET 8ET — — — — tRSTO 1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns. 2. Parameters listed are guaranteed by design. 3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock, txtal, textal or tosc. 4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 5. The interrupt instruction fetch is visible on the pins only in Mode 3. 6. Fast stop mode: Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less cycle and tclk will continue same value it had before stop mode was entered. 7. Normal stop mode: As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate. 8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns. 56855 Technical Data, Rev. 6 Freescale Semiconductor 29 RESET tRAZ tRA tRDA A0–A20, D0–D15 CS, RD, WR First Fetch First Fetch Figure 4-11 Asynchronous Reset Timing IRQA IRQB tIRW Figure 4-12 External Interrupt Timing (Negative-Edge-Sensitive) A0–A20, CS, RD, WR IRQA, IRQB First Interrupt Instruction Execution tIDM a) First Interrupt Instruction Execution General Purpose I/O Pin IRQA, IRQB b) General Purpose I/O tIG Figure 4-13 External Level-Sensitive Interrupt Timing 56855 Technical Data, Rev. 6 30 Freescale Semiconductor Host Interface Port IRQA, IRQB tIRI A0–A20, CS, RD, WR First Interrupt Vector Instruction Fetch Figure 4-14 Interrupt from Wait State Timing tIW IRQA tIF A0–A20, CS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 4-15 Recovery from Stop State Using Asynchronous Interrupt Timing RESET tRSTO Figure 4-16 Reset Output Timing 4.8 Host Interface Port Table 4-8 Host Interface Port Timing1 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Access time Disable time Time to disassert Lead time Symbol TACKDV TACKDZ TACKREQH Min — 3 3.5 0 Max 13 — 9 — Unit ns ns ns ns See Figure 4-17 4-17 4-17 4-20 4-17 4-20 TREQACKL 56855 Technical Data, Rev. 6 Freescale Semiconductor 31 Table 4-8 Host Interface Port Timing1 (Continued) Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Access time Disable time Disable time Setup time Hold time Setup time Hold time Pulse width Time to re-assert 1. After second write in 16-bit mode 2. After first write in 16-bit mode or after write in 8-bit mode Symbol TRADV Min — 5 3 3 1 3 1 5 Max 13 — — — — — — — Unit ns ns ns ns ns ns ns ns See Figure 4-18 4-19 4-18 4-19 4-18 4-19 4-20 4-20 4-21 4-23 4-21 4-22 4-21 4-22 4-17 4-20 TRADX TRADZ TDACKS TACKDH TADSS TDSAH TWDS TACKREQL 4T + 5 5 5T + 9 13 ns ns 1. The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns. HACK TACKDZ TACKDV HD TREQACKL TACKREQH TACKREQL HREQ Figure 4-17 Controller-to-Host DMA Read Mode 56855 Technical Data, Rev. 6 32 Freescale Semiconductor Host Interface Port HA TRADX HCS HDS HRW TRADV TRADZ HD Figure 4-18 Single Strobe Read Mode HA TRADX HCS HWR HRD TRADZ TRADV HD Figure 4-19 Dual Strobe Read Mode 56855 Technical Data, Rev. 6 Freescale Semiconductor 33 HACK TDACKS TACKDH HD TREQACKL TACKREQH TACKREQL HREQ Figure 4-20 Host-to-Controller DMA Write Mode HA TDSAH HCS TWDS HDS TDSAH HRW TADSS TADSS TDSAH HD Figure 4-21 Single Strobe Write Mode HA HCS TWDS HWR TADSS TDSAH HRD TADSS HD Figure 4-22 Dual Strobe Write Mode 56855 Technical Data, Rev. 6 34 Freescale Semiconductor Quad Timer Timing 4.9 Quad Timer Timing Table 4-9 Quad Timer Timing1, 2 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period Symbol PIN PINHL POUT POUTHL Min 2T + 3 1T + 3 2T - 3 1T - 3 Max — — — — Unit ns ns ns ns 1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns. 2. Parameters listed are guaranteed by design. Timer Inputs PIN PINHL PINHL Timer Outputs POUT POUTHL POUTHL Figure 4-23 Timer Timing 56855 Technical Data, Rev. 6 Freescale Semiconductor 35 4.10 Enhanced Synchronous Serial Interface (ESSI) Timing Table 4-10 ESSI Master Mode1 Switching Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Parameter SCK frequency SCK period3 SCK high time SCK low time Output clock rise/fall time Delay from SCK high to SC2 (bl) high - Master5 Delay from SCK high to SC2 (wl) high - Master5 Delay from SC0 high to SC1 (bl) high - Master5 Delay from SC0 high to SC1 (wl) high - Master5 Delay from SCK high to SC2 (bl) low - Master5 Delay from SCK high to SC2 (wl) low - Master5 Delay from SC0 high to SC1 (bl) low - Master5 Delay from SC0 high to SC1 (wl) low - Master5 SCK high to STD enable from high impedance - Master SCK high to STD valid - Master SCK high to STD not valid - Master SCK high to STD high impedance - Master SRD Setup time before SC0 low - Master SRD Hold time after SC0 low - Master Symbol fs tSCKW tSCKH tSCKL — tTFSBHM tTFSWHM tRFSBHM tRFSWHM tTFSBLM tTFSWLM tRFSBLM tRFSWLM tTXEM tTXVM tTXNVM tTXHIM tSM tHM Min — 66.7 33.44 33.44 — -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -0.1 -0.1 -0.1 -4 4 4 Typ — — — — 4 — — — — — — — — — — — — — — Max 152 — — — — 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2 2 — 0 — — Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Synchronous Operation (in addition to standard internal clock parameters) SRD Setup time before SCK low - Master SRD Hold time after SCK low - Master 1. Master mode is internally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part. tTSM tTHM 4 4 — — — — ns ns 56855 Technical Data, Rev. 6 36 Freescale Semiconductor Enhanced Synchronous Serial Interface (ESSI) Timing 3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length tSCKH SCK output tSCKW tSCKL tTFSBHM SC2 (bl) output tTFSWHM SC2 (wl) output tTXVM tTXEM STD SC0 output tRFSBHM SC1 (bl) output tRFSWHM SC1 (wl) output First Bit tTFSBLM tTFSWLM tTXNVM Last Bit tTXHIM tRFBLM tRFSWLM tSM SRD tHM tTSM tTHM Figure 4-24 Master Mode Timing Diagram 56855 Technical Data, Rev. 6 Freescale Semiconductor 37 Table 4-11 ESSI Slave Mode1 Switching Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Parameter SCK frequency SCK period3 SCK high time SCK low time Output clock rise/fall time Delay from SCK high to SC2 (bl) high - Slave5 Delay from SCK high to SC2 (wl) high - Slave5 Delay from SC0 high to SC1 (bl) high - Slave5 Delay from SC0 high to SC1 (wl) high - Slave5 Delay from SCK high to SC2 (bl) low - Slave5 Delay from SCK high to SC2 (wl) low - Slave5 Delay from SC0 high to SC1 (bl) low - Slave5 Delay from SC0 high to SC1 (wl) low - Slave5 SCK high to STD enable from high impedance - Slave SCK high to STD valid - Slave SC2 high to STD enable from high impedance (first bit) - Slave SC2 high to STD valid (first bit) - Slave SCK high to STD not valid - Slave SCK high to STD high impedance - Slave SRD Setup time before SC0 low - Slave SRD Hold time after SC0 low - Slave Symbol fs tSCKW tSCKH tSCKL — tTFSBHS tTFSWHS tRFSBHS tRFSWHS tTFSBLS tTFSWLS tRFSBLS tRFSWLS tTXES tTXVS tFTXES tFTXVS tTXNVS tTXHIS tSS tHS Min — 66.7 33.44 33.44 — -1 -1 -1 -1 -29 -29 -29 -29 — 4 4 4 4 4 4 4 Typ — — — — 4 — — — — — — — — — — — — — — — — Max 152 — — — — 29 29 29 29 29 29 29 29 15 15 15 15 15 15 — — Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Synchronous Operation (in addition to standard external clock parameters) SRD Setup time before SCK low - Slave SRD Hold time after SCK low - Slave 1. Slave mode is externally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part. tTSS tTHS 4 4 — — — — ns ns 56855 Technical Data, Rev. 6 38 Freescale Semiconductor Enhanced Synchronous Serial Interface (ESSI) Timing 3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length tSCKW tSCKH SCK input tTFSBHS SC2 (bl) input tTFSWHS SC2 (wl) input tFTXES tTXES STD SC0 input tRFSBHS SC1 (bl) input tRFSWHS SC1 (wl) input tSS SRD tHS tTSS tTHS tRFSWLS tTXVS First Bit tFTXVS tTXNVS tTXHIS Last Bit tTFSWLS tTFSBLS tSCKL tRFBLS Figure 4-25 Slave Mode Clock Timing 56855 Technical Data, Rev. 6 Freescale Semiconductor 39 4.11 Serial Communication Interface (SCI) Timing Table 4-12 SCI Timing4 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Baud Rate1 RXD2 Pulse Width TXD3 Pulse Width Symbol BR RXDPW TXDPW Min — 0.965/BR 0.965/BR Max (fMAX)/(32) 1.04/BR 1.04/BR Unit Mbps ns ns 1. fMAX is the frequency of operation of the system clock in MHz. 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. RXD SCI receive data pin (Input) RXDPW Figure 4-26 RXD Pulse Width TXD SCI receive data pin (Input) TXDPW Figure 4-27 TXD Pulse Width 56855 Technical Data, Rev. 6 40 Freescale Semiconductor JTAG Timing 4.12 JTAG Timing Table 4-13 JTAG Timing1, 3 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic TCK frequency of operation2 TCK cycle time TCK clock pulse width TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time Symbol fOP tCY tPW tDS tDH tDV tTS tTRST tDE Min DC 33.3 16.6 3 3 — — 35 4T Max 30 — — — — 12 10 — — Unit MHz ns ns ns ns ns ns ns ns 1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz operation, T = 8.33ns. 2. TCK frequency of operation must be less than 1/4 the processor rate. 3. Parameters listed are guaranteed by design. tCY tPW VIH tPW VM TCK (Input) VM = VIL + (VIH – VIL)/2 VM VIL Figure 4-28 Test Clock Input Timing Diagram 56855 Technical Data, Rev. 6 Freescale Semiconductor 41 TCK (Input) TDI TMS (Input) TDO (Output) tTS tDS tDH Input Data Valid tDV Output Data Valid TDO (Output) Figure 4-29 Test Access Port Timing Diagram TRST (Input) tTRST Figure 4-30 TRST Timing Diagram DE tDE Figure 4-31 Enhanced OnCE—Debug Event 56855 Technical Data, Rev. 6 42 Freescale Semiconductor GPIO Timing 4.13 GPIO Timing Table 4-14 GPIO Timing1, 2 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic GPIO input period GPIO input high/low period GPIO output period GPIO output high/low period 1. Symbol PIN PINHL POUT POUTHL Min 2T + 3 1T + 3 2T - 3 1T - 3 Max — — — — Unit ns ns ns ns In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns Parameters listed are guaranteed by design. 2. GPIO Inputs PIN PINHL PINHL GPIO Outputs POUT POUTHL POUTHL Figure 4-32 GPIO Timing 56855 Technical Data, Rev. 6 Freescale Semiconductor 43 Part 5 Packaging 5.1 Package and Pin-Out Information 56855 This section contains package and pin-out information for the 100-pin LQFP configuration of the 56855. D15 D14 D13 VSSIO VDDIO D12 D11 SC02 SC01 SC00 SCK0 SRD0 STD0 VSSIO VDDIO VSS VDD D10 D9 D8 D7 D6 VSSIO TIO0 VDDIO VDDIO VSSIO RD WR A0 A1 A2 A3 VDD VSS MODA MODB MODC VDDIO VSSIO IRQA IRQB VDDA VSSA XTAL EXTAL A4 A5 A6 A7 PIN 76 PIN 1 ORIENTATION MARK PIN 26 PIN 51 TXD1 RXD1 VSSIO VDDIO D5 D4 D3 D2 D1 VSS VDD CS3 CS2 CS1 CS0 VSSIO D0 VDDIO A20 A19 A18 A17 A16 TXDO RXD0 Figure 5-1 Top View, 56855 100-pin LQFP Package 44 CLKO RSTO RESET VDDIO VSSIO A8 A9 A10 A11 VDD VSS DE TRST TDO TDI TMS TCK VDDIO VSSIO A12 A13 A14 A15 VDDIO VSSIO 56855 Technical Data, Rev. 6 Freescale Semiconductor Package and Pin-Out Information 56855 Table 5-1 56855 Pin Identification By Pin Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal Name VDDIO VSSIO RD WR A0 A1 A2 A3 VDD VSS MODA MODB MODC VDDIO VSSIO IRQA IRQB VDDA VSSA XTAL EXTAL A4 A5 A6 A7 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name CLKO RSTO RESET VDDIO VSSIO A8 A9 A10 A11 VDD VSS DE TRST TDO TDI TMS TCK VDDIO VSSIO A12 A13 A14 A15 VDDIO VSSIO Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name RXD0 TXD0 A16 A17 A18 A19 A20 VDDIO D0 VSSIO CS0 CS1 CS2 CS3 VDD VSS D1 D2 D3 D4 D5 VDDIO VSSIO RXD1 TXD1 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name VDDIO TIO0 VSSIO D6 D7 D8 D9 D10 VDD VSS VDDIO VSSIO STD0 SRD0 SCK0 SC00 SC01 SC02 D11 D12 VDDIO VSSIO D13 D14 D15 56855 Technical Data, Rev. 6 Freescale Semiconductor 45 S 0.15 (0.006)S -TNOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.070 (0.003). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 13.950 14.050 0.549 0.553 B 13.950 14.050 0.549 0.553 C 1.400 1.600 0.055 0.063 D 0.170 0.270 0.007 0.011 E 1.350 1.450 0.053 0.057 F 0.170 0.230 0.007 0.009 G 0.500 BSC 0.020 BSC H 0.050 0.150 0.002 0.006 J 0.090 0.200 0.004 0.008 K 0.500 0.700 0.020 0.028 M 12° REF 12° REF N 0.090 0.160 0.004 0.006 Q 1° 5° 1° 5° R 0.150 0.250 0.006 0.010 S 15.950 16.050 0.628 0.632 V 15.950 16.050 0.628 0.632 W 0.200 REF 0.008 REF X 1.000 REF 0.039 REF AC T-U S Z S S T-U S AC Z -ZB -UA 0.15 (0.006)S AB T-U S V (0.006)S 9 Z S AE AD -AB-AC96X G 0.100 (0.004) AC (24X PER SIDE) SEATING PLANE AE M° R 0.25 (0.010) GAUGE PLANE D F N J C E H W K X DETAIL AD Q° 0.20 (0.008)M AC T-U SECTION AE-AE S 0.15 (0.006)S 0.15 AC Z S T-U S Z S Figure 5-2 100-pin LQPF Mechanical Information Please see www.freescale.com for the most current case outline. 56855 Technical Data, Rev. 6 46 Freescale Semiconductor Thermal Design Considerations Part 6 Design Considerations 6.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: TJ = TA + (PD x RθJA) Where: TA = ambient temperature °C RθJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: RθJA = RθJC + RθCA Where: RθJA = package junction-to-ambient thermal resistance °C/W RθJC = package junction-to-case thermal resistance °C/W RθCA = package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: • • • Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case determined by a thermocouple. 56855 Technical Data, Rev. 6 Freescale Semiconductor 47 As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 6.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation: • • Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the board ground to each VSS (GND) pin. The minimum bypass requirement is to place six 0.01–0.1 μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND. Bypass the VDD and GND layers of the PCB with approximately 100 μF, preferably with a high-grade capacitor such as a tantalum capacitor. Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal. • • • • 56855 Technical Data, Rev. 6 48 Freescale Semiconductor Electrical Design Considerations • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels. Take special care to minimize noise levels on the VDDA and VSSA pins. When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device. Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together. The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but requires that TRST be asserted at power on. • • • • • 56855 Technical Data, Rev. 6 Freescale Semiconductor 49 Part 7 Ordering Information Table 7-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 7-1 56855 Ordering Information Part DSP56855 DSP56855 Supply Voltage 1.8V, 3.3V 1.8V, 3.3V Package Type Low-Profile Quad Flat Pack (LQFP) Low-Profile Quad Flat Pack (LQFP) Pin Count 100 100 Frequency (MHz) 120 120 Order Number DSP56855BU120 DSP56855BUE * *This package is RoHS compliant. 56855 Technical Data, Rev. 6 50 Freescale Semiconductor Electrical Design Considerations 56855 Technical Data, Rev. 6 Freescale Semiconductor 51 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 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Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56855 Rev. 6 01/2007