56F800

56F827 Evaluation Module User Manual 56F800 16-bit Digital Signal Controllers DSP56F827EVMUM Rev. 2 07/2005 freescale.com TABLE OF CONTENTS Preface vii Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii Notation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x Chapter 1 Introduction 1.1 1.2 1.3 56F827EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 56F827EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 56F827EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Chapter 2 Technical Summary 2.1 56F827. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 SPI EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.6 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.7 Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.8 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.8.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.8.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.9 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.10 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.12 Stereo Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.12.1 Analog Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.12.2 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.13 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.13.1 Memory Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.13.2 Peripheral Daughter Card Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Table of Contents, Rev. 2 Freescale Semiconductor i 2.14 2.15 SCI Port #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Appendix A 56F827EVM Schematics Appendix B 56F827EVM Bill of Material 56F827EVM User Manual, Rev. 2 ii Freescale Semiconductor LIST OF FIGURES 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 Block Diagram of the 56F827EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 56F827EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Connecting the 56F827EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Schematic Diagram of the External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . 2-3 SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Codec Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 CS4218 Stereo Audio Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 List of Figures, Rev. 2 Freescale Semiconductor iii 56F827EVM User Manual, Rev. 2 iv Freescale Semiconductor LIST OF TABLES 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 56F827EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 SPI Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . . 2-9 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Codec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-19 SCI Port #2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 List of Tables, Rev. 2 Freescale Semiconductor v 56F827EVM User Manual, Rev. 2 vi Freescale Semiconductor Preface This reference manual describes in detail the hardware on the 56F827 Evaluation Module. Audience This document is intended for application developers who are creating software for devices using the 56F827 part. Organization This manual is organized into two chapters and two appendixes. • • • • Chapter 1, Introduction - provides an overview of the EVM and its features. Chapter 2, Technical Summary - describes in detail the 56F827 hardware. Appendix A, "56F827EVM Schematics" contains the schematics of the DSP56F827EVM. Appendix B, 56F827EVM Bill of Material - provides a list of the materials used on the DSP56F827EVM board. Suggested Reading More documentation on the 56F827 and the DSP56F827EVM kit may be found at URL: www.freescale.com Preface, Rev. 2 Freescale Semiconductor vii Notation Conventions This manual uses the following notational conventions: Term or Value Active High Signals (Logic One) Active Low Signals (Logic Zero) Symbol No special symbol attached to the signal name Noted with an overbar in text and in most figures Begin with a “$” symbol No special symbol attached to the number Begin with the letter “b” attached to the number Considered positive unless specifically noted as a negative value Linkable on-line Reference sources, paths, emphasis Examples A0 CLKO WE OE In schematic drawings, Active Low Signals may be noted by a backslash: /WE Exceptions Hexadecimal Values Decimal Values $0FF0 $80 10 34 b1010 b0011 5 -10 Voltage is often shown as positive: +3.3V Binary Values Numbers Blue Text Bold ...refer to Figure 1-1 ...see: http://www.freescale.com/... DSP56F827EVM User Manual, Rev. 2 viii Freescale Semiconductor Definitions, Acronyms, and Abbreviations Definitions, acronyms and abbreviations for terms used in this document are defined below for reference. Codec EEPROM EVM GPIO COder/DECoder; a part used to convert analog signals to digital (Coder) and digital signals to analog (Decoder) Electrically Erasable Programmable Read Only Memory Evaluation Module; a hardware platform which allows a customer to evaluate the silicon and develop their application General Purpose Input and Output Port; does not share pin functionality with any other peripheral on the chip and can only be set as an input, output or level-sensitive interrupt input Integrated Circuit Joint Test Action Group; a bus protocol/interface used for test and debug Low-profile Quad Flat Pack Multi-Purpose Input/Output Port; shares package pins with other peripherals on the chip and can function as a GPIO On-Chip Emulation, a debug bus and port created by Freescale to enable designers to create a low-cost hardware interface for a professional quality debug environment Printed Circuit Board Phase Locked Loop Random Access Memory Read-Only Memory Serial Communications Interface Port Serial Peripheral Interface Port Static Random Access Memory Synchronous Serial Interface Port Wait State IC JTAG LQFP MPIO OnCETM PCB PLL RAM ROM SCI SPI SRAM SSI WS Preface, Rev. 2 Freescale Semiconductor ix References The following sources were referenced to produce this manual: [1] DSP56800 Family Manual, DSP56800FM, Freescale Semiconductor [2] DSP56F826/827 Digital Signal Processor User’s Manual, DSP56F826_827UM, Freescale Semiconductor [3] DSP56F827 Technical Data, DSP56F827, Freescale Semiconductor DSP56F827EVM User Manual, Rev. 2 x Freescale Semiconductor Chapter 1 Introduction The 56F827EVM is used to demonstrate the abilities of the 56F827 and to provide a hardware tool allowing the development of applications that use the 56F827. The 56F827EVM is an evaluation module board that includes a 56F827 part, 16-bit stereo codec, external memory and a daughter card expansion interface. The daughter card expansion connectors are for signal monitoring and user feature expandability. The 56F827EVM is designed for the following purposes: • Allowing new users to become familiar with the features of the 56800 architecture. The tools and examples provided with the 56F827EVM facilitate evaluation of the feature set and the benefits of the family. Serving as a platform for real-time software development. The tool suite enables the user to develop and simulate routines, download the software to on-chip or on-board RAM, run it, and debug it using a debugger via the JTAG/OnCETM port. The breakpoint features of the OnCE port enable the user to easily specify complex break conditions and to execute user-developed software at full-speed, until the break conditions are satisfied. The ability to examine and modify all user accessible registers, memory and peripherals through the OnCE port greatly facilitates the task of the developer. Serving as a platform for hardware development. The hardware platform enables the user to connect external hardware peripherals. The on-board peripherals can be disabled, providing the user with the ability to reassign any and all of the controller's peripherals. The OnCE port's unobtrusive design means that all of the memory on the board and on the controller chip are available to the user. • • 1.1 56F827EVM Architecture The 56F827EVM facilitates the evaluation of various features present in the 56F827 part. The 56F827EVM can be used to develop real-time software and hardware products based Introduction, Rev. 2 Freescale Semiconductor 1-1 on the 56F827. The 56F827EVM provides the features necessary for a user to write and debug software, demonstrate the functionality of that software and interface with the customer's application-specific device(s). The 56F827EVM is flexible enough to allow a user to fully exploit the 56F827's features to optimize the performance of his product, as shown in Figure 1-1. 56F827 RESET LOGIC RESET SPI IRQ MODE LOGIC MODE SCI SPI EEPROM 1M-bit IRQ Interface RS-232 Interface DSub 9-Pin Program Memory 64Kx16-bit SRAM Address, Data & Control Data Memory 64Kx16-bit SRAM A/D Peripheral Daughter Card Connector Memory Daughter Card Connector JTAG Connector Parallel JTAG Interface JTAG/OnCE Stereo 16-bit Codec Amp GPIO +2.5V, +3.3V & GND Debug LEDs Stereo Line In Stereo Line Out Headphone Jack SSI DSub 25-Pin 4.00MHz Crystal XTAL/EXTAL Power Supply +2.5V, +3.3V & +5.0V Figure 1-1. Block Diagram of the 56F827EVM 1.2 56F827EVM Configuration Jumpers Seven jumper groups, (JG1-JG7), shown in Figure 1-2, are used to configure various features on the 56F827EVM board. Table 1-1 describes the default jumper group settings. 56F827EVM User Manual, Rev. 2 1-2 Freescale Semiconductor 56F827EVM Connections JG2 2 JG7 1 7 P3 JG1 JG3 8 TB1 JG2 S1 JG5 P2 JG1 P1 JG5 3 1 JG4 1 3 RESET JG7 J2 JG4 Y1 JG3 J3 JTAG Figure 1-2. 56F827EVM Jumper Reference Table 1-1. 56F827EVM Default Jumper Options Jumper Group JG1 JG2 JG3 JG4 JG5 JG6 JG7 Comment Enable on-board Parallel JTAG Host/Target Interface Enable RS-232 output Enable on-board SRAM Use on-board EXTAL crystal input for controller oscillator Use on-board XTAL crystal input for controller oscillator Selects controller’s Mode 0 operation upon exit from reset Enable SPI EEPROM Jumpers Connections NC NC 1–2 2–3 1–2 1-2 1–2, 3–4, 5–6 & 7–8 1.3 56F827EVM Connections An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external +12.0V DC power supply or external +5.0V DC lab power supply to the 56F827EVM board. S/N U1 U2 S2 JG6 HEADPHONE DSP56F827EVM J1 LEDS IRQA S3 P6 IRQB S4 LINE IN P4 P5 LINE OUT JG6 U5 U7 Introduction, Rev. 2 Freescale Semiconductor 1-3 Parallel Extension Cable 56F827EVM PC-compatible Computer P2 Connect cable to Parallel/Printer port External with 2.1mm, +12.0V receptacle Power connector P1 TB1 +5.0V Lab Supply or Figure 1-3. Connecting the 56F827EVM Cables Perform the following steps to connect the 56F827EVM cables: 1. Connect the parallel extension cable to the parallel port of the host computer. 2. Connect the other end of the parallel extension cable to P2, shown in Figure 1-3, on the 56F827EVM board. This provides the connection which allows the host computer to control the board. 3. Make sure that the external +12.0V DC 1.2A switching power supply or the external +5.0V DC 1.0A lab power supply is not plugged into a 120V AC power source. 4. Connect the 2.1mm output power plug from the external switching power supply into P1, shown in Figure 1-3, on the 56F827EVM board. Optionally, attach an external +5.0V DC lab power supply via the 2-pin terminal block, TB1. 5. Apply power to the external power supply. The green Power-On LED, LED7, will illuminate when power is correctly applied. 56F827EVM User Manual, Rev. 2 1-4 Freescale Semiconductor Chapter 2 Technical Summary The 56F827EVM is designed as a versatile controller development card for developing real-time software and hardware products to support a new generation of applications in digital and wireless messaging, digital answering machines, feature phones, modems, and digital cameras. The power of the 16-bit 56F827 controller, combined with the on-board 64K 16-bit external program static RAM (SRAM), 64K 16-bit external data SRAM, RS-232 interface, stereo 16-bit codec interface, Daughter Card Expansion interface and parallel JTAG interface, makes the 56F827EVM ideal for developing and implementing many audio and voice algorithms, as well as for learning the architecture and instruction set of the 56F827 processor. The main features of the 56F827EVM, with board and schematic reference designators include: • • 56F827 16-bit +2.5V/+3.3V controller operating at 80MHz [U1] External fast static RAM (FSRAM) memory [U2], configured as: — 64K 16 bits of program memory with 0 wait states at 70MHz — 64K 16 bits of data memory with 0 wait states at 70MHz • • • • • • • • 1M-bit Serial EEPROM [U4] 4.00MHz crystal oscillator for controller frequency generation [Y1] Optional external oscillator frequency input connector [JG4 and JG5] Joint Test Action Group (JTAG) port interface connector for an external debug Host Target Interface [J3] On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port cable [P2] RS-232 interface for easy connection to a host processor [U3 and P3] 16-bit stereo codec interface [U5, P4 and P5] Stereo headphone interface [U6 and P6] Technical Summary, Rev. 2 Freescale Semiconductor 2-1 • • • • • • • • • • Codec sample rate selector [S4] Peripheral Daughter Card Expansion Connector, to allow the user to connect his own SCI, SSI, SPI or GPIO-compatible peripheral to the controller[J2] Memory Daughter Card Expansion Connector, to allow the user to connect his own memory or memory device to the controller[J1] On-board power regulation from an external +12V DC-supplied power input [P1] On-board power regulation from an optional +5V DC-supplied power input [TB1] Light Emitting Diode (LED) power indicator [LED7] Six on-board real-time user debugging LEDs [LED1-6] Manual RESET push-button [S1] Manual interrupt push-button for IRQA [S2] Manual interrupt push-button for IRQB [S3] 2.1 56F827 The 56F827EVM uses a Freescale DSP56F827FG80 part, designated as U1 on the board and in the schematics. This part will operate at a maximum speed of 80MHz. A full description of the 56F827, including functionality and user information, is provided in these documents: • DSP56F827 Technical Data, (DSP56F827): Provides features list and specifications including signal descriptions, DC power requirements, AC timing requirements and available packaging. DSP56F826/827 16-Bit Digital Signal Processor User’s Manual, (DSP56F826_827UM): Provides an overview description of the controller and detailed information about the on-chip components including the memory and I/O maps, peripheral functionality, and control/status register descriptions for each subsystem. DSP56800 Family Manual, (DSP56800FM): Provides a detailed description of the core processor, including internal status and control registers and a detailed description of the family instruction set. • • Refer to these documents for detailed information about chip functionality and operation. They can be found on this URL: www.freescale.com 56F827EVM User Manual, Rev. 2 2-2 Freescale Semiconductor Program and Data Memory 2.2 Program and Data Memory The 56F827EVM uses one bank of 128K 16-bit Fast Static RAM (GSI GS72116, labelled U2) for external memory expansion; see the FSRAM schematic diagram in Figure 2-1. This physical memory bank is split into two logical memory banks of 64Kx16-bits: one for program memory and the other for data memory. By using the controller’s program strobe, PS, signal line along with the memory chip’s A0 signal line, half of the memory chip is selected when program memory accesses are requested and the other half of the memory chip is selected when data memory access are requested. This memory bank will operate with zero wait-state accesses while the 56F827 is running at 70MHz. However, when running at 80MHz, the memory bank operates with four wait-state accesses. This memory bank can be disabled by removing the jumper at JG3. 56F827 A0-A15 PS D0-D15 RD WR +3.3V GS72116 A1-A16 A0 DQ0-DQ15 OE WE JG3 1 2 Jumper Pin 1-2: Enable SRAM Jumper Removed: Disable SRAM CE Figure 2-1. Schematic Diagram of the External Memory Interface Technical Summary, Rev. 2 Freescale Semiconductor 2-3 2.3 SPI EEPROM Memory A 1M-bit +3.3V SPI serial EEPROM Memory, Atmel AT45DB011-SC, is provided on the 56F827EVM, reference Figure 2-2. This memory connects directly to the SPI Port through a header on the 56F827. It can be used to load program code and data into the 56F827’s internal or external memory spaces. A jumper block is provided, JG7, to allow the user to disconnect the on-board SPI EEPROM from the SPI port and allow him to connect his own SPI port peripheral. The header details are shown in Table 2-1. EEPROM Enable 56F827 MOSI MISO (SPI Port Connector) Serial EEPROM SDI SDO SCLK GPIOF7 SCK CS Figure 2-2. SPI EEPROM Memory Block Diagram Table 2-1. SPI Port Connector Description JG7 Pin # 1 3 5 7 Signal SS/GPIO7 MISO MOSI SCLK Pin # 2 4 6 8 Signal CS SDO SDI SCK 56F827EVM User Manual, Rev. 2 2-4 Freescale Semiconductor RS-232 Serial Communications 2.4 RS-232 Serial Communications The 56F827EVM provides an RS-232 interface by the use of an RS-232 level converter, (Maxim MAX3245EEAI, designated as U3). Refer to the RS-232 schematic diagram in Figure 2-3. The RS-232 level converter transitions the SCI UART’s +3.3V signal levels to RS-232 compatible signal levels and connects to the host’s serial port via connector P3. Flow control is not provided, but could be implemented using uncommitted GPIO signals. The pinout of connector P3 is listed in Table 2-2. The RS-232 level converter/transceiver can be disabled by placing a jumper at JG2. 56F827 RS-232 Level Converter Interface 1 6 2 7 3 8 4 9 5 P3 TXDO RXDO +3.3V T1in R1out T1out R1in x FORCEOFF Jumper Removed: Enable RS-232 Jumper Pin 1-2: Disable RS-232 JG2 1 2 Figure 2-3. Schematic Diagram of the RS-232 Interface Table 2-2. RS-232 Serial Connector Description P3 Pin # 1 2 3 4 5 Signal Jumper to 6 & 4 TXD RXD Jumper to 1 & 6 GND Pin # 6 7 8 9 Signal Jumper to 1 & 4 Jumper to 8 Jumper to 7 N/C Technical Summary, Rev. 2 Freescale Semiconductor 2-5 2.5 Clock Source The 56F827EVM uses a 4.00MHz crystal, Y1, connected to its External Crystal Inputs, EXTAL and XTAL. The 56F827 uses its internal PLL to multiply the input frequency by 20, achieving its 80MHz maximum operating frequency. An external oscillator source can be connected to the controller by using the oscillator bypass connectors, JG4 and JG5; see Figure 2-4. If the input frequency is above 4MHz, then the EXTAL input should be jumpered to ground by adding a jumper between JG4 pins 2 and 3. The input frequency would then be injected on JG5’s pin 2. If the controller needs to be synchronized to the codec’s sample frequency, then the controller’s input frequency should be jumpered using the 12.2280MHz codec frequency. If the input frequency is below 4MHz, then the input frequency can be injected on JG4’s pin 2. EXTERNAL OSCILLATOR HEADERS JG4 3 2 1 4.00MHz 10M JG5 1 2 12.2880MHz 3 56F827 EXTAL XTAL Figure 2-4. Schematic Diagram of the Clock Interface 56F827EVM User Manual, Rev. 2 2-6 Freescale Semiconductor Operating Mode 2.6 Operating Mode The 56F827EVM provides a boot-up MODE selection jumper, JG6. This jumper is used to select the operating mode of the controller as it exits RESET. Refer to the DSP56F827 User’s Manual for a complete description of the chip’s operating modes. Table 2-3 shows the two operation modes available on the 56F827. Table 2-3. Operating Mode Selection Operating Mode 0 3 JG6 1–2 No Jumper Comment Bootstrap from internal memory Bootstrap from external memory Technical Summary, Rev. 2 Freescale Semiconductor 2-7 2.7 Debug LEDs Six on-board Light-Emitting Diodes, (LEDs), are provided to allow real-time debugging for user programs. These LEDs will allow the programmer to monitor program execution without having to stop the program during debugging; refer to Figure 2-5. User LED1 is controlled by Port B’s PB0 signal. User LED2 is controlled by PB1. User LED3 is controlled by PB2. User LED4 is controlled by PB3. User LED5 is controlled by PB4. User LED6 is controlled by PB5. Setting PB0, PB1, PB2, PB3, PB4 or PB5 to a Logic One value will turn on the associated LED. 56F827 PB0 INVERTING BUFFER RED LED +3.3V YELLOW LED PB1 GREEN LED PB2 RED LED PB3 YELLOW LED PB4 GREEN LED PB5 Figure 2-5. Schematic Diagram of the Debug LED Interface 2.8 Debug Support The 56F827EVM provides an on-board Parallel JTAG Host Target Interface and a JTAG interface connector for external Target Interface support. Two interface connectors are provided to support each of these debugging approaches. These two connectors are designated the JTAG connector and the Host Parallel Interface Connector. 56F827EVM User Manual, Rev. 2 2-8 Freescale Semiconductor Debug Support 2.8.1 JTAG Connector The JTAG connector on the 56F827EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56F827’s registers. This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program. Table 2-4 shows the pin-out for this connector. Table 2-4. JTAG Connector Description J3 Pin # 1 3 5 7 9 11 13 Signal TDI TDO TCK NC RESET +3.3V NC Pin # 2 4 6 8 10 12 14 Signal GND GND GND KEY TMS NC TRST When this connector is used with an external Host Target Interface, the parallel JTAG interface should be disabled by placing a jumper in jumper block JG1. See Table 2-5 for this jumper’s selection options. Table 2-5. Parallel JTAG Interface Disable Jumper Selection JG1 No jumpers 1–2 Comment On-board Parallel JTAG Interface Enabled Disable on-board Parallel JTAG Interface Technical Summary, Rev. 2 Freescale Semiconductor 2-9 2.8.2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector, P2, allows the 56F827 to communicate with a Parallel Printer Port on a Windows PC; reference Figure 2-6. By using this connector, the user can download programs and work with the 56F827’s registers. Table 2-6 shows the pin-out for this connector. When using the parallel JTAG interface, the jumper at JG1 should be removed, as shown in Table 2-5. DB-25 Connector TDI TDO P_TRST TMS TCK P_RESET +3.3V Parallel JTAG Interface IN OUT OUT IN IN IN IN IN JG1 56F827 TDI TDO TRST TMS TCK RESET OUT OUT OUT OUT EN Jumper Removed: Enable JTAG I/F Jumper Pin 1-2: Disable JTAG I/F 1 2 Figure 2-6. Block Diagram of the Parallel JTAG Interface 56F827EVM User Manual, Rev. 2 2-10 Freescale Semiconductor Debug Support Table 2-6. Parallel JTAG Interface Connector Description P2 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 Signal NC PORT_RESET PORT_TMS PORT_TCK PORT_TDI PORT_TRST NC PORT_IDENT PORT_VCC NC PORT_TDO NC PORT_CONNECT Pin # 14 15 16 17 18 19 20 21 22 23 24 25 Signal NC PORT_IDENT NC NC GND GND GND GND GND GND GND GND Technical Summary, Rev. 2 Freescale Semiconductor 2-11 2.9 External Interrupts Two on-board push-button switches are provided for external interrupt generation, as shown in Figure 2-7. S2 allows the user to generate a hardware interrupt for signal line IRQA. S3 allows the user to generate a hardware interrupt for signal line IRQB. These two switches allow the user to generate interrupts for his user-specific programs. +3.3V 56F827 SW2 0.1µF +3.3V 10K IRQA SW3 0.1µF 10K IRQB Figure 2-7. Schematic Diagram of the User Interrupt Interface 56F827EVM User Manual, Rev. 2 2-12 Freescale Semiconductor Reset 2.10 Reset Logic is provided on the 56F827 to generate an internal Power-On RESET. Additional reset logic is provided to support the RESET signals from the JTAG connector, the Parallel JTAG Interface and the user RESET push-button; refer to Figure 2-8. JTAG_RESET RESET RESET PUSHBUTTON MANUAL RESET TRST JTAG_TAP_RESET Figure 2-8. Schematic Diagram of the RESET Interface Technical Summary, Rev. 2 Freescale Semiconductor 2-13 2.11 Power Supply The main power input, +12.0V DC, to the 56F827EVM is through a 2.1mm coax power jack, P1. An optional +5.0V DC power supply input is available through a 2-pin terminal block, TB1. A 1.2A power supply is provided with the 56F827EVM; however, less than 500mA is required by the EVM. The remaining current is available for user daughter card applications when connected to the daughter card interface. The power regulation on the 56F827EVM provides +5.0V DC voltage regulation for the codec’s analog circuits and to the additional voltage regulation logic on the EVM. The additional voltage regulation logic provides +2.5V DC voltage regulation for the controller’s core and +3.3V DC voltage regulation for the controller’s I/O, memory, parallel JTAG interface and supporting logic; refer to Figure 2-9. Power applied to the 56F827EVM is indicated with a Power-On LED, referenced as LED7. P1 +12.0V DC +5.0V Regulator TB1 +5.0V DC GND Power Condition +5.0V DC Analog Codec +3.3V Regulator +3.3V DC 56F827 56F827EVM Parts +2.5V Regulator +2.5V DC 56F827 Core Figure 2-9. Schematic Diagram of the Power Supply 2.12 Stereo Codec A 16-bit audio quality stereo codec, Crystal Semiconductor CS4218, is connected to the 56F827’s SSI port to support audio, voice and signal analysis applications. The codec is clocked with a 12.288MHz oscillator. This allows the codec to operate between a sample frequency of 8kHz and 48kHz. The sample rate can be manually set by setting the appropriate switch positions on dip switch S4. The sample rate selections possible using this three-position dip switch are detailed in Table 2-7. The codec supports +3.3V digital levels, eliminating the need for voltage-level translation circuitry. Additionally, a set of zero ohm resistors are provided on the EVM to allow a user to disconnect the on-board codec from the SSI port and to connect his own codec to the SSI port; refer to Figure 2-11. The on-board codec has analog signal conditioning 56F827EVM User Manual, Rev. 2 2-14 Freescale Semiconductor Stereo Codec logic, allowing direct connection to its line-level input and line-level output signals through two 1/8” stereo jacks; see Figure 2-10. Table 2-7. Codec Sample Rate Selector SW 4 Position 3 (MF6) ON ON ON ON OFF OFF OFF OFF SW 4 Position 2 (MF7) ON ON OFF OFF ON ON OFF OFF SW 4 Position 1 (MF8) ON OFF ON OFF ON OFF ON OFF Sample Rate 48.00kHz 32.00kHz 24.00kHz 19.20kHz 16.00kHz 12.00KHz 9.60kHz 8.00kHz CS4218 P4 RIN1 Line-level Input LIN1 A P5 LOUTL LOUTR A Line-level Output LM4880 P6 Headphone Output A Figure 2-10. Codec Analog Connections Technical Summary, Rev. 2 Freescale Semiconductor 2-15 56F827 Codec Enable Logic STD SRD STCK STFS PD0 CS4218 SDIN SDOUT SCLK FSYNC RESET PD1 PD2 PD3 CCS CDIN CCLK Figure 2-11. CS4218 Stereo Audio Codec 2.12.1 Analog Input/Output The 56F827EVM uses jacks for line-level stereo input, line-level stereo output and stereo headphone output. A National Semiconductor LM4880 is used to provide the drive required for the use of headphones. This device offers a THD, which is superior to the CS4218’s on-chip headphone drive circuitry by a factor of two. The basic Analog codec connections are shown in Figure 2-10. 2.12.2 Digital Interface The serial interface of the codec transfers digital audio data and control data into and out of the device. The SSI port, which consists of independent transmitter and receiver sections, is used for serial communication with the codec. On the controller side, the Serial Transmit Data pin, STD, is an output when data is being transmitted to the codec. The Serial Receive Data pin, SRD, is an input when data is being received from the codec. These two pins are connected to the codec’s Serial Data Input pin, SDIN, and Serial Data Output pin, SDOUT. The controller’s Transmit Serial Clock pin, STCK, provides the serial bit rate clock for the SSI interface. It is connected to the codec’s Serial Port Clock pin, SCLK. Data is transmitted on the rising edge of SCLK and is received on the falling edge of SCLK. 56F827EVM User Manual, Rev. 2 2-16 Freescale Semiconductor Daughter Card Connectors The device’s GPIO PORT D Bit 0 pin, PD0, is programmed to control the codec’s Active Low Reset signal, RESET. The Serial Transmit Frame Sync pin, STFS, is programmed to control the codec’s Frame Sync signal, FSYNC. FSYNC is sampled by SCLK, with a rising edge indicating a new frame is about to start. The FSYNC frequency is always the system’s sample rate. It may be an input to the codec, or it may be an output from the codec in data mode. The basic codec digital connections are shown in Figure 2-11. The codec’s MODE is set by the three MODE selection resistors, R96-R98. In the factory default setting of MODE 4, the codec is set to be the Master of the SPI bus with its data word set at 32 bits per frame; i.e., a 16-bit Left channel and a 16-bit Right channel. The sample rate is selected on Sample Rate Selector switch S4; reference Table 2-7 for selection options. Codec control information is sent over a separate serial port using: PD1 as the Control Chip Select signal, CCS; PD2 as the Control Data Input signal, CDIN; and PD3 as the Control Clock signal, CCLK. 2.13 Daughter Card Connectors The EVM board contains two daughter card expansion connectors. One connector, J1, contains the controller’s external memory bus signals. The other connector, J2, contains the device’s peripheral port signals. 2.13.1 Memory Daughter Card Expansion Connector The controller’s external memory bus signals are connected to the Memory Daughter Card Expansion connector, J1. Table 2-8 shows the port signal to pin assignments. Table 2-8. Memory Daughter Card Connector Description J1 Pin # 1 3 5 7 9 Signal A10 A9 A8 A7 GND Pin # 2 4 6 8 10 Signal A11 DS A15 A14 PCS7 Technical Summary, Rev. 2 Freescale Semiconductor 2-17 Table 2-8. Memory Daughter Card Connector Description J1 Pin # 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 Signal WR D0 D1 D2 GND D3 D4 D5 D6 PCS6 D7 PS A0 A1 PCS4 A2 A3 PCS3 +3.3V GND GND Pin # 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Signal A13 A12 D8 D9 GND D10 D11 D12 D13 PCS5 D14 D15 RD A6 GND A5 A4 PCS2 +3.3V GND 2.13.2 Peripheral Daughter Card Expansion Connector The controller’s peripheral port signals are connected to the Peripheral Daughter Card Expansion connector, J2. Table 2-9 shows the port signal to pin assignments. 56F827EVM User Manual, Rev. 2 2-18 Freescale Semiconductor Daughter Card Connectors Table 2-9. Peripheral Daughter Card Connector Description J2 Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 Signal PB0 CLKO TA0 PB3 TA2 PB5 ANA0 SRD SRFS SCLK ANA2 MOSI MISO ANA4 SS SRCK STFS RESET ANA6 STD STCK IRQB IRQA +3.3V Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 Signal PB1 PB2 TA1 PB4 TA3 PB6 ANA1 PB7 PD0 PD1 ANA3 PD2 PD3 ANA5 PD4 PD5 PD6 PD7 ANA7 RXD1 TXD1 RXD0 TXD0 +3.3V Technical Summary, Rev. 2 Freescale Semiconductor 2-19 Table 2-9. Peripheral Daughter Card Connector Description (Continued) J2 Pin # 49 51 Signal ANA8 GND Pin # 50 Signal ANA9 2.14 SCI Port #2 A separate connector, J4, is provided to allow the easy connection of SCI Port #2 signals along with a reference GND signal. Table 2-10. SCI Port #2 Connector J4 1 2 3 Signal Description TXD2 RXD2 GND 2.15 Test Points The 56F827EVM board has a total of seven test points. Three digital GND test points are located in corners of the board. The +5.0VA and AGND test points are located in the bottom right, analog corner, of the board. The +2.5V and +3.3V test points are located in the upper right, power supply section, of the board. 56F827EVM User Manual, Rev. 2 2-20 Freescale Semiconductor Appendix A 56F827EVM Schematics Appendix A, Rev. 2 Freescale Semiconductor A-1 A-2 B C D A E D[0..15] A[0..15] R79 +3.3V DNP U 1 1A L E D1 PB0 M C 74AC04AD U 1 1B L E D2 PB1 3 4 R6 R80 10K TCK DNP R81 U11C L E D3 PB2 5 6 R9 27 0 R4 PB0 U11D L E D4 PB3 9 8 R11 27 0 PB1 47 K U 1 1E L E D5 PB4 EXTA L XT AL M C 74AC04AD U11F L E D6 PB5 13 12 M C 74AC04AD R14 PB4 CLKO /IRQA /IRQB 11 10 R13 27 0 PB2 47 K R7 47 K R5 TDI DNP 10K 27 0 TCS 1 2 R3 /DE 27 0 R93 10K R92 10K TM S 10K U1 +3.3V 4 4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 125 126 127 128 1 2 3 6 7 8 9 10 11 12 13 14 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0/PE0 A1/PE1 A2/PE2 A3/PE3 A4/PE4 A5/PE5 A6/PE6 A7/PE7 A8/PA0 A9/PA1 A10/PA2 A11/PA3 A12/PA4 A13/PA5 A14/PA6 A15/PA7 21 22 23 24 25 26 27 28 31 32 33 34 35 36 37 38 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 0 A1 1 A1 2 A1 3 A1 4 A1 5 RED LED YELLOW LED M C 74AC04AD MIS O MOSI S C LK /SS MISO/PF6 MOSI/PF5 SCLK/PF4 SS/PF7 TXD0/SCLK0 RXD0/MOSI0 108 107 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 100 101 102 99 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 TXD0 RXD0 124 123 122 121 120 119 118 117 GREEN LED M C 74AC04AD TXD1 RXD1 TXD1/MISO0 RXD1/SS0 TXD2 RXD2 98 97 96 95 94 93 92 91 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 104 103 106 105 3 TXD2 RXD2 3 SRD STD STFS SRFS STCK SRCK 55 52 51 54 50 53 SRD/PC0 STD/PC3 STFS/PC4 SRFS/PC1 STCK/PC5 SRCK/PC2 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 RED LED M C 74AC04AD / R E S ET RESET XBOOT CLKO IRQA IRQB 40 49 57 EXTAL XTAL 59 60 39 42 WR RD PS/PCS0 DS/PCS1 16 15 18 17 /WR /RD /PS /DS XBOO T YELLOW LED R8 PB3 47 K R10 TA0 TA1 TA2 TA3 TA0/PF0 TA1/PF1 TA2/PF2 TA3/PF3 112 111 110 109 GREEN LED 27 0 47 K 2 2 P C S2 P C S3 P C S4 P C S5 P C S6 P C S7 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 ANA8 ANA9 VREFHI VREFLO VREFP VREFMID VREFN VPP + 3 .3V 65 68 66 90 1 1 1 1 T1 6 T1 7 T1 8 T1 9 67 64 +3.3VA 70 71 72 73 74 75 76 77 78 79 A N A0 A N A1 A N A2 A N A3 A N A4 A N A5 A N A6 A N A7 A N A8 A N A9 84 85 86 87 88 89 R12 PB5 47 K 56F827EVM User Manual, Rev. 2 J4 TXD2 RXD2 1 2 3 48 47 44 46 45 41 43 TDI TDO TCK TMS TRST DE TCS VDDA_PLL VDDA_ADC VSSA_PLL VSSA_ADC 62 69 61 63 + 2 .5V 114 83 58 30 5 115 80 20 GND1 GND3 GND5 GND7 GND10 GNDC1 GNDC2 GNDC3 VDD1 VDD3 VDD5 VDD7 VDD10 VDDC1 VDDC2 VDDC3 113 82 56 29 4 116 81 19 TDI TDO TCK TMS /TR ST /DE TCS + 3 .3VA DSP Standard Pro ducts Division 2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510 1 1 DSP56 F827FG80 Titl e Size B B C DSP56F827 Processor and DEBUG LE DS Docum ent Numb er DSP56F827EVM. DSN Date : Monday, April 09, 2001 D Rev. Design er: DSPD Design Sheet 1 E of 10 1.0 A Freescale Semiconductor Figure A-1. 56F827 Processor and Debug LEDS A D B C E +3.3V JG4 3 2 1 EX TAL 4 IRQA PUSHBUTTON S2 /IRQA C30 0.1uF R70 10K 4 Freescale Semiconductor OSC BYPASS JG5 1 2 12.288MHZ 3 +3.3V XTA L Y1 4.00MHz 10M R1 EXT OSC >8MHZ IRQB PUSHBUTTON S3 R71 10K 3 /IRQB S1 /POR C32 0.1uF C31 0.1uF 3 RESET PUSHBUTTON +3.3V +3.3V U12 Vcc RST GND DS1818 DNP 1 /POR R72 10K JG6 2 1 X B O OT 2 Appendix A, Rev. 2 2 2 3 BOOT MODE JUMPER EXT BOOT NC INT BOOT 1 - 2 DS P Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 3 DS1818 1 2 (480) 413-5090 FAX: (480) 413-2510 1 1 Tit le Siz e A B RESET, CLOCK, BOOT MODE & I RQS Docu ment Numbe r DSP56F8 27EVM.DSN Date: Monday, April 09, 2001 C Rev. Design er: D S P D D e s i g n D Shee t 2 of E 10 1.0 A Figure A-2. Reset, Clock, Boot Mode & IRQs A-3 A-4 B D C E A 64Kx16-bit Program and 64Kx16-bit Data Memory 4 4 /PS U2 D[0..15] A[0..15] +3.3V 3 SRAM ENABLE JUMPER OPTION JG3 1-2 NC GS72116TP-12 R68 1K R69 1K 1 2 VSS VSS 12 34 JG3 /RD /WR 41 17 6 39 40 OE WE CE LB UB VDD VDD 11 33 +3.3V R67 10K A0 A1 A2 A3 A4 A5 A6 A12 A13 A14 A15 A10 A9 A8 A7 A11 5 4 3 2 1 44 43 42 27 26 25 24 21 20 19 18 22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 D7 D6 D5 D4 D3 D2 D1 D0 D8 D9 D10 D11 D12 D13 D14 D15 3 SRAM ENABLE SRAM DISABLE 56F827EVM User Manual, Rev. 2 Tit le Siz e A B 2 2 DS P Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510 1 1 PROGRAM and DATA SRAM M E M O R Y Docu ment Numbe r DSP56F8 27EVM.DSN Date: Monday, April 09, 2001 C Rev. Design er: D S P D D e s i g n D Shee t 3 of E 10 1.0 A Freescale Semiconductor Figure A-3. Program & Data SRAM Memory A B C D E Freescale Semiconductor 4 4 +3.3V U4 JG7 /SS 1 3 5 7 8 AT45DB011-SC EE_SCK 2 SCK GND 7 6 EE_SI 1 SI WP 5 /WP 3 2 4 EE_SO 8 SO RESET 3 /RES /EE_CS 4 CS VCC 6 MISO MOSI SCLK 3 EEPROM Enable +3.3V R90 /RES R91 /WP 10K 2 Appendix A, Rev. 2 Tit le Siz e A B 10K 2 DS P Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510 1 1 SPI Serial 1M-Bit E E P R O M M E M O R Y Docu ment Numbe r DSP56F8 27EVM.DSN Date: Monday, April 09, 2001 C Rev. Design er: D S P D D e s i g n D Shee t 4 of E 10 1.0 A Figure A-4. SPI Serial 1M-bit Serial EEPROM Memory A-5 A-6 B D C E A +3.3V U3 28 C1+ VC1C2+ V+ 2 C2P3 GND 25 27 C28 1.0uF 3 C27 VCC C26 1.0uF 24 1 C29 1.0uF R88 TXD0 T2IN T3IN 1 1 T8 T9 R89 T10 1 RXD0 0 Ohm T1IN T2IN T3IN T1OUT T2OUT T3OUT 14 13 12 9 10 11 0 Ohm 26 4 4 3 1 6 2 7 3 8 4 9 5 DCD DSR TXD CTS RXD RTS DTR RI GND /EN T2IN T3IN R2IN R3IN R4IN R5IN R55 R56 R58 R59 R60 1K 1K 1K 1K 1K R61 R62 1K 1K +3.3V 3 +3.3V /EN 23 FORCEON INVALID FORCEOFF MAX3245EEAI 21 1 T15 22 R57 1K T11 T12 T13 T14 1 1 1 1 20 19 18 17 16 15 R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT R1IN R2IN R3IN R4IN R5IN R2IN R3IN R4IN R5IN 4 5 6 7 8 RS-2 32 ENABLE N/C 1 2 JG2 SCI RS-232 CONNECTOR RS-232 ENABLE RS-232 DISABLE 1-2 56F827EVM User Manual, Rev. 2 Tit le Siz e A B 2 2 DS P Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510 1 1 SCI PORT, RS-232 AND CO NNECTOR Docu ment Numbe r DSP56F8 27EVM.DSN Date: Monday, April 09, 2001 C Rev. Design er: D S P D D e s i g n D Shee t 5 of E 10 1.0 A Freescale Semiconductor Figure A-5. SCI Port, RS-232 and Connector A B C D E R30 +3.3V /PDN C10 4 7 0pF 10 K U5 P5 RING_OUT MODE2 TIP _OUT 19 RIN1 LOUT 21 LIN1 C15 0.00 22uF 1/ 8" MF6 C16 0.00 22uF R34 3 9 .2K 1% R35 39. 2K 1% C17 0.47 uF 20 RIN2 C18 0.47 uF 22 LIN2 WF6 WF7 WF8 REFBUF MODE3 MODE2 MODE1 /CCS + C7 4 7 uF 10VDC 28 25 24 MF6 MF7 MF8 C21 0.47 uF 14 U7 VCC EN OUT 1K REFBY C9 0.1u F REFGND VDD GND 2 0 .0K 1% MF1 R46 S4 MF6 MF7 MF8 6 4 2 5 3 1 C20 R39 + C8 0.33u F R82 5.6 2K 1% P4 MODE1 ROUT 10 L O UT C13 1uF 25 V 9 ROUT C11 1uF 25 V 3 11 10 2 1 10 K 10 K R84 R83 R31 5. 62K 1% RING_IN 4 3 11 10 2 1 C12 4 7 0pF C14 0.33u F TIP_IN 4 R51 LOUT 1uF 25 V 20. 0K 1% BYPASS SHUTDN C25 1uF 25 V STFS CODEC_FSYNC 2 3 5 0 0 1 0 0 1 0 1 8.00 1 9.60 1 12.00 0 1 1 1 16.00 1 1 19.20 1 0 24.00 IN_A BYPASS SHUTDN OUT_A VDD GND LM4880 M 1 8 4 + Freescale Semiconductor Line Out Stereo Jack MODE3 R85 10 K R43 10 K MF7 R44 10 K MF8 35 26 23 15 MF5 R45 10 K R36 10 K R37 10 K 3 1/ 8" R32 5. 62K 1% Line-Input Stereo Jack MF5 MF4 MF3 MF2 MF1 32 30 29 33 34 MF5 /CCS CCLK CDIN MF1 R33 5.6 2K 1% + 3 .3V 12. 288MHZ R41 5 R86 8 3 + 3 .3V GND 1 SWODE3 SWODE2 SWODE1 1K 4 1 2 . 2 8 8 M HZ OSC 16 42 +3.3V R40 43 1 2 .288MHZ / C O D E C _ R E SET /PDN CODEC_FSYNC C O D E C _ S C LK C O D E C _ S D O UT CODEC_SDIN 41 40 7 39 38 37 36 CLKIN RESET PDN SSYNC SCLK SDOUT SDIN VDDA GNDA C S 4218-KQ 18 17 +5.0VA SHUTDN R87 10 K R42 10 K R49 STD CODEC_SDIN 2 0 .0K 1% U6 P6 6 1uF 25 V C19 R38 20. 0K 1% IN_B OUT_B 7 RING_PHN TIP_PHN 0 Oh m R50 ROUT SRD C O D E C _ S D O UT Sample Select Appendix A, Rev. 2 MF6 0 0 0 1 32.00 0 0 48.00 MF7 MF8 FS (KHZ) SERIAL MODE 4 SELECTED MASTER, 32BITS PER FRAME R96 M O D E1 0 Oh m R97 M O D E2 0 Oh m R98 M O D E3 0 Ohm DNP B C 0 Oh m 2 2 R47 STCK C O D E C _ S C LK C24 4 7 uF 10VDC 3 11 10 2 1 0 Oh m Headphone Out Stereo Jack 1/8 " +5.0VA C23 4 7 uF 10VDC 0 Oh m R48 PD0 / C O D E C _ R E SET 0 Oh m R52 PD1 /CCS 0 Oh m R53 PD2 CDIN DSP Standard Pro ducts Division 2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510 1 0 Oh m 1 R54 PD3 CCLK 0 Oh m Titl e Size B SSI 16-BIT S TEREO CODEC Docum ent Numb er DSP56F827EVM. DSN Rev. Date : Monday, April 09, 2001 D Design er: DSPD Design Sheet 6 E of 10 1.0 A Figure A-6. SSI 16-Bit Stereo Codec A-7 13 51 O h m DB2 5M JG1 2 1 A-8 B C A D E Parallel JTAG Interface R15 4 4 27 0 P O R T _ I DENT R16 P2 1 14 2 R17 1A1 1A2 1A3 1A4 2A1 2Y2 2Y3 2Y4 2A4 17 2A3 15 +3.3V R20 5.1 K 3 27 0 U8 P O RT_RESET 2 1Y1 1Y2 1Y3 1Y4 2Y1 2A2 13 TDO 9 /J_T RST 12 TDI 14 TCK 16 TMS 4 6 R18 8 27 0 11 7 5 T7 1 + 3 .3V P O RT_TDO 51 O h m P O R T _ C O N NECT R23 5.1 K R22 MC74LCX244A D W 20 1 19 VCC 1G 2G GND R21 3 R19 27 0 P O R T _ VCC 18 PORT _TMS 27 0 P O RT_TCK P O R T _ TDI / P O RT_TRST P O R T _DE P_RESET 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 3 10 On-Board Host Target Interface Disable +3.3V U9A / J _ R E SET 1 3 /POR 7 4 AC00 R25 U9B Q1 2N2222A 4 /J_T RST 5 7 4 AC00 +3.3V 6 13 7 4 AC00 5. 1K R26 47 K 12 11 /T RST 2 10 7 4 AC00 U9D TCK TDO TDI 9 8 /RE SET / J _ R E SET R24 5.1 K / J _ R E SET U9C +3.3V J3 /J_T RST TM S KEY 2 56F827EVM User Manual, Rev. 2 /POR 47 K TDO 47 K /J_T RST 47 K R29 R28 R27 2 P_RESET 13 11 9 7 5 3 1 14 12 10 8 6 4 2 JTAG Connector DSP Standard Pro ducts Division 2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510 1 1 Titl e Size B PARALLE L JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR Docum ent Numb er DSP56F827EVM. DSN Date : Monday, April 09, 2001 C Rev. Design er: DSPD Design D Sheet 7 E of 10 1.0 A B Freescale Semiconductor Figure A-7. Parallel JTAG Host Target Interface and JTAG Connector A B C D E 4 4 Freescale Semiconductor J1 /CS1 J2 A10 A9 A8 A7 A20 A19/GND GND GND /WR D0 D1 D2 GND GND GND A11 /DS A15 A14 PCS7 A13 A12 D8 D9 GND GND GND A17/GND GND 3 3 A18/GND /CS0 A16/GND GND D10 D11 D12 D13 PCS5 D14 D15 /RD A6 GND GND CS3/GND D3 D4 D5 D6 PCS6 D7 /PS A0 A1 PCS4 A2 A3 PCS3 A5 A4 PCS2 CS2/GND PB0 CLKO TA0 PB3 TA2 PB5 ANA0 SRD SRFS SCLK ANA2 MOSI MISO ANA4 /SS SRCK STFS /RESET ANA6 STD STCK /IRQB /IRQA +3.3V +3.3V GND ANA8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 PB1 PB2 TA1 PB4 TA3 PB6 ANA1 PB7 PD0 PD1 ANA3 PD2 PD3 ANA5 PD4 PD5 PD6 PD7 ANA7 RXD1 TXD1 RXD0 TXD0 +3.3V GND GND GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND +3.3V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 A N A 9 GND Appendix A, Rev. 2 Daughter Address/Data Connector Daughter Peripheral Port Connector 2 2 GND DS P Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510 1 1 Tit le Siz e A B D A U G H T E R C ARD EXPANSION CONNECTORS Docu ment Numbe r DSP56F8 27EVM.DSN Date: Monday, April 09, 2001 C Rev. Design er: D S P D D e s i g n D Shee t 8 of E 10 1.0 A Figure A-8. Daughter Card Expansion Connectors A-9 4 5 3 8 A-10 B D C E A EXTERNAL POWER INPUT 7-12VDC/AC D3 L5 +3.3VA D1 FERRITE BEAD P1 2 U14 1 FM4001 FM4001 + C58 47uF 10VDC D4 +5.0V VOUT 2 4 U10 3 VIN L1 4 FERRITE BEAD MC33269DT-3.3 + C5 47uF 10VDC GND VOUT VOUT C4 0.1uF 1 2 V CC +3.3V 43 VIN GND MC33269DT-5 VOUT 4 +1 + C3 470uF 16VDC 1 D2 3 TB1 FM4001 U13 3 VIN GND MC33269DT-ADJ +5.0VA C6 0.1uF VOUT 4 FERRITE BEAD + C56 47uF 10VDC 3 +5VDC INPUT VOUT 2 + - 1 2 +5.0V L4 C55 0.1uF 1 +2.5V L2 +5.0V FERRITE BEAD R94 243 1% Rlow Vout = 1.25( 1 + (Rhigh/Rlow)) + 2 L3 Rhigh 56F827EVM User Manual, Rev. 2 C57 47uF 10VDC FERRITE BEAD R95 243 1% Rhigh = 243 1% for 2.5V 2 +3.3V R2 470 5.0V, 3.3V & Adj REGULATOR 4 1 2 3 DS P Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510 1 LED7 1 Tit le Siz e A B P O W ER SUPPLIES Docu ment Numbe r D SP56F8 27EVM.DSN Date: Monday, April 09, 2001 C Rev. Design er: D S P D D e s i g n D POWER GOOD LED MC33269 Shee t 9 of E 10 1.0 A Freescale Semiconductor Figure A-9. Power Supplies A B C D E DSP56F827 +2.5V C37 1.0uF C33 0.01uF C34 0.1uF C38 0.1uF C39 0.01uF C40 1.0uF C41 0.01uF C42 0.1uF +3.3V +3.3V +3.3V +3.3V +3.3V +3.3VA +3.3VA +3.3VA +2.5V +2.5V 1 1 TP1 TP2 TP6 TP5 1 TP7 C52 0.01uF C53 0.1uF C54 0.01uF +5.0VA TEST POINT 1 +3.3V TEST POINT +2.5V TEST POINT DS P Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 (480) 413-5090 FAX: (480) 413-2510 1 1 Tit le Siz e A B BYPASS CAPS Docu ment Numbe r DSP56F8 27EVM.DSN Date: Monday, April 09, 2001 C 1 Freescale Semiconductor C59 1.0uF 4 4 C35 0.01uF C36 0.1uF GS72116 +3.3V C45 0.01uF C46 0.1uF C48 0.1uF C49 0.01uF DNP C50 0.1uF C51 0.1uF +3.3V +3.3V +3.3V +3.3V +3.3V +5.0VA AT45DB011 74AC04 74AC00 DS1818 MAX3245 74LCX244 LM4880 +3.3V +3.3V 3 3 C43 0.01uF C44 0.1uF C22 0.1uF CS4218 +5.0VA +3.3V TP4 TP3 1 1 OSC ANALOG GROUND TEST POINT GROUND TEST POINTS +3.3V +2.5V 2 Appendix A, Rev. 2 D +3.3V +3.3V 2 Rev. Design er: D S P D D e s i g n Shee t 1 0 of E 10 1.0 A Figure A-10. Bypass Caps A-11 56F827EVM User Manual, Rev. 2 A-12 Freescale Semiconductor Appendix B 56F827EVM Bill of Material Qty. Description Ref. Designators Integrated Circuits 1 1 1 1 1 1 1 1 1 1 1 1 1 DSP56F827FG80 GS72116 MAX3245 AT45DB011 CS4218 LM4880 12.288MHZ OSC 74LCX244 74AC00 +3.3V Voltage Regulator 74AC04 +2.5V Voltage Regulator +5.0V Voltage Regulator U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U13 U14 Resistors 1 1 11 10 4 10M 470 270 47K 5.1K R1 R2 R3, R6, R9, R11, R13 - R19 R4, R5, R7, R8, R10, R12, R26 - R29 R20, R23 - R25 SMEC, RC73L2A10MOHMJT SMEC, RC73L2A470OHMJT SMEC, RC73L2A270OHMJT SMEC, RC73L2A47KOHMJT SMEC, RC73L2A5.1KOHMJT Freescale, DSP56F827FG80 GSI, GS72116TP-12 Maxim, MAX3245EEAI Atmel, AT45DB011-SC Crystal Semiconductor, CS4218-KQ National Semiconductor, LM4880M Epson, SG-531P-12.288MC ON Semiconductor, MC74LCX244ADW Fairchild, 74AC00SC ON Semiconductor, MC33269DT-3.3 ON Semiconductor, MC74AC04AD ON Semiconductor, MC33269DT-ADJ ON Semiconductor, MC33269DT-5 Vendor Part #s Appendix B, Rev. 2 Freescale Semiconductor B-1 Qty. Description Ref. Designators Resistors (Continued) Vendor Part #s 2 4 2 19 51 5.62K 39.2K 10K R21, R22 R30 - R33 R34, R35 R36, R37, R42 - R45, R67, R70 R72, R82 - R85, R87, R90 - R93 R38 - R40, R46 R41, R55 - R62, R68, R69, R86 R47 - R54, R88, R89, R96, R97 SMEC, RC73L2A51OHMJT SMEC, RC73L2A5.62KOHMFT SMEC, RC73L2A39.2KOHMFT SMEC, RC73L2A10KOHMJT 4 12 12 2 20.0K 1K SMEC, RC73L20.0KOHMFT SMEC, RC73L2A1KOHMJT SMEC, RC73JP2A SMEC, RC73L243OHMFT 243 1% R94, R95 Inductors 4 1.0mH FERRITE BEAD L1, L2, L3, L4 LEDs Panasonic, EXC-ELSA35V 2 2 3 Red LED Yellow LED Green LED LED1, LED4 LED2, LED5 LED3, LED6, LED7 Diode Hewlett-Packard, HSMS-C650 Hewlett-Packard, HSMY-C650 Hewlett-Packard, HSMG-C650 2 1 S2B-FM401 1Amp Bridge Rectifier D1, D2, D3 D4 Capacitors Vishay, DL4001DICT General Semiconductor, DF02S 1 18 470 F, +16V DC 0.1 F C3 C4, C6, C9, C22, C30 - C32, C34, C36, C38, C42, C44, C46, C48, C50, C51, C53, C55 C5, C7, C23, C24, C56, C57, C58 C8, C14 C10, C12 C11, C13, C19, C20, C25 - C29, C37, C40, C59 ELMA, RV-16V471MH10R SMEC, MCCE104K2NR-T1 7 2 2 12 47 F, +16V DC 0.33 F 470pF 1.0 F, +25V DC ELMA, RV2-16V470M-R SMEC, MCCE334K3NR-T1 SMEC, MCCE471J2NO-T1 SMEC, MCCE105K3NR-T1 56F827EVM User Manual, Rev. 2 B-2 Freescale Semiconductor Qty. Description Ref. Designators Capacitors (Continued) Vendor Part #s 2 3 9 0.0022 F 0.47 F 0.01 F C15, C16 C17, C18, C21 C33, C35, C39, C41, C43, C45, C49, C52, C54 Jumpers SMEC, MCCE222K2NR-T1 SMEC, MCCE474K3NR-T1 SMEC, MCCE103K2NR-T1 4 2 1 1 3 4 2, 2mm Header 1, 2mm Header 2, 2mm Header JG1 - JG3, JG6 JG4, JG5 JG7 Test Points SAMTEC, TMM-102-03-S-S SAMTEC, TMM-103-03-S-S SAMTEC, TMM-104-03-S-D 7 1 1, Pin TP1 - TP7 Samtec, TSW-101-06-S-S Crystals 1 4.00MHz Crystal Y1 Connectors 1 2.1mm coax Power Connector DB25M Connector DE9S Connector 1/8” Stereo Jack 51-Pin HD Connector 7 x 2 Bergstick 2-Pin Terminal Block P1 Switchcraft, RAPC-722 CTS, ATS04ASM-T 1 1 3 2 1 1 P2 P3 P4 - P6 J1, J2 J3 TB1 Switches AMPHENOL, 617-C025P-AJ121 AMPHENOL, 617-C009S-AJ120 Switchcraft, 35RAPC4BHN2 FCI Framatome Conn, 91930-21151 SAMTEC, TSW-107-07-S-D On-Shore Technology, ED500/2DS 3 1 SPST Pushbutton 3-Position DIP SW S1 - S3 S4 Transistors Panasonic, EVQ-PAD05R CTS, 209-3LPST 1 2N2222A Q1 ZETEX, FMMT2222ACT Appendix B, Rev. 2 Freescale Semiconductor B-3 Qty. Description Ref. Designators Miscellaneous Vendor Part #s 8 4 2mm Shunt Rubber Feet SH1–SH8 RF1–RF4 Samtec, 2SN-BK-T 3M, SJ5018BLKC 56F827EVM User Manual, Rev. 2 B-4 Freescale Semiconductor INDEX Numerics 1.2A power supply 2-14 16-bit 2.5V/3.3V hybrid controller 2-1 16-bit stereo codec interface 2-1 1M-bit Serial EEPROM 2-1 4.00MHz crystal oscillator 2-1 64Kx16 bits of data memory 2-1 64Kx16 bits of program memory 2-1 I IC IC Preface-ix Integrated Circuit Preface-ix J Joint Test Action Group Preface-ix JTAG 1-1, 2-1 connector 2-9 JTAG Preface-ix JTAG port interface 2-1 Jumper Group 1-3 JG1 1-3 JG2 1-3 JG3 1-3 JG4 1-3 JG5 1-3 JG6 1-3 JG7 1-3 C Codec Preface-ix D Data memory 2-3 Daughter Card Expansion interface 2-1 Debugging 2-8 Development Card 2-1 E EEPROM EEPROM Preface-ix Electrically Erasable Programmable Read Only Memory Preface-ix Evaluation Module Preface-ix EVM EVM Preface-ix External oscillator frequency input 2-1 L Low-profile Quad Flat Pack Preface-ix LQFP LQFP Preface-ix M MPIO MPIO Preface-ix Multi-Purpose Input/Output port Preface-ix F FSRAM 2-1, 2-3 O On-board power regulation 2-2 OnCE 1-1 OnCE(TM) OnCE Preface-ix On-Chip Emulation Preface-ix Operating Mode 2-7 G General Purpose Input/Output port Preface-ix GPIO 2-2 GPIO Preface-ix H Host Parallel Interface Connector 2-8 Host Target Interface 2-8 Index, Rev. 2 Freescale Semiconductor Index - i P Parallel JTAG Host Target Interface 2-1 PCB PCB Preface-ix Phase Locked Loop Preface-ix PLL PLL Preface-ix Printed Circuit Board Preface-ix Program memory 2-3 W Wait State Preface-ix WS WS Preface-ix R RAM RAM Preface-ix Random Access Memory Preface-ix Read-Only Memory Preface-ix Real-time debugging 2-8 ROM ROM Preface-ix RS-232 interface 2-1, 2-5 level converter 2-5 schematic diagram 2-5 RS-232 interface 2-1 S SCI SCI Preface-ix SCI-compatible peripheral 2-2 Serial Communications Interface port Preface-ix Serial Peripheral Interface port Preface-ix SPI 2-2 SPI Preface-ix SRAM external data 2-1 external program 2-1 SRAM Preface-ix SSI 2-2 SSI Preface-ix Static Random Access Memory Preface-ix Stereo 16-bit codec interface 2-1 Stereo headphone interface 2-1 Synchronous Serial Interface port Preface-ix DSP56F827EVM User Manual, Rev. 2 Index - ii Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56F827EVMUM Rev. 2 07/2005