56F8013

56F8013/56F8011 Data Sheet Preliminary Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8013 Rev. 10 01/2007 freescale.com Document Revision History Version History Rev. 0 Rev. 1 Initial release. Updates to Part 10, Specifications, Table 10-1, added maximum clamp current, per pin Table 10-12, clarified variation over temperature table and graph Table 10-16, added LIN slave timing Added alternate pins to Figure 11-1 and Table 11-1. Corrected ADC offering on page 3, clarified Section 1.4.1, corrected bit selects in Timer Channel 3 Input (TC3_INP) bit 9, Section 6.3.1.7, and simplified notes in Table 10-9. Added clarification on sync inputs in Section 1.4.1, added voltage difference specification to Table 10-1 and Table 10-4, deleted formula for Ambient Operating Temperature in Table 10-4, also a note for pin group 3 to Table 10-1, corrected Table 8-1, error in Port C peripheral function configuration, removed text from notes in Table 10-9 that referred to multiple flash blocks - this family has one flash block. Added RoHs and “pb-free” language to back cover. Updates to Section 10 Table 10-5, corrected max values for ADC Input Current High and Low; corrected typ value for pull-up disabled Digital Input Current Low (a) Table 10-6, corrected typ and added max values for Standby > Stop and Powerdown modes Table 10-7, corrected min value for Low-Voltage Interrupt for 3.3V Table 10-11, corrected typ and max values and units for PLL lock time Table 10-12, corrected typ values for Relaxation Oscillator output frequency and variation over temperature (also increased temp range to 150 degreesC) and added variation over temperature from 0—105 degreesC Updated Figure 10-5 Table 10-19, updated max values for Integral Non-Linearity full input signal range, Negative Differential Non-Linearity, ADC internal clock, Offset Voltage Internal Ref, Gain Error and Offset Voltage External Ref; updated typ values for Negative Differential Non-Linearity, Offset Voltage Internal Ref, Gain Error and Offset Voltage External Ref; added new min values and corrected typ values for Signal-to-noise ratio, Total Harmonic Distortion, Spurious Free Dynamic Range, Signal-to-noise plus distortion, Effective Number of Bits Added details to Section 1. Clarified language in State During Reset column in Table 2-3; corrected flash data retention temperature in Table 10-4; moved input current high/low toTable 10-19 and location of footnotes in Table 10-5; reorganized Table 10-19; clarified title of Figure 10-1. Added information on automotive device for 56F8013. Added information on 56F8011device; edited to indicate differences in 56F8013 and 56F8011 devices. Updated values for VEI3.3 and VEI2.5 in Table 10-7. Deleted values for input and output voltage in Table 10-8. Added row for MC56F8013MFAE in Table 10-12. Description of Change Rev. 2 Rev. 3 Rev. 4 Rev. 5 Rev. 6 Rev. 7 56F8013/56F8011 Data Sheet, Rev. 10 2 Freescale Semiconductor Preliminary Document Revision History (Continued) Version History Rev. 8 Description of Change • In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). • In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. • In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz. Rev. 9 Rev. 10 In Table 10-19, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz. Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pin to VDD through a 2.2K resistor. Please see http://www.freescale.com for the most current data sheet revision. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 3 56F8013/56F8011 General Description Note: Features in italics describe the 56F8011 device. • Up to 32 MIPS at 32MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 56F8013 device offers 16KB Program Flash 56F8011 device offers 12KB Program Flash • 56F8013 device offers 4KB Unified Data/Program RAM 56F8011 device offers 2KB Unified Data/Program RAM • One 6-channel PWM module • Two 3-channel 12-bit ADCs • One Serial Communication Interface (SCI) with LIN slave functionality • One Serial Peripheral Interface (SPI) • One 16-bit Quad Timer • One Inter-Integrated Circuit (I2C) Port • Computer Operating Properly (COP)/Watchdog • On-Chip Relaxation Oscillator • Integrated Power-On Reset and Low-Voltage Interrupt Module • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 26 GPIO lines • 32-pin LQFP Package RESET VCAP 4 JTAG/EOnCE Port or GPIOD VDD VSS 2 VDDA VSSA 7 PWM Outputs PWM or Timer Port or GPIOA Program Controller and Hardware Looping Unit Digital Reg Analog Reg 16-Bit 56800E Core Low-Voltage Supervisor Bit Manipulation Unit Address Generation Unit Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators 3 AD0 3 ADC or GPIOC PAB PDB CDBR CDBW Memory Program Memory 8K x 16 Flash 6K x 16 Flash Unified Data / Program RAM 4KB 2KB XDB2 XAB1 XAB2 PAB PDB CDBR CDBW R/W Control AD1 System Bus Control IPBus Bridge (IPBB) 2 Timer or GPIOB SPI or I2C or Timer or GPIOB 4 SCI or I2C or GPIOB 2 COP/ Watchdog Interrupt Controller System Integration Module P O R O Clock S Generator* C *Includes On-Chip Relaxation Oscillator 56F8013/56F8011 Block Diagram 56F8013/56F8011 Data Sheet, Rev. 10 4 Freescale Semiconductor Preliminary 56F8013/56F8011 Data Sheet Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 6 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8013/56F8011 Features . . . . . . . . . . . . . . 6 56F8013/56F8011 Description . . . . . . . . . . . 8 Award-Winning Development Environment . 9 Architecture Block Diagram . . . . . . . . . . . . . 9 Product Documentation . . . . . . . . . . . . . . . 13 Data Sheet Conventions . . . . . . . . . . . . . . . 13 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . .85 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 85 8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . . 87 Part 9: Joint Test Action Group (JTAG) . . . 92 9.1. 56F8013/56F8011 Information . . . . . . . . . . 92 Part 2: Signal/Connection Descriptions . . 14 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2. 56F8013/56F8011 Signal Pins . . . . . . . . . . 18 Part 10: Specifications. . . . . . . . . . . . . . . . . 92 10.1. General Characteristics . . . . . . . . . . . . . . . 92 10.2. DC Electrical Characteristics . . . . . . . . . . . 96 10.3. AC Electrical Characteristics . . . . . . . . . . . 98 10.4. Flash Memory Characteristics . . . . . . . . . . 99 10.5. External Clock Operation Timing . . . . . . . 100 10.6. Phase Locked Loop Timing . . . . . . . . . . . 100 10.7. Relaxation Oscillator Timing. . . . . . . . . . . 101 10.8. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . 102 10.9. Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . 104 10.10. Quad Timer Timing. . . . . . . . . . . . . . . . . 107 10.11. Serial Communication Interface (SCI) Timing. . . . . . . . . . . . . . . . . 109 10.12. Inter-Integrated Circuit Interface (I2C) Timing . . . . . . . . . . . . . . . . . 110 10.13. JTAG Timing. . . . . . . . . . . . . . . . . . . . . . 111 10.14. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . 113 10.15. Equivalent Circuit for ADC Inputs . . . . . . 114 10.16. Power Consumption . . . . . . . . . . . . . . . . 114 Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1. 3.2. 3.3. 3.4. 3.5. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating Modes . . . . . . . . . . . . . . . . . . . . . 26 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 28 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . 29 Part 4: Memory Map . . . . . . . . . . . . . . . . . . 29 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt Vector Table . . . . . . . . . . . . . . . . . 29 Program Map . . . . . . . . . . . . . . . . . . . . . . . 31 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 EOnCE Memory Map . . . . . . . . . . . . . . . . . . 34 Peripheral Memory Mapped Registers . . . . 35 Part 5: Interrupt Controller (ITCN) . . . . . . . 44 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 44 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Functional Description . . . . . . . . . . . . . . . . 44 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 46 Operating Modes . . . . . . . . . . . . . . . . . . . . . 46 Register Descriptions . . . . . . . . . . . . . . . . . . 47 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Part 11: Packaging . . . . . . . . . . . . . . . . . . .117 11.1. 56F8013/56F8011 Package and Pin-Out Information . . . . . . . . . . . 117 Part 6: System Integration Module (SIM). . 63 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . Clock Generation Overview . . . . . . . . . . . . Power-Down Modes . . . . . . . . . . . . . . . . . . Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 63 64 65 78 78 80 82 83 Part 12: Design Considerations . . . . . . . . .120 12.1. Thermal Design Considerations . . . . . . . . 120 12.2. Electrical Design Considerations . . . . . . . 122 Part 13: Ordering Information . . . . . . . . . . 124 Part 14: Appendix. . . . . . . . . . . . . . . . . . . . 124 Part 7: Security Features . . . . . . . . . . . . . . . 83 7.1. Operation with Security Enabled . . . . . . . . 84 7.2. Flash Access Lock and Unlock Mechanisms . . . . . . . . . . . 84 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 5 Part 1 Overview 1.1 56F8013/56F8011 Features 1.1.1 • • • • • • • • • • • • • • Digital Signal Controller Core Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits 32-bit arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging 1.1.2 Differences Between Devices Table 1-1 outlines the key differences between the 56F8013 and 56F8011 devices. Table 1-1 Device Differences Feature Program Flash Unified Data/Program RAM 56F8013 16KB 4KB 56F8011 12KB 2KB 1.1.3 • • • Memory Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security and protection that prevent unauthorized users from gaining access to the internal Flash On-chip memory: — 16KB of Program Flash (56F8013 device) 12KB of Program Flash (56F8011 device) — 4KB of Unified Data/Program RAM (56F8013 device) 2KB of Unified Data/Program RAM (56F8011 device) • EEPROM emulation capability using Flash 56F8013/56F8011 Data Sheet, Rev. 10 6 Freescale Semiconductor Preliminary 56F8013/56F8011 Features 1.1.4 • Peripheral Circuits for 56F8013/56F8011 One multi-function six-output Pulse Width Modulator (PWM) module — Up to 96MHz PWM operating clock — 15 bits of resolution — Center-aligned and Edge-aligned PWM signal mode — Four programmable fault inputs with programmable digital filter — Double-buffered PWM registers — Taking into account values setting ADC high- and low-limit registers, each complementary PWM signal pair allows selection of a PWM supply source from: – PWM generator – External GPIO – Internal timers – ADC conversion result Two independent 12-bit Analog-to-Digital Converters (ADCs) — 2 x 3 channel inputs — Supports both simultaneous and sequential conversions — ADC conversions can be synchronized by both PWM and timer modules — Sampling rate up to 2.67MSPS — 8-word result buffer registers — ADC Smart Power Management (Auto-standby, auto-powerdown) One 16-bit multi-purpose Quad Timer module (TMR) — Up to 96MHz operating clock — Four independent 16-bit counter/timers with cascading capability — Each timer has capture and compare capability — Up to 12 operating modes One Serial Communication Interface (SCI) with LIN Slave functionality — Full-duplex or single-wire operation — Two receiver wake-up methods: – Idle line – Address mark One Serial Peripheral Interface (SPI) — Full-duplex operation — Master and slave modes — Programmable Length Transactions (2 to 16 bits) One Inter-Integrated Circuit (I2C) port — Operates up to 400kbps — Supports both master and slave operation Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources Up to 26 General-Purpose I/O (GPIO) pins with 5V tolerance Integrated Power-On Reset and Low-Voltage Interrupt Module • • • • • • • • 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 7 • • • • Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals Clock Sources: — On-chip relaxation oscillator — External clock source On-chip regulators for digital and analog circuitry to lower cost and reduce noise JTAG/EOnCE debug programming interface for real-time debugging 1.1.5 • • • • • Energy Information Fabricated in high-density CMOS with 5V tolerance On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power 1.2 56F8013/56F8011 Description The 56F8013/56F8011 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8013/56F8011 is well-suited for many applications. The 56F8013/56F8011 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general purpose inverters, smart sensors, fire and security systems, power management, and medical monitoring applications. The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F8013/56F8011 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8013/56F8011 also offers up to 26 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F8013 Digital Signal Controller includes 16KB of Program Flash and 4KB of Unified Data/Program RAM. The 56F8011 Digital Signal Controller includes 12KB of Program Flash and 2KB of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages. Program Flash page erase size is 512 Bytes (256 Words). A full set of programmable peripherals—PWM, ADCs, SCI, SPI, I2C, Quad Timer—supports various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs). 56F8013/56F8011 Data Sheet, Rev. 10 8 Freescale Semiconductor Preliminary Award-Winning Development Environment 1.3 Award-Winning Development Environment Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Architecture Block Diagram The 56F8013/56F8011’s architecture is shown in Figure 1-1, Figure 1-2, and Figure 1-3. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2 and Figure 1-3 show the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the on-board regulator and power and ground signals. They also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals. 1.4.1 PWM, TMR and ADC Connections Figure 1-3 shows the over/under voltage connections from the ADC to the PWM and the connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar manner to the over/under voltage control signals. See the 56F801X Peripheral Reference Manual for additional information. The PWM_reload_sync output can be connected to the TMR channel 3 input and the TMR channels 2 and 3 outputs are connected to the ADC sync inputs. TMR channel 3 output is connected to SYNC0 and TMR channel 2 is connected to SYNC1. SYNC0 is the master ADC sync input that is used to trigger ADCA and ADCB in sequence and parallel mode. SYNC1 is used to trigger ABCB in parallel independent mode. These are controlled by bits in the SIM Control Register; see Section 6.3.1. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 9 DSP56800E Core Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) M01 N3 ALU1 ALU2 Instruction Decoder Interrupt Unit Looping Unit R0 R1 R2 R3 R4 R5 N SP XAB1 XAB2 PAB PDB CDBW CDBR XDB2 Data / Program RAM Program Memory BitManipulation Unit Enhanced OnCE™ Y A2 B2 C2 D2 A1 B1 C1 D1 Y1 Y0 X0 A0 B0 C0 D0 Data Arithmetic Logic Unit (ALU) Multi-Bit Shifter IPBUS Interface JTAG TAP MAC and ALU Figure 1-1 56800E Core Block Diagram 56F8013/56F8011 Data Sheet, Rev. 10 10 Freescale Semiconductor Preliminary Architecture Block Diagram To/From IPBus Bridge CLKGEN (ROSC / PLL / CLKIN) Interrupt Controller Low-Voltage Interrupt GPIOAn GPIOBn GPIOCn GPIODn 8 8 6 4 GPIO A POR & LVI GPIO B System POR GPIO C SIM RESET / GPIOA7 GPIO D COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 11 (Continued from Figure 1-2) To/From IPBus Bridge PWM0 - 3 PWM PWM4, 5 Fault1, 2 Fault0 Output Controls Reload Pulse Fault3 2 4 2 PWM4, 5 Fault1, 2 T2, 3 2 GPIOA4 - 5 PWM0 - 3 GPIOA0 - 3 3 from ADC 2 Fault0 Fault3 GPIOA6 T3i Timer T2o, T3o T2/3 T1 T0 2 T1 GPIOB5 T0 CLKO 2 GPIOB4 I2C is muxed with both SPI and SCI. T2 and T3 are muxed with SPI and PWM. 2 SCI TXD, RXD 2 I2C SDA, SCL 2 GPIOB6 - 7 SCLK, SS SPI MISO, MOSI 2 2 T2, 3 GPIOB0 - 1 3 Sync0, Sync1 Over/Under Limits ADC to PWM ANA0, 1, 3 ANA2 VREFH, VREFL ANB2 ANB0, 1, 3 2 3 3 ANA0, 1, 3 ANA2 ANB2 VREFH, VREFL GPIOB2 - 3 GPIOC0, 1, 3 GPIOC2, 6 ANB0, 1, 3 GPIOC4, 5, 7 IPBus Figure 1-3 56F8013/56F8011 Peripheral I/O Pin-Out 56F8013/56F8011 Data Sheet, Rev. 10 12 Freescale Semiconductor Preliminary Product Documentation 1.5 Product Documentation The documents listed in Table 1-2 are required for a complete description and proper design with the 56F8013 or 56F8011. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.com Table 1-2 56F8013/56F8011 Chip Documentation Topic DSP56800E Reference Manual 56F801X Peripheral Reference Manual 56F801X Serial Bootloader User Guide 56F8013/56F8011 Technical Data Sheet Errata Description Detailed description of the 56800E family architecture, 16-bit Digital Signal Controller core processor, and the instruction set Detailed description of peripherals of the 56F801X family of devices Detailed description of the Serial Bootloader in the 56F801x family of devices Electrical and timing specifications, pin descriptions, and package descriptions (this document) Details any chip issues that might be present Order Number DSP56800ERM MC56F8000RM 56F801XBLUG MC56F8013 MC56F8013E MC56F8011E 1.6 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL “asserted” “deasserted” Examples: 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 13 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8013/56F8011 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present on a pin, sorted by pin number. Table 2-1 Functional Group Pin Allocations Functional Group Power (VDD or VDDA) Ground (VSS or VSSA) Supply Capacitors Reset Pulse Width Modulator (PWM) Ports1 Serial Peripheral Interface (SPI) Ports2 Analog-to-Digital Converter (ADC) Ports Timer Module Ports3 Serial Communications Interface (SCI) Ports4 JTAG/Enhanced On-Chip Emulation (EOnCE) 1. Pins in this section can function as TMR and GPIO. 2. Pins in this section can function as TMR, I2C, and GPIO. 3. Pins can function as PWM and GPIO. 4. Pins in this section can function as I2C and GPIO. Number of Pins 2 3 1 1 7 4 6 2 2 4 56F8013/56F8011 Data Sheet, Rev. 10 14 Freescale Semiconductor Preliminary Introduction Table 2-2 56F8013/56F8011 Pins Peripherals: LQFP Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name Signal Name GPIO I2C B6 B1 B7 B5 C4 C5 C6 ANB0 ANB1 ANB2, VREFL VDDA VSSA C2 C1 C0 ANA2, VREFH ANA1 ANA0 VSS D2 A7 B3 B2 A6 B4 A5 B0 A4 A2 A3 SCL SCLK PWM4, FAULT1 PWM2 PWM3 T2 PWM5, FAULT2 MOSI MISO FAULT0 T0 T3 CLKO T3 T2 TCK RESET SDA SDA SCL TXD FAULT3 T1 SCI RXD SS SPI ADC PWM Quad Power & Timer Ground JTAG Misc. CLKIN GPIOB6 GPIOB6, RXD, SDA, CLKIN GPIOB1 GPIOB1, SS, SDA GPIOB7 GPIOB7, TXD, SCL GPIOB5 GPIOB5, T1, FAULT3 ANB0 ANB1 ANB2 VDDA VSSA ANA2 ANA1 ANA0 VSS_IO TCK RESET ANB0, GPIOC4 ANB1, GPIOC5 ANB2, VREFL, GPIOC6 VDDA VSSA ANA2, VREFH, GPIOC2 ANA1, GPIOC1 ANA0, GPIOC0 VSS TCK, GPIOD2 RESET, GPIOA7 GPIOB3 GPIOB3, MOSI, T3 GPIOB2 GPIOB2, MISO, T2 GPIOA6 GPIOA6, FAULT0 GPIOB4 GPIOB4, T0, CLKO GPIOA5 GPIOA5, PWM5, FAULT2, T3 GPIOB0 GPIOB0, SCLK, SCL GPIOA4 GPIOA4, PWM4, FAULT1, T2 GPIOA2 GPIOA2, PWM2 GPIOA3 GPIOA3, PWM3 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 15 Table 2-2 56F8013/56F8011 Pins (Continued) Peripherals: LQFP Pin # 25 26 27 28 29 30 31 32 Pin Name VCAP VDD VSS_IO Signal Name VCAP VDD VSS A1 A0 D0 D3 D1 PWM1 PWM0 TDI TMS TDO GPIO I2C SCI SPI ADC PWM Quad Power & Timer Ground VCAP VDD VSS JTAG Misc. GPIOA1 GPIOA1, PWM1 GPIOA0 GPIOA0, PWM0 TDI TMS TDO TDI, GPIOD0 TMS, GPIOD3 TDO, GPIOD1 56F8013/56F8011 Data Sheet, Rev. 10 16 Freescale Semiconductor Preliminary Introduction Power Ground Power Ground Other Supply Ports VDD VSS VDDA VSSA 1 2 1 1 VCAP 56F8013 / 56F8011 1 1 1 1 GPIOB0 (SCLK, SCL) GPIOB1 (SS, SDA) GPIOB2 (MISO, T2) GPIOB3 (MOSI, T3) GPIOA0 - 2 (PWM0 - 2) GPIOA3 (PWM3) GPIOA4 (PWM4, FAULT1, T2) GPIOA5 (PWM5, FAULT2, T3) GPIOA6 (FAULT0) PWM Port or Timer Port or GPIO SPI Port or I2C Port or Timer Port or GPIO 1 SCI Port or I2C Port or GPIO GPIOB6 (RXD, SDA, CLKIN) GPIOB7 (TXD, SCL) 1 1 3 1 1 RESET RESET (GPIOA7) 1 1 1 2 Timer Port or GPIO GPIOB4 (T0, CLKO) GPIOB5 (T1, FAULT3) 1 1 1 ANA0 - 1 (GPIOC0 - 1) ANA2 (VREFH, GPIOC2) ADC Port or GPIO ANB0 - 1 (GPIOC4 - 5) ANB2 (VREFL, GPIOC6) 2 1 TCK (GPIOD2) JTAG/ EOnCE Port or GPIO TMS (GPIOD3) TDI (GPIOD0) TDO (GPIOD1) 1 1 1 1 Figure 2-1 56F8013/56F8011 Signals Identified by Functional Group 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 17 2.2 56F8013/56F8011 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP Signal Name VDD VSS VSS VDDA VSSA VCAP LQFP Pin No. 26 13 27 8 Supply Supply ADC Power — This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. ADC Analog Ground — This pin supplies an analog ground to the ADC modules. VCAP — Connect this pin to a 4.4μF or greater bypass capacitor in order to bypass the core voltage regulator, required for proper chip operation. See Section 10.2.1. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Type Supply Supply State During Reset Supply Supply Signal Description I/O Power — This pin supplies 3.3V power to the chip I/O interface. VSS — These pins provide ground for chip logic and I/O drivers. 9 Supply Supply 25 Supply Supply GPIOB6 1 Input/ Output (RXD) (SDA1) Input Input/ Output Input Output disabled, internal pull-up enabled, pin is in input mode Receive Data — SCI receive data input. Serial Data — This pin serves as the I2C serial data line. (CLKIN) Clock Input — This pin serves as an optional external clock input. After reset, the default state is GPIOB6. The peripheral functionality is controlled via the SIM (See Section 6.3.8) and the CLKMODE bit of the OCCS Oscillator Control Register. 1. This signal is also brought out on the GPIOB1 pin. Return to Table 2-2 56F8013/56F8011 Data Sheet, Rev. 10 18 Freescale Semiconductor Preliminary 56F8013/56F8011 Signal Pins Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP Signal Name GPIOB7 LQFP Pin No. 3 Type Input/ Output State During Reset Output disabled, internal pull-up enabled, pin is in input mode Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (TXD) Input/ Output Input/ Output Transmit Data — SCI transmit data output or transmit / receive in single wire operation. Serial Clock — This pin serves as the I2C serial clock. After reset, the default state is GPIOB7. The peripheral functionality is controlled via the SIM. See Section 6.3.8. (SCL2) 2. This signal is also brought out on the GPIOB0 pin. RESET 15 (GPIOA7) Output disabled, internal pull-up enabled, pin is in input Input/Open mode Drain Output Input Reset — This input is a direct hardware reset on the processor. When RESET is asserted low, the chip is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. Port A GPIO — This GPIO pin can be individually programmed as an input or open drain output pin. Note that RESET functionality is disabled in this mode and the chip can only be reset via POR, COP reset, or software reset. After reset, the default state is RESET. GPIOB4 19 Input/ Output (T0) Input/ Output Output (CLKO) Output Port B GPIO — This GPIO pin can be individually programmed as disabled, an input or output pin. internal pull-up enabled, T0 — Timer, Channel 0 pin is in input mode Clock Output — This is a buffered clock signal. Using the SIM_CLKO Select Register (SIM_CLKOSR), this pin can be programmed as any of the following: disabled (logic 0), CLK_MSTR (system clock), IPBus clock, or oscillator output. See Section 6.3.7. After reset, the default state is GPIOB4. The peripheral functionality is controlled via the SIM. See Section 6.3.8. Return to Table 2-2 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 19 Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP Signal Name GPIOB5 LQFP Pin No. 4 Type Input/ Output State During Reset Signal Description (T1) Input/ Output Output (FAULT3) Output Port B GPIO — This GPIO pin can be individually programmed as disabled, an input or output pin. internal pull-up enabled, T1 — Timer, Channel 1 pin is in input mode FAULT3 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOB5. The peripheral functionality is controlled via the SIM. See Section 6.3.8. TCK 14 Input (GPIOD2) Input/ Output Output disabled, internal pull-up enabled, pin is in input mode Test Clock Input — This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-up resistor. A Schmitt trigger input is used for noise immunity. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TCK. TMS 31 Input (GPIOD3) Input/ Output Output disabled, internal pull-up enabled, pin is in input mode Test Mode Select Input — This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TMS. Note: Always tie the TMS pin to VDD through a 2.2K resistor. TDI 30 Input (GPIOD0) Input/ Output Output disabled, internal pull-up enabled, pin is in input mode Test Data Input — This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDI. Return to Table 2-2 56F8013/56F8011 Data Sheet, Rev. 10 20 Freescale Semiconductor Preliminary 56F8013/56F8011 Signal Pins Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP Signal Name TDO LQFP Pin No. 32 Type Output State During Reset Output disabled, internal pull-up enabled Signal Description Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDO. GPIOB0 21 Input/ Output Output disabled, internal pull-up enabled, pin is in input mode Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (GPIOD1) Input/ Output (SCLK) Input/ Output SPI Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. Serial Data — This pin serves as the I2C serial clock. After reset, the default state is GPIOB0. The peripheral functionality is controlled via the SIM. See Section 6.3.8. (SCL3) Input/ Output 3. This signal is also brought out on the GPIOB7 pin. GPIOB1 2 Input/ Output (SS) Input Output disabled, internal pull-up enabled, pin is in input mode Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. SPI Slave Select — SS is used in slave mode to indicate to the SPI module that the current transfer is to be received. Serial Clock — This pin serves as the I2C serial data line. After reset, the default state is GPIOB1. The peripheral functionality is controlled via the SIM. See Section 6.3.8. (SDA4) Input/ Output 4. This signal is also brought out on the GPIOB6 pin. Return to Table 2-2 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 21 Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP Signal Name GPIOB2 LQFP Pin No. 17 Type Input/ Output State During Reset Output disabled, internal pull-up enabled, pin is in input mode Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (MISO) Input/ Output SPI Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. T2 — Timer, Channel 2 After reset, the default state is GPIOB2. The peripheral functionality is controlled via the SIM. See Section 6.3.8. (T25) Input/ Output 5. This signal is also brought out on the GPIOA4 pin. GPIOB3 16 Input/ Output (MOSI) Input/ Output Output disabled, internal pull-up enabled, pin is in input mode Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. SPI Master Out/Slave In— This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. T3 — Timer, Channel 3 After reset, the default state is GPIOB3. The peripheral functionality is controlled via the SIM. See Section 6.3.8. (T36) Input/ Output 6. This signal is also brought out on the GPIOA5 pin. GPIOA0 29 Input/ Output (PWM0) Output Output disabled, internal pull-up enabled, pin is in input mode Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0. Return to Table 2-2 56F8013/56F8011 Data Sheet, Rev. 10 22 Freescale Semiconductor Preliminary 56F8013/56F8011 Signal Pins Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP Signal Name GPIOA1 LQFP Pin No. 28 Type Input/ Output State During Reset Output disabled, internal pull-up enabled, pin is in input mode Output disabled, internal pull-up enabled, pin is in input mode Output disabled, internal pull-up enabled, pin is in input mode Output disabled, internal pull-up enabled, pin is in input mode Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (PWM1) Output PWM1 — This is one of the six PWM output pins. After reset, the default state is GPIOA1. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA2 23 Input/ Output (PWM2) Output PWM2 — This is one of the six PWM output pins. After reset, the default state is GPIOA2. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA3 24 Input/ Output (PWM3) Output PWM3 — This is one of the six PWM output pins. After reset, the default state is GPIOA3. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA4 22 Input/ Output (PWM4) (FAULT1) Output Input PWM4 — This is one of the six PWM output pins. Fault1 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. T2 — Timer, Channel 2 After reset, the default state is GPIOA4. The peripheral functionality is controlled via the SIM. See Section 6.3.8. (T27) Input/ Output 7. This signal is also brought out on the GPIOB2 pin. Return to Table 2-2 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 23 Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP Signal Name GPIOA5 LQFP Pin No. 20 Type Input/ Output State During Reset Output disabled, internal pull-up enabled, pin is in input mode Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (PWM5) (FAULT2) Output Input/ Output Input/ Output PWM5 — This is one of the six PWM output pins. Fault2 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. T3 — Timer, Channel 3 After reset, the default state is GPIOA5. The peripheral functionality is controlled via the SIM. See Section 6.3.8. (T38) 8. This signal is also brought out on the GPIOB3 pin. GPIOA6 18 Input/ Output (FAULT0) Input Output disabled, internal pull-up enabled, pin is in input mode Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault0 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOA6. ANA0 12 Input Analog Input ANA0 — Analog input to ADC A, channel 0 (GPIOC0) Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANA0. ANA1 11 Input Analog Input ANA1 — Analog input to ADC A, channel 1 (GPIOC1) Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANA1. Return to Table 2-2 56F8013/56F8011 Data Sheet, Rev. 10 24 Freescale Semiconductor Preliminary 56F8013/56F8011 Signal Pins Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP Signal Name ANA2 LQFP Pin No. 10 Type Input State During Reset Analog Input Signal Description ANA2 — Analog input to ADC A, channel 2 (VREFH) (GPIOC2) Input Input/ Output VREFH — Analog reference voltage high Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANA2. ANB0 5 Input Analog Input ANB0 — Analog input to ADC B, channel 0 (GPIOC4) Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANB0. ANB1 6 Input Analog Input ANB1 — Analog input to ADC B, channel 1 (GPIOC5) Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANB1. ANB2 7 Input Analog Input ANB2 — Analog input to ADC B, channel 2 (VREFL) Input VREFL — Analog reference voltage low. This should normally be connected to a low-noise VSS. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANB2. (GPIOC6) Input/ Output Return to Table 2-2 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 25 Part 3 OCCS 3.1 Overview This module provides the 2X system clock frequency to the System Integration Module (SIM), which uses it to generate the various chip clocks. This module also produces the OSC_CLK signals plus the ADC clock and high-speed peripheral clock. The on-chip clock synthesis module allows product design using an internal relaxation oscillator to run 56F801X family parts at user-selectable frequencies up to 32MHz. 3.2 Features The On-Chip Clock Synthesis (OCCS) module interfaces to the oscillator and PLL. The OCCS module features: • • • • • • • • • Internal relaxation oscillator Ability to power down the internal relaxation oscillator Ability to put the internal relaxation oscillator into a standby mode 3-bit postscaler provides control for the PLL output Ability to power down the internal PLL Provides 2X master clock frequency and OSC_CLK signals Provides 3X fast peripheral clock to PWM and Timer Safety shutdown feature is available in the event that the PLL reference clock disappears Can be driven from an external clock source The clock generation module provides the programming interface for both the PLL and internal relaxation oscillator. 3.3 Operating Modes In 56F801X family parts, either an internal oscillator or an external frequency source can be used to provide a reference clock (SYS_CLK2) to the SIM. The 2X system clock source output from the OCCS can be described by one of the following equations: 2X system frequency = oscillator frequency 2X system frequency = (oscillator frequency X 8) / (postscaler) where: postscaler = 1, 2, 4, 8, 16, or 32 PLL output divider The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle in the system clock output. 56F8013/56F8011 Data Sheet, Rev. 10 26 Freescale Semiconductor Preliminary Operating Modes The 56F801X family parts’ on-chip clock synthesis module has the following registers: • • • • • Control Register (OCCS_CR) Divide-by Register (OCCS_DB) Status Register (OCCS_SR) Shutdown Register (OCCS_SHUTDN) Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please refer to the 56F801X Peripheral Reference Manual. 3.3.1 External Clock Source The recommended method of connecting an external clock is illustrated in Figure 3-1. The external clock source is connected to GPIOB6 / RXD. 56F8013/56F8011 GPIOB6 / RXD External Clock Figure 3-1 Connecting an External Clock Signal using GPIOB6 / RXD 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 27 3.4 Block Diagram Figure 3-2 provides a block diagram which shows how the 56F8013/56F8011 creates its internal clock, using the relaxation oscillator as an 8MHz clock reference for the PLL. TRIM[9:0] Relaxation OSC ROSB ROPD Bus Interface and Control Bus Interface GPIOB6 / RXD MUX PRECS MSTR_OSC MUX SYS_CLK_x2 source to the SIM (64MHz max) PLL X 24 FOUT ÷3 Postscaler (÷ 1, 2, 4, 8, 16, 32) ZSRC ÷2 PLLCOD FEEDBACK MUX HS PERF CLK (96MHz max) Postscaler (÷ 1, 2, 4, 8, 16, 32) FOUT/2 Lock Detector LCK Loss of Reference Clock Detector Loss of Reference Clock Interrupt Figure 3-2 OCCS Block Diagram with Relaxation Oscillator 56F8013/56F8011 Data Sheet, Rev. 10 28 Freescale Semiconductor Preliminary Pin Descriptions 3.5 Pin Descriptions 3.5.1 External Reference (GPIOB6 / RXD) The relaxation oscillator is included on chip and the reset mode is to use this as the clock source for the chip. The user then has the option of switching to an external clock reference if desired. Part 4 Memory Map 4.1 Introduction The 56F8013/56F8011 device is a 16-bit motor-control chip based on the 56800E core. It uses a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is used in both spaces and Flash memory is used only in Program space. This section provides memory maps for: • • Program Address Space, including the Interrupt Vector Table Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 4-1. Table 4-1 Chip Memory Configurations On-Chip Memory Program Flash (PFLASH) Unified RAM (ram) 56F8013 8k x 16 2k x 16 56F8011 6k x 16 1k x 16 Use Restrictions Erase / Program via Flash interface unit and word writes to CDBW Usable by both the Program and Data memory spaces 4.2 Interrupt Vector Table Table 4-2 provides the 56F8013/56F8011’s reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.6.11 for the reset value of the VBA. By default, VBA = 0, and the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 29 Table 4-2 Interrupt Vector Table Contents1 Peripheral core core core core core core core core core core core core core core 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PS OCCS FM FM FM GPIOD GPIOC GPIOB GPIOA SPI SPI SCI SCI SCI SCI SCI I2C Timer Timer 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33, 34 35 36 37 0-2 0-2 0-2 P:$46 P:$48 P:$4A 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 P:$2C P:$2E P:$30 P:$32 P:$34 P:$36 P:$38 P:$3A P:$3C P:$3E P:$40 0-2 0-2 0-2 0-2 0-2 P:$20 P:$22 P:$24 P:$26 P:$28 3 3 3 3 1-3 1-3 1-3 1-3 1-3 2 1 0 Vector Number Priority Level Vector Base Address + P:$00 P:$02 P:$04 P:$06 P:$08 P:$0A P:$0C P:$0E P:$10 P:$12 P:$14 P:$16 P:$18 P:$1A Interrupt Function Reserved for Reset Overlay2 Reserved for COP Reset Overlay Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access EOnCE Step Counter EOnCE Breakpoint Unit 0 EOnCE Trace Buffer EOnCE Transmit Register Empty EOnCE Receive Register Full SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 Reserved Reserved Power Sense PLL Lock, Loss of Clock Reference Interrupt FM Access Error Interrupt FM Command Complete FM Command, data and address Buffers Empty Reserved GPIOD GPIOC GPIOB GPIOA SPI Receiver Full / Error SPI Transmitter Empty SCI Transmitter Empty SCI Transmitter Idle SCI Reserved SCI Receiver Error SCI Receiver Full Reserved I2C Timer Channel 0 Timer Channel 1 (Continues next page) 56F8013/56F8011 Data Sheet, Rev. 10 30 Freescale Semiconductor Preliminary Program Map Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Timer Timer ADC ADC ADC PWM PWM SWILP Vector Number 38 39 40 41 42 43 44 45 Priority Level 0-2 0-2 0-2 0-2 0-2 0-2 0-2 -1 Vector Base Address + P:$4C P:$4E P:$50 P:$52 P:$54 P:$56 P:$58 P:$5A Timer Channel 2 Timer Channel 3 ADCA Conversion Complete ADCB Conversion Complete ADC Zero Crossing or Limit Error Reload PWM PWM Fault SW Interrupt Low Priority Interrupt Function 1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. If the VBA is set to $0000, the first two locations of the vector table will overlay the chip reset addresses. 4.3 Program Map The Program Memory map is shown in Table 4-3. Table 4-3 Program Memory Map for 56F80131 Begin/End Address P: $FF FFFF P: $00 8800 P: $00 87FF P: $00 8000 P: $00 7FFF P: $00 2000 P: $00 1FFF P: $00 0000 RESERVED On-Chip RAM2 4KB RESERVED Internal Program Flash 16KB Cop Reset Address = $00 0002 Boot Location = $00 0000 Memory Allocation 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 31 Table 4-4 Program Memory Map for 56F80111 Begin/End Address P: $1F FFFF P: $00 8400 P: $00 83FF P: $00 8000 P: $00 7FFF P: $00 2000 P: $00 1FFF P: $00 0800 RESERVED On-Chip RAM2 2KB RESERVED Internal Program Flash 12KB Cop Reset Address = $00 0802 Boot Location = $00 0800 RESERVED Memory Allocation P: $00 07FF P: $00 0000 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1. 4.4 Data Map Table 4-5 Data Memory Map for 56F80131 Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 8800 X:$00 EFFF X:$00 0800 X:$00 7FFF X:$00 0040 X:$00 07FF X:$00 0000 Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED RESERVED RESERVED On-Chip Data RAM2 4KB 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1. 56F8013/56F8011 Data Sheet, Rev. 10 32 Freescale Semiconductor Preliminary Data Map Table 4-6 Data Memory Map for 56F80111 Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 0400 X:$00 03FF X:$00 0000 Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED On-Chip Data RAM2 2KB 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1. Program Reserved Data EOnCE Reserved RAM Reserved Flash Peripherals Dual Port RAM Reserved RAM Figure 4-1 Dual Port RAM 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 33 4.5 EOnCE Memory Map Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE. Table 4-7 EOnCE Memory Map Address X:$FF FFFF X:$FF FFFE X:$FF FFFD X:$FF FFFC X:$FF FFFB - X:$FF FFA1 X:$FF FFA0 X:$FF FF9F X:$FF FF9E X:$FF FF9D X:$FF FF9C X:$FF FF9B X:$FF FF9A X:$FF FF99 X:$FF FF98 X:$FF FF97 X:$FF FF96 X:$FF FF95 X:$FF FF94 X:$FF FF93 X:$FF FF92 X:$FF FF91 X:$FF FF90 X:$FF FF8F X:$FF FF8E X:$FF FF8D X:$FF FF8C X:$FF FF8B X:$FF FF8A X:$FF FF89 - X:$FF FF00 OESCR OBCNTR OBMSK (32 bits) OBAR2 (32 bits) OBAR1 (24 bits) OBCR (24 bits) OSCNTR (24 bits) OSR OBASE OTBCR OTBPR OCR Register Acronym OTX1 / ORX1 OTX / ORX (32 bits) OTXRXSR OCLSR Register Name Transmit Register Upper Word Receive Register Upper Word Transmit Register Receive Register Transmit and Receive Status and Control Register Core Lock / Unlock Status Register Reserved Control Register Instruction Step Counter Instruction Step Counter Status Register Peripheral Base Address Register Trace Buffer Control Register Trace Buffer Pointer Register Trace Buffer Register Stages OTB (21 - 24 bits/stage) Trace Buffer Register Stages Breakpoint Unit Control Register Breakpoint Unit Control Register Breakpoint Unit Address Register 1 Breakpoint Unit Address Register 1 Breakpoint Unit Address Register 2 Breakpoint Unit Address Register 2 Breakpoint Unit Mask Register 2 Breakpoint Unit Mask Register 2 Reserved EOnCE Breakpoint Unit Counter Reserved Reserved Reserved External Signal Control Register Reserved 56F8013/56F8011 Data Sheet, Rev. 10 34 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers 4.6 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only. Table 4-8 summarizes base addresses for the set of peripherals on the 56F8013/56F8011 device. Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals. Table 4-8 Data Memory Peripheral Base Address Map Summary Peripheral Timer PWM ITCN ADC SCI SPI I 2C Prefix TMRn PWM ITCN ADC SCI SPI I2C COP OCCS GPIOA GPIOB GPIOC GPIOD SIM PS FM Base Address X:$00 F000 X:$00 F040 X:$00 F060 X:$00 F080 X:$00 F0B0 X:$00 F0C0 X:$00 F0D0 X:$00 F0E0 X:$00 F0F0 X:$00 F100 X:$00 F110 X:$00 F120 X:$00 F130 X:$00 F140 X:$00 F160 X:$00 F400 Table Number 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 COP CLK, PLL, OSC, TEST GPIO Port A GPIO Port B GPIO Port C GPIO Port D SIM Power Supervisor FM Table 4-9 Quad Timer Registers Address Map (TMR_BASE = $00 F000) Register Acronym TMR0_COMP1 TMR0_COMP2 TMR0_CAPT TMR0_LOAD TMR0_HOLD TMR0_CNTR TMR0_CTRL TMR0_SCTRL TMR0_CMPLD1 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 35 Table 4-9 Quad Timer Registers Address Map (Continued) (TMR_BASE = $00 F000) Register Acronym TMR0_CMPLD2 TMR0_CSCTRL TMR1_COMP1 TMR1_COMP2 TMR1_CAPT TMR1_LOAD TMR1_HOLD TMR1_CNTR TMR1_CTRL TMR1_SCTRL TMR1_CMPLD1 TMR1_CMPLD2 TMR1_CSCTRL TMR2_COMP1 TMR2_COMP2 TMR2_CAPT TMR2_LOAD TMR2_HOLD TMR2_CNTR TMR2_CTRL TMR2_SCTRL TMR2_CMPLD1 TMR2_CMPLD2 TMR2_CSCTRL TMR3_COMP1 TMR3_COMP2 TMR3_CAPT TMR3_LOAD TMR3_HOLD TMR3_CNTR TMR3_CTRL TMR3_SCTRL TMR3_CMPLD1 TMR3_CMPLD2 TMR3_CSCTRL Address Offset $9 $A $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A Register Description Comparator Load Register 2 Comparator Status and Control Register Reserved Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register 56F8013/56F8011 Data Sheet, Rev. 10 36 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-10 Pulse Width Modulator Registers Address Map (PWM_BASE = $00 F040) Register Acronym PWM_CTRL PWM_FCTRL PWM_FLTACK PWM_OUT PWM_CNTR PWM_CMOD PWM_VAL0 PWM_VAL1 PWM_VAL2 PWM_VAL3 PWM_VAL4 PWM_VAL5 PWM_DTIM0 PWM_DTIM1 PWM_DMAP1 PWM_DMAP2 PWM_CNFG PWM_CCTRL PWM_PORT PWM_ICCTRL PWM_SCTRL Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 Control Register Fault Control Register Fault Status Acknowledge Register Output Control Register Counter Register Counter Modulo Register Value Register 0 Value Register 1 Value Register 2 Value Register 3 Value Register 4 Value Register 5 Dead Time Register 0 Dead Time Register 1 Disable Mapping Register 1 Disable Mapping Register 2 Configure Register Channel Control Register Port Register Internal Correction Control Register Source Control Register Register Description Table 4-11 Interrupt Control Registers Address Map (ITCN_BASE = $00 F060) Register Acronym ITCN_IPR0 ITCN_IPR1 ITCN_IPR2 ITCN_IPR3 ITCN_IPR4 ITCN_VBA ITCN_FIM0 ITCN_FIVAL0 ITCN_FIVAH0 ITCN_FIM1 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 Register Description Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Vector Base Address Register Fast Interrupt Match 0 Register Fast Interrupt Vector Address Low 0 Register Fast Interrupt Vector Address High 0 Register Fast Interrupt Match 1 Register 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 37 Table 4-11 Interrupt Control Registers Address Map (Continued) (ITCN_BASE = $00 F060) Register Acronym ITCN_FIVAL1 ITCN_FIVAH1 ITCN_IRQP0 ITCN_IRQP1 ITCN_IRQP2 ITCN_ICTRL Address Offset $A $B $C $D $E $12 Register Description Fast Interrupt Vector Address Low 1 Register Fast Interrupt Vector Address High 1 Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 Reserved Interrupt Control Register Reserved Table 4-12 Analog-to-Digital Converter Registers Address Map (ADC_BASE = $00 F080) Register Acronym ADC_CTRL1 ADC_CTRL2 ADC_ZXCTRL ADC_CLIST 1 ADC_CLIST 2 ADC_SDIS ADC_STAT ADC_LIMSTAT ADC_ZXSTAT ADC_RSLT0 ADC_RSLT1 ADC_RSLT2 ADC_RSLT3 ADC_RSLT4 ADC_RSLT5 ADC_RSLT6 ADC_RSLT7 ADC_LOLIM0 ADC_LOLIM1 ADC_LOLIM2 ADC_LOLIM3 ADC_LOLIM4 ADC_LOLIM5 ADC_LOLIM6 ADC_LOLIM7 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 Register Description Control Register 1 Control Register 2 Zero Crossing Control Register Channel List Register 1 Channel List Register 2 Sample Disable Register Status Register Limit Status Register Zero Crossing Status Register Result Register 0 Result Register 1 Result Register 2 Result Register 3 Result Register 4 Result Register 5 Result Register 6 Result Register 7 Low Limit Register 0 Low Limit Register 1 Low Limit Register 2 Low Limit Register 3 Low Limit Register 4 Low Limit Register 5 Low Limit Register 6 Low Limit Register 7 56F8013/56F8011 Data Sheet, Rev. 10 38 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-12 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080) Register Acronym ADC_HILIM0 ADC_HILIM1 ADC_HILIM2 ADC_HILIM3 ADC_HILIM4 ADC_HILIM5 ADC_HILIM6 ADC_HILIM7 ADC_OFFST0 ADC_OFFST1 ADC_OFFST2 ADC_OFFST3 ADC_OFFST4 ADC_OFFST5 ADC_OFFST6 ADC_OFFST7 ADC_PWR ADC_VREF Address Offset $19 $1A $1B $1C $1D $1E $1F $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Register Description High Limit Register 0 High Limit Register 1 High Limit Register 2 High Limit Register 3 High Limit Register 4 High Limit Register 5 High Limit Register 6 High Limit Register 7 Offset Register 0 Offset Register 1 Offset Register 2 Offset Register 3 Offset Register 4 Offset Register 5 Offset Register 6 Offset Register 7 Power Control Register Voltage Reference Register Reserved Table 4-13 Serial Communication Interface Registers Address Map (SCI_BASE = $00 F0B0) Register Acronym SCI_RATE SCI_CTRL1 SCI_CTRL2 SCI_STAT SCI_DATA Address Offset $0 $1 $2 $3 $4 Register Description Baud Rate Register Control Register 1 Control Register 2 Status Register Data Register Table 4-14 Serial Peripheral Interface Registers Address Map (SPI_BASE = $00 F0C0) Register Acronym SPI_SCTRL SPI_DSCTRL SPI_DRCV SPI_DXMIT Address Offset $0 $1 $2 $3 Register Description Status and Control Register Data Size and ControlRegister Data Receive Register Data Transmit Register 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 39 Table 4-15 I2C Registers Address Map (I2C_BASE = $00 F0D0) Register Acronym I2C_ADDR I2C_FDIV I2C_CTRL I2C_STAT I2C_DATA I2C_NFILT Address Offset $0 $1 $2 $3 $4 $5 Register Description Address Register Frequency Divider Register Control Register Status Register Data I/O Register Noise Filter Register Table 4-16 Computer Operating Properly Registers Address Map (COP_BASE = $00 F0E0) Register Acronym COP_CTRL COP_TOUT COP_CNTR Address Offset $0 $1 $2 Control Register Time-Out Register Counter Register Register Description Table 4-17 Clock Generation Module Registers Address Map (OCCS_BASE = $00 F0F0) Register Acronym OCCS_CTRL OCCS_DIVBY OCCS_STAT OCCS_SHUTDN OCCS_OCTRL Address Offset $0 $1 $2 $4 $5 Control Register Divide-By Register Status Register Reserved Shutdown Register Oscillator Control Register Register Description 56F8013/56F8011 Data Sheet, Rev. 10 40 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-18 GPIOA Registers Address Map (GPIOA_BASE = $00 F100) Register Acronym GPIOA_PUPEN GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Edge Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Output Mode Control Register Raw Data Register Drive Strength Control Register Table 4-19 GPIOB Registers Address Map (GPIOB_BASE = $00 F110) Register Acronym GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT GPIOB_IEN GPIOB_IEPOL GPIOB_IPEND GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Edge Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Output Mode Control Register Raw Data Register Drive Strength Control Register 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 41 Table 4-20 GPIOC Registers Address Map (GPIOC_BASE = $00 F120) Register Acronym GPIOC_PUPEN GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IEPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Edge Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Output Mode Control Register Raw Data Register Drive Strength Control Register Table 4-21 GPIOD Registers Address Map (GPIOD_BASE = $00 F130) Register Acronym GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN GPIOD_IEPOL GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Edge Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Output Mode Control Register Raw Data Register Drive Strength Control Register 56F8013/56F8011 Data Sheet, Rev. 10 42 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-22 System Integration Module Registers Address Map (SIM_BASE = $00 F140) Register Acronym SIM_CTRL SIM_RSTAT SIM_SWC0 SIM_SWC1 SIM_SWC2 SIM_SWC3 SIM_MSHID SIM_LSHID SIM_PWR SIM_CLKOUT SIM_GPS SIM_PCE SIM_IOSAHI SIM_IOSALO Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $A $B $C $D $E Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half JTAG ID Least Significant Half JTAG ID Power Control Register Reserved Clock Out Select Register GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register Register Description Table 4-23 Power Supervisor Registers Address Map (PS_BASE = $00 F160) Register Acronym PS_CTRL PS_STAT Address Offset $0 $1 Control Register Status Register Register Description Table 4-24 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym FM_CLKDIV FM_CNFG FM_SECHI FM_SECLO FM_PROT FM_USTAT Address Offset $0 $1 $2 $3 $4 $5 - $9 $10 $11 - $12 $13 Register Description Clock Divider Register Configuration Register Reserved Security High Half Register Security Low Half Register Reserved Protection Register Reserved User Status Register 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 43 Table 4-24 Flash Module Registers Address Map (Continued) (FM_BASE = $00 F400) Register Acronym FM_CMD Address Offset $14 $15 $16 $17 FM_DATA $18 $19 $1A FM_OPT1 FM_TSTSIG $1B $1D Reserved Reserved Reserved Data Buffer Register Reserved Reserved Optional Data 1 Register Reserved Test Array Signature Register Register Description Command Register Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt. 5.2 Features The ITCN module design includes these distinctive features: • • • • Programmable priority levels for each IRQ Two programmable Fast Interrupts Notification to SIM module to restart clocks out of Wait and Stop modes Ability to drive initial address on the address bus after reset For further information, see Table 4-2, Interrupt Vector Table Contents. 5.3 Functional Description The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 46 interrupt sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority and number 45 is the lowest. 56F8013/56F8011 Data Sheet, Rev. 10 44 Freescale Semiconductor Preliminary Functional Description 5.3.1 Normal Interrupt Handling Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base Address (VBA) and the vector number to determine the vector address, generating an offset into the vector table for each interrupt. 5.3.2 Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following table defines the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition SR[9] 0 0 1 1 SR[8] 0 1 0 1 Exceptions Permitted Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3 Exceptions Masked None Priority 0 Priorities 0, 1 Priorities 0, 1, 2 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes Fast Interrupts before the core does. A Fast Interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIMn register to the appropriate vector number 3. Setting the FIVALn and FIVAHn registers with the address of the code for the Fast Interrupt When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts its Fast Interrupt handling. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 45 5.4 Block Diagram Priority Level any0 Level 0 46 -> 6 Priority Encoder 6 INT0 2 -> 4 Decode INT VAB CONTROL IPIC any3 Level 3 Priority Level 46 -> 6 Priority Encoder IACK SR[9:8] 6 PIC_EN INT45 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. 56F8013/56F8011 Data Sheet, Rev. 10 46 Freescale Semiconductor Preliminary Register Descriptions 5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN module has 16 registers. Table 5-2 ITCN Register Summary (ITCN_BASE = $00 F060) Register Acronym IPR0 IPR1 IPR2 IPR3 IPR4 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 Base Address + $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Vector Base Address Register Fast Interrupt Match 0 Register Fast Interrupt 0 Vector Address Low Register Fast Interrupt 0 Vector Address High 0 Register Fast Interrupt Match 1 Register Fast Interrupt 1 Vector Address Low Register Fast Interrupt 1 Vector Address High Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 Reserved ICTRL $12 Interrupt Control Register Reserved 5.6.16 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 47 Add. Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E Register Name IPR0 IPR1 IPR2 IPR3 IPR4 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 0 12 0 11 0 10 0 9 8 7 6 5 4 3 2 1 0 LVI IPL GPIOB IPL SCI_RCV IPL ADCA_CC IPL 0 0 0 0 0 0 RX_REG IPL 0 0 TX_REG IPL FM_CBE IPL SCI_XMIT IPL TMR_0 IPL PWM_F IPL TRBUF IPL FM_CC IPL SPI_XMIT IPL I2C_ADDR IPL PWM_RL IPL BKPT_U IPL FM_ERR IPL SPI_RCV IPL 0 0 STPCNT IPL PLL IPL GPIOA IPL 0 0 GPIOC IPL SCI_RERR IPL TMR_3 IPL 0 0 GPIOD IPL 0 0 SCI_TIDL IPL TMR_1 IPL 0 0 TMR_2 IPL 0 0 ADC_ZC_LE IPL ADCB_CC IPL VECTOR_BASE_ADDRESS 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT 1 FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH 1 PENDING[16:2] PENDING[32:17] 1 1 1 PENDING[45:33] $12 ICTRL Reserved INT IPIC VAB INT_ DIS 1 1 1 0 0 = Reserved Figure 5-2 ITCN Register Map Summary 5.6.1 Interrupt Priority Register 0 (IPR0) 15 14 13 0 0 Base + $0 Read Write RESET 12 0 0 11 0 0 10 0 0 9 8 7 6 5 4 3 2 1 0 LVI IPL 0 0 RX_REG IPL 0 0 TX_REG IPL 0 0 TRBUF IPL 0 0 BKPT_U IPL 0 0 STPCNT IPL 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 56F8013/56F8011 Data Sheet, Rev. 10 48 Freescale Semiconductor Preliminary Register Descriptions 5.6.1.1 LVI IPL—Bits 15–14 This field is used to set the interrupt priority levels for a peripheral IRQ. This IRQ is limited to priorities 0 through 2 and is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.1.2 5.6.1.3 Reserved—Bits 13–10 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)— Bits 9–8 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.4 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.5 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 49 5.6.1.6 EOnCE Breakpoint Unit Interrupt Priority Level (BKPT_U IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.7 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $1 Read Write RESET 15 14 13 12 11 10 9 0 0 8 0 0 7 6 5 4 3 2 1 0 GPIOB IPL 0 0 GPIOC IPL 0 0 GPIOD IPL 0 0 FM_CBE IPL 0 0 FM_CC IPL 0 0 FM_ERR IPL 0 0 PLL IPL 0 0 Figure 5-4 Interrupt Priority Register 1 (IPR1) 5.6.2.1 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.2 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8013/56F8011 Data Sheet, Rev. 10 50 Freescale Semiconductor Preliminary Register Descriptions 5.6.2.3 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.4 5.6.2.5 Reserved—Bits 9–8 FM Command, Data, Address Buffers Empty Interrupt Priority Level (FM_CBE IPL)—Bits 7–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.6 FM Command Complete Priority Level (FM_CC IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.7 FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 51 5.6.2.8 PLL Loss of Reference or Change in Lock Status Interrupt Priority Level (PLL IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3 Interrupt Priority Register 2 (IPR2) 15 14 13 12 11 0 0 Base + $2 Read Write RESET 10 0 0 9 8 7 6 5 4 3 2 1 0 SCI_RCV IPL 0 0 SCI_RERR IPL 0 0 SCI_TIDL IPL 0 0 SCI_XMIT IPL SPI_XMIT IPL 0 0 0 0 SPI_RCV IPL 0 0 GPIOA IPL 0 0 Figure 5-5 Interrupt Priority Register 2 (IPR2) 5.6.3.1 SCI Receiver Full Interrupt Priority Level (SCI_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.2 SCI Receiver Error Interrupt Priority Level (SCI_RERR IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.3 Reserved—Bits 11–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F8013/56F8011 Data Sheet, Rev. 10 52 Freescale Semiconductor Preliminary Register Descriptions 5.6.3.4 SCI Transmitter Idle Interrupt Priority Level (SCI_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.5 SCI Transmitter Empty Interrupt Priority Level (SCI_XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.6 SPI Transmitter Empty Interrupt Priority Level (SPI_XMIT IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.7 SPI Receiver Full Interrupt Priority Level (SPI_RCV IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 53 5.6.3.8 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $3 Read Write RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 2 0 0 1 0 0 0 0 0 ADCA_CC IPL 0 0 TMR_3 IPL 0 0 TMR_2 IPL 0 0 TMR_1 IPL 0 0 TMR_0 IPL 0 0 I2C_ADDR IPL 0 0 Figure 5-6 Interrupt Priority Register 3 (IPR3) 5.6.4.1 ADCA Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.2 Timer Channel 3 Interrupt Priority Level (TMR_3 IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.3 Timer Channel 2 Interrupt Priority Level (TMR_2 IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8013/56F8011 Data Sheet, Rev. 10 54 Freescale Semiconductor Preliminary Register Descriptions 5.6.4.4 Timer Channel 1 Interrupt Priority Level (TMR_1 IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.5 Timer Channel 0 Interrupt Priority Level (TMR_0 IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.6 I2C Address Detect Interrupt Priority Level (I2C_ADDR IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.7 Reserved—Bits 3–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.5 Interrupt Priority Register 4 (IPR4) 15 0 0 Base + $4 Read Write RESET 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 6 5 4 3 2 1 0 PWM_F IPL 0 0 PWM_RL IPL 0 0 ADC_ZC_LE IPL 0 0 ADCB_CC IPL 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 Reserved—Bits 15–8 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 55 5.6.5.2 PWM Fault Interrupt Priority Level (PWM_F IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.3 Reload PWM Interrupt Priority Level (PWM_RL IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.4 ADC Zero Crossing or Limit Error Interrupt Priority Level (ADC_ZC_LE IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.5 ADCB Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8013/56F8011 Data Sheet, Rev. 10 56 Freescale Semiconductor Preliminary Register Descriptions 5.6.6 Vector Base Address Register (VBA) 15 0 0 Base + $5 Read Write RESET 14 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VECTOR_BASE_ADDRESS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-8 Vector Base Address Register (VBA) 5.6.6.1 5.6.6.2 Reserved—Bits 15–14 Vector Address Bus (VAB) Bits 13—0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits are determined based on the highest priority interrupt and are then appended onto VBA before presenting the full VAB to the Core. 5.6.7 Fast Interrupt Match 0 Register (FIM0) 15 0 0 Base + $6 Read Write RESET 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 4 3 2 1 0 FAST INTERRUPT 0 0 0 0 0 0 0 Figure 5-9 Fast Interrupt Match 0 Register (FIM0) 5.6.7.1 5.6.7.2 Reserved—Bits 15–6 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 5–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. These values determine which IRQ will be Fast Interrupt 0. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 57 5.6.8 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write RESET 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 Base + $7 Figure 5-10 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.8.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15—0 The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 5.6.9 Fast Interrupt 0 Vector Address High Register (FIVAH0) 15 0 0 Base + $8 Read Write RESET 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 3 2 1 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH 0 0 0 0 0 Figure 5-11 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.9.1 5.6.9.2 Reserved—Bits 15–5 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 5.6.10 Fast Interrupt 1 Match Register (FIM1) 15 0 0 Base + $9 Read Write RESET 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 4 3 2 1 0 FAST INTERRUPT 1 0 0 0 0 0 0 Figure 5-12 Fast Interrupt 1 Match Register (FIM1) 5.6.10.1 5.6.10.2 Reserved—Bits 15–6 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast 56F8013/56F8011 Data Sheet, Rev. 10 58 Freescale Semiconductor Preliminary Register Descriptions Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table. 5.6.11 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Base + $A RESET Figure 5-13 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 5.6.11.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.12 Fast Interrupt 1 Vector Address High (FIVAH1) 15 0 0 Base + $B Read Write RESET 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 3 2 1 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH 0 0 0 0 0 Figure 5-14 Fast Interrupt 1 Vector Address High Register (FIVAH1) 5.6.12.1 5.6.12.2 Reserved—Bits 15–5 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.13 IRQ Pending Register 0 (IRQP0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 Base + $C Read Write RESET PENDING[16:2] 1 1 1 1 1 1 1 1 1 Figure 5-15 IRQ Pending Register 0 (IRQP0) 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 59 5.6.13.1 IRQ Pending (PENDING)—Bits 15–1 This register combines with IRQP1 and IRQP2 to represent the pending IRQs for interrupt vector numbers 2 through 45. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.13.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.14 IRQ Pending Register 1 (IRQP1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write PENDING[32:17] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Base + $D RESET Figure 5-16 IRQ Pending Register 1 (IRQP1) 5.6.14.1 IRQ Pending (PENDING)—Bits 32–17 This register combines with IRQP0 and IRQP2 to represent the pending IRQs for interrupt vector numbers 2 through 45. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.15 IRQ Pending Register 2 (IRQP2) 15 1 1 Base + $E Read Write RESET 14 1 1 13 1 1 12 11 10 9 8 7 6 5 4 3 2 1 0 PENDING[45:33] 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-17 IRQ Pending Register 2 (IRQP2) 5.6.15.1 IRQ Pending (PENDING)—Bits 45–33 This register combines with IRQP0 and IRQP1 to represent the pending IRQs for interrupt vector numbers 2 through 45. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 56F8013/56F8011 Data Sheet, Rev. 10 60 Freescale Semiconductor Preliminary Register Descriptions 5.6.16 Interrupt Control Register (ICTRL) 15 INT 0 0 $Base + $12 Read Write RESET 14 IPIC 13 12 11 10 9 VAB 8 7 6 5 INT_ DIS 4 1 1 3 1 1 2 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-18 Interrupt Control Register (ICTRL) 5.6.16.1 • • Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core 5.6.16.2 Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: • • • • Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 00 = Required nested exception priority levels are 0, 1, 2, or 3 01 = Required nested exception priority levels are 1, 2, or 3 10 = Required nested exception priority levels are 2 or 3 11 = Required nested exception priority level is 3 Table 5-3 Interrupt Priority Encoding IPIC_VALUE[1:0] 00 01 10 11 Current Interrupt Priority Level No interrupt or SWILP Priority 0 Priority 1 Priority 2 or 3 Required Nested Exception Priority Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3 5.6.16.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows the vector number (VAB[6:0]) used at the time the last IRQ was taken. In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 61 5.6.16.4 • • Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled. 0 = Normal operation (default) 1 = All interrupts disabled 5.6.16.5 5.6.16.6 Reserved—Bits 4–2 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.7 Resets 5.7.1 General Table 5-4 Reset Summary Reset Core Reset Priority Source RST Characteristics Core reset from the SIM 5.7.2 5.7.2.1 Description of Reset Operation Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET is released. The general timing is shown in Figure 5-19. RES CLK VAB PAB RESET_VECTOR_ADR READ_ADR Figure 5-19 Reset Interface 56F8013/56F8011 Data Sheet, Rev. 10 62 Freescale Semiconductor Preliminary Introduction 5.7.3 ITCN After Reset After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities: • • • • • • • • Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 SW Interrupt LP These interrupts are enabled at their fixed priority levels. Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The System Integration Module is responsible for the following functions: • • • • • • • • Reset sequencing Clock control & distribution Stop/Wait control System status registers Registers for software access to the JTAG ID of the chip Test registers Power control I/O pad multiplexing These are discussed in more detail in the sections that follow. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 63 6.2 Features The SIM has the following features: • • System bus clocks with pipeline hold-off support System clocks for non-pipelined interfaces • • • • Peripheral clocks for TMR and PWM with high-speed (3X) option Power-saving clock gating for peripherals ITCK clock to the 56800E core TAP interface Three power modes (Run, Wait, Stop) to control power utilization — Stop mode shuts down the 56800E core, system clock, and peripheral clock — Wait mode shuts down the 56800E core and unnecessary system clock operation — Run mode supports full part operation Controls, with write protection, the enable/disable of 56800E core WAIT and STOP instructions Controls, with write protection, the enable/disable of Large Regulator Standby mode Controls to route functional signals to selected peripherals and I/O pads Controls deassertion sequence of internal resets Software-initiated reset Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control Timer channel Stop mode clocking controls SCI Stop mode clocking control to support LIN Sleep mode stop recovery Short addressing location control • • • • • • • • • • • Registers for software access to the JTAG ID of the chip Controls output to CLKO pin 56F8013/56F8011 Data Sheet, Rev. 10 64 Freescale Semiconductor Preliminary Register Descriptions 6.3 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F140) Address Offset Base + $0 Base + $1 Base + $2 Base + $3 Base + $4 Base + $5 Base + $6 Base + $7 Base + $8 Address Acronym SIM_CTRL SIM_RSTAT SIM_SWC0 SIM_SWC1 SIM_SWC2 SIM_SWC3 SIM_MSHID SIM_LSHID SIM_PWR Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID Least Significant Half of JTAG ID Power Control Register Reserved Base + $A Base + $B Base + $C Base + $D Base + $E SIM_CLKOUT SIM_GPS SIM_PCE SIM_IOSAHI SIM_IOSALO CLKO Select Register GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register 6.3.7 6.3.8 6.3.9 6.3.10 6.3.10 Section Location 6.3.1 6.3.2 6.3.3 6.3.3 6.3.3 6.3.3 6.3.4 6.3.5 6.3.6 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 65 Add. Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 Address Acronym SIM_ CTRL SIM_ RSTAT SIM_SWC0 SIM_SWC1 SIM_SWC2 SIM_SWC3 SIM_MSHID SIM_LSHID SIM_PWR Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 TC3_ SD 0 14 TC2_ SD 0 13 TC1_ SD 0 12 TC0_ SD 0 11 SCI_ SD 0 10 0 0 9 TC3_ INP 0 8 0 0 7 0 0 6 0 0 5 ONCE EBL0 SWR 4 SW RST 3 2 1 0 STOP_ DISABLE POR WAIT_ DISABLE 0 0 COPR EXTR Software Control Data 0 Software Control Data 1 Software Control Data 2 Software Control Data 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 LRSTDBY $A $B $C $D $E SIM_ CLKOUT SIM_GPS SIM_PCE SIM_IOSAHI SIM_IOSALO 0 0 0 0 0 0 0 0 0 CFG_ B7 0 0 0 PWM3 PWM2 PWM1 PWM0 CFG_ B3 0 0 CFG_ B2 TMR 0 CLK DIS CFG_ B1 0 0 CFG_ B0 SCI 0 CLKOSEL CFG_A5 0 0 SPI 0 CFG_A4 0 PWM TCR I2C 0 PCR 0 0 CFG_ CFG_ CFG_ B6 B5 B4 0 0 0 0 0 0 ADC 0 ISAL[23:22] ISAL[21:6] 0 = Read as 0 = Reserved 1 = Read as 1 = Reserved Figure 6-1 SIM Register Map Summary 6.3.1 SIM Control Register (SIM_CTRL) 15 TC3_ SD 0 Base + $0 Read Write RESET 14 TC2_ SD 0 13 TC1_ SD 0 12 TC0_ SD 0 11 SCI_ SD 0 10 0 0 9 TC3_ INP 0 8 0 0 7 0 0 6 0 0 5 ONCE EBL 0 4 SW RST 0 3 2 1 0 STOP_ DISABLE 0 0 WAIT_ DISABLE 0 0 Figure 6-2 SIM Control Register (SIM_CTRL) 6.3.1.1 • • Timer Channel 3 Stop Disable (TC3_SD)—Bit 15 This bit enables the operation of the Timer Channel 3 peripheral clock in Stop mode. 0 = Timer Channel 3 disabled in Stop mode 1 = Timer Channel 3 enabled in Stop mode 56F8013/56F8011 Data Sheet, Rev. 10 66 Freescale Semiconductor Preliminary Register Descriptions 6.3.1.2 • • Timer Channel 2 Stop Disable (TC2_SD)—Bit 14 This bit enables the operation of the Timer Channel 2 peripheral clock in Stop mode. 0 = Timer Channel 2 disabled in Stop mode 1 = Timer Channel 2 enabled in Stop mode 6.3.1.3 • • Timer Channel 1 Stop Disable (TC1_SD)—Bit 13 This bit enables the operation of the Timer Channel 1 peripheral clock in Stop mode. 0 = Timer Channel 1 disabled in Stop mode 1 = Timer Channel 1 enabled in Stop mode 6.3.1.4 • • Timer Channel 0 Stop Disable (TC0_SD)—Bit 12 This bit enables the operation of the Timer Channel 0 peripheral clock in Stop mode. 0 = Timer Channel 0 disabled in Stop mode 1 = Timer Channel 0 enabled in Stop mode 6.3.1.5 SCI Stop Disable (SCI_SD)—Bit 11 This bit enables the operation of the SCI peripheral clock in Stop mode. This is recommended for use in LIN mode so that the SCI can generate interrupts and recover from Stop mode while the LIN interface is in Sleep mode and using Stop mode to reduce power consumption. • • 0 = SCI disabled in Stop mode 1 = SCI enabled in Stop mode 6.3.1.6 6.3.1.7 • • Reserved—Bit 10 Timer Channel 3 Input (TC3_INP)—Bit 9 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This bit selects the input of Timer Channel 3 to be from the PWM or GPIO. 1 = Timer Channel 3 Input from PWM reload_sync signal 0 = Timer Channel 3 Input controlled by SIM_GPS register CFG_B3 and CFG_A5 fields 6.3.1.8 6.3.1.9 • • Reserved—Bits 8–6 OnCE Enable (ONCEEBL)—Bit 5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 0 = OnCE clock to 56800E core enabled when core TAP is enabled 1 = OnCE clock to 56800E core is always enabled 6.3.1.10 Software Reset (SWRST)—Bit 4 Writing 1 to this field will cause the part to reset. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 67 6.3.1.11 • • • • Stop Disable (STOP_DISABLE[1:0])—Bits 3–2 00 = Stop mode will be entered when the 56800E core executes a STOP instruction 01 = The 56800E STOP instruction will not cause entry into Stop mode 10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the STOP_DISABLE field is write-protected until the next reset 11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is write-protected until the next reset 6.3.1.12 • • • • Wait Disable (WAIT_DISABLE[1:0])—Bits 1–0 00 = Wait mode will be entered when the 56800E core executes a WAIT instruction 01 = The 56800E WAIT instruction will not cause entry into Wait mode 10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the WAIT_DISABLE field is write-protected until the next reset 11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is write-protected until the next reset 6.3.2 SIM Reset Status Register (SIM_RSTAT) This register is updated upon any system reset and indicates the cause of the most recent reset. It also controls whether the COP reset vector or regular reset vector in the vector table is used. This register is asynchronously reset during Power-On Reset (see power supervisor module) and subsequently is synchronously updated based on the level of the external reset, software reset, or cop reset inputs. Only one source will ever be indicated. In the event that multiple reset sources assert simultaneously, the highest-precedence source will be indicated. The precedence from highest to lowest is POR, EXTR, COPR, and SWR. While POR is always set during a Power-On Reset, EXTR will become set if the external reset pin is asserted or remains asserted after the Power-On Reset (POR) has deasserted. Base + $1 Read Write RESET 0 0 0 0 0 0 0 0 0 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 SWR 4 COPR 3 EXTR 2 POR 1 0 0 0 0 0 Figure 6-3 SIM Reset Status Register (SIM_RSTAT) 6.3.2.1 6.3.2.2 Reserved—Bits 15–6 Software Reset (SWR)—Bit 5 This bit field is reserved or not implemented. It is read as zero and cannot be modified by writing. When set, this bit indicates that the previous system reset occurred as a result of a software reset (written 1 to SWRST bit in the SIM_CTRL register). It will not be set if a COP, external, or POR reset also occurred. 6.3.2.3 COP Reset (COPR)—Bit 4 When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly (COP) timer. It will not be set if an external or POR reset also occurred. If COPR is set as code starts executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used. 56F8013/56F8011 Data Sheet, Rev. 10 68 Freescale Semiconductor Preliminary Register Descriptions 6.3.2.4 External Reset (EXTR)—Bit 3 When set, this bit indicates that the previous system reset was caused by an external reset. It will only be set if the external reset pin was asserted or remained asserted after the Power-On Reset deasserted. 6.3.2.5 6.3.2.6 Power-On Reset (POR)—Bit 2 Reserved—Bits 1–0 This bit is set during a Power-On Reset. This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3) Only SIM_SWC0 is shown in this section. SIM_SWC1, SIM_SWC2, and SIM_SWC3 are identical in functionality. Base + $2 Read Write RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Software Control Data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-4 SIM Software Control Register 0 (SIM_SWC0) 6.3.3.1 Software Control Data 0 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (RESET pin, software reset, and COP reset). 6.3.4 Most Significant Half of JTAG ID (SIM_MSHID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F2. Base + $6 Read Write RESET 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 0 0 2 0 0 1 1 1 0 0 0 Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID) 6.3.5 Least Significant Half of JTAG ID (SIM_LSHID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $401D. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 69 Base + $7 Read Write RESET 15 0 0 14 1 1 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 1 1 3 1 1 2 1 1 1 0 0 0 1 1 Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID) 6.3.6 SIM Power Control Register (SIM_PWR) This register controls the Standby mode of the large regulator. The large regulator derives the core digital logic power supply from the IO power supply. In some circumstances, the large regulator may be put in a reduced-power Standby mode without interfering with part operation. Refer to the overview of power-down modes and the overview of clock generation for more information on the use of large regulator standby. Base + $8 Read Write RESET 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 LRSTDBY 0 0 Figure 6-7 SIM Power Control Register (SIM_PWR) 6.3.6.1 6.3.6.2 • • • • This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This bit controls the pull-up resistors on the IRQA pin. Reserved—Bits 15–2 Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0 00 = Large regulator is in Normal mode 01 = Large regulator is in Standby (reduced-power) mode 10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset 11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset 6.3.7 CLKO Select Register (SIM_CLKOUT) The CLKO select register can be used to multiplex out selected clocks generated inside the clock generation and SIM modules. All functionality is for test purposes only and is subject to unspecified latencies. Glitches may be produced when the clock is enabled or switched. The lower four bits of the GPIO A register can function as GPIO, PWM, or as additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOA_PEREN. If GPIOA[3:0] are programmed to operate as peripheral outputs, then the choice between PWM and additional clock outputs is done here in the CLKOUT. The default state is for the peripheral function of GPIOA[3:0] to be programmed as PWM. This can be changed by altering PWM3 through PWM0. 56F8013/56F8011 Data Sheet, Rev. 10 70 Freescale Semiconductor Preliminary Register Descriptions Base + $A Read Write RESET 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 PWM3 0 8 PWM2 0 7 6 5 CLK DIS 1 4 3 2 CLKOSEL 1 0 PWM1 PWM0 0 0 0 0 0 0 0 Figure 6-8 CLKO Select Register (SIM_CLKOUT) 6.3.7.1 6.3.7.2 • • Reserved—Bits 15–10 PWM3—Bit 9 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 0 = Peripheral output function of GPIOA[3] is defined to be PWM3 1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock 6.3.7.3 • • PWM2—Bit 8 0 = Peripheral output function of GPIOA[2] is defined to be PWM2 1 = Peripheral output function of GPIOA[2] is defined to be the system clock 6.3.7.4 • • PWM1—Bit 7 0 = Peripheral output function of GPIOA[1] is defined to be PWM1 1 = Peripheral output function of GPIOA[1] is defined to be two times the rate of the system clock 6.3.7.5 • • PWM0—Bit 6 0 = Peripheral output function of GPIOA[0] is defined to be PWM0 1 = Peripheral output function of GPIOA[0] is defined to be three times the rate of the system clock 6.3.7.6 • • Clockout Disable (CLKDIS)—Bit 5 0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL 1 = CLKOUT is 0 6.3.7.7 • • • • • • • Clockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO pin. 00000 = Reserved for factory test—Continuous system clock 01001 = Reserved for factory test—OCCS MSTR OSC clock 01011 = Reserved for factory test—ADC clock 01100 = Reserved for factory test—JTAG TCLK 01101 = Reserved for factory test—Continuous peripheral clock 01110 = Reserved for factory test—Continuous inverted peripheral clock 01111 = Reserved for factory test—Continuous high-speed peripheral clock 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 71 6.3.8 SIM GPIO Peripheral Select Register (SIM_GPS) All of the peripheral pins on the 56F8013/56F8011 share their Input/Output (I/O) with GPIO ports. In order to select peripheral or GPIO control, program the GPIOx_PEREN register. In some cases, there are two possible peripherals as well as the GPIO functionality available for control of the I/O. In these cases, the SIM_GPS register is used to determine which peripheral has control. As shown in Figure 6-9, the GPIO Peripheral Enable Register (PEREN) has the final control over which pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when PEREN = 1. GPIOB_PEREN Register GPIO Controlled 0 I/O Pad Control 1 SIM_GPS Register Quad Timer Controlled 0 SCI Controlled 1 Figure 6-9 Overall Control of Pads Using SIM_GPS Control Base + $B Read Write RESET 15 TCR 0 14 PCR 0 13 0 0 12 0 0 11 CFG_ B7 0 10 CFG_ B6 0 9 CFG_ B5 0 8 CFG_ B4 0 7 CFG_ B3 0 6 CFG_ B2 0 5 CFG_ B1 0 4 CFG_ B0 0 3 2 1 0 CFG_A5 0 0 CFG_A4 0 0 Figure 6-10 GPIO Peripheral Select Register (SIM_GPS) 6.3.8.1 • • TMR Clock Rate (TCR)—Bit 15 This bit selects the clock speed for the TMR module. 0 = TMR module clock rate equals core clock rate, typically 32MHz (default) 1 = TMR module clock rate equals three times core clock rate Note: This bit should only be changed while the TMR module’s clock is disabled. See Section 6.3.9. Note: High-speed clocking is only available when the PLL is being used. Note: If the PWM reload pulse is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section 6.3.1.7), then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2. 56F8013/56F8011 Data Sheet, Rev. 10 72 Freescale Semiconductor Preliminary Register Descriptions 6.3.8.2 • • PWM Clock Rate (PCR)—Bit 14 This bit selects the clock speed for the PWM module. 0 = PWM module clock rate equals core clock rate, typically 32MHz (default) 1 = PWM module clock rate equals three times core clock rate Note: This bit should only be changed while the PWM module’s clock is disabled. See Section 6.3.9. Note: High-speed clocking is only available when the PLL is being used. Note: If the PWM reload pulse is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section 6.3.1.7), then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2. Table 6-2 Allowable Quad Timer and PWM Clock Rates when Using PWM Reload Pulse Quad Timer Clock Speed PWM 1X 3X 1X OK NO 3X OK OK 6.3.8.3 Reserved—Bits 13–12 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. Note: Take care when programming the following CFG_* signals so as not to connect two different I/O pads to the same peripheral input. For example, do not set CFG_B7 to select SCL and also set CFG_B0 to select SCL. If this occurs for an output signal, then the signal will be routed to two I/O pads. For input signals, the values on the two I/O pads will be ORed together before reaching the peripheral. 6.3.8.4 • • Configure GPIOB7 (CFG_B7)—Bit 11 This bit selects the alternate function for GPIOB7. 0 = TXD (default) 1 = SCL 6.3.8.5 • • Configure GPIOB6 (CFG_B6)—Bit 10 This bit selects the alternate function for GPIOB6. 0 = RXD (default) 1 = SDA Note: The CLKMODE bit in the OCCS Oscillator Control register can enable this pin as the source clock to the chip. In this mode, make sure that no on-chip peripheral (including the GPIO) is driving this pin. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 73 6.3.8.6 • • Configure GPIOB5 (CFG_B5)—Bit 9 This bit selects the alternate function for GPIOB5. 0 = T1 (default) 1 = FAULT3 6.3.8.7 • • Configure GPIOB4 (CFG_B4)—Bit 8 This bit selects the alternate function for GPIOB4. 0 = T0 (default) 1 = CLKO 6.3.8.8 • • Configure GPIOB3 (CFG_B3)—Bit 7 This bit selects the alternate function for GPIOB3. 0 = MOSI (default) 1 = T3 6.3.8.9 • • Configure GPIOB2 (CFG_B2)—Bit 6 This bit selects the alternate function for GPIOB2. 0 = MISO (default) 1 = T2 6.3.8.10 • • Configure GPIOB1 (CFG_B1)—Bit 5 This bit selects the alternate function for GPIOB1. 0 = SS (default) 1 = SDA 6.3.8.11 • • Configure GPIOB0 (CFG_B0)—Bit 4 This bit selects the alternate function for GPIOB0. 0 = SCLK (default) 1 = SCL 6.3.8.12 • • • • Configure GPIOA5[1:0] (CFG_A5)—Bits 3–2 These bits select the alternate function for GPIOA5. 00 = Select PWM5 when peripheral mode is enabled in GPIOA5 (default) 01 = Select PWM5 when peripheral mode is enabled in GPIOA5 10 = Select FAULT2 when peripheral mode is enabled in GPIOA5 11 = Select T3 when peripheral mode is enabled in GPIOA5 56F8013/56F8011 Data Sheet, Rev. 10 74 Freescale Semiconductor Preliminary Register Descriptions 6.3.8.13 • • • • Configure GPIOA4[1:0] (CFG_A4)—Bits 1–0 These bits select the alternate function for GPIOA4. 00 = Select PWM4 when peripheral mode is enabled in GPIOA4 (default) 01 = Select PWM4 when peripheral mode is enabled in GPIOA4 10 = Select FAULT1 when peripheral mode is enabled in GPIOA4 11 = Select T2 when peripheral mode is enabled in GPIOA4 6.3.9 Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip. The corresponding peripheral should itself be disabled while its clock is shut off. IPBus writes cannot be made to a module that has its clock disabled. Base + $C Read Write RESET 15 I2C 0 14 0 13 ADC 0 12 0 11 0 10 0 9 0 8 0 7 0 6 TMR 0 5 0 4 SCI 0 3 0 2 SPI 0 1 0 0 PWM 0 0 0 0 0 0 0 0 0 0 0 Figure 6-11 Peripheral Clock Enable Register (SIM_PCE) 6.3.9.1 • • I2C IPBus Clock Enable (I2C)—Bit 15 Each bit controls clocks to the indicated peripheral. 0 = The clock is not provided to the peripheral (the peripheral is disabled) 1 = Clocks are enabled 6.3.9.2 6.3.9.3 • • Reserved—Bit 14 Analog-to-Digital Converter IPBus Clock Enable (ADC)—Bit 13 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. Each bit controls clocks to the indicated peripheral. 0 = The clock is not provided to the peripheral (the peripheral is disabled) 1 = Clocks are enabled 6.3.9.4 6.3.9.5 • • Reserved—Bits 12–7 Timer IPBus Clock Enable (TMR)—Bit 6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. Each bit controls clocks to the indicated peripheral. 0 = The clock is not provided to the peripheral (the peripheral is disabled) 1 = Clocks are enabled 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 75 6.3.9.6 6.3.9.7 • • Reserved—Bit 5 SCI IPBus Clock Enable (SCI)—Bit 4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. Each bit controls clocks to the indicated peripheral. 0 = The clock is not provided to the peripheral (the peripheral is disabled) 1 = Clocks are enabled 6.3.9.8 6.3.9.9 • • Reserved—Bit 3 SPI IPBus Clock Enable (SPI)—Bit 2 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. Each bit controls clocks to the indicated peripheral. 0 = The clock is not provided to the peripheral (the peripheral is disabled) 1 = Clocks are enabled 6.3.9.10 6.3.9.11 • • Reserved—Bit 1 PWM IPBus Clock Enable (PWM)—Bit 0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. Each bit controls clocks to the indicated peripheral. 0 = The clock is not provided to the peripheral (the peripheral is disabled) 1 = Clocks are enabled 6.3.10 I/O Short Address Location Register (SIM_IOSAHI and SIM_IOSALO) The I/O Short Address Location registers are used to specify the memory referenced via the I/O short address mode. The I/O short address mode allows the instruction to specify the lower six bits of address; the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure 6-12. 56F8013/56F8011 Data Sheet, Rev. 10 76 Freescale Semiconductor Preliminary Register Descriptions “Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction Instruction Portion 16 Bits from SIM_IOSALO Register 2 bits from SIM_IOSAHI Register Full 24-Bit for Short I/O Address Figure 6-12 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_IOSALO register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents prior to returning from interrupt. Note: Note: The default value of this register set points to the EOnCE registers. The pipeline delay between setting this register set and using short I/O addressing with the new value is five instruction cycles. Base + $D Read Write RESET 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 ISAL[23:22] 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-13 I/O Short Address Location High Register (SIM_IOSAHI) 6.3.10.1 6.3.10.2 Reserved—Bits 15—2 Input/Output Short Address Location (ISAL[23:22])—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field represents the upper two address bits of the “hard coded” I/O short address. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 77 Base + $E Read Write RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISAL[21:6] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO) 6.3.10.3 Input/Output Short Address Location (ISAL[21:6])—Bits 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.4 Clock Generation Overview The SIM uses master clocks from the OCCS module to produce the peripheral and system (core and memory) clocks. The HS_PERF clock input from OCCS operates at three times the system and peripheral bus rate, or a maximum of 96MHz. The SYS_CLK_x2 clock input from OCCS operates at two times the system and peripheral bus rate, or a maximum of 64MHz. Peripheral and system clocks are generated at a maximum of 32MHz by dividing the SYS_CLK_x2 clock by two and gating it with appropriate power mode and clock gating controls. The PWM and TIMER peripheral clocks can optionally be generated at three times the normal rate at a maximum of 96MHz. These clocks are generated by gating the HS_PERF clock with appropriate power mode and clock gating controls. The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either an external clock or the relaxation oscillator can be selected as the master clock source (MSTR_OSC). When selected, the relaxation oscillator can be operated at full speed (8MHz), standby speed (400kHz using ROSB), or powered down (using ROPD). An 8MHz MSTR_OSC can be multiplied to 196MHz using the PLL and postscaled to provide a variety of high speed clock rates. Either the postscaled PLL output or MSTR_OSC signal can be selected to produce the master clocks to the SIM. When the PLL is not selected, the HS_PERF clock is disabled and the SYS_CLK_x2 clock is MSTR_OSC. In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL), and clock rate controls (TCR, PCR) to provide flexible control of clocking and power utilization. The SIM’s clock enable controls can be used to disable individual clocks when not needed. The clock rate controls enable the high speed clocking option for the Timer channels and PWM but require the PLL to be on and selected. Refer to the 56F801X Peripheral User Manual for further details. 6.5 Power-Down Modes The 56F8013/56F8011 operates in one of five Power-Down modes, as shown in Table 6-3. 56F8013/56F8011 Data Sheet, Rev. 10 78 Freescale Semiconductor Preliminary Power-Down Modes Table 6-3 Clock Operation in Power-Down Modes Mode Run Wait Core Clocks Core and memory clocks disabled Core and memory clocks disabled Peripheral Clocks Peripheral clocks enabled Peripheral clocks enabled Description Device is fully functional Core executes WAIT instruction to enter this mode. Typically used for power-conscious applications. Possible recoveries from Wait mode to Run mode are: 1. Any interrupt 2. Executing a Debug mode entry command during the 56800E core JTAG interface 2. Any reset (POR, external, software, COP) Core executes STOP instruction to enter this mode. Possible recoveries from Stop mode to Run mode are: 1. Interrupt from TMR channels that have been configured to operate in Stop mode (TCx_SD) 2. Interrupt for SCI configured to operate in Stop mode (SCI_SD) 3. Low-voltage interrupt 4. Executing a Debug mode entry command using the 56800E core JTAG interface 5. Any reset (POR, external, software, COP) The user configures the OCCS and SIM to select the relaxation oscillator clock source (PRECS), shut down the PLL (PLLPD), put the relaxation oscillator in Standby mode (ROSB), and put the large regulator in Standby (LRSTDBY). The part is fully operational, but operating at a minimum frequency and power configuration. Recovery requires reversing the sequence used to enter this mode (allowing for PLL lock time). The user configures the OCCS and SIM to enter Standby mode as shown in the previous description, followed by powering down the oscillator (ROPD). The only possible recoveries from this mode are: 1. External Reset 2. Power-On Reset Stop Master clock generation in the OCCS remains operational, but the SIM disables the generation of system and peripheral clocks. Standby The OCCS generates the SYS_CLK_x2 clock at a reduced frequency (400kHz). The PLL and HS_PERF clocks are disabled and the high-speed peripheral option is not available. System and peripheral clocks operate at 200kHz. Power-Down Master clock generation in the OCCS is completely shut down. All system and peripheral clocks are disabled. The power modes provide additional means to disable clock domains, configure the voltage regulator, and configure clock generation to manage power utilization, as shown in Table 6-3. Run, Wait, and Stop modes provide means of enabling/disabling the peripheral and/or core clocking as a group. Stop disable controls are provided for selected peripherals in the control register (SCI and TMR channels) so that these peripheral clocks can optionally continue to operate in Stop mode and generate interrupts which will return the part from Stop to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is possible to invoke Stop or Wait mode while in Standby mode for even greater levels of 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 79 power reduction. A 400kHz clock external clock can optionally be used in Standby mode to produce the required Standby 200kHz system bus rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully disables the part and minimizes its power utilization but is only recoverable via reset. When the PLL is not selected and the system bus is operating at 200kHz or less, the large regulator can be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator. All peripherals, except the COP/watchdog timer, run at the IPBus clock (peripheral bus) frequency1, which is the same as the main processor frequency in this architecture. The COP timer runs at MSTR_OSC / 1024. The maximum frequency of operation is SYS_CLK = 32MHz. The only exception is the TMR and PWM, which can be configured to operate at three times the system bus rate using TCR and PCR controls, provided the PLL is active and selected. 6.6 Resets The SIM supports four sources of reset, as shown in Figure 6-15. The two asynchronous sources are the external reset pin and the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1, and the COP reset. The SIM uses these to generate resets for the internal logic. These are outlined in Table 6-4. The first column lists the four primary resets which are calculated. The JTAG circuitry is reset by the Power-On Reset. Columns two through five indicate which reset sources trigger these reset signals. The last column provides additional detail. Table 6-4 Primary System Resets Reset Sources Reset Signal EXTENDED_POR POR X External Software COP Comments Stretched version of POR. Relevant 64 Relaxation Oscillator Clock cycles after POR deasserts. X X X Released 32 Relaxation Oscillator Clock cycles after all reset sources have released. Releases 32 Relaxation Oscillator Clock cycles after the CLKGEN_RST is released. Releases 32 SYS_CLK periods after PERIP_RST is released. CLKGEN_RST X PERIP_RST X X X X CORE_RST X X X X Figure 6-15 provides a graphic illustration of the details in Table 6-4. Note that the POR_Delay blocks use the Relaxation Oscillator Clock as their time base since other system clocks are inactive during this phase of reset. 1. The TMR ans PWM modules can be operated at three times the IPBus clock frequency. 56F8013/56F8011 Data Sheet, Rev. 10 80 Freescale Semiconductor Preliminary Resets EXTENDED_POR JTAG Power-On Reset (active low) POR pulse shaper Delay 64 MSTR_OSC Clocks CLKGEN_RST OCCS Memory Subsystem External RESET IN RESET (active low) COMBINED_RST Delay 32 MSTR_OSC Clocks pulse shaper Delay 32 sys clocks pulse shaper Delay 32 sys clocks pulse shaper CORE_RST 56800E PERIP_RST Peripherals COP (active low) SW Reset Delay blocks assert immediately and deassert only after the programmed number of clock cycles. Figure 6-15 Sources of RESET Functional Diagram (Test modes not included) POR resets are extended 64 MSTR_OSC clocks to stabilize the power supply. All resets are subsequently extended for an additional 32 MSTR_OSC clocks and 64 system clocks as the various internal reset controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a POR reset from when power comes on to when code is running is 28μS. An external reset generation chip may also be used. Resets may be asserted asynchronously, but they are always released internally on a rising edge of the system clock. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 81 6.7 Clocks The memory, peripheral and core clocks all operate at the same frequency (32MHz max) with the exception of the TMR and PWM peripheral clocks, which have the option (using TCR and PCR) to operate three times faster. The SIM is responsible for stalling individual clocks as a response to various hold-off requests, low power modes, and other configuration parameters. The SIM has access to the following signals from the OCCS module: MSTR_OSC This comes from the input clock source mux of the OCCS. It is the output of the relaxation oscillator or the external clock source, depending on PRECS. It is not guaranteed to be at 50% duty cycle (+ or - 10% can probably be assumed for design purposes). This clock runs continuously, even during resetm and is used for reset generation. The PLL multiplies the MSTR_OSC by 24, to a maximum of 192MHz. The ZSRC field in OCCS selects the active source to be the PLL. This is divided by 2 and postscaled to produce this maximum 96MHz clock. It is used without further division to produce the high-speed (3x system bus rate) variants of the TMR and PWM peripheral clocks. This clock is disabled when ZSRC is selecting MSTR_OSC. The PLL can multiply the MSTR_OSC by 24, to a maximum of 192MHz. When the PLL is selected by the OCCS ZSRC field, the PLL is divided by three and postscaled to produce this maximum 64MHz clock. When MSTR_OSC is selected by the OCCS ZSRC field, MSTR_OSC feeds SYS_CLK_x2 directly. The SIM takes this clock and divides it by two to generate all the normal (1x system bus rate) peripheral and system clocks. HS_PERF SYS_CLK_x2 While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks, the ADC standby and conversion clocks are generated by a direct interface between the ADC and the OCCS module. Figure 6-16 illustrates clock relationships to one another and to the various resets as the device comes out of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external reset, COP and Software reset). In the 56F8013/56F8011 architecture, this signal will be stretched by the SIM for a period of time (up to 96 MSTR_OSC clock cycles, depending upon the status of the POR) to create the clock generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST synchronously with the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is delayed 32 SYS_CLK cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then delayed by 32 SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active. 56F8013/56F8011 Data Sheet, Rev. 10 82 Freescale Semiconductor Preliminary Interrupts Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles for combined reset extension RST MSTR_OSC Switch on falling OSC_CLK 96 MSTR_OSC cycles CKGEN_RST SYS_CLK_x2 SYS_CLK SYS_CLK_D SYS_CLK_DIV2 32 SYS_CLK cycles delay PERIP_RST Switch on falling SYS_CLK 32 SYS_CLK cycles delay CORE_RST Switch on falling SYS_CLK Figure 6-16 Timing Relationships of Reset Signal to Clocks 6.8 Interrupts The SIM generates no interrupts. Part 7 Security Features The 56F8013/56F8011 offer security features intended to prevent unauthorized users from reading the contents of the Flash Memory (FM) array. The 56F8013/56F8011’s Flash security consists of several hardware interlocks that prevent unauthorized users from gaining access to the Flash array. Note, however, that part of the security must lie with the user’s code. An extreme example would be user’s code that includes a subroutine to read and transfer the contents of the internal program to SCI, SPI or another peripheral, as this code would defeat the purpose of security. At the same time, the user may also wish to put a “backdoor” in his program. As an example, the user downloads a security key through the SCI, allowing access to a programming routine that updates parameters stored in another section of the Flash. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 83 7.1 Operation with Security Enabled Once the user has programmed the Flash with his application code, the 56F8013/56F8011 can be secured by programming the security bytes located in the FM configuration field, which are located at the last nine words of Program Flash. These non-volatile bytes will keep the part secured through reset and through power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory chapter in the 56F801X Peripheral User Manual for the state of the security bytes and the resulting state of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module chapter, the 56F8013/56F8011 will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms The 56F8013/56F8011 have several operating functional and debug modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be read without explicit user permission. 7.2.1 Disabling EOnCE Access On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the 56F8013/56F8011 boot, the chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability and access to the ID register, but proper implementation of Flash security will block any attempt to access the internal Flash memory via the EOnCE port when security is enabled. 7.2.2 Flash Lockout Recovery Using JTAG If a user inadvertently enables security on the 56F8013/56F8011, the only lockout recovery mechanism is the complete erasure of the internal Flash contents, including the configuration field, and thus disables security (the protection register is cleared). This does not compromise security, as the entire contents of the user’s secured code stored in Flash are erased before security is disabled on the 56F8013/56F8011 on the next reset or power-up sequence. To start the lockout recovery sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller’s instruction register. Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. Refer to the 56F801X Peripheral User Manual for more details, or contact Freescale. Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by advancing the TAP state machine to the reset state) and the 56F8013/56F8011 (by asserting external chip reset) to return to normal unsecured operation. 56F8013/56F8011 Data Sheet, Rev. 10 84 Freescale Semiconductor Preliminary Introduction 7.2.3 Flash Lockout Recovery using CodeWarrior CodeWarrior can unlock a device using the command sequence described in Section 7.2.2 by selecting the Debug menu, then selecting DSP56800E, followed by Unlock Flash. Another mechanism is also built into CodeWarrior using the device’s memory configuration file. The command “Unlock_Flash_on_Connect1” in the .cfg file accomplishes the same task as using the Debug menu. 7.2.4 Product Analysis The recommended method of unsecuring a programmed 56F8013/56F8011 for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows backdoor key access must be set. An alternative method for performing analysis on a secured microcontroller would be to mass-erase and reprogram the Flash with the original code, but modify the security bytes. To insure that a customer does not inadvertently lock himself out of the 56F8013/56F8011 during programming, it is recommended that the user program the backdoor access key first, the application code second and the security bytes within the FM configuration field last. Part 8 General Purpose Input/Output (GPIO) 8.1 Introduction This section is intended to supplement the GPIO information found in the 56F801X Peripheral User Manual and contains only chip-specific information. This information supercedes the generic information in the 56F801X Peripheral User Manual. 8.2 Configuration There are four GPIO ports defined on the 56F8013/56F8011. The width of each port, the associated peripheral and reset functions are shown in Table 8-1. The specific mapping of GPIO port pins is shown in Table 8-2. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 85 Table 8-1 GPIO Ports Configuration GPIO Port A B C D Available Pins in 56F8013/56F8011 8 8 6 4 Peripheral Function PWM, Reset SPI, SCI, Timer ADC (GPIOC3 and GPIOC7 are not bonded out on the 56F8013/56F8011) JTAG Reset Function GPIO, except GPIOA7 GPIO Analog JTAG Table 8-2 GPIO External Signals Map Pins in shaded rows are not available in 56F8013/56F8011 GPIO Function GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 Peripheral Function PWM0 PWM1 PWM2 PWM3 PWM4 / FAULT1 / T2 LQFP Package Pin 29 28 23 24 22 Defaults to A0 Defaults toA1 Defaults to A2 Defaults to A3 Notes SIM register SIM_GPS is used to select between PWM4, FAULT1, and T2 Defaults to A4 SIM register SIM_GPS is used to select between PWM5, FAULT2, and T3 Defaults to A5 Defaults to A6 Defaults to RESET SIM register SIM_GPS is used to select between SCLK and SCL Defaults to B0 SIM register SIM_GPS is used to select between SS and SDA Defaults to B1 SIM register SIM_GPS is used to select between MISO and T2 Defaults to B2 SIM register SIM_GPS is used to select between MOSI and T3 Defaults to B3 GPIOA5 PWM5 / FAULT2 / T3 20 GPIOA6 GPIOA7 GPIOB0 FAULT0 RESET SCLK / SCL 18 15 21 GPIOB1 SS / SDA 2 GPIOB2 MISO / T2 17 GPIOB3 MOSI / T3 16 56F8013/56F8011 Data Sheet, Rev. 10 86 Freescale Semiconductor Preliminary Reset Values Table 8-2 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8013/56F8011 GPIO Function GPIOB4 Peripheral Function T0 / CLKO LQFP Package Pin 19 Notes SIM register SIM_GPS is used to select between T0 and CLKO Defaults to B4 SIM register SIM_GPS is used to select between T1 and FAULT3 Defaults to B5 SIM register SIM_GPS is used to select between RXD and SDA. CLKIN functionality is enabled using the PLL Control Register within the OCCS block. Defaults to B6 SIM register SIM_GPS is used to select between TXD and SCL Defaults to B7 Defaults to ANA0 Defaults to ANA1 Defaults to ANA2 Not bonded out in 56F8013/56F8011 Defaults to ANA3 GPIOB5 T1 / FAULT3 4 GPIOB6 RXD / SDA / CLKIN 1 GPIOB7 TXD / SCL 3 GPIOC0 GPIOC1 GPIOC2 GPIOC3 GPIOC4 GPIOC5 GPIOC6 GPIOC7 GPIOD0 GPIOD1 GPIOD2 GPIOD3 ANA0 ANA1 ANA2 / VREFH ANA3 ANB0 ANB1 ANB2 / VREFL ANB3 TDI TDO TCK TMS 12 11 10 5 6 7 Defaults to ANB0 Defaults to ANB1 Defaults to ANB2 Not bonded out in 56F8013/56F8011 Defaults to ANB3 30 32 14 31 Defaults to TDI Defaults to TDO Defaults to TCK Defaults to TMS 8.3 Reset Values Tables 4-18 through 4-21 detail registers for the 56F8013/56F8011; Figures 8-1 through 8-4 summarize register maps and reset values. 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 87 Add. Offset Register Acronym R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 7 6 5 4 3 2 1 0 $0 GPIOA_PUPEN PU 1 1 1 1 D 0 1 1 1 DD 0 0 0 0 PE 1 0 0 0 IA 0 0 0 0 IEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 $1 GPIOA_DATA $2 GPIOA_DDIR $3 GPIOA_PEREN $4 GPIOA_IASSRT $5 GPIOA_IEN $6 GPIOA_IEPOL IEPOL 0 0 0 0 IPR 0 0 0 0 IES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $7 GPIOA_IPEND $8 GPIOA_IEDGE $9 GPIOA_PPOUTM OEN 1 1 1 1 1 1 1 1 RAW DATA X X X X X X X X $A GPIOA_RDATA $B GPIOA_DRIVE DRIVE 0 0 0 0 0 0 0 0 Read as 0 Reserved Reset Figure 8-1 GPIOA Register Map Summary 56F8013/56F8011 Data Sheet, Rev. 10 88 Freescale Semiconductor Preliminary Reset Values Add. Offset Register Acronym R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 7 6 5 4 3 2 1 0 $0 GPIOB_PUPEN PU 1 1 1 1 D 1 1 1 1 DD 0 0 0 0 PE 0 0 0 0 IA 0 0 0 0 IEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 $1 GPIOB_DATA $2 GPIOB_DDIR $3 GPIOB_PEREN $4 GPIOB_IASSRT $5 GPIOB_IEN $6 GPIOB_IEPOL IEPOL 0 0 0 0 IPR 0 0 0 0 IES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $7 GPIOB_IPEND $8 GPIOB_IEDGE $9 GPIOB_PPOUTM OEN 1 1 1 1 1 1 1 1 RAW DATA X X X X X X X X $A GPIOB_RDATA $B GPIOB_DRIVE DRIVE 0 0 0 0 0 0 0 0 Read as 0 Reserved Reset Figure 8-2 GPIOB Register Map Summary 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 89 Add. Offset Register Acronym R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 7 6 5 4 3 2 1 0 $0 GPIOC_PUPEN PU 1 1 1 1 D 0 0 0 0 DD 0 0 0 0 PE 1 1 1 1 IA 0 0 0 0 IEN 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 $1 GPIOC_DATA $2 GPIOC_DDIR $3 GPIOC_PEREN $4 GPIOC_IASSRT $5 GPIOC_IEN $6 GPIOC_IEPOL IEPOL 0 0 0 0 IPR 0 0 0 0 IES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $7 GPIOC_IPEND $8 GPIOC_IEDGE $9 GPIOC_PPOUTM OEN 1 1 1 1 1 1 1 1 RAW DATA X X X X X X X X $A GPIOC_RDATA $B GPIOC_DRIVE DRIVE 0 0 0 0 0 0 0 0 Read as 0 Reserved Reset Figure 8-3 GPIOC Register Map Summary 56F8013/56F8011 Data Sheet, Rev. 10 90 Freescale Semiconductor Preliminary Reset Values Add. Offset Register Acronym R W RS R 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 3 2 1 0 $0 GPIOD_PUPEN PU 1 1 D 0 0 DD 0 0 PE 1 1 IA 0 0 IEN 0 0 0 0 0 0 1 1 0 0 0 0 1 1 $1 GPIOD_DATA W RS R W RS R W RS R W RS R $2 GPIOD_DDIR $3 GPIOD_PEREN $4 GPIOD_IASSRT $5 GPIOD_IEN W RS R IEPOL 0 0 IPR 0 0 IES 0 0 0 OEN 1 1 1 1 0 0 0 0 0 $6 GPIOD_IEPOL W RS R W RS R W RS R W RS R W RS R W RS R W RS $7 GPIOD_IPEND $8 GPIOD_IEDGE $9 GPIOD_PPOUTM RAW DATA X X X X $A GPIOD_RDATA $B GPIOD_DRIVE DRIVE 0 0 0 0 Read as 0 Reserved Reset Figure 8-4 GPIOD Register Map Summary 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 91 Part 9 Joint Test Action Group (JTAG) 9.1 56F8013/56F8011 Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to VDD in the package. The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high for five rising edges of TCK, as described in the 56F801X Peripheral User Manual. Part 10 Specifications 10.1 General Characteristics The 56F8013/56F8011 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels, combined with the ability to receive 5V levels without damage. Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40ºC to 125ºC ambient temperature over the following supply ranges: VSS = VSSA = 0V, VDD = VDDA = 3.0–3.6V, CL < 50pF, fOP = 32MHz Note: The 56F8011 device is specified to meet Industrial requirements only. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. 56F8013/56F8011 Data Sheet, Rev. 10 92 Freescale Semiconductor Preliminary General Characteristics Table 10-1 Absolute Maximum Ratings (VSS = 0V, VSSA = 0V) Characteristic Supply Voltage Range Analog Supply Voltage Range ADC High Voltage Reference Voltage difference VDD to VDDA Voltage difference VSS to VSSA Input Voltage Range (Digital inputs) Input Voltage Range (ADC inputs)1 Input clamp current, per pin (VIN < 0)2 Output clamp current, per pin (VO < 0)2 Output Voltage Range (Normal Push-Pull mode) Output Voltage Range (Open Drain mode) Ambient Temperature Storage Temperature Symbol VDD VDDA VREFH ΔVDD ΔVSS VIN VINA VIC VOC VOUT VOUTOD TA TSTG Pin Group 1 Pin Groups 1, 2 Pin Group 3 Notes Min -0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 -0.3 -0.3 -40 -55 Max 4.0 4.0 4.0 0.3 0.3 6.0 4.0 -20 -20 4.0 6.0 105 150 Unit V V V V V V V mA mA V V °C °C Pin Groups 1, 2 1. Pin Group 3 can tolerate 6V for less than 5 seconds when they are configured as ADC inputs or during reset. Pin Group 3 can tolerate 6V if they are configured as GPIO. 2. Continuous input current per pin is -2 mA Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC Analog Inputs 10.1.1 ElectroStatic Discharge (ESD) Model Table 10-2 56F8013/56F8011 ESD Protection Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Min 2000 200 750 Typ — — — Max — — — Unit V V V 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor Preliminary 93 Table 10-3 LQFP Package Thermal Characteristics6 Characteristic Junction to ambient Natural convection Junction to ambient Natural convection Junction to ambient (@200 ft/min) Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to package top Natural Convection Comments Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) Symbol RθJA RθJMA RθJMA RθJMA RθJB RθJC ΨJT Value (LQFP) 74 50 67 46 23 20 4 Unit Notes °C/W °C/W °C/W °C/W °C/W °C/W °C/W 1,2 1,3 1,3 1,3 4 5 6 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESC51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 7. See Section 12.1 for more details on thermal design considerations. 56F8013/56F8011 Data Sheet, Rev. 10 94 Freescale Semiconductor Preliminary General Characteristics Table 10-4 Recommended Operating Conditions (VREFL = 0V, VSSA = 0V, VSS = 0V ) Characteristic Supply voltage ADC Supply voltage ADC High Voltage Reference Voltage difference VDD to VDDA Voltage difference VSS to VSSA Device Clock Frequency Using relaxation oscillator Using external clock source Input Voltage High (digital inputs) Input Voltage Low (digital inputs) Output Source Current High (at VOH min.) When programmed for low drive strength When programmed for high drive strength Output Source Current Low (at VOL max.) When programmed for low drive strength When programmed for high drive strength Ambient Operating Temperature Flash Endurance (Program Erase Cycles) Flash Data Retention Flash Data Retention with