56F826

56F826 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F826 Rev. 14 01/2007 freescale.com 56F826 General Description • • • • Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 31.5K × 16-bit words (64KB) Program Flash 512 × 16-bit words (1KB) Program RAM 2K × 16-bit words (4KB) Data Flash 4K × 16-bit words (8KB) Data RAM 2K × 16-bit words (4KB) BootFLASH Up to 64K × 16-bit words each of external memory expansion for Program and Data memory • • • • • • • • One Serial Port Interface (SPI) One additional SPI or two optional Serial Communication Interfaces (SCI) One Synchronous Serial Interface (SSI) One General Purpose Quad Timer JTAG/OnCE™ for debugging 100-pin LQFP Package 16 dedicated and 30 shared GPIO Time-of-Day (TOD) Timer • • • • • • EXTBOOT RESET IRQA IRQB 6 JTAG/ OnCE Port TOD Timer Interrupt Controller Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Bit Manipulation Unit VDD 3 VSS 4 4 VDDIO VSSIO 4 Analog Reg VDDA VSSA Low Voltage Supervisor 4 Quad Timer or GPIO Program Memory 32252 x 16 Flash 512 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 2048 x 16 Flash 4096 x 16 SRAM PAB PDB XDB2 CGDB XAB1 XAB2 INTERRUPT CONTROLS 16 IPBB CONTROLS 16 16-Bit 56800 Core PLL Clock Gen CLKO XTAL EXTAL 6 SSI or GPIO SCI0 & SCI1 or SPI0 SPI1 or GPIO Dedicated GPIO 4 COP/ Watchdog COP RESET MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0] External Address Bus Switch 16 A[00:15] or GPIO D[00:15] 4 16 Application-Specific Memory & Peripherals IPBus Bridge (IPBB) External Bus Interface Unit External Data Bus Switch Bus Control 16 PS Select[0] DS Select[1] WR Enable RD Enable 56F826 Block Diagram 56F826 Technical Data, Rev. 14 Freescale Semiconductor 3 Part 1 Overview 1.1 56F826 Features 1.1.1 • • • • • • • • • • • • • • Processing Core Efficient 16-bit 56800 family controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators, including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique processor addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C Compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE Debug Programming Interface 1.1.2 • • Memory Harvard architecture permits as many as three simultaneous accesses to Program and Data memory On-chip memory including a low-cost, high-volume Flash solution — 31.5K × 16-bit words of Program Flash — 512 × 16-bit words of Program RAM — 2K × 16-bit words of Data Flash — 4K × 16-bit words of Data RAM — 2K × 16-bit words of BootFLASH • Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states — As much as 64K × 16-bit Data memory — As much as 64K × 16-bit Program memory 1.1.3 • • • • Peripheral Circuits for 56F826 One General Purpose Quad Timer totalling 7 pins One Serial Peripheral Interface with 4 pins (or four additional GPIO lines) One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces totalling 4 pins Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines) 56F826 Technical Data, Rev. 14 4 Freescale Semiconductor 56F826 Description • • • • • • • • • Sixteen (16) dedicated General Purpose I/O (GPIO) pins Thirty (30) shared General Purpose I/O (GPIO) pins Computer-Operating Properly (COP) Watchdog timer Two external interrupt pins External reset pin for hardware reset JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs One Time of Day module 1.1.4 • • Energy Information Dual power supply, 3.3V and 2.5V Wait and Multiple Stop modes available 1.2 56F826 Description The 56F826 is a member of the 56800 core-based family of processors. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution for general purpose applications. Because of its low cost, configuration flexibility, and compact program code, the 56F826 is well-suited for many applications. The 56F826 includes many peripherals that are especially useful for applications such as: noise suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic alarms, POS terminals, feature phones. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications. The 56F826 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It also supports program execution from external memory. The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased. 56F826 Technical Data, Rev. 14 Freescale Semiconductor 5 This controller also provides a full set of standard programmable peripherals including one Synchronous Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and Quad Timer can be used as General Purpose Input/Outputs (GPIOs) if a timer function is not required. 1.3 Award-Winning Development Environment • • Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Product Documentation The four documents listed in Table 1-1 are required for a complete description and proper design with the 56F826. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Table 1-1 56F826 Chip Documentation Topic 56800E Family Manual DSP56F826/F827 User’s Manual 56F826 Technical Data Sheet 56F826 Product Brief 56F826 Errata Description Detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the 56F826 and 56F827 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Summary description and block diagram of the 56F826 core, memory, peripherals and interfaces Details any chip issues that might be present Order Number 56800EFM DSP56F826-827UM DSP56F826 DSP56F826PB DSP56F826E 56F826 Technical Data, Rev. 14 6 Freescale Semiconductor Data Sheet Conventions 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR “asserted” “deasserted” Examples: This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F826 Technical Data, Rev. 14 Freescale Semiconductor 7 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F826 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. Table 2-1 describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Functional Group Power (VDD, VDDIO or VDDA) Ground (VSS, VSSIO or VSSA) PLL and Clock Address Bus1 Data Bus1 Bus Control Quad Timer Module Ports1 JTAG/On-Chip Emulation (OnCE) Dedicated General Purpose Input/Output Synchronous Serial Interface (SSI) Port1 Serial Peripheral Interface (SPI) Port1 Serial Communications Interface (SCI) Ports Interrupt and Program Control 1. Alternately, GPIO pins Number of Pins (3,4,1) (3,4,1) 3 16 16 4 4 6 16 6 4 4 5 56F826 Technical Data, Rev. 14 8 Freescale Semiconductor Introduction 2.5V Power 3.3V Analog Power 3.3V Power Ground Analog Ground Ground VDD VDDA VDDIO VSS VSSA VSSIO 3 1 4 4* 1 4 8 8 GPIOB0–7 GPIOD0–7 Dedicated GPIO 1 1 1 1 1 1 SRD (GPIOC0) SRFS (GPIOC1) SRCK (GPIOC2) STD (GPIOC3) STFS (GPIOC4) STCK (GPIOC5) SSI Port or GPIO 56F826 PLL and Clock EXTAL XTAL (CLOCKIN) CLKO 1 1 1 1 1 1 1 1 1 1 1 SCLK (GPIOF4) MOSI (GPIOF5) MISO (GPIOF6) SS (GPIOF7) TXD0 (SCLK0) RXD0 (MOSI0) TXD1 (MISO0) RXD1 (SS0) SCI0, SCI1 Port or SPI0 Port SPI1 Port or GPIO External Address Bus or GPIO External Data Bus A0-A7 (GPIOE) A8-A15 (GPIOA) 8 8 D0–D15 16 PS External Bus Control DS RD WR 1 1 1 1 TA0 (GPIOF0) Quad Timer A or GPIO TA1 (GPIOF1) TA2 (GPIOF2) TA3 (GPIOF3) 1 1 1 1 TCK TMS JTAG/OnCE™ Port TDI TDO TRST DE 1 1 1 1 1 1 1 1 1 1 IRQA IRQB RESET EXTBOOT Interrupt/ Program Control *Includes TCS pin, which is reserved for factory use and is tied to VSS Figure 2-1 56F826 Signals Identified by Functional Group1 1. Alternate pin functionality is shown in parentheses. 56F826 Technical Data, Rev. 14 Freescale Semiconductor 9 2.2 Signals and Package Information All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When a pin is owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP Signal Name VDD VDD VDD VDDA VDDIO VDDIO VDDIO VDDIO VSS VSS VSS VSSA VSSIO VSSIO VSSIO VSSIO TCS EXTAL Pin No. 20 64 94 59 5 30 57 80 19 63 95 60 6 31 58 81 99 61 Type VDD VDD VDD VDDA VDDIO VDDIO VDDIO VDDIO VSS VSS VSS VSSA VSSIO VSSIO VSSIO VSSIO Input/Output (Schmitt) Input TCS—This pin is reserved for factory use. It must be tied to VSS for normal use. In block diagrams, this pin is considered an additional VSS. External Crystal Oscillator Input—This input should be connected to a 4MHz external crystal or ceramic resonator. For more information, please refer to Section 3.6. Analog Ground—This pin supplies an analog ground. GND In/Out—These pins provide grounding for the I/O ring on the chip. All should be attached to VSS. GND—These pins provide grounding for the internal structures of the chip. All should be attached to VSS. Analog Power—This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low-noise 3.3V supply. Power In/Out—These pins provide power to the I/O structures of the chip, and are generally connected to a 3.3V supply. Description Power—These pins provide power to the internal structures of the chip, and are generally connected to a 2.5V supply. 56F826 Technical Data, Rev. 14 10 Freescale Semiconductor Signals and Package Information Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name XTAL Pin No. 62 Type Output Description Crystal Oscillator Output—This output connects the internal crystal oscillator output to an external crystal or ceramic resonator. If an external clock source over 4MHz is used, XTAL must be used as the input and EXTAL connected to VSS. For more information, please refer to Section 3.6.3. External Clock Input—This input should be asserted when using an external clock or ceramic resonator. Clock Output—This pin outputs a buffered clock signal. By programming the CLKO Select Register (CLKOSR), the user can select between outputting a version of the signal applied to XTAL and a version of the device master clock at the output of the PLL. The clock frequency on this pin can be disabled by programming the CLKO Select Register (CLKOSR). Address Bus—A0–A7 specify the address for external program or data memory accesses. Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. (CLOCKIN) CLKO 65 Input Output A0 (GPIOE0) A1 (GPIOE1) A2 (GPIOE2) A3 (GPIOE3) A4 (GPIOE4) A5 (GPIOE5) A6 (GPIOE6) A7 (GPIOE7) 24 23 22 21 18 17 16 15 Output Input/Output 56F826 Technical Data, Rev. 14 Freescale Semiconductor 11 Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name A8 (GPIOA0) A9 (GPIOA1) A10 (GPIOA2) A11 (GPIOA3) A12 (GPIOA4) A13 (GPIOA5) A14 (GPIOA6) A15 (GPIOA7) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PS DS Pin No. 14 13 12 11 10 9 8 7 34 35 36 37 38 39 40 41 42 43 44 46 47 48 49 50 29 28 Output Output Program Memory Select—PS is asserted low for external program memory access. Data Memory Select—DS is asserted low for external data memory access. Input/Output Data Bus— D0–D15 specify the data for external program or data memory accesses. D0–D15 are tri-stated when the external bus is inactive. Type Output Description Address Bus—A8–A15 specify the address for external program or data memory accesses. Port A GPIO—These eight General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. Input/Output 56F826 Technical Data, Rev. 14 12 Freescale Semiconductor Signals and Package Information Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name RD Pin No. 26 Type Output Description Read Enable—RD is asserted during external memory read cycles. When RD is asserted low, pins D0–D15 become inputs and an external device is enabled onto the device data bus. When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. Write Enable—WR is asserted during external memory write cycles. When WR is asserted low, pins D0–D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of a Static RAM. TA0–3—Timer A Channels 0, 1, 2, and 3 Port F GPIO—These four General Purpose I/O (GPIO) pins can be individually programmed as input or output. After reset, the default state is Quad Timer. WR 27 Output TA0 (GPIOF0) TA1 (GPIOF1) TA2 (GPIOF2) TA3 (GPIOF3) TCK 91 90 89 88 100 Input/Output Input/Output Input (Schmitt) Input (Schmitt) Test Clock Input—This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor. Test Mode Select Input—This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Note: Always tie the TMS pin to VDD through a 2.2K resistor. TMS 1 TDI 2 Input (Schmitt) Output Test Data Input—This input pin provides a serial input data stream to the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Test Data Output—This tri-statable output pin provides a serial output data stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. Test Reset—As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the JTAG/OnCE module. In this case, assert RESET, but do not assert TRST. TRST must always be asserted at power-up. Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. TDO 3 TRST 4 Input (Schmitt) DE 98 Output Debug Event—DE provides a low pulse on recognized debug events. 56F826 Technical Data, Rev. 14 Freescale Semiconductor 13 Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name GPIOB0 GPIOB1 GPIOB2 GPIOB3 GPIOB4 GPIOB5 GPIOB6 GPIOB7 GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 GPIOD6 GPIOD7 SRD Pin No. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 82 83 51 Input/Output SSI Receive Data (SRD)—This input pin receives serial data and transfers the data to the SSI Receive Shift Receiver. Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output. After reset, the default state is GPIO input. SRFS 52 Input/ Output SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by the receive section of the SSI as frame sync I/O or flag I/O. The STFS can be used only by the receiver. It is used to synchronize data transfer and can be an input or an output. Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output. After reset, the default state is GPIO input. Input or Output Port D GPIO—These eight dedicated GPIO pins can be individually programmed as an input or output pins. After reset, the default state is GPIO input. Type Input or Output Description Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is GPIO input. (GPIOC0) Input/Output (GPIOC1) Input/Output 56F826 Technical Data, Rev. 14 14 Freescale Semiconductor Signals and Package Information Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name SRCK Pin No. 53 Type Input/Output Description SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial bit rate clock for the Receive section of the SSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output. After reset, the default state is GPIO input. STD 54 Output SSI Transmit Data (STD)—This output pin transmits serial data from the SSI Transmitter Shift Register. Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output. After reset, the default state is GPIO input. STFS 55 Input SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by the Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be used by both the transmitter and receiver in synchronous mode. It is used to synchronize data transfer and can be an input or output pin. Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output. After reset, the default state is GPIO input. STCK 56 Input/ Output SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial bit rate clock for the transmit section of the SSI. The clock signal can be continuous or gated. It can be used by both the transmitter and receiver in synchronous mode. Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output. After reset, the default state is GPIO input. SCLK 84 Input/Output SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output. After reset, the default state is SCLK. MOSI 85 Input/Output SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output. (GPIOC2) Input/Output (GPIOC3) Input/Output (GPIOC4) Input/Output (GPIOC5) Input/Output (GPIOF4) Input/Output (GPIOF5) Input/Output 56F826 Technical Data, Rev. 14 Freescale Semiconductor 15 Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name MISO Pin No. 86 Type Input/Output Description SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output. After reset, the default state is MISO. SS 87 Input SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output. After reset, the default state is SS. TXD0 (SCLK0) 97 Output Input/Output Transmit Data (TXD0)—transmit data output SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. After reset, the default state is SCI output. RXD0 96 Input Receive Data (RXD0)— receive data input (GPIOF6) Input/Output (GPIOF7) Input/Output (MOSI0) Input/Output SPI Master Out/Slave In—This serial data pin is an output from a master device, and an input to a slave device. The master device places data on the MOSI line one half-cycle before the clock edge the slave device uses to latch the data. After reset, the default state is SCI input. TXD1 (MISO0) 93 Output Input/Output Transmit Data (TXD1)—transmit data output SPI Master In/Slave Out—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. After reset, the default state is SCI output. RXD1 92 Input (Schmitt) Input Receive Data (RXD1)— receive data input (SS0) SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. After reset, the default state is SCI input. 56F826 Technical Data, Rev. 14 16 Freescale Semiconductor Signals and Package Information Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name IRQA Pin No. 32 Type Input (Schmitt) Description External Interrupt Request A—The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull-up resistor is required for wired-OR operation. If the processor is in the Stop state and IRQA is asserted, the processor will exit the Stop state. IRQB 33 Input (Schmitt) External Interrupt Request B—The IRQB input is an external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull-up resistor is required for wired-OR operation. Reset—This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the external boot pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. EXTBOOT 25 Input (Schmitt) External Boot—This input is tied to VDD to force device to boot from off-chip memory. Otherwise, it is tied to ground. RESET 45 Input (Schmitt) 56F826 Technical Data, Rev. 14 Freescale Semiconductor 17 Part 3 Specifications 3.1 General Characteristics The 56F826 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage. This 5V-tolerant capability, therefore, offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The 56F826 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. 56F826 Technical Data, Rev. 14 18 Freescale Semiconductor General Characteristics Table 3-1 Absolute Maximum Ratings Characteristic Supply voltage, core Supply voltage, IO Supply voltage, Analog Digital input voltages Analog input voltages - XTAL, EXTAL Voltage difference VDD to VDD_IO, VDDA Voltage difference VSS to VSS _IO, VSSA Current drain per pin excluding VDD, VSS, VDDA, VSSA, VDDIO, VSSIO Junction temperature Storage temperature range 1. VDD must not exceed VDDIO 2. VDDIO and VDDA must not differ by more that 0.5V Symbol VDD1 VDDIO2 VDDA 2 Min VSS – 0.3 VSSIO – 0.3 VSSA – 0.3 VSSIO – 0.3 VSSA – 0.3 - 0.3 - 0.3 — Max VSS + 3.0 VSSIO + 4.0 VSSA + 4.0 VSSIO + 5.5 VDDA + 0.3 0.3 0.3 10 Unit V V VIN VINA ΔVDD ΔVSS I V V V mA °C °C TJ TSTG — –55 150 150 Table 3-2 Recommended Operating Conditions Characteristic Supply voltage, core Supply Voltage, IO and analog Voltage difference VDD to VDD_IO, VDDA Voltage difference VSS to VSS _IO, VSSA Ambient operating temperature Symbol VDD VDDIO,VDDA ΔVDD ΔVSS TA Min 2.25 3.0 -0.1 -0.1 –40 Typ 2.5 3.3 – Max 2.75 3.6 0.1 0.1 85 Unit V V V V °C 56F826 Technical Data, Rev. 14 Freescale Semiconductor 19 Table 3-3 Thermal Characteristics6 Value Characteristic Comments Symbol 100-pin LQFP Unit Notes Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to case Junction to center of case I/O pin power dissipation Power dissipation Junction to center of case Four layer board (2s2p) RθJA RθJMA RθJMA (2s2p) RθJMA RθJC ΨJT P I/O PD PDMAX 48.3 43.9 40.7 °C/W °C/W °C/W 2 2 1.2 Four layer board (2s2p) 38.6 13.5 1.0 User Determined P D = (IDD x VDD + P I/O) (TJ - TA) /RθJA °C/W °C/W °C/W W W W 1,2 3 4, 5 7 Notes: 1. 2. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. Junction to case thermal resistance, Theta-JC (RθJC), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. Thermal Characterization Parameter, Psi-JT (ΨJT), is the “resistance” from junction to reference point thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in steady state customer environments. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. See Section 5.1 for more details on thermal design considerations. TJ = Junction Temperature TA = Ambient Temperature 3. 4. 5. 6. 7. 56F826 Technical Data, Rev. 14 20 Freescale Semiconductor DC Electrical Characteristics 3.2 DC Electrical Characteristics Table 3-4 DC Electrical Characteristics Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Input high voltage (XTAL/EXTAL) Input low voltage (XTAL/EXTAL) Input high voltage (Schmitt trigger inputs)1 Input low voltage (Schmitt trigger inputs)1 Input high voltage (all other digital inputs) Input low voltage (all other digital inputs) Input current high (pull-up/pull-down resistors disabled, VIN=VDD) Input current low (pull-up/pull-down resistors disabled, VIN=VSS) Input current high (with pull-up resistor, VIN=VDD) Input current low (with pull-up resistor, VIN=VSS) Input current high (with pull-down resistor, VIN=VDD) Input current low (with pull-down resistor, VIN=VSS) Nominal pull-up or pull-down resistor value Output tri-state current low Output tri-state current high Input current high (analog inputs, VIN=VDDA)2 Input current low (analog inputs, VIN=VSSA)2 Output High Voltage (at IOH) Output Low Voltage (at IOL) Output source current Output sink current PWM pin output source current3 PWM pin output sink current4 Symbol VIHC VILC VIHS VILS VIH VIL IIH IIL IIHPU IILPU IIHPD IILPD RPU, RPD IOZL IOZH IIHA IILA VOH VOL IOH IOL IOHP IOLP -10 -10 -15 -15 VDD – 0.7 — 4 4 10 16 Min 2.25 0 2.2 -0.3 2.0 -0.3 -1 -1 -1 -210 20 -1 Typ — — — — — — — — — — — — 30 — — — — — — — — — — 10 10 15 15 — 0.4 — — — — Max 3.6 0.5 5.5 0.8 5.5 0.8 1 1 1 -50 180 1 Unit V V V V V V μA μA μA μA μA μA KΩ μA μA μA μA V V mA mA mA mA 56F826 Technical Data, Rev. 14 Freescale Semiconductor 21 Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Input capacitance Output capacitance VDD supply current Run 6 Wait7 Stop Low Voltage Interrupt, VDDIO power supply8 Low Voltage Interrupt, VDD power supply9 Power on Reset10 1. Symbol CIN COUT IDDT5 Min — — Typ 8 12 Max — — Unit pF pF — — — VEIO VEIC VPOR 2.4 2.0 — 47 21 2 2.7 2.2 1.7 75 36 8 3.0 2.4 2.0 mA mA mA V V V 1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, TCK, TRST, TMS, TDI and RXD1 2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling. 3. PWM pin output source current measured with 50% duty cycle. 4. PWM pin output sink current measured with 50% duty cycle. 5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA) 6. Run (operating) IDD measured using 4MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled. 7. Wait IDD measured using external square wave clock source (fosc = 4MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured with PLL enabled. 8. This low-voltage interrupt monitors the VDDIO power supply. If VDDIO drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDIO >VEIO (between the minimum specified VDDIO and the point when the VEIO interrupt is generated). 9. This low-voltage interrupt monitors theVDD power supply. If VDDIO drops below VEIC, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDD >VEIC (between the minimum specified VDD and the point when the VEIC interrupt is generated). 10. Power–on reset occurs whenever the VDD power supply drops below VPOR. While power is ramping up, this signal remains active for as long as VDD is below VPOR no matter how long the ramp-up rate is. 56F826 Technical Data, Rev. 14 22 Freescale Semiconductor Supply Voltage Sequencing and Separation Cautions 100 75 IDD Digital IDD Analog IDD Total IDD (mA) 50 25 0 20 40 60 80 Freq. (MHz) Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-4) 3.3 Supply Voltage Sequencing and Separation Cautions Figure 3-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies. DC Power Supply Voltage 3.3V VDDIO, VDDA 2 Supplies Stable VDD 2.5V 1 0 Notes: 1. VDD rising before VDDIO, VDDA 2. VDDIO, VDDA rising much faster than VDD Time Figure 3-2 Supply Voltage Sequencing and Separation Cautions 56F826 Technical Data, Rev. 14 Freescale Semiconductor 23 VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD supply (2.5V) from the voltage generated by the 3.3V VDDIO supply, see Figure 3-3. This keeps VDD from rising faster than VDDIO. VDD should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 3-3. The series diodes forward bias when the difference between VDDIO and VDD reaches approximately 1.4, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper operation, the difference between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially leakage current. During supply sequencing, the following general relationship should be adhered to: VDDIO > VDD > (VDDIO - 1.4V) In practice, VDDA is typically connected directly to VDDIO with some filtering. 3.3V Regulator 2.5V Regulator VDDIO, VDDA Supply VDD Figure 3-3 Example Circuit to Control Supply Sequencing 3.4 AC Electrical Characteristics Timing waveforms in Section 3.4 are tested using the VIL and VIH levels specified in the DC Characteristics table. The levels of VIH and VIL for an input signal are shown in Figure 3-4. Pulse Width VIH Input Signal Midpoint1 Fall Time Note: The midpoint is VIL + (VIH – VIL)/2. Low High 90% 50% 10% VIL Rise Time Figure 3-4 Input Signal Measurement References Figure 3-5 shows the definitions of the following signal states: • • • • Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH 56F826 Technical Data, Rev. 14 24 Freescale Semiconductor Flash Memory Characteristics Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data3 Valid Data3 Data Active Figure 3-5 Signal States 3.5 Flash Memory Characteristics Table 3-5 Flash Memory Truth Table Mode Standby Read Word Program Page Erase Mass Erase XE1 L H H H H YE2 L H H L L SE3 L H L L L OE4 L H L L L PROG5 L L H L L ERASE6 L L L H H MAS17 L L L L H NVSTR8 L L H H H 1. X address enable, all rows are disabled when XE = 0 2. Y address enable, YMUX is disabled when YE = 0 3. Sense amplifier enable 4. Output enable, tri-state Flash data out bus when OE = 0 5. Defines program cycle 6. Defines erase cycle 7. Defines mass erase cycle, erase whole block 8. Defines non-volatile store cycle Table 3-6 IFREN Truth Table Mode Read Word program Page erase Mass erase IFREN = 1 Read information block Program information block Erase information block Erase both block IFREN = 0 Read main memory block Program main memory block Erase main memory block Erase main memory block 56F826 Technical Data, Rev. 14 Freescale Semiconductor 25 Table 3-7 Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Program time Erase time Mass erase time Endurance1 Data Retention1 Symbol Min 20 20 100 10,000 10 Typ – – – 20,000 30 Max – – – – – Unit us ms ms cycles years Figure Figure 3-6 Figure 3-7 Figure 3-8 Tprog* Terase* Tme* ECYC DRET The following parameters should only be used in the Manual Word Programming Mode PROG/ERASE to NVSTR set up time NVSTR hold time NVSTR hold time (mass erase) NVSTR to program set up time Recovery time Tnvs* – 5 – us Figure 3-6, Figure 3-7, Figure 3-8 Figure 3-6, Figure 3-7 Figure 3-8 Figure 3-6 Figure 3-6, Figure 3-7, Figure 3-8 Figure 3-6 Tnvh* Tnvh1* Tpgs* Trcv* – – – – 5 100 10 1 – – – – us us us us Cumulative program HV period2 Program hold time3 Address/data set up time3 Address/data hold time3 Thv Tpgh Tads Tadh – 3 – ms – – – – – – – – – Figure 3-6 Figure 3-6 Figure 3-6 1. One cycle is equal to an erase program and read. 2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase. 3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *The Flash interface unit provides registers for the control of these parameters. 56F826 Technical Data, Rev. 14 26 Freescale Semiconductor Flash Memory Characteristics IFREN XADR XE Tadh YADR YE DIN Tads PROG Tnvs Tprog Tpgh NVSTR Tpgs Thv Tnvh Trcv Figure 3-6 Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Terase Trcv Figure 3-7 Flash Erase Cycle 56F826 Technical Data, Rev. 14 Freescale Semiconductor 27 IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 3-8 Flash Mass Erase Cycle 3.6 External Clock Operation The 56F826 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 3.6.1 Crystal Oscillator The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 3-9. A recommended crystal oscillator circuit is shown in Figure 3-9. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.The internal 56F82x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-9, no external load capacitors should be used. The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF 56F826 Technical Data, Rev. 14 28 Freescale Semiconductor External Clock Operation as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as determined by the following equation: CL1 * CL2 CL1 + CL2 12 * 12 12 + 12 CL = + Cs = + 3 = 6 + 3 = 9pF This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit. EXTAL XTAL Rz fc Recommended External Crystal Parameters: Rz = 1 to 3MΩ fc = 4Mhz (optimized for 4MHz) Figure 3-9 Connecting to a Crystal Oscillator Circuit 3.6.2 Ceramic Resonator It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-10. Refer to supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The internal 56F82x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-10, no external load capacitors should be used. EXTAL XTAL Rz fc Recommended Ceramic Resonator Parameters: Rz = 1 to 3 MΩ fc = 4Mhz (optimized for 4MHz) Figure 3-10 Connecting a Ceramic Resonator Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators (which contain an internal bypass capacitor to ground). 56F826 Technical Data, Rev. 14 Freescale Semiconductor 29 3.6.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-11. The external clock source is connected to XTAL and the EXTAL pin is held VDDA/2. 56F826 XTAL EXTAL External Clock VDDA/2 Figure 3-11 Connecting an External Clock Signal Table 3-8 External Clock Operation Timing Requirements Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Frequency of operation (external clock driver)1 Clock Pulse Width3, 4 Symbol fosc tPW Min 0 6.25 Typ 4 — Max 802 — Unit MHz ns 1. See Figure 3-11 for details on using the recommended connection of an external clock driver. 2. When using Time of Day (TOD), maximum external frequency is 6MHz. 3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function. 4. Parameters listed are guaranteed by design. VIH External Clock 90% 50% 10% tPW tPW 90% 50% 10% VIL Note: The midpoint is VIL + (VIH – VIL)/2. Figure 3-12 External Clock Timing 56F826 Technical Data, Rev. 14 30 Freescale Semiconductor External Bus Asynchronous Timing 3.6.4 Phase Locked Loop Timing Table 3-9 PLL Timing Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz Characteristic External reference crystal frequency for the PLL1 PLL output frequency2 PLL stabilization time 3 -40o to +85oC Symbol fosc fout/2 tplls Min 2 40 — Typ 4 — 1 Max 6 110 10 Unit MHz MHz ms 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 4MHz input crystal. 2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the User Manual. ZCLK = fop 3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation. 3.7 External Bus Asynchronous Timing Table 3-10 External Bus Asynchronous Timing1, 2 Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Address Valid to WR Asserted WR Width Asserted Wait states = 0 Wait states > 0 WR Asserted to D0–D15 Out Valid Data Out Hold Time from WR Deasserted Data Out Set Up Time to WR Deasserted Wait states = 0 Wait states > 0 RD Deasserted to Address Not Valid Address Valid to RD Deasserted Wait states = 0 Wait states > 0 Symbol tAWR tWR Min 6.5 Max — Unit ns 7.5 (T*WS) + 7.5 — 4.8 — — T + 4.2 — ns ns ns ns tWRD tDOH tDOS 2.2 (T*WS) + 6.4 0 — — — — ns ns ns tRDA tARDD 18.7 (T*WS) + 18.7 ns ns 56F826 Technical Data, Rev. 14 Freescale Semiconductor 31 Table 3-10 External Bus Asynchronous Timing1, 2 (Continued) Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Input Data Hold to RD Deasserted RD Assertion Width Wait states = 0 Wait states > 0 Address Valid to Input Data Valid Wait states = 0 Wait states > 0 Address Valid to RD Asserted RD Asserted to Input Data Valid Wait states = 0 Wait states > 0 WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted Symbol tDRD tRD Min 0 Max — Unit ns 19 (T*WS) + 19 — — ns ns tAD — — -4.4 1 (T*WS) + 1 — ns ns ns tARDA tRDD — — 6.8 0 14.1 12.8 2.4 (T*WS) + 2.4 — — — — ns ns ns ns ns ns tWRRD tRDRD tWRWR tRDWR 1. Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and T = Clock Period. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula: Top = Clock period @ desired operating frequency WS = Number of wait states Memory Access Time = (Top*WS) + (Top- 11.5) 56F826 Technical Data, Rev. 14 32 Freescale Semiconductor External Bus Asynchronous Timing A0–A15, PS, DS (See Note) tARDA tARDD tRDA tRDRD RD tAWR tWRWR tWR tWRRD tRD tRDWR WR tWRD tDOS tAD tDOH tRDD tDRD D0–D15 Data Out Data In Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 3-13 External Bus Asynchronous Timing 56F826 Technical Data, Rev. 14 Freescale Semiconductor 33 3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5 Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1 RESET Deassertion to First External Address Output Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State3 IRQA Width Assertion to Recover from Stop State4 Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Symbol tRAZ tRA Min — Max 21 Unit ns See Figure Figure 3-14 Figure 3-14 275,000T 128T 33T 1.5T 15T — — 34T — — ns ns ns ns ns Figure 3-14 Figure 3-15 Figure 3-16 tRDA tIRW tIDM tIG 16T — ns Figure 3-16 tIRI tIW tIF 13T 2T — — ns ns Figure 3-17 Figure 3-18 Figure 3-18 — — tIRQ — — tII — — 275,000T 12T ns ns Figure 3-19 275,000T 12T ns ns Figure 3-19 275,000T 12T ns ns 1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns. 2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: • After power-on reset • When recovering from Stop state 3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 4. The interrupt instruction fetch is visible on the pins only in Mode 3. 5. Parameters listed are guaranteed by design. 56F826 Technical Data, Rev. 14 34 Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing RESET tRA tRAZ tRDA A0–A15, D0–D15 PS, DS, RD, WR First Fetch First Fetch Figure 3-14 Asynchronous Reset Timing IRQA, IRQB tIRW Figure 3-15 External Interrupt Timing (Negative-Edge-Sensitive) A0–A15, PS, DS, RD, WR IRQA, IRQB First Interrupt Instruction Execution tIDM a) First Interrupt Instruction Execution General Purpose I/O Pin IRQA, IRQB b) General Purpose I/O tIG Figure 3-16 External Level-Sensitive Interrupt Timing 56F826 Technical Data, Rev. 14 Freescale Semiconductor 35 IRQA, IRQB tIRI A0–A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 3-17 Interrupt from Wait State Timing tIW IRQA tIF A0–A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 3-18 Recovery from Stop State Using Asynchronous Interrupt Timing tIRQ IRQA tII A0–A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch Figure 3-19 Recovery from Stop State Using IRQA Interrupt Service 56F826 Technical Data, Rev. 14 36 Freescale Semiconductor Serial Peripheral Interface (SPI) Timing 3.9 Serial Peripheral Interface (SPI) Timing Table 3-12 SPI Timing1 Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCLK) high time Master Slave Clock (SCLK) low time Master Slave Data set-up time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters are guaranteed by design. Symbol tC Min 50 25 — 25 — 100 24 12 24.1 12 20 0 0 2 4.8 3.7 — — 0 0 — — — — Max — — — — — — — — — — — — — — 15 15.2 4.5 20.4 — — 11.5 10.0 9.7 9.0 Unit ns ns ns ns See Figure Figures 3-20, 3-21, 3-22, 3-23 Figure 3-23 tELD tELG Figure 3-23 ns ns ns ns Figures 3-20, 3-21, 3-22, 3-23 Figures 3-20, 3-21, 3-22, 3-23 Figures 3-20, 3-21, 3-22, 3-23 Figures 3-20, 3-21, 3-22, 3-23 Figure 3-23 ns Figure 3-23 ns ns ns ns ns ns ns ns ns Figures 3-20, 3-21, 3-22, 3-23 Figures 3-20, 3-21, 3-22, 3-23 Figures 3-20, 3-21, 3-22, 3-23 Figures 3-20, 3-21, 3-22, 3-23 tCH tCL ns ns ns ns ns ns tDS tDH tA tD tDV tDI tR tF 56F826 Technical Data, Rev. 14 Freescale Semiconductor 37 (Input) SS SS is held High on master tC tR tF tCL tCH tCL tF tR SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) tDS tDH tCH MISO (Input) MSB in tDI Bits 14–1 tDV LSB in tDI(ref) MOSI (Output) Master MSB out tF Bits 14–1 Master LSB out tR Figure 3-20 SPI Master Timing (CPHA = 0) (Input) SS tC SS is held High on master tF tCL tR SCLK (CPOL = 0) (Output) tCH tCL tF SCLK (CPOL = 1) (Output) tCH tR tDS tDH MISO (Input) tDV(ref) MSB in tDI Bits 14–1 tDV LSB in MOSI (Output) Master MSB out tF Bits 14– 1 Master LSB out tR Figure 3-21 SPI Master Timing (CPHA = 1) 56F826 Technical Data, Rev. 14 38 Freescale Semiconductor Serial Peripheral Interface (SPI) Timing (Input) SS tC tCL tF tR tELG SCLK (CPOL = 0) (Input) tELD tCH tCL SCLK (CPOL = 1) (Input) tA tCH tR tF tD MISO (Output) tDS Slave MSB out tDH Bits 14–1 tDV Slave LSB out tDI tDI MOSI (Input) MSB in Bits 14–1 LSB in Figure 3-22 SPI Slave Timing (CPHA = 0) (Input) SS tC tCL tR tF SCLK (CPOL = 0) (Input) tELD tCH tCL tELG SCLK (CPOL = 1) (Input) tDV tA tCH tF tR tD MISO (Output) tDS Slave MSB out tDH Bits 14–1 tDV tDI Slave LSB out MOSI (Input) MSB in Bits 14–1 LSB in Figure 3-23 SPI Slave Timing (CPHA = 1) 56F826 Technical Data, Rev. 14 Freescale Semiconductor 39 3.10 Synchronous Serial Interface (SSI) Timing Table 3-13 SSI Master Mode1 Switching Characteristics Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Parameter STCK frequency STCK period3 STCK high time STCK low time Output clock rise/fall time (STCK, SRCK) Delay from STCK high to STFS (bl) high - Master5 Delay from STCK high to STFS (wl) high - Master5 Delay from SRCK high to SRFS (bl) high - Master5 Delay from SRCK high to SRFS (wl) high - Master5 Delay from STCK high to STFS (bl) low - Master5 Delay from STCK high to STFS (wl) low - Master5 Delay from SRCK high to SRFS (bl) low - Master5 Delay from SRCK high to SRFS (wl) low - Master5 STCK high to STXD enable from high impedance - Master STCK high to STXD valid - Master STCK high to STXD not valid - Master STCK high to STXD high impedance - Master SRXD Setup time before SRCK low - Master SRXD Hold time after SRCK low - Master tTFSBHM tTFSWHM tRFSBHM tRFSWHM tTFSBLM tTFSWLM tRFSBLM tRFSWLM tTXEM tTXVM tTXNVM tTXHIM tSM tHM Symbol fs tSCKW tSCKH tSCKL 100 504 504 — 0.1 0.1 0.6 0.6 -1.0 -1.0 -0.1 -0.1 20 24 0.1 24 4 4 4 Min Typ Max 102 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns — — — — — — — — — — — — — — — — — — — — — 0.5 0.5 1.3 1.3 -0.1 -0.1 0 0 22 26 0.2 25.5 — — Synchronous Operation (in addition to standard internal clock parameters) SRXD Setup time before STCK low - Master SRXD Hold time after STCK low - Master 1. Master mode is internally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part. tTSM tTHM 4 4 — — — — 56F826 Technical Data, Rev. 14 40 Freescale Semiconductor Synchronous Serial Interface (SSI) Timing 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the tables and in the figures. 4. 50% duty cycle 5. bl = bit length; wl = word length tSCKH STCK output tSCKW tSCKL tTFSBHM STFS (bl) output tTFSWHM STFS (wl) output tTXVM tTXEM STXD SRCK output tRFSBHM SRFS (bl) output tRFSWHM SRFS (wl) output First Bit tTFSBLM tTFSWLM tTXNVM Last Bit tTXHIM tRFBLM tRFSWLM tSM SRXD tHM tTSM tTHM Figure 3-24 Master Mode Timing Diagram 56F826 Technical Data, Rev. 14 Freescale Semiconductor 41 Table 3-14 SSI Slave Mode1 Switching Characteristics Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Parameter STCK frequency STCK period3 STCK high time STCK low time Output clock rise/fall time Delay from STCK high to STFS (bl) high - Slave5 Delay from STCK high to STFS (wl) high - Slave5 Delay from SRCK high to SRFS (bl) high - Slave5 Delay from SRCK high to SRFS (wl) high - Slave5 Delay from STCK high to STFS (bl) low - Slave5 Delay from STCK high to STFS (wl) low - Slave5 Delay from SRCK high to SRFS (bl) low - Slave5 Delay from SRCK high to SRFS (wl) low - Slave5 STCK high to STXD enable from high impedance - Slave STCK high to STXD valid - Slave STFS high to STXD enable from high impedance (first bit) Slave STFS high to STXD valid (first bit) - Slave STCK high to STXD not valid - Slave STCK high to STXD high impedance - Slave SRXD Setup time before SRCK low - Slave SRXD Hold time after SRCK low - Slave Symbol fs tSCKW tSCKH tSCKL Min Typ — Max 102 — — — — 46 46 46 46 — — — — — 25 25 27 13 28.5 — — Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 504 504 — — — — TBD — — — — — — — — — tTFSBHS tTFSWHS tRFSBHS tRFSWHS tTFSBLS tTFSWLS tRFSBLS tRFSWLS tTXES tTXVS tFTXES tFTXVS tTXNVS tTXHIS tSS tHS 0.1 0.1 0.1 0.1 -1 -1 -46 -46 1 5.5 6 11 11 4 4 — — — — — — — 56F826 Technical Data, Rev. 14 42 Freescale Semiconductor Synchronous Serial Interface (SSI) Timing Table 3-14 SSI Slave Mode1 Switching Characteristics Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Parameter Symbol Min Typ Max Units Synchronous Operation (in addition to standard external clock parameters) SRXD Setup time before STCK low - Slave SRXD Hold time after STCK low - Slave 1. Slave mode is externally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the tables and in the figures. 4. 50% duty cycle 5. bl = bit length; wl = word length tTSS tTHS 4 4 — — — — 56F826 Technical Data, Rev. 14 Freescale Semiconductor 43 tSCKW tSCKH STCK input tTFSBHS STFS (bl) input tTFSWHS STFS (wl) input tFTXES tTXVS tTXES STXD SRCK input tRFSBHS SRFS (bl) input tRFSWHS SRFS (wl) input tSS SRXD tHS tTSS tTHS tRFSWLS First Bit tFTXVS tTXNVS tTXHIS Last Bit tTFSWLS tTFSBLS tSCKL tRFBLS Figure 3-25 Slave Mode Clock Timing 3.11 Quad Timer Timing Table 3-15 Timer Timing1, 2 Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period Symbol PIN PINHL POUT POUTHL Min 4T+6 2T+3 2T 1T Max — — — — Unit ns ns ns ns 1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. 56F826 Technical Data, Rev. 14 44 Freescale Semiconductor Serial Communication Interface (SCI) Timing Timer Inputs PIN PINHL PINHL Timer Outputs POUT POUTHL POUTHL Figure 3-26 Quad Timer Timing 3.12 Serial Communication Interface (SCI) Timing Table 3-16 SCI Timing4 Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Baud Rate1 RXD2 Pulse Width TXD3 Pulse Width Symbol BR RXDPW TXDPW Min — 0.965/BR 0.965/BR Max (fMAX*2.5)/(80) 1.04/BR 1.04/BR Unit Mbps ns ns 1. fMAX is the frequency of operation of the system clock in MHz. 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. RXD SCI receive data pin (Input) RXDPW Figure 3-27 RXD Pulse Width 56F826 Technical Data, Rev. 14 Freescale Semiconductor 45 TXD SCI receive data pin (Input) TXDPW Figure 3-28 TXD Pulse Width 3.13 JTAG Timing Table 3-17 JTAG Timing1, 3 Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic TCK frequency of operation2 TCK cycle time TCK clock pulse width TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time Symbol fOP tCY tPW tDS tDH tDV tTS tTRST tDE Min DC 100 50 0.4 1.2 — — 50 4T Max 10 — — — — 26.6 23.5 — — Unit MHz ns ns ns ns ns ns ns ns 1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. TCK frequency of operation must be less than 1/8 the processor rate. 3. Parameters listed are guaranteed by design. tCY tPW VIH tPW VM TCK (Input) VM = VIL + (VIH – VIL)/2 VM VIL Figure 3-29 Test Clock Input Timing Diagram 56F826 Technical Data, Rev. 14 46 Freescale Semiconductor JTAG Timing TCK (Input) TDI TMS (Input) TDO (Output) tTS tDS tDH Input Data Valid tDV Output Data Valid TDO (Output) tDV TDO (Output) Output Data Valid Figure 3-30 Test Access Port Timing Diagram TRST (Input) tTRST Figure 3-31 TRST Timing Diagram DE tDE Figure 3-32 OnCE—Debug Event 56F826 Technical Data, Rev. 14 Freescale Semiconductor 47 Part 4 Packaging 4.1 Package and Pin-Out Information 56F826 This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F826. TCK TCS DE TXD0 RXD0 VSS VDD TXD1 RXD1 TA0 TA1 TA2 TA3 SS MISO MOSI SCLK GPIOD7 GPIOD6 VSSIO VDDIO GPIOD5 GPIOD4 GPIOD3 GPIOD2 TMS TDI TDO TRST VDDIO VSSIO A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 VSS VDD A3 A2 A1 A0 EXTBOOT PIN 76 PIN 1 ORIENTATION MARK PIN 26 PIN 51 GPIOD1 GPIOD0 GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2 GPIOB1 GPIOB0 CLKO VDD VSS XTAL EXTAL VSSA VDDA VSSIO VDDIO STCK STFS STD SRCK SRFS SRD Figure 4-1 Top View, 56F826 100-pin LQFP Package 48 VDDIO VSSIO IRQA IRQB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 RESET D11 D12 D13 D14 D15 56F826 Technical Data, Rev. 14 Freescale Semiconductor RD WR DS PS Package and Pin-Out Information 56F826 Table 4-1 56F826 Pin Identification by Pin Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal Name TMS TDI TDO TRST VDDIO VSSIO A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 VSS VDD A3 A2 A1 A0 EXTBOOT Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name RD WR DS PS VDDIO VSSIO IRQA IRQB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 RESET D11 D12 D13 D14 D15 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name SRD SRFS SRCK STD STFS STCK VDDIO VSSIO VDDA VSSA EXTAL XTAL VSS VDD CLKO GPIOB0 GPIOB1 GPIOB2 GPIOB3 GPIOB4 GPIOB5 GPIOB6 GPIOB7 GPIOD0 GPIOD1 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name GPIOD2 GPIOD3 GPIOD4 GPIOD5 VDDIO VSSIO GPIOD6 GPIOD7 SCLK MOSI MISO SS TA3 TA2 TA1 TA0 RXD1 TXD1 VDD VSS RXD0 TXD0 DE TCS TCK 56F826 Technical Data, Rev. 14 Freescale Semiconductor 49 S 0.15(0.006) -TNOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.070 (0.003). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS DIM MIN MAX A 13.950 14.050 B 13.950 14.050 C 1.400 1.600 D 0.170 0.270 E 1.350 1.450 F 0.170 0.230 G 0.500 BSC H 0.050 0.150 J 0.090 0.200 K 0.500 0.700 M 12° REF N 0.090 0.160 Q 1° 5° R 0.150 0.250 S 15.950 16.050 V 15.950 16.050 W 0.200 REF X 1.000 REF INCHES MIN MAX 0.549 0.553 0.549 0.553 0.055 0.063 0.007 0.011 0.053 0.057 0.007 0.009 0.020 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12° REF 0.004 0.006 1° 5° 0.006 0.010 0.628 0.632 0.628 0.632 0.008 REF 0.039 REF S AC T-U S Z S S T-U S AC Z -ZB -UA 0.15(0.006) S V S 9 AB T-U S Z S AE AD -AB-AC96X G 0.100(0.004) AC (24X PER SIDE) SEATING PLANE AE M° R 0.25 (0.010) GAUGE PLANE D F N J C E H W K X DETAIL AD Q° 0.20(0.008) M AC T-U SECTION AE-AE S 0.15(0.006) S 0.15(0.006) AC Z S T-U S Z S CASE 842F-01 Figure 4-2 100-pin LQPF Mechanical Information Please see www.freescale.com for the most current case outline. 56F826 Technical Data, Rev. 14 50 Freescale Semiconductor Thermal Design Considerations Part 5 Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: TJ = T A + ( P D × Rθ JA ) Where: TA = ambient temperature °C RθJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: Rθ JA = R θ JC + R θ CA Where: RθJA = package junction-to-ambient thermal resistance °C/W RθJC = package junction-to-case thermal resistance °C/W RθCA = package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: • • Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction-to-board thermal resistance. 56F826 Technical Data, Rev. 14 Freescale Semiconductor 51 • Use the value obtained by the equation (TJ – TT)/PD, where TT is the temperature of the package case determined by a thermocouple. The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. 5.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation: • • Provide a low-impedance path from the board power supply to each VDD, VDDIO, and VDDA pin on the controller, and from the board ground to each VSS,VSSIO, and VSSA (GND) pin. The minimum bypass requirement is to place 0.1μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA and VDDIO/VSSIO. Ceramic and tantalum capacitors tend to provide better performance tolerances. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD, VDDIO, and VDDA and VSS, VSSIO, and VSSA (GND) pins are less than 0.5 inch per capacitor lead. Bypass the VDD and VSS layers of the PCB with approximately 100μF, preferably with a high-grade capacitor such as a tantalum capacitor. • • 56F826 Technical Data, Rev. 14 52 Freescale Semiconductor Electrical Design Considerations • • Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. Take special care to minimize noise levels on the VREF, VDDA and VSSA pins. When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device. Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs that do not require debugging functionality, such as consumer products, TRST should be tied low. Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. • • • • 56F826 Technical Data, Rev. 14 Freescale Semiconductor 53 Part 6 Ordering Information Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 6-1 56F826 Ordering Information Part 56F826 Supply Voltage 3.0–3.6 V 2.25-2.75 V 3.0–3.6 V 2.25-2.75 V Package Type Plastic Quad Flat Pack (LQFP) Pin Count 100 Ambient Frequency (MHz) 80 Order Number DSP56F826BU80 56F826 Plastic Quad Flat Pack (LQFP) 100 80 DSP56F826BU80E * *This package is RoHS compliant. 56F826 Technical Data, Rev. 14 54 Freescale Semiconductor Electrical Design Considerations 56F826 Technical Data, Rev. 14 Freescale Semiconductor 55 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56F826 Rev. 14 01/2007