56F8323

56F8323/56F8123 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8323 Rev. 17 04/2007 freescale.com Document Revision History Version History Rev 1.0 Rev 2.0 Rev 3.0 Description of Change Pre-Release version, Alpha customers only Initial Public Release Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional grammar issues. Added Package Pins to GPIO Table in Section 8. Removed reference to pin group 9 in Table 10-5. Replacing TBD Typical Min with values in Table 10-17. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters, Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing, Table 10-18, ADC Parameters, Table 10-24, and IO Loading Coefficients at 10MHz, Table 10-25. Updated values in Power-On Reset Low Voltage, Table 10-6. Correcting package pin numbers in Table 2-2, PhaseA0 changed from 38 to 52, PhaseB0 changed from 37 to 51, Index0 changed from 36 to 50, and Home0 changed from 35 to 49. All pin changes in Table 2-2 were do to data entry errors - This package pin-out has not changed Added Part 4.8, added addition text to Part 6.9 on POR reset, added the word “access” to FM Error Interrupt in Table 4-3, removed min and max numbers; only documenting Typ. numbers for LVI in Table 10-6. Updated numbers in Table 10-7 and Table 10-8 with more recent data. Corrected typo in Table 10-3 in Pd characteristics. Replace any reference to Flash Interface Unit with Flash Memory Module; changed example in Part 2.2; added note on VREFH and VREFLO in Table 2-2 and Table 11-1; added note to Vcap pin in Table 2-2; corrected typo FIVAL1 and FIVAH1 in Table 4-12; removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new graphs in Figure 10-21. Clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1. Added 56F8123 information; edited to indicate differences in 56F8323 and 56F8123.Reformatted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of electrical tables for consistency throughout the family. Clarified I/O power description in Table 2-2, added note to Table 10-7 and clarified Section 12.3 . Added output voltage maximum value and note to clarify in Table 10-1; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. Clarified value and unit measure for Maximum allowed PD in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4. Added new RoHS-compliant orderable part numbers in Table 13-1. Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in Table 10-4. Added RoHS-compliance and “pb-free” language to back cover. Rev 4.0 Rev 5.0 Rev 6.0 Rev 7.0 Rev 8.0 Rev 9.0 Rev 10.0 Rev. 11.0 Rev 12.0 Rev 13.0 56F8323 Technical Data, Rev. 17 2 Freescale Semiconductor Preliminary Document Revision History Version History Rev 14.0 Description of Change Added information/corrected state during reset in Table 2-2. Clarified external reference crystal frequency for PLL in Table 10-14 by increasing maximum value to 8.4MHz. Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2. • Added the following note to the description of the TMS signal in Table 2-2: Note: Always tie the TMS pin to VDD through a 2.2K resistor. • Added the following note to the description of the TRST signal in Table 2-2: Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. Rev. 17 Changed the “Frequency Accuracy” specification in Table 10-16 (was ±2.0%, is +2 / -3%). Rev 15.0 Rev. 16 Please see http://www.freescale.com for the most current data sheet revision. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 3 56F8323 Technical Data, Rev. 17 4 Freescale Semiconductor Preliminary 56F8323/56F8123 General Description Note: Features in italics are NOT available in the 56F8123 device. • Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 32KB Program Flash • 4KB Program RAM • 8KB Data Flash • 8KB Data RAM • 8KB Boot Flash • One 6-channel PWM module • Two 4-channel 12-bit ADCs • Temperature Sensor • One Quadrature Decoder • One FlexCAN module • Up to two Serial Communication Interfaces (SCIs) • Up to two Serial Peripheral Interfaces (SPIs) • Two general-purpose Quad Timers • Computer Operating Properly (COP)/Watchdog • On-Chip Relaxation Oscillator • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 27 GPIO lines • 64-pin LQFP Package RESET 5 6 3 3 OCR_DIS VCAP 4 VDD 4 4 VSS VDDA 2 VSSA PWM Outputs Current Sense Inputs Fault Inputs PWMA or SPI1 or GPIOA Program Controller and Hardware Looping Unit JTAG/ EOnCE Port Digital Reg Analog Reg 16-Bit 56800E Core Low Voltage Supervisor Bit Manipulation Unit Address Generation Unit Data ALU 16 x 16 + 36 −> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators 4 4 5 AD0 AD1 VREF TEMP_SENSE PAB PDB CDBR CDBW Memory Program Memory 16K x 16 Flash 2K x 16 RAM 4K x 16 Boot Flash Data Memory 4K x 16 Flash 4K x 16 RAM R/W Control XDB2 XAB1 XAB2 PAB PDB CDBR CDBW 4 Quadrature Decoder 0 or Quad Timer A or GPIO B System Bus Control IPBus Bridge (IPBB) 3 Quad Timer C or SCI0 or GPIOC FlexCAN or GPIOC Peripheral Device Selects RW Control IPAB IPWDB IPRDB 2 Decoding Peripherals Clock resets PLL SPI0 or SCI1 or GPIOB 4 COP/ Watchdog Interrupt Controller System O Integration R Module P O Clock S Generator* C XTAL or GPIOC EXTAL or GPIOC IRQA *Includes On-Chip Relaxation Oscillator 56F8323/56F8123 Block Diagram 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 5 Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 7 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8323/56F8123 Features . . . . . . . . . . . . . 7 Device Description . . . . . . . . . . . . . . . . . . . . 9 Award-Winning Development Environment 10 Architecture Block Diagram . . . . . . . . . . . . 11 Product Documentation . . . . . . . . . . . . . . . 15 Data Sheet Conventions . . . . . . . . . . . . . . . 15 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . 102 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 102 8.2. Configuration. . . . . . . . . . . . . . . . . . . . . . . 102 8.3. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 104 Part 9: Joint Test Action Group (JTAG) . . 104 9.1. JTAG Information . . . . . . . . . . . . . . . . . . . 104 Part 2: Signal/Connection Descriptions . . 16 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 19 Part 10: Specifications. . . . . . . . . . . . . . . . 105 10.1. General Characteristics . . . . . . . . . . . . . . 105 10.2. DC Electrical Characteristics. . . . . . . . . . 109 10.3. AC Electrical Characteristics . . . . . . . . . . 113 10.4. Flash Memory Characteristics. . . . . . . . . 114 10.5. External Clock Operation Timing . . . . . . 114 10.6. Phase Locked Loop Timing . . . . . . . . . . . 115 10.7. Crystal Oscillator Parameters . . . . . . . . . 115 10.8. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . 117 10.9. Serial Peripheral Interface (SPI) Timing . . 119 10.10. Quad Timer Timing . . . . . . . . . . . . . . . . 122 10.11. Quadrature Decoder Timing . . . . . . . . . . 122 10.12. Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . 123 10.13. Controller Area Network (CAN) Timing . 124 10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 124 10.15. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . 126 10.16. Equivalent Circuit for ADC Inputs . . . . . 129 10.17. Power Consumption . . . . . . . . . . . . . . . . 129 Part 3: On-Chip Clock Synthesis (OCCS) . . 30 3.1. 3.2. 3.3. 3.4. 3.5. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . External Clock Operation . . . . . . . . . . . . . . Use of On-Chip Relaxation Oscillator . . . . . Internal Clock Operation . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 32 33 Part 4: Memory Map. . . . . . . . . . . . . . . . . . . 33 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . Program Map. . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Table . . . . . . . . . . . . . . . . . Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Map . . . . . . . . . . . . . . . . . . . EOnCE Memory Map . . . . . . . . . . . . . . . . . Peripheral Memory Mapped Registers . . . . Factory Programmed Memory. . . . . . . . . . . 33 33 34 37 37 39 40 56 Part 5: Interrupt Controller (ITCN) . . . . . . . . 57 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 57 57 59 59 60 82 Part 11: Packaging 131 11.1. 56F8323 Package and Pin-Out Information . . . . . . . . . . . . . . . . . . 131 11.2. 56F8123 Package and Pin-Out Information . . . . . . . . . . . . . . . . . 133 Part 6: System Integration Module (SIM) . . 83 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. 6.9. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . Operating Mode Register . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . Clock Generation Overview. . . . . . . . . . . . . Power-Down Modes . . . . . . . . . . . . . . . . . . Stop and Wait Mode Disable Function . . . . Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 83 84 84 85 97 97 98 98 Part 12: Design Considerations . . . . . . . . 136 12.1. Thermal Design Considerations . . . . . . . 136 12.2. Electrical Design Considerations . . . . . . . 137 12.3. Power Distribution and I/O Ring Implementation . . . . . . . . . . . . . . 138 Part 13: Ordering Information . . . . . . . . . . 139 Part 7: Security Features . . . . . . . . . . . . . . 99 7.1. Operation with Security Enabled . . . . . . . . 99 7.2. Flash Access Blocking Mechanisms . . . . . . 99 56F8323 Technical Data, Rev. 17 6 Freescale Semiconductor Preliminary 56F8323/56F8123 Features Part 1 Overview 1.1 56F8323/56F8123 Features 1.1.1 • • • • • • • • • • • • • • Core Efficient 16-bit 56800E family engine with dual Harvard architecture Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits Arithmetic and logic multi-bit shifter Parallel instruction set with unique addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/EOnCE debug programming interface 1.1.2 Differences Between Devices Table 1-1 outlines the key differences between the 56F8323 and 56F8123 devices. Table 1-1 Device Differences Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quadrature Decoder Temperature Sensor Dedicated GPIO 56F8323 60MHz/60 MIPS 4KB 8KB 1x6 1 1x4 1 — 56F8123 40MHz/40 MIPS Not Available Not Available Not Available Not Available Not Available Not Available 10 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 7 1.1.3 • • • Memory Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security protection On-chip memory, including a low-cost, high-volume Flash solution — 32KB of Program Flash — 4KB of Program RAM — 8KB of Data Flash — 8KB of Data RAM — 8KB of Boot Flash Note: Features in italics are NOT available in the 56F8123 device. • EEPROM emulation capability 1.1.4 • • • • Peripheral Circuits One Pulse Width Modulator module with six PWM outputs, three Current Sense inputs and three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with dual, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, channel 2 Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the on-chip temperature Two 16-bit Quad Timer modules (TMR) totaling seven pins: — In the 56F8323, Timer A works in conjunction with Quad Decoder 0 and Timer C works in conjunction with the PWMA and ADCA — In the 56F8123, Timer C works in conjunction with ADCA One Quadature Decoder which works in conjunction with Quad Timer A FlexCAN (CAN Version 2.0 B-compliant) module with 2-pin port for transmit and receive Up to two Serial Communication Interfaces (SCIs) Up to two Serial Peripheral Interfaces (SPIs) Computer Operating Properly (COP)/Watchdog timer One dedicated external interrupt pin 27 General Purpose I/O (GPIO) pins Integrated Power-On Reset and Low-Voltage Interrupt Module JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent, real-time debugging Software-programmable, Phase Lock Loop (PLL) On-chip relaxation oscillator Note: Features in italics are NOT available in the 56F8123 device. • • • • • • • • • • • 56F8323 Technical Data, Rev. 17 8 Freescale Semiconductor Preliminary Device Description 1.1.5 • • • • • • Energy Information Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power 1.2 Device Description The 56F8323 and 56F8123 are members of the 56800E core-based family of controllers. Each combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of their low cost, configuration flexibility, and compact program code, the 56F8323 and 56F8123 are well-suited for many applications. The devices include many peripherals that are especially useful for automotive control (56F8323 only); industrial control and networking; motion control; home appliances; general purpose inverters; smart sensors; fire and security systems; power management; and medical monitoring applications. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C Compilers to enable rapid development of optimized control applications. The 56F8323 and 56F8123 support program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide one external dedicated interrupt line and up to 27 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. 1.2.1 56F8323 Features The 56F8323 controller includes 32KB of Program Flash and 8KB of Data Flash, each programmable through the JTAG port, with 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F8323 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and is also capable of supporting six independent PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 9 synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1/2 (center-aligned mode only) to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters (ADCs) through Quad Timer C, Channel 2. The 56F8323 incorporates one Quadrature Decoder capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), two Quad Timers, and FlexCAN. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A Flex Controller Area Network (FlexCAN) interface (CAN Version 2.0 B-compliant) and an internal interrupt controller are also a part of the 56F8323. 1.2.2 56F8123 Features The 56F8123 controller includes 32KB of Program Flash, programmable through the JTAG port, and 8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program Flash memory area. The Program Flash memory can be independently bulk erased or erased in pages; Program Flash page erase size is 1KB. The Boot Flash memory can also be either bulk or page erased. This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), and two Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An internal interrupt controller is also a part of the 56F8123. 1.3 Award-Winning Development Environment Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 56F8323 Technical Data, Rev. 17 10 Freescale Semiconductor Preliminary Architecture Block Diagram 1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8123 device and are shaded in the following figures. The 56F8323/56F8123 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the on-board regulator and power and ground signals. They also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see Part 2 Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals. Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The Timer C, Channel 2, output can generate periodic start (SYNC) signals to the ADC to start its conversions. In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer C, Channel 2, input as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 11 5 JTAG / EOnCE Boot Flash pdb_m[15:0] pab[20:0] Program Flash Program RAM cdbw[31:0] CHIP TAP Controller 56800E TAP Linking Module xab1[23:0] xab2[23:0] Data RAM External JTAG Port cdbr_m[31:0] xdb2_m[15:0] Data Flash IPBus Bridge To Flash Control Logic NOT available on the 56F8123 device. Flash Memory Module IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. The primary data RAM port is 32 bits wide. Other data ports are 16 bits. Note: 56F8323 Technical Data, Rev. 17 12 Freescale Semiconductor Preliminary Architecture Block Diagram To/From IPBus Bridge CLKGEN (OSC/PLL) (ROSC) Timer A Interrupt Controller Low-Voltage Interrupt POR & LVI 4 Quadrature Decoder 0 System POR SIM RESET COP Reset 2 FlexCAN COP SPI 1 4 SPI 0 PWM A 8 SYNC Output GPIO A GPIO B GPIO C Timer C ch2o 4 2 SCI 1 SCI 0 2 ch2i 3 ADCA TEMP_SENSE NOT available on the 56F8123 device. IPBus 8 Figure 1-2 Peripheral Subsystem 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 13 Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] cdbw[15:0] pab[20:0] cdbr_m[31:0] cdbw[31:0] xab1[23:0] Program data bus for instruction word fetches or read operations. Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus Primary core data bus for memory reads. Addressed via xab1 bus. Primary core data bus for memory writes. Addressed via xab1 bus. Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O. Secondary Data Memory Interface xdb2_m[15:0] xab2[23:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads. Secondary data address bus used for the second of two simultaneous accesses. Capable of addressing only words. Data is returned on xdb2_m. Peripheral Interface Bus IPBus [15:0] Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate as the Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m. 1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0. 56F8323 Technical Data, Rev. 17 14 Freescale Semiconductor Preliminary Product Documentation 1.5 Product Documentation The documents listed in Table 1-3 are required for a complete description and proper design with the 56F8323 and 56F8123 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com/semiconductors. Table 1-3 Chip Documentation Topic DSP56800E Reference Manual Description Detailed description of the 56800E family architecture, 16-bit controller core processor, and the instruction set Order Number DSP56800ERM MC56F8300UM MC56F83xxBLUM 56F8300 Peripheral User Detailed description of peripherals of the 56800E family Manual of devices 56F8300 SCI/CAN Bootloader User Manual 56F8323/56F8123 Technical Data Sheet Errata Detailed description of the SCI/CAN Bootloaders 56F8300 family of devices Electrical and timing specifications, pin descriptions, and MC56F8323 package descriptions (this document) Details any chip issues that might be present MC56F8323E MC56F8123E 1.6 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL “asserted” “deasserted” Examples: 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 15 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8323 and 56F8123 are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2. In Table 2-2, each table row describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Number of Pins in Package Functional Group 56F8323 Power (VDD or VDDA) Power Option Control Ground (VSS or VSSA) Supply Capacitors1 & VPP2 PLL and Clock Interrupt and Program Control Pulse Width Modulator (PWM) Ports3 Serial Peripheral Interface (SPI) Port 04 Quadrature Decoder Port 05 CAN Ports Analog-to-Digital Converter (ADC) Ports Timer Module Port C6 Timer Module Port A JTAG/Enhanced On-Chip Emulation (EOnCE) Temperature Sensse Dedicated GPIO 2. The VPP input shares the IRQA input 3. Pins in this section can function as SPI #1 and GPIO 4. Pins in this section can function as SCI #1 and GPIO 5. Alternately, can function as Quad Timer A pins or GPIO 6. Two pins can function as SCI #0 and GPIO Note: See Table 1-1 for 56F8123 functional differences. 56F8123 6 1 5 4 2 2 — 8 — — 13 3 4 5 — 10 6 1 5 4 2 2 12 4 4 2 13 3 — 5 1 — 1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs 56F8323 Technical Data, Rev. 17 16 Freescale Semiconductor Preliminary Introduction Power Power Ground Power Ground VDD_IO VDDA_OSC_PLL VSS VDDA_ADC VSSA_ADC 4 1 4 1 1 1 1 1 1 PHASEA0 (TA0, GPIOB7) PHASEB0 (TA1, GPIOB6) INDEX0 (TA2, GPIOB5) HOME0 (TA3, GPIOB4) Quadrature Decoder 0 or Quad Timer A or GPIO 1 Other Supply Ports VCAP1 - VCAP4 OCR_DIS 4 1 1 1 SCLK0 (GPIOB3) MOSI0 (GPIOB2) MISO0 (RXD1, GPIOB1) SS0 (TXD1, GPIOB0) SPI0 or SCI1 or GPIO PLL and Clock or GPIO EXTAL (GPIOC0) XTAL (GPIOC1) 56F8323 1 1 1 2 1 1 1 1 3 3 1 8 5 PWMA0-1 (GPIOA0-1) PWMA2 (SS1, GPIOA2) PWMA3 (MISO1, GPIOA3) PWMA4 (MOSI1, GPIOA4) PWMA5 (SCLK1, GPIOA5) FAULTA0 - 2 (GPIOA6-8) ISA0 - 2 (GPIOA9-11) TEMP_SENSE ANA0 - 7 VREF CAN_RX (GPIOC2) CAN_TX (GPIOC3) PWMA or SPI1 or GPIO Temperature Sensor ADCA 1 1 FlexCAN or GPIO 1 TCK JTAG/ EOnCE Port TMS TDI TDO TRST 1 1 1 1 1 1 1 1 1 TC0 (TXD0, GPIOC6) TC1 (RXD0, GPIOC5) TC3 (GPIOC4) QUAD TIMER C or SCI0 or GPIO INTERRUPT/ PROGRAM CONTROL IRQA (VPP) RESET Figure 2-1 56F8323 Signals Identified by Functional Group (64-Pin LQFP) 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 17 Power Power Ground Power Ground VDD_IO VDDA_OSC_PLL VSS VDDA_ADC VSSA_ADC 4 1 4 1 1 1 1 1 1 TA0 (GPIOB7) TA1 (GPIOB6) TA2 (GPIOB5) TA3 (GPIOB4) Quad Timer A or GPIO 1 Other Supply Ports VCAP1 - VCAP4 OCR_DIS 4 1 1 1 SCLK0 (GPIOB3) MOSI0 (GPIOB2) MISO0 (RXD1, GPIOB1) SS0 (TXD1, GPIOB0) SPI0 or SCI1 or GPIO PLL and Clock or GPIO EXTAL (GPIOC0) XTAL (GPIOC1) 56F8123 1 1 1 2 1 1 1 1 3 3 GPIOA0-1 SS1 (GPIOA2) MISO1 (GPIOA3) MOSI1 (GPIOA4) SCLK1 (GPIOA5) GPIOA6-8 GPIOA9-11 SPI1 or GPIO 8 5 ANA0 - 7 VREF GPIOC2 GPIOC3 GPIO ADCA 1 1 1 TCK JTAG/ EOnCE Port TMS TDI TDO TRST 1 1 1 1 1 1 1 1 1 TC0 (TXD0, GPIOC6) TC1 (RXD0, GPIOC5) TC3 (GPIOC4) QUAD TIMER C or SCI0 or GPIO IRQA (VPP) RESET INTERRUPT/ PROGRAM CONTROL Figure 2-2 56F8123 Signals Identified by Functional Group (64-Pin LQFP) 56F8323 Technical Data, Rev. 17 18 Freescale Semiconductor Preliminary Signal Pins 2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). In the 56F8123, after reset, each pin must be configured for the desired function. The initialization software will configure each pin for the function listed first for each pin, as shown in Table 2-2. Any alternate functionality must be programmed. Note: Signals in italics are not available in the 56F8123 device. If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other states show the reset condition of the alternate function, which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral. For example, the SCLK0/GPIOB3 pin shows that it is tri-stated during reset. If the GPIOB_PER is changed to select the GPIO function of the pin, it will become an input if no other registers are changed. Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name VDD_IO VDD_IO VDD_IO VDD_IO VDDA_OSC_PLL Pin No. 6 20 48 59 42 Supply Oscillator and PLL Power — This pin supplies 3.3V power to the OSC and to the internal regulator that in turn supplies the Phase Locked Loop. It must be connected to a clean analog power supply. ADC Power — This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. Ground — These pins provide ground for chip logic and I/O drivers. Type Supply State During Reset Signal Description I/O Power — This pin supplies 3.3V power to the chip I/O interface and also the Processor core throught the on-chip voltage regulator, if it is enabled. VDDA_ADC VSS VSS VSS VSS VSSA_ADC 41 Supply 11 17 44 60 39 Supply Supply ADC Analog Ground — This pin supplies an analog ground to the ADC modules. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 19 Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name VCAP1 VCAP2 VCAP3 VCAP4 Pin No. 57 23 5 43 When OCR_DIS is tied to VDD, (regulator disabled), these pins become VDD_CORE and should be connected to a regulated 2.5V power supply. Note: This bypass is required even if the chip is powered with an external supply. OCR_DIS 45 On-Chip Regulator Disable — Tie this pin to VSS to enable the on-chip regulator Tie this pin to VDD to disable the on-chip regulator This pin is intended to be a static DC signal from power-up to shut down. Do not try to toggle this pin for power savings during operation. EXTAL 46 Input Input External Crystal Oscillator Input — This input can be connected to an 8MHz external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to VSS. The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL. (GPIOC0) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is an EXTAL input with pull-ups disabled. XTAL 47 Output Output Crystal Oscillator Output — This output can be connected to an 8MHz external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to VSS. The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL. (GPIOC1) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is an XTAL input with pull-ups disabled. TCK 53 Schmitt Input Input, pulled low internally Test Clock Input — This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-down resistor. A Schmitt trigger input is used for noise immunity. Type Supply State During Reset Supply Signal Description VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled), connect each pin to a 2.2μF or greater bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. 56F8323 Technical Data, Rev. 17 20 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name TMS Pin No. 54 Type Schmitt Input State During Reset Input, pulled high internally Signal Description Test Mode Select Input — This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Note: TDI 55 Schmitt Input Input, pulled high internally In reset, output is disabled, pull-up is enabled Input, pulled high internally Always tie the TMS pin to VDD through a 2.2K resistor. Test Data Input — This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. TDO 56 Output TRST 58 Schmitt Input Test Reset — As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and the EOnCE/JTAG module must not be reset. In this case, assert RESET, but do not assert TRST. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register. Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. PHASEA0 52 Schmitt Input Schmitt Input/ Output Schmitt Input/ Output Output Input, pull-up enabled Phase A — Quadrature Decoder 0, PHASEA input (TA0) TA0 — Timer A, Channel 0 (GPIOB7) Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (oscillator_ clock) Clock Output - can be used to monitor the internal oscillator clock signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR). In the 56F8323, the default state after reset is PHASEA0. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 21 Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name PHASEB0 Pin No. 51 Type Schmitt Input Schmitt Input/ Output Schmitt Input/ Output Output State During Reset Input, pull-up enabled Signal Description Phase B — Quadrature Decoder 0, PHASEB input (TA1) TA1 — Timer A ,Channel 1 (GPIOB6) Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (SYS_CLK2) Clock Output - can be used to monitor the internal SYS_CLK2 signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR). In the 56F8323, the default state after reset is PHASEB0. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. INDEX0 50 Schmitt Input Input, pull-up enabled Index — Quadrature Decoder 0, INDEX input (TA2) Schmitt Input/ Output Schmitt Input/ Output Output TA2 — Timer A, Channel 2 (GPIOB5) Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (SYS_CLK) Clock Output - can be used to monitor the internal SYS_CLK signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR). In the 56F8323, the default state after reset is INDEX0. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. 56F8323 Technical Data, Rev. 17 22 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name HOME0 Pin No. 49 Type Schmitt Input Schmitt Input/ Output Schmitt Input/ Output Output State During Reset Input, pull-up enabled Signal Description Home — Quadrature Decoder 0, HOME input (TA3) TA3 — Timer A, Channel 3 (GPIOB4) Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (prescaler_ clock) Clock Output - can be used to monitor the internal prescaler_clock signal (see Part 6.5.7 CLKO Select Register, SIM_CLKOSR). In the 56F8323, the default state after reset is HOME0. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. SCLK0 25 Schmitt Input/ Output Input, pull-up enabled SPI 0 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCLK0. (GPIOB3) Schmitt Input/ Output MOSI0 24 Schmitt Input/ Output In reset, output is disabled, pull-up is enabled SPI 0 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is MOSI0. (GPIOB2) Schmitt Input/ Output 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 23 Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name MISO0 Pin No. 22 Type Schmitt Input/ Output State During Reset Input, pull-up enabled Signal Description SPI 0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. Receive Data — SCI1 receive data input (RXD1) Schmitt Input Schmitt Input/ Output (GPIOB1) Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is MISO0. SS0 21 Schmitt Input Output Schmitt Input/ Output Input, pull-up enabled SPI 0 Slave Select — SS0 is used in slave mode to indicate to the SPI module that the current transfer is to be received. Transmit Data — SCI1 transmit data output Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SS0. (TXD1) (GPIOB0) PWMA0 (GPIOA0) 3 Output Schmitt Input/ Output In reset, output is disabled, pull-up is enabled PWMA0 — This is one of six PWMA output pins. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is PWMA0. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. PWMA1 (GPIOA1) 4 Output Schmitt Input/ Output In reset, output is disabled, pull-up is enabled PWMA1 — This is one of six PWMA output pins. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is PWMA1. In the 56F8123, the default state is not one of the functions offered and must be reconfigured 56F8323 Technical Data, Rev. 17 24 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name PWMA2 (SS1) Pin No. 7 Type Output Schmitt Input Schmitt Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description PWMA2 — This is one of six PWMA output pins. SPI 1 Slave Select — SS1 is used in slave mode to indicate to the SPI module that the current transfer is to be received. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is PWMA2. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. PWMA3 (MISO1) 8 Output Schmitt Input/ Output In reset, output is disabled, pull-up is enabled PWMA3 — This is one of six PWMA output pins. SPI 1 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is PWMA3. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. PWMA4 (MOSI1) 9 Output Schmitt Input/ Output In reset, output is disabled, pull-up is enabled PWMA4 — This is one of six PWMA output pins. SPI 1 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is PWMA4. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. (GPIOA2) (GPIOA3) Schmitt Input/ Output (GPIOA4) Schmitt Input/ Output 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 25 Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name PWMA5 (SCLK1) Pin No. 10 Type Output Schmitt Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description PWMA5 — This is one of six PWMA output pins. SPI 1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is PWMA5. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. FAULTA0 13 Schmitt Input Schmitt Input/ Output Input FAULTA0 — This fault input pin is used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is FAULTA0. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. FAULTA1 14 Schmitt Input Schmitt Input/ Output Input FAULTA1 — This fault input pin is used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is FAULTA1. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. FAULTA2 15 Schmitt Input Schmitt Input/ Output Input FAULTA2 — This fault input pin is used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is FAULTA2. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. (GPIOA5) Schmitt Input/ Output (GPIOA6) (GPIOA7) (GPIOA8) 56F8323 Technical Data, Rev. 17 26 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name ISA0 Pin No. 16 Type Schmitt Input Schmitt Input/ Output State During Reset Input, pull-up enabled Signal Description ISA0 — This input current status pin is used for top/bottom pulse width correction in complementary channel operation for PWMA. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is ISA0. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. ISA1 18 Schmitt Input Schmitt Input/ Output Input, pull-up enabled ISA1 — This input current status pin is used for top/bottom pulse width correction in complementary channel operation for PWMA. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is ISA1. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. ISA2 19 Schmitt Input Schmitt Input/ Output Input, pull-up enabled ISA2 — This input current status pin is used for top/bottom pulse width correction in complementary channel operation for PWMA. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is ISA2. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 VREFH 26 27 28 29 30 31 32 33 40 Schmitt Input Analog Input VREFH — Analog Reference Voltage High Input Analog Input ANA4 - 7 — Analog inputs to ADCA, Channel 1 Input Analog Input ANA0 - 3 — Analog inputs to ADCA, Channel 0 (GPIOA9) (GPIOA10) (GPIOA11) 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 27 Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name VREFP VREFMID VREFN VREFLO Pin No. 37 36 35 38 Schmitt Input Output Analog Input VREFLO — Analog Reference Voltage Low. This should normally be connected to a low-noise VSS. Analog Output Temperature Sense Diode — This signal connects to an on-chip diode that can be connected to one of the ADC inputs and used to monitor the temperature of the die. Must be bypassed with a 0.01μF capacitor FlexCAN Receive Data — This is the CAN input. This pin has an internal pull-up resistor. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is CAN_RX. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. CAN_TX 62 Open Drain Output Open Drain Output FlexCAN Transmit Data — CAN output with internal pull-up enable at reset.* * Note: If a pin is configured as open drain output mode, internal pull-up will automatically be disabled when it outputs low. Internal pull-up will be enabled unless it has been manually disabled by clearing the corresponding bit in the PUREN register of the GPIO module, when it outputs high. If a pin is configured as push-pull output mode, internal pull-up will automatically be disabled, whether it outputs low or high. (GPIOC3) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. In the 56F8323, the default state after reset is CAN_TX. In the 56F8123, the default state is not one of the functions offered and must be reconfigured. Type Input/ Output State During Reset Signal Description Analog Input/ VREFP, VREFMID & VREFN — Internal pins for voltage reference which Output are brought off-chip so that they can be bypassed. Connect to a 0.1μF ceramic low ESR capacitor TEMP_SENSE 34 CAN_RX 61 Schmitt Input Schmitt Input/ Output Input, pull-up enabled (GPIOC2) 56F8323 Technical Data, Rev. 17 28 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 64-Pin LQFP Signal Name TC0 Pin No. 1 Type Schmitt Input/ Output Input Schmitt Input/ Output State During Reset Input, pull-up enabled Signal Description TC0 — Timer C, Channel 0 (TXD0) (GPIOC6) Transmit Data — SCI0 transmit data output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TC0. TC1 64 Schmitt Input/ Output Schmitt Input Schmitt Input/ Output Input, pull-up enabled TC1 — Timer C, Channel 1 (RXD0) Receive Data — SCI0 receive data input (GPIOC5) Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TC1. TC3 63 Schmitt Input/ Output Schmitt Input/ Output Input, pull-up enabled TC3 — Timer C Channel 3 (GPIOC4) Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TC3. IRQA 12 Schmitt Input Input, pull-up enabled External Interrupt Request A — The IRQA input is an asynchronous external interrupt request during Stop and Wait mode operation. During other operating modes, it is a synchronized external interrupt request which indicates an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered VPP — This pin is used for Flash debugging purposes. (VPP) RESET 2 Input Schmitt Input Input, pull-up enabled Reset — This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and the JTAG/EOnCE module must not be reset. In this case, assert RESET, but do not assert TRST. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 29 Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. 3.2 External Clock Operation The system clock can be derived from an external crystal, ceramic resonator, or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic resonator must be connected between the EXTAL and XTAL pins. 3.2.1 Crystal Oscillator The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown in Figure 3-1. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL Rz CLKMODE = 0 EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 750 KΩ Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg Ω CL1 CL2 Figure 3-1 Connecting to a Crystal Oscillator Note: The OCCS_COHL bit should be set to 1 when a crystal oscillator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User Manual. 3.2.2 Ceramic Resonator (Default) It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-2. Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins. 56F8323 Technical Data, Rev. 17 30 Freescale Semiconductor Preliminary Use of On-Chip Relaxation Oscillator Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 2 Terminal 3 Terminal EXTAL XTAL Rz EXTAL XTAL Rz Sample External Ceramic Resonator Parameters: Rz = 750 KΩ CL1 CL2 CLKMODE = 0 C1 C2 Figure 3-2 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a crystal resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User Manual. 3.2.3 External Clock Source The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to XTAL and the EXTAL pin is grounded. The external clock input must be generated using a relatively low impedance driver, as the XTAL pin is actually the output pin of the oscillator (it has a very weak driver). XTAL External Clock EXTAL VSS Note: When using an external clocking source with this configuration, the “CLKMODE” and COHL bits of the OSCTL register should be set to 1. Figure 3-3 Connecting an External Clock Signal 3.3 Use of On-Chip Relaxation Oscillator An internal relaxtion oscillator can supply the reference frequency when an external frequency source of crystal is not used. During a boot or reset sequence, the relaxation oscillator is enabled by default, and the PRECS bit in the PLLCR word is set to 0. If an external oscillator is connected, the relaxation oscillator can be deselected instead by setting the PRECS bit in the PLLCR to 1. If a changeover between internal and external oscillators is required at start up, internal device circuits compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not switched until the desired clock is enabled and stable. To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.1% of 8MHz by trimming an internal capacitor. Bits 0-9 of the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset value 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 31 to increase or decrease capacitance. Upon power-up, the default value of this trim is 512 units. Each unit added or deleted changes the output frequency by about 0.1%, allowing incremental adjustment until the desired frequency accuracy is achieved. The internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the 56F8300 Peripherals User Manual. 3.4 Internal Clock Operation At reset, both oscillators will be powered up; however, the relaxation oscillator will be the default clock reference for the PLL. Software should power down the block not being used and program the PLL for the correct frequency. CLK_MODE Relaxation OSC MUX XTAL Crystal OSC EXTAL MUX PRECS ZSRC SYS_CLK2 source to the SIM PLLCID FREF PLLDB PLLCOD Prescaler ÷ (1, 2, 4, 8) PLL x (1 to 128) FEEDBACK FOUT ÷2 FOUT/2 Postscaler ÷ (1, 2, 4, 8) Postscaler CLK MSTR_OSC Bus Interface & Control MUX LCK Bus Interface Lock Detector Loss of Reference Clock Detector loss of reference clock interrupt Figure 3-4 Internal Clock Operation 56F8323 Technical Data, Rev. 17 32 Freescale Semiconductor Preliminary Registers 3.5 Registers When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the register definitions with the internal Relaxation Oscillator, since the 56F8323 and 56F8123 contain this oscillator. Part 4 Memory Map 4.1 Introduction The 56F8323 and 56F8123 devices are 16-bit motor-control chips based on the 56800E core. These parts use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM and Flash memories are used in both spaces. This section provides memory maps for: • • Program Address Space, including the Interrupt Vector Table Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 4-1. Note: Data Flash and Program RAM are NOT available on the 56F8123 device. Table 4-1 Chip Memory Configurations On-Chip Memory Program Flash 56F8323 32KB 56F8123 32KB Use Restrictions Erase / Program via Flash interface unit and word writes to CDBW Erase / Program via Flash interface unit and word writes to CDBW. Data Flash can be read via either CDBR or XDB2, but not by both simultaneously None None Erase / Program via Flash Interface unit and word writes to CDBW Data Flash 8KB — Program RAM Data RAM Program Boot Flash 4KB 8KB 8KB — 8KB 8KB 4.2 Program Map The Program Memory map is located in Table 4-2. The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program Memory map. Because the 56F8323 and 56F8123 do not include EMI, the OMR MA bit, which is used to decide internal or external BOOT, will have no effect on the Program Memory Map. OMR MB reflects the security status of the Program Flash. After reset, changing the OMR MB bit will have no effect on the Program Flash. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 33 Note: Program RAM is NOT available on the 56F8123 device. Table 4-2 Program Memory Map at Reset Begin/End Address P: $1F FFFF P: $03 0000 P: $02 FFFF P: $02 F800 P: $02 F7FF P: $02 1000 P: $02 0FFF P: $02 0000 RESERVED On-Chip Program RAM 4KB RESERVED Boot Flash 8KB Cop Reset Address = $02 0002 Boot Location = $02 0000 RESERVED Internal Program Flash 32KB Memory Allocation P: $01 FFFF P: $00 4000 P: $00 3FFF P: $00 0000 4.3 Interrupt Vector Table Table 4-3 provides the device’s reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA). Please see Part 5.6.11 for the reset value of the VBA. In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. Note: PWMA, CAN and Quadrature Decoder are NOT available on the 56F8123 device. Table 4-3 Interrupt Vector Table Contents1 Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function Reserved for Reset Overlay2 Reserved for COP Reset Overlay2 core core 2 3 3 3 P:$04 P:$06 Illegal Instruction SW Interrupt 3 56F8323 Technical Data, Rev. 17 34 Freescale Semiconductor Preliminary Interrupt Vector Table Table 4-3 Interrupt Vector Table Contents1 (Continued) Peripheral core core core core Vector Number 4 5 6 7 3 3 1-3 1-3 Priority Level Vector Base Address + P:$08 P:$0A P:$0C P:$0E HW Stack Overflow Misaligned Long Word Access OnCE Step Counter OnCE Breakpoint Unit 0 Reserved core core core 9 10 11 1-3 1-3 1-3 P:$12 P:$14 P:$16 OnCE Trace Buffer OnCE Transmit Register Empty OnCE Receive Register Full Reserved core core core core 14 15 16 17 2 1 0 0-2 P:$1C P:$1E P:$20 P:$22 SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 IRQA Reserved LVI PLL FM FM FM 20 21 22 23 24 0-2 0-2 0-2 0-2 0-2 P:$28 P:$2A P:$2C P:$2E P:$30 Low-Voltage Detector (power sense) PLL FM Access Error Interrupt FM Command Complete FM Command, data and address Buffers Empty Reserved FLEXCAN FLEXCAN FLEXCAN FLEXCAN 26 27 28 29 0-2 0-2 0-2 0-2 P:$34 P:$36 P:$38 P:$3A FLEXCAN Bus Off FLEXCAN Error FLEXCAN Wake Up FLEXCAN Message Buffer Interrupt Reserved GPIOC GPIOB GPIOA 33 34 35 0-2 0-2 0-2 P:$42 P:$44 P:$46 GPIO C GPIO B GPIO A Reserved SPI1 SPI1 SPI0 SPI0 SCI1 SCI1 38 39 40 41 42 43 0-2 0-2 0-2 0-2 0-2 0-2 P:$4C P:$4E P:$50 P:$52 P:$54 P:$56 SPI 1 Receiver Full SPI 1 Transmitter Empty SPI 0 Receiver Full SPI 0 Transmitter Empty SCI 1 Transmitter Empty SCI 1Transmitter Idle Reserved Interrupt Function 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 35 Table 4-3 Interrupt Vector Table Contents1 (Continued) Peripheral SCI1 SCI1 Vector Number 45 46 Priority Level 0-2 0-2 Vector Base Address + P:$5A P:$5C SCI 1 Receiver Error SCI 1 Receiver Full Reserved DEC0 DEC0 49 50 0-2 0-2 P:$62 P:$64 Quadrature Decoder #0 Home Switch or Watchdog Quadrature Decoder #0 INDEX Pulse Reserved TMRC TMRC TMRC TMRC 56 57 58 59 0-2 0-2 0-2 0-2 P:$70 P:$72 P:$74 P:$76 Timer C Channel 0 Timer C Channel 1 Timer C Channel 2 Timer C Channel 3 Reserved TMRA TMRA TMRA TMRA SCI0 SCI0 64 65 66 67 68 69 0-2 0-2 0-2 0-2 0-2 0-2 P:$80 P:$82 P:$84 P:$86 P:$88 P:$8A Timer A Channel 0 Timer A Channel 1 Timer A Channel 2 Timer A Channel 3 SCI 0 Transmitter Empty SCI 0 Transmitter Idle Reserved SCI0 SCI0 71 72 0-2 0-2 P:$8E P:$90 SCI 0 Receiver Error SCI 0 Receiver Full Reserved ADCA 74 0-2 P:$94 ADC A Conversion Complete / End of Scan Reserved ADCA 76 0-2 P:$98 ADC A Zero Crossing or Limit Error Reserved PWMA 78 0-2 P:$9C Reload PWM A Reserved PWMA core 80 81 82 0-2 -1 0-2 P:$A0 P:$A2 P:$A4 PWM A Fault SW Interrupt LP Interrupt Function 1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. If the VBA is set to $0200, the first two locations of the vector table will overlay the chip reset addresses. 56F8323 Technical Data, Rev. 17 36 Freescale Semiconductor Preliminary Data Map 4.4 Data Map Note: Data Flash is NOT available on the 56F8122 device. Table 4-4 Data Memory Map1 Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 2000 X:$00 1FFF X:$00 1000 X:$00 0FFF X:$00 0000 Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED On-Chip Data Flash 8KB On-Chip Data RAM 8KB2 1. All addresses are 16-bit Word addresses. 2. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle, long-word operations. 4.5 Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides on the Data Memory buses and is controlled separately by its own set of banked registers. The top nine words of the Program Memory Flash are treated as special memory locations. The content of these words is used to control the operation of the Flash controller. Because these words are part of the Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located between $00_3FF7 and $00_3FFF. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 37 Program Memory BOOT_FLASH_START + $0FFF BOOT_FLASH_START = $02_0000 Data Memory FM_BASE + $14 8KB Boot Banked Registers Unbanked Registers FM_BASE + $00 Reserved DATA_FLASH_START + $0FFF 8KB DATA_FLASH_START + $0000 PROG_FLASH_START + $00_3FFF PROG_FLASH_START + $00_3FF7 PROG_FLASH_START + $00_3FF6 FM_PROG_MEM_TOP = $00_3FFF Configure Field Block 0 Odd Block 0 Even ... BLOCK 0 Odd (2 Bytes) $00_0003 BLOCK 0 Even (2 Bytes) $00_0002 BLOCK 0 Odd (2 Bytes) $00_0001 BLOCK 0 Even (2 Bytes) $00_0000 Note: Data Flash is NOT available in the 56F8123 device. 32KB PROG_FLASH_START = $00_0000 Figure 4-1 Flash Array Memory Maps Table 4-5 shows the page and sector sizes used within each Flash memory block on the chip. Note: Data Flash is NOT available on the 56F8123 device. Table 4-5. Flash Memory Partitions Flash Size Program Flash Data Flash Boot Flash 32KB 8KB 8KB Sectors 16 16 4 Sector Size 1K x 16 bits 256 x 16 bits 1K x 16 bits Page Size 512 x 16 bits 256 x 16 bits 256 x 16 bits Please see the 56F8300 Peripheral User Manual for additional Flash information. 56F8323 Technical Data, Rev. 17 38 Freescale Semiconductor Preliminary EOnCE Memory Map 4.6 EOnCE Memory Map Table 4-6 EOnCE Memory Map Address Register Acronym Reserved X:$FF FF8A OESCR External Signal Control Register Reserved X:$FF FF8E OBCNTR Breakpoint Unit [0] Counter Reserved X:$FF FF90 X:$FF FF91 X:$FF FF92 X:$FF FF93 X:$FF FF94 X:$FF FF95 X:$FF FF96 X:$FF FF97 X:$FF FF98 X:$FF FF99 X:$FF FF9A X:$FF FF9B X:$FF FF9C X:$FF FF9D X:$FF FF9E X:$FF FF9F X:$FF FFA0 OBMSK (32 bits) — OBAR2 (32 bits) — OBAR1 (24 bits) — OBCR (24 bits) — OTB (21-24 bits/stage) — OTBPR (8 bits) OTBCR OBASE (8 bits) OSR OSCNTR (24 bits) — OCR (bits) Breakpoint 1 Unit [0] Mask Register Breakpoint 1 Unit [0] Mask Register Breakpoint 2 Unit [0] Address Register Breakpoint 2 Unit [0] Address Register Breakpoint 1 Unit [0] Address Register Breakpoint 1 Unit [0] Address Register Breakpoint Unit [0] Control Register Breakpoint Unit [0] Control Register Trace Buffer Register Stages Trace Buffer Register Stages Trace Buffer Pointer Register Trace Buffer Control Register Peripheral Base Address Register Status Register Instruction Step Counter Instruction Step Counter Control Register Reserved X:$FF FFFC X:$FF FFFD X:$FF FFFE X:$FF FFFF OCLSR (8 bits) OTXRXSR (8 bits) OTX / ORX (32 bits) OTX1 / ORX1 Core Lock / Unlock Status Register Transmit and Receive Status and Control Register Transmit Register / Receive Register Transmit Register Upper Word Receive Register Upper Word Register Name 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 39 4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only. Table 4-7 summarizes base addresses for the set of peripherals on the 56F8323 and 56F8123 devices. Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals. Note: Features in italics are NOT available in the 56F8123 device. Table 4-7 Data Memory Peripheral Base Address Map Summary Peripheral Timer A Timer C PWM A Quadrature Decoder 0 ITCN ADC A Temperature Sensor SCI #0 SCI #1 SPI #0 SPI #1 COP PLL, OSC GPIO Port A GPIO Port B GPIO Port C SIM Power Supervisor FM FlexCAN TMRA TMRC PWMA DEC0 ITCN ADCA TSENSOR SCI0 SCI1 SPI0 SPI1 COP CLKGEN GPIOA GPIOB GPIOC SIM LVI FM FC Prefix Base Address X:$00 F040 X:$00 F0C0 X:$00 F140 X:$00 F180 X:$00 F1A0 X:$00 F200 X:$00 F270 X:$00 F280 X:$00 F290 X:$00 F2A0 X:$00 F2B0 X:$00 F2C0 X:$00 F2D0 X:$00 F2E0 X:$00 F300 X:$00 F310 X:$00 F350 X:$00 F360 X:$00 F400 X:$00 F800 Table Number 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 56F8323 Technical Data, Rev. 17 40 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-8 Quad Timer A Registers Address Map (TMRA_BASE = $00 F040) Register Acronym TMRA0_CMP1 TMRA0_CMP2 TMRA0_CAP TMRA0_LOAD TMRA0_HOLD TMRA0_CNTR TMRA0_CTRL TMRA0_SCR TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_COMSCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRA1_CMP1 TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 $20 $21 $22 $23 $24 $25 $26 $27 $28 Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 41 Table 4-8 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym TMRA2_CMPLD2 TMRA2_COMSCR Address Offset $29 $2A Register Description Comparator Load Register 2 Comparator Status and Control Register Reserved TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSCR $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Table 4-9 Quad Timer C Registers Address Map (TMRC_BASE = $00 F0C0) Register Acronym TMRC0_CMP1 TMRC0_CMP2 TMRC0_CAP TMRC0_LOAD TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD $10 $11 $12 $13 Compare Register 1 Compare Register 2 Capture Register Load Register 56F8323 Technical Data, Rev. 17 42 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-9 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR Address Offset $14 $15 $16 $17 $18 $19 $1A Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRC3_CMP1 TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Register Description 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 43 Table 4-10 Pulse Width Modulator A Registers Address Map (PWMA_BASE = $00 F140) PWM is NOT available in the 56F8123 device Register Acronym PWMA_PMCTRL PWMA_PMFCTRL PWMA_PMFSA PWMA_PMOUT PWMA_PMCNT PWMA_PWMCM PWMA_PWMVAL0 PWMA_PWMVAL1 PWMA_PWMVAL2 PWMA_PWMVAL3 PWMA_PWMVAL4 PWMA_PWMVAL5 PWMA_PMDEADTM PWMA_PMDISMAP1 PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 Control Register Fault Control Register Fault Status Acknowledge Register Output Control Register Counter Register Counter Modulo Register Value Register 0 Value Register 1 Value Register 2 Value Register 3 Value Register 4 Value Register 5 Dead Time Register Disable Mapping Register 1 Disable Mapping Register 2 Configure Register Channel Control Register Port Register Internal Correction Control Register Register Description Table 4-11 Quadrature Decoder 0 Registers Address Map (DEC0_BASE = $00 F180) Quadrature Decoder is NOT available in the 56F8123 device Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH DEC0_REV DEC0_REVH DEC0_UPOS DEC0_LPOS Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 Register Description Decoder Control Register Filter Interval Register Watchdog Time-out Register Position Difference Counter Register Position Difference Counter Hold Register Revolution Counter Register Revolution Hold Register Upper Position Counter Register Lower Position Counter Register 56F8323 Technical Data, Rev. 17 44 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-11 Quadrature Decoder 0 Registers Address Map (Continued) (DEC0_BASE = $00 F180) Quadrature Decoder is NOT available in the 56F8123 device Register Acronym DEC0_UPOSH DEC0_LPOSH DEC0_UIR DEC0_LIR DEC0_IMR Address Offset $9 $A $B $C $D Register Description Upper Position Hold Register Lower Position Hold Register Upper Initialization Register Lower Initialization Register Input Monitor Register Table 4-12 Interrupt Control Registers Address Map (ITCN_BASE = $00 F1A0) Register Acronym IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 IRQP3 IRQP4 IRQP5 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 Register Description Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 Interrupt Priority Register 8 Interrupt Priority Register 9 Vector Base Address Register Fast Interrupt Match Register 0 Fast Interrupt Vector Address Low 0 Register Fast Interrupt Vector Address High 0 Register Fast Interrupt Match Register 1 Fast Interrupt Vector Address Low 1 Register Fast Interrupt Vector Address High 1 Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 IRQ Pending Register 3 IRQ Pending Register 4 IRQ Pending Register 5 Reserved ICTL $1D Interrupt Control Register 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 45 Table 4-13 Analog-to-Digital Converter Registers Address Map (ADCA_BASE = $00 F200) Register Acronym ADCA_CR1 ADCA_CR2 ADCA_ZCC ADCA_LST 1 ADCA_LST 2 ADCA_SDIS ADCA_STAT ADCA_LSTAT ADCA_ZCSTAT ADCA_RSLT 0 ADCA_RSLT 1 ADCA_RSLT 2 ADCA_RSLT 3 ADCA_RSLT 4 ADCA_RSLT 5 ADCA_RSLT 6 ADCA_RSLT 7 ADCA_LLMT 0 ADCA_LLMT 1 ADCA_LLMT 2 ADCA_LLMT 3 ADCA_LLMT 4 ADCA_LLMT 5 ADCA_LLMT 6 ADCA_LLMT 7 ADCA_HLMT 0 ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 ADCA_HLMT 4 ADCA_HLMT 5 ADCA_HLMT 6 ADCA_HLMT 7 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $20 Register Description Control Register 1 Control Register 2 Zero Crossing Control Register Channel List Register 1 Channel List Register 2 Sample Disable Register Status Register Limit Status Register Zero Crossing Status Register Result Register 0 Result Register 1 Result Register 2 Result Register 3 Result Register 4 Result Register 5 Result Register 6 Result Register 7 Low Limit Register 0 Low Limit Register 1 Low Limit Register 2 Low Limit Register 3 Low Limit Register 4 Low Limit Register 5 Low Limit Register 6 Low Limit Register 7 High Limit Register 0 High Limit Register 1 High Limit Register 2 High Limit Register 3 High Limit Register 4 High Limit Register 5 High Limit Register 6 High Limit Register 7 56F8323 Technical Data, Rev. 17 46 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-13 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym ADCA_OFS 0 ADCA_OFS 1 ADCA_OFS 2 ADCA_OFS 3 ADCA_OFS 4 ADCA_OFS 5 ADCA_OFS 6 ADCA_OFS 7 ADCA_POWER ADCA_CAL Address Offset $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Register Description Offset Register 0 Offset Register 1 Offset Register 2 Offset Register 3 Offset Register 4 Offset Register 5 Offset Register 6 Offset Register 7 Power Control Register ADC Calibration Register Table 4-14 Temperature Sensor Register Address Map (TSENSOR_BASE = $00 F270) Temperature Sensor is NOT available in the 56F8123 device Register Acronym TSENSOR_CNTL Address Offset $0 Control Register Register Description Table 4-15 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00 F280) Register Acronym SCI0_SCIBR SCI0_SCICR Address Offset $0 $1 Register Description Baud Rate Register Control Register Reserved SCI0_SCISR SCI0_SCIDR $3 $4 Status Register Data Register Table 4-16 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00 F290) Register Acronym SCI1_SCIBR SCI1_SCICR Address Offset $0 $1 Register Description Baud Rate Register Control Register Reserved SCI1_SCISR SCI1_SCIDR $3 $4 Status Register Data Register 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 47 Table 4-17 Serial Peripheral Interface 0 Registers Address Map (SPI0_BASE = $00 F2A0) Register Acronym SPI0_SPSCR SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Address Offset $0 $1 $2 $3 Register Description Status and Control Register Data Size Register Data Receive Register Data Transmitter Register Table 4-18 Serial Peripheral Interface 1 Registers Address Map (SPI1_BASE = $00 F2B0) Register Acronym SPI1_SPSCR SPI1_SPDSR SPI1_SPDRR SPI1_SPDTR Address Offset $0 $1 $2 $3 Register Description Status and Control Register Data Size Register Data Receive Register Data Transmitter Register Table 4-19 Computer Operating Properly Registers Address Map (COP_BASE = $00 F2C0) Register Acronym COPCTL COPTO COPCTR Address Offset $0 $1 $2 Control Register Time-Out Register Counter Register Register Description Table 4-20 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00 F2D0) Register Acronym PLLCR PLLDB PLLSR Address Offset $0 $1 $2 Control Register Divide-By Register Status Register Reserved SHUTDOWN OSCTL $4 $5 Shutdown Register Oscillator Control Register Register Description 56F8323 Technical Data, Rev. 17 48 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-21 GPIOA Registers Address Map (GPIOA_BASE = $00 F2E0) Register Acronym GPIOA_PUR GPIOA_DR GPIOA_DDR GPIOA_PER GPIOA_IAR GPIOA_IENR GPIOA_IPOLR GPIOA_IPR GPIOA_IESR GPIOA_PPMODE GPIOA_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 0FFF 0 x 0000 0 x 0000 0 x 0FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0FFF — Table 4-22 GPIOB Registers Address Map (GPIOB_BASE = $00 F300) Register Acronym GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR GPIOB_PPMODE GPIOB_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 00FF 0 x 0000 0 x 0000 0 x 00FF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 00FF — 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 49 Table 4-23 GPIOC Registers Address Map (GPIOC_BASE = $00 F310) Register Acronym GPIOC_PUR GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE GPIOC_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 007C 0 x 0000 0 x 0000 0 x 007F 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 007F — Table 4-24 System Integration Module Registers Address Map (SIM_BASE = $00 F350) Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half JTAG ID Least Significant Half JTAG ID Pull-up Disable Register Reserved SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL $A $B $C $D $E Clock Out Select Register GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register Register Description 56F8323 Technical Data, Rev. 17 50 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-25 Power Supervisor Registers Address Map (LVI_BASE = $00 F360) Register Acronym LVI_CONTROL LVI_STATUS Address Offset $0 $1 Control Register Status Register Register Description Table 4-26 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym FMCLKD FMMCR Address Offset $0 $1 Register Description Clock Divider Register Module Control Register Reserved FMSECH FMSECL $3 $4 Security High Half Register Security Low Half Register Reserved Reserved FMPROT FMPROTB $10 $11 Protection Register (Banked) Protection Boot Register (Banked) Reserved FMUSTAT FMCMD $13 $14 User Status Register (Banked) Command Register (Banked) Reserved Reserved FMOPT 0 $1A 16-Bit Information Option Register 0 Hot temperature ADC reading of Temperature Sensor; value set during factory test 16-Bit Information Option Register 1 Trim cap setting of the relaxation oscillator 16-Bit Information Option Register 2 Room temperature ADC reading of Temperature Sensor; value set during factory test FMOPT 1 FMOPT 2 $1B $1C 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 51 Table 4-27 FlexCAN Registers Address Map (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym FCMCR Address Offset $0 Register Description Module Configuration Register Reserved FCCTL0 FCCTL1 FCTMR FCMAXMB $3 $4 $5 $6 Control Register 0 Register Control Register 1 Register Free-Running Timer Register Maximum Message Buffer Configuration Register Reserved FCRXGMASK_H FCRXGMASK_L FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L $8 $9 $A $B $C $D Receive Global Mask High Register Receive Global Mask Low Register Receive Buffer 14 Mask High Register Receive Buffer 14 Mask Low Register Receive Buffer 15 Mask High Register Receive Buffer 15 Mask Low Register Reserved FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS $10 $11 $12 $13 Error and Status Register Interrupt Masks 1 Register Interrupt Flags 1 Register Receive and Transmit Error Counters Register Reserved Reserved Reserved FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA $40 $41 $42 $43 $44 $45 $46 Message Buffer 0 Control / Status Register Message Buffer 0 ID High Register Message Buffer 0 ID Low Register Message Buffer 0 Data Register Message Buffer 0 Data Register Message Buffer 0 Data Register Message Buffer 0 Data Register Reserved FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW $48 $49 $4A Message Buffer 1 Control / Status Register Message Buffer 1 ID High Register Message Buffer 1 ID Low Register 56F8323 Technical Data, Rev. 17 52 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-27 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA Address Offset $4B $4C $4D $4E Register Description Message Buffer 1 Data Register Message Buffer 1 Data Register Message Buffer 1 Data Register Message Buffer 1 Data Register Reserved FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA $50 $51 $52 $53 $54 $55 $56 Message Buffer 2 Control / Status Register Message Buffer 2 ID High Register Message Buffer 2 ID Low Register Message Buffer 2 Data Register Message Buffer 2 Data Register Message Buffer 2 Data Register Message Buffer 2 Data Register Reserved FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA $58 $59 $5A $5B $5C $5D $5E Message Buffer 3 Control / Status Register Message Buffer 3 ID High Register Message Buffer 3 ID Low Register Message Buffer 3 Data Register Message Buffer 3 Data Register Message Buffer 3 Data Register Message Buffer 3 Data Register Reserved FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB4_DATA $60 $61 $62 $63 $64 $65 $66 Message Buffer 4 Control / Status Register Message Buffer 4 ID High Register Message Buffer 4 ID Low Register Message Buffer 4 Data Register Message Buffer 4 Data Register Message Buffer 4 Data Register Message Buffer 4 Data Register Reserved FCMB5_CONTROL FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA $68 $69 $6A $6B Message Buffer 5 Control / Status Register Message Buffer 5 ID High Register Message Buffer 5 ID Low Register Message Buffer 5 Data Register 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 53 Table 4-27 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym FCMB5_DATA FCMB5_DATA FCMB5_DATA Address Offset $6C $6D $6E Register Description Message Buffer 5 Data Register Message Buffer 5 Data Register Message Buffer 5 Data Register Reserved FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA $70 $71 $72 $73 $74 $75 $76 Message Buffer 6 Control / Status Register Message Buffer 6 ID High Register Message Buffer 6 ID Low Register Message Buffer 6 Data Register Message Buffer 6 Data Register Message Buffer 6 Data Register Message Buffer 6 Data Register Reserved FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA $78 $79 $7A $7B $7C $7D $7E Message Buffer 7 Control / Status Register Message Buffer 7 ID High Register Message Buffer 7 ID Low Register Message Buffer 7 Data Register Message Buffer 7 Data Register Message Buffer 7 Data Register Message Buffer 7 Data Register Reserved FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA $80 $81 $82 $83 $84 $85 $86 Message Buffer 8 Control / Status Register Message Buffer 8 ID High Register Message Buffer 8 ID Low Register Message Buffer 8 Data Register Message Buffer 8 Data Register Message Buffer 8 Data Register Message Buffer 8 Data Register Reserved FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA $88 $89 $8A $8B $8C Message Buffer 9 Control / Status Register Message Buffer 9 ID High Register Message Buffer 9 ID Low Register Message Buffer 9 Data Register Message Buffer 9 Data Register 56F8323 Technical Data, Rev. 17 54 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-27 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym FCMB9_DATA FCMB9_DATA Address Offset $8D $8E Register Description Message Buffer 9 Data Register Message Buffer 9 Data Register Reserved FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB10_DATA $90 $91 $92 $93 $94 $95 $96 Message Buffer 10 Control / Status Register Message Buffer 10 ID High Register Message Buffer 10 ID Low Register Message Buffer 10 Data Register Message Buffer 10 Data Register Message Buffer 10 Data Register Message Buffer 10 Data Register Reserved FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB11_DATA $98 $99 $9A $9B $9C $9D $9E Message Buffer 11 Control / Status Register Message Buffer 11 ID High Register Message Buffer 11 ID Low Register Message Buffer 11 Data Register Message Buffer 11 Data Register Message Buffer 11 Data Register Message Buffer 11 Data Register Reserved FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB12_DATA $A0 $A1 $A2 $A3 $A4 $A5 $A6 Message Buffer 12 Control / Status Register Message Buffer 12 ID High Register Message Buffer 12 ID Low Register Message Buffer 12 Data Register Message Buffer 12 Data Register Message Buffer 12 Data Register Message Buffer 12 Data Register Reserved FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA $A8 $A9 $AA $AB $AC $AD Message Buffer 13 Control / Status Register Message Buffer 13 ID High Register Message Buffer 13 ID Low Register Message Buffer 13 Data Register Message Buffer 13 Data Register Message Buffer 13 Data Register 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 55 Table 4-27 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8123 device Register Acronym FCMB13_DATA Address Offset $AE Register Description Message Buffer 13 Data Register Reserved FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA $B0 $B1 $B2 $B3 $B4 $B5 $B6 Message Buffer 14 Control / Status Register Message Buffer 14 ID High Register Message Buffer 14 ID Low Register Message Buffer 14 Data Register Message Buffer 14 Data Register Message Buffer 14 Data Register Message Buffer 14 Data Register Reserved FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA $B8 $B9 $BA $BB $BC $BD $BE Message Buffer 15 Control / Status Register Message Buffer 15 ID High Register Message Buffer 15 ID Low Register Message Buffer 15 Data Register Message Buffer 15 Data Register Message Buffer 15 Data Register Message Buffer 15 Data Register Reserved 4.8 Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program. The Serial Bootloader application can be used to load a user application into the Program and Data Flash (NOT available in the 56F8123) memories of the device. The 56F83xx SCI/CAN Bootloader User Manual provides detailed information on this firmware. An application note, Production Flash Programming, details how the Serial Bootloader program can be used to perform production Flash programming of the on-board Flash memories as well as other optional methods. Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user. The Serial Bootloader application is programmed as an aid to the end user, but is not required to be used or maintained in the Boot Flash memory. 56F8323 Technical Data, Rev. 17 56 Freescale Semiconductor Preliminary Introduction Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt. 5.2 Features The ITCN module design includes these distinctive features: • • • • Programmable priority levels for each IRQ Two programmable Fast Interrupts Notification to SIM module to restart clocks out of Wait and Stop modes Drives initial address on the address bus after reset For further information, see Table 4-3, Interrupt Vector Table Contents. 5.3 Functional Description The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number 81 is the lowest. 5.3.1 Normal Interrupt Handling Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the vector number to determine the vector address. In this way, an offset is generated into the vector table for each interrupt. 5.3.2 Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition SR[9]1 0 0 1 1 0 1 0 1 SR[8]1 Permitted Exceptions Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3 Masked Exceptions None Priority 0 Priorities 0, 1 Priorities 0, 1, 2 1. Core status register bits indicating current interrupt mask within the core. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 57 Table 5-2. Interrupt Priority Encoding IPIC_LEVEL[1:0]1 00 01 10 11 Current Interrupt Priority Level No Interrupt or SWILP Priority 0 Priority 1 Priorities 2 or 3 Required Nested Exception Priority Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3 1. See IPIC field definition in Section 5.6.30.2 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A fast interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIMn register to the appropriate vector number 3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts its fast interrupt handling. 56F8323 Technical Data, Rev. 17 58 Freescale Semiconductor Preliminary Block Diagram 5.4 Block Diagram Priority Level any0 Level 0 82 -> 7 Priority Encoder 7 INT1 2 -> 4 Decode INT VAB CONTROL IPIC any3 Level 3 Priority Level 82 -> 7 Priority Encoder IACK SR[9:8] 7 PIC_EN INT82 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA signal automatically becomes low-level sensitive in these modes, even if the control register bits are set to make them falling-edge sensitive. This is because there is no clock available to detect the falling edge. A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 59 5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers. Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F1A0) Register Acronym IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 IRQP3 IRQP4 IRQP5 Base Address + $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 Interrupt Priority Register 8 Interrupt Priority Register 9 Vector Base Address Register Fast Interrupt 0 Match Register Fast Interrupt 0 Vector Address Low Register Fast Interrupt 0 Vector Address High Register Fast Interrupt 1 Match Register Fast Interrupt 1 Vector Address Low Register Fast Interrupt 1 Vector Address High Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 IRQ Pending Register 3 IRQ Pending Register 4 IRQ Pending Register 5 Reserved ICTL $1D Interrupt Control Register 5.6.30 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 5.6.20 5.6.21 5.6.22 5.6.23 56F8323 Technical Data, Rev. 17 60 Freescale Semiconductor Preliminary Register Descriptions Add. Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 Register Name IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 IRQP3 IRQP4 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Reserved 15 0 0 14 0 0 13 12 11 10 9 0 0 8 0 0 7 0 0 6 0 0 5 0 4 0 3 0 2 0 1 0 0 0 BKPT_ U0 IPL 0 0 STPCNT IPL 0 0 RX_REG IPL 0 0 TX_REG IPL 0 0 TRBUF IPL IRQA IPL 0 0 FMCBE IPL 0 0 FMCC IPL 0 0 FMERR IPL 0 0 LOCK IPL FCMSGBUF IPL 0 0 LVI IPL FCWKUP IPL 0 0 0 0 0 0 0 0 FCERR IPL GPIOA IPL SCI1_TIDL IPL 0 0 0 0 FCBOFF IPL GPIOB IPL SCI1_XMIT IPL DEC0_XIRQ IPL TMRC2 IPL TMRA2 IPL ADCA_CC IPL SPI0_RCV IPL 0 0 SPI1_XMIT IPL 0 0 0 0 0 0 SPI1_RCV IPL SCI1_RCV IPL 0 0 0 0 0 0 GPIOC IPL SPI0_XMIT IPL DEC0_HIRQ IPL TMRC1 IPL TMRA1 IPL 0 0 SCI1_RERR IPL 0 0 0 0 TMRC0 IPL TMRA0 IPL SCI0_RCV IPL PWMA F IPL 0 0 0 0 TMRC3 IPL TMRA3 IPL 0 0 SCI0_RERR IPL 0 0 0 0 0 SCI0_TIDL IPL 0 0 SCI0_XMIT IPL ADCA_ZC IPL PWMA_RL IPL VECTOR BASE ADDRESS 0 0 0 0 0 FAST INTERRUPT 0 FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT 1 FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH 1 PENDING [16:2] PENDING [32:17] PENDING [48:33] PENDING [64:49] PENDING [80:65] $16 IRQP5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PENDING [81] $1D ICTL R W INT IPIC VAB INT_ DIS 1 0 IRQA STATE 0 IRQA EDG = Reserved Figure 5-2 ITCN Register Map Summary 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 61 5.6.1 Interrupt Priority Register 0 (IPR0) 15 0 Base + $0 Read Write RESET 14 0 13 12 11 10 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 BKPT_U0 IPL 0 0 0 0 STPCNT IPL 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 5.6.1.2 Reserved—Bits 15–14 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)— Bits13–12 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.4 Reserved—Bits 9–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $1 Read Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 4 3 2 1 0 RX_REG IPL TX_REG IPL TRBUF IPL Figure 5-4 Interrupt Priority Register 1 (IPR1) 56F8323 Technical Data, Rev. 17 62 Freescale Semiconductor Preliminary Register Descriptions 5.6.2.1 5.6.2.2 Reserved—Bits 15–6 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.2.3 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.3 Interrupt Priority Register 2 (IPR2) 15 14 13 12 11 10 9 8 7 6 5 0 FMCBE IPL FMCC IPL 0 0 FMERR IPL 0 0 LOCK IPL 0 0 LVI IPL 0 0 0 0 0 0 Base + $2 Read Write RESET 4 0 3 0 2 0 1 0 IRQA IPL 0 0 0 0 Figure 5-5 Interrupt Priority Register 2 (IPR2) 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 63 5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.2 Flash Memory Command Complete Priority Level (FMCC IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 64 Freescale Semiconductor Preliminary Register Descriptions 5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.6 5.6.3.7 Reserved—Bits 5–2 External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $3 Read Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 14 0 13 0 12 0 11 0 10 0 9 8 7 6 5 4 3 2 1 0 0 0 FCMSGBUF IPL FCWKUP IPL FCERR IPL FCBOFF IPL Figure 5-6 Interrupt Priority Register 3 (IPR3) 5.6.4.1 5.6.4.2 Reserved—Bits 15–10 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)—Bits 9–8 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 65 5.6.4.3 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.4 FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.5 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.6 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.5 Interrupt Priority Register 4 (IPR4) 15 14 13 12 11 10 9 0 Base + $4 Read Write RESET 8 0 7 0 6 0 5 4 3 2 1 0 SPI0_RCV IPL 0 0 SPI1_XMIT IPL 0 0 SPI1_RCV IPL 0 0 GPIOA IPL 0 0 0 0 0 0 GPIOB IPL 0 0 GPIOC IPL 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 56F8323 Technical Data, Rev. 17 66 Freescale Semiconductor Preliminary Register Descriptions 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.2 SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.4 5.6.5.5 Reserved—Bits 9–6 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 67 5.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.7 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) 15 0 Base + $5 Read Write RESET 14 0 13 0 12 0 11 10 9 8 7 0 6 0 5 4 3 2 1 0 SCI1_RCV IPL 0 0 SCI1_RERR IPL 0 0 SCI1_TIDL IPL 0 0 SCI1_XMIT IPL 0 0 SPI0_XMIT IPL 0 0 0 0 0 0 0 0 Figure 5-8 Interrupt Priority Register 5 (IPR5) 5.6.6.1 5.6.6.2 Reserved—Bits 15–12 SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)— Bits 11–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 68 Freescale Semiconductor Preliminary Register Descriptions 5.6.6.3 SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.4 5.6.6.5 Reserved—Bits 7–6 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.6 SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.7 SPI0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 69 5.6.7 Interrupt Priority Register 6 (IPR6) 15 14 13 0 TMRC0 IPL Base + $6 Read Write RESET 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 2 1 0 DEC0_XIRQ IPL 0 0 DEC0_HIRQ IPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.2 5.6.7.3 Reserved—Bits 13–4 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)—Bits 3–2 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.4 Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 70 Freescale Semiconductor Preliminary Register Descriptions 5.6.8 Interrupt Priority Register 7 (IPR7) 15 14 13 0 TMRA0 IPL Base + $7 Read Write RESET 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 4 3 2 1 0 TMRC3 IPL 0 0 0 0 0 0 0 0 0 0 TMRC2 IPL 0 0 TMRC1 IPL 0 0 0 0 Figure 5-10 Interrupt Priority Register (IPR7) 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.2 5.6.8.3 Reserved—Bits 13–6 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.4 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 71 5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9 Interrupt Priority Register 8 (IPR8) 15 14 13 12 11 0 Base + $8 Read Write RESET 10 0 9 8 7 6 5 4 3 2 1 0 SCI0_RCV IPL 0 0 SCI0_RERR IPL 0 0 SCI0_TIDL IPL 0 0 SCI0_XMIT IPL 0 0 TMRA3 IPL 0 0 TMRA2 IPL 0 0 TMRA1 IPL 0 0 0 0 Figure 5-11 Interrupt Priority Register 8 (IPR8) 5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0 RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0 RERR IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 72 Freescale Semiconductor Preliminary Register Descriptions 5.6.9.3 5.6.9.4 Reserved—Bits 11–10 SCI0 Transmitter Idle Interrupt Priority Level (SCI0 TIDL IPL)— Bits 9–8 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0 XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA 3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA 2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 73 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA 1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10 Interrupt Priority Register 9 (IPR9) 15 14 13 0 PWMA F IPL Base + $9 Read Write RESET 12 0 11 10 9 0 8 0 7 6 5 0 4 0 3 2 1 0 0 0 PWMA_RL IPL 0 0 ADCA_ZC IPL 0 0 0 0 0 0 ADCA_CC IPL 0 0 0 0 0 0 0 0 Figure 5-12 Interrupt Priority Register 9 (IPR9) 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA F IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.2 5.6.10.3 Reserved—Bits 13–12 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)— Bits 11–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8323 Technical Data, Rev. 17 74 Freescale Semiconductor Preliminary Register Descriptions 5.6.10.4 5.6.10.5 Reserved—Bits 9–8 ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)—Bits 7–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.6 5.6.10.7 Reserved—Bits 5–4 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.8 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.11 Vector Base Address Register (VBA) 15 0 Base + $A Read Write RESET 14 0 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 VECTOR BASE ADDRESS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-13 Vector Base Address Register (VBA) 5.6.11.1 Reserved—Bits 15–13 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 75 5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)— Bits 12–0 The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt vector address. The lower eight bits of the ISR address are determined based upon the highest-priority interrupt; see Part 5.3.1 for details. 5.6.12 Fast Interrupt 0 Match Register (FIM0) 15 0 Base + $B Read Write RESET 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 5 4 3 2 1 0 FAST INTERRUPT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-14 Fast Interrupt 0 Match Register (FIM0) 5.6.12.1 5.6.12.2 Reserved—Bits 15–7 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; for details, see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-3. 5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write Base + $C FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 56F8323 Technical Data, Rev. 17 76 Freescale Semiconductor Preliminary Register Descriptions 5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0) 15 0 Base + $D Read Write RESET 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 3 2 1 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.14.1 5.6.14.2 Reserved—Bits 15–5 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 5.6.15 Fast Interrupt 1 Match Register (FIM1) 15 0 Base + $E Read Write RESET 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 5 4 3 2 1 0 FAST INTERRUPT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-17 Fast Interrupt 1 Match Register (FIM1) 5.6.15.1 5.6.15.2 Reserved—Bits 15–7 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0 This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing. This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; for details, see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-3. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 77 5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write Base + $F FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1) 15 0 Base + $10 Read Write RESET 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 3 2 1 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1) 5.6.17.1 5.6.17.2 Reserved—Bits 15–5 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.18 IRQ Pending 0 Register (IRQP0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 Base + $11 Read Write RESET PENDING [16:2] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-20 IRQ Pending 0 Register (IRQP0) 5.6.18.1 IRQ Pending (PENDING)—Bits 16–2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 56F8323 Technical Data, Rev. 17 78 Freescale Semiconductor Preliminary Register Descriptions 5.6.18.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.19 IRQ Pending 1 Register (IRQP1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write PENDING [32:17] $Base + $12 RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-21 IRQ Pending 1 Register (IRQP1) 5.6.19.1 IRQ Pending (PENDING)—Bits 32–17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.20 IRQ Pending 2 Register (IRQP2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write PENDING [48:33] Base + $13 RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.21 IRQ Pending 3 Register (IRQP3) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write PENDING [64:49] Base + $14 RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-23 IRQ Pending 3 Register (IRQP3) 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 79 5.6.21.1 IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers two through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.22 IRQ Pending 4 Register (IRQP4) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write PENDING [80:65] Base + $15 RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-24 IRQ Pending 4 Register (IRQP4) 5.6.22.1 IRQ Pending (PENDING)—Bits 80–65 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.23 IRQ Pending 5 Register (IRQP5) 15 1 Base + $16 Read Write RESET 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 PENDING [81] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 5.6.23.2 Reserved—Bits 96–82 IRQ Pending (PENDING)—Bit 81 This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing. This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 56F8323 Technical Data, Rev. 17 80 Freescale Semiconductor Preliminary Register Descriptions 5.6.24 5.6.25 5.6.26 5.6.27 5.6.28 5.6.29 5.6.30 Reserved—Base + 17 Reserved—Base + 18 Reserved—Base + 19 Reserved—Base + 1A Reserved—Base + 1B Reserved—Base + 1C ITCN Control Register (ICTL) 15 INT Base + $1D Read Write RESET 14 IPIC 13 12 11 10 9 VAB 8 7 6 5 INT_DIS 4 1 3 0 2 IRQA STATE 1 0 0 IRQA EDG 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 Figure 5-26 ITCN Control Register (ICTL) 5.6.30.1 • • Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core 5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: • • • • Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 00 = Required nested exception priority levels are 0, 1, 2, or 3 01 = Required nested exception priority levels are 1, 2, or 3 10 = Required nested exception priority levels are 2 or 3 11 = Required nested exception priority level is 3 5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 81 5.6.30.4 • • Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled. 0 = Normal operation (default) 1 = All interrupts disabled 5.6.30.5 5.6.30.6 5.6.30.7 5.6.30.8 5.6.30.9 Reserved—Bit 4 Reserved—Bit 3 IRQA State Pin (IRQA STATE)—Bit 2 Reserved—Bit 1 IRQA Edge Pin (IRQA Edg)—Bit 0 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This read-only bit reflects the state of the external IRQA pin. This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait modes, it is automatically level-sensitive. • • 0 = IRQA interrupt is a low-level sensitive (default) 1 = IRQA interrupt is falling-edge sensitive 5.7 Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 5.7.2 ITCN After Reset After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled except the core IRQs with fixed priorities • • • • • • • • Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 SW Interrupt LP These interrupts are enabled at their fixed priority levels. 56F8323 Technical Data, Rev. 17 82 Freescale Semiconductor Preliminary Introduction Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system integration module is responsible for the following functions: • • • • • • • Reset sequencing Clock control & distribution Stop/Wait control Pull-up enables for selected peripherals System status registers Registers for software access to the JTAG ID of the chip Enforcing Flash security These are discussed in more detail in the sections that follow. 6.2 Features The SIM has the following features: • • • Flash security feature prevents unauthorized access to code/data contained in on-chip flash memory Power-saving clock gating for peripherals Three power modes (Run, Wait, Stop) to control power utilization — Stop mode shuts down the 56800E core, system clock, and peripheral clock — Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart) — Wait mode shuts down the 56800E core and unnecessary system clock operation — Run mode supports full part operation • • • • • • Controls to enable/disable the 56800E core WAIT and STOP instructions Controls reset sequencing after reset Software-initiated reset Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control System Control Register Registers for software access to the JTAG ID of the chip 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 83 6.3 Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — Total Reset Mode – 56800E Core and all peripherals are reset — Core-Only Reset Mode – 56800E Core in reset, peripherals are active – This mode is required to provide the on-chip Flash interface module time to load data from Flash into FM registers. • • Run Mode The primary mode of operation for this device, in which the 56800E controls chip operation Debug Mode 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details. Wait Mode In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped. Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other peripherals continue to run. Stop Mode 56800E, memory, and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode. • • 6.4 Operating Mode Register Bit 15 NL 14 13 12 11 10 9 8 CM R/W 7 XP R/W 0 6 SD R/W 0 5 R R/W 0 4 SA R/W 0 3 EX R/W 0 2 0 1 MB R/W 0 MA R/W 0 Type RESET R/W 0 0 0 0 0 0 0 0 0 X Figure 6-1 OMR The reset state for MB will depend on the Flash secured state. See Part 4.2 and Part 7 for detailed information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. The EX bit is not functional in this device since there is no external memory interface. For all other bits, see the 56F8300 Peripheral User Manual. Note: The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR. 56F8323 Technical Data, Rev. 17 84 Freescale Semiconductor Preliminary Register Descriptions 6.5 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00F350) Address Offset Base + $0 Base + $1 Base + $2 Base + $3 Base + $4 Base + $5 Base + $6 Base + $7 Base + $8 Address Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID Least Significant Half of JTAG ID Pull-up Disable Register Reserved Base + $A Base + $B Base + $C Base + $D Base + $E SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL CLKO Select Register GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register 6.5.7 6.5.7 6.5.8 6.5.9 6.5.10 Section Location 6.5.1 6.5.2 6.5.3 6.5.3 6.5.3 6.5.3 6.5.4 6.5.5 6.5.6 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 85 Add. Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 Register Name SIM_ CONTROL SIM_ RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 ONCE EBL0 SWR 4 SW RST 3 2 1 0 STOP_ DISABLE POR WAIT_ DISABLE 0 0 COPR EXTR FIELD FIELD FIELD FIELD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 0 RESET IRQ JTAG $A $B $C $D $E SIM_ CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 PHSA PHSB INDEX HOME 0 1 1 0 C6 1 1 C5 TMRA 1 CLK DIS B1 SCI1 1 B0 SCI0 1 A5 SPI1 1 CLKOSEL A4 SPI0 1 A3 1 A2 PWMA ADCA 1 CAN 1 DEC0 1 TMRC 1 ISAL[23:22] ISAL[21:6] = Reserved Figure 6-2 SIM Register Map Summary 6.5.1 SIM Control Register (SIM_CONTROL) 15 0 Base + $0 Read Write POR 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 ONCE EBL0 0 4 SW RST 0 3 2 1 0 STOP_ DISABLE 0 0 WAIT_ DISABLE 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-3 SIM Control Register (SIM_CONTROL) 6.5.1.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 56F8323 Technical Data, Rev. 17 86 Freescale Semiconductor Preliminary Register Descriptions 6.5.1.2 • • OnCE Enable (ONCE EBL)—Bit 5 0 = OnCE clock to 56800E core enabled when core TAP is enabled 1 = OnCE clock to 56800E core is always enabled 6.5.1.3 6.5.1.4 • • • • Software Reset (SW RST)—Bit 4 Stop Disable (STOP_DISABLE)—Bits 3–2 Writing 1 to this field will cause the part to reset. 00 = Stop mode will be entered when the 56800E core executes a STOP instruction 01 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be reprogrammed in the future 10 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be changed by resetting the device 11 = Same operation as 10 6.5.1.5 • • • • Wait Disable (WAIT_DISABLE)—Bits 1–0 00 = Wait mode will be entered when the 56800E core executes a WAIT instruction 01 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be reprogrammed in the future 10 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only be changed by resetting the device 11 = Same operation as 10 6.5.2 SIM Reset Status Register (SIM_RSTSTS) Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this register. Base + $1 Read Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 SWR 4 COPR 3 EXTR 2 POR 1 0 0 0 Figure 6-4 SIM Reset Status Register (SIM_RSTSTS) 6.5.2.1 6.5.2.2 Reserved—Bits 15–6 Software Reset (SWR)—Bit 5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST bit in the SIM CONTROL register). This bit will be cleared by any hardware reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 87 6.5.2.3 COP Reset (COPR)—Bit 4 When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.4 External Reset (EXTR)—Bit 3 If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit while writing a 1 to the bit position will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET pin being asserted low. 6.5.2.5 Power-On Reset (POR)—Bit 2 When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be cleared only by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On Reset. 6.5.2.6 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3) Only SIM SCR0 is shown in this section. SIM SCR1, SIM SCR2, and SIM SCR3 are identical in functionality. Base + $2 Read 15 14 13 12 11 10 9 8 FIELD 7 6 5 4 3 2 1 0 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-5 SIM Software Control Register 0 (SIM_SCR0) 6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (RESET pin, software reset, and COP reset). 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F4. 56F8323 Technical Data, Rev. 17 88 Freescale Semiconductor Preliminary Register Descriptions Base + $6 Read Write RESET 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 1 7 1 6 1 5 1 4 1 3 0 2 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID) 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $001D. Base + $7 Read Write RESET 15 0 14 1 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID) 6.5.6 SIM Pull-up Disable Register (SIM_PUDR) Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See Table 2-2 to identify which pins can deactivate the internal pull-up resistor. Base + $8 Read Write RESET 15 0 14 0 13 0 12 0 11 RESET 10 IRQ 0 9 0 8 0 7 0 6 0 5 0 4 0 3 JTAG 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR) 6.5.6.1 6.5.6.2 Reserved—Bits 15–12 RESET—Bit 11 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This bit controls the pull-up resistors on the RESET pin. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 89 6.5.6.3 6.5.6.4 6.5.6.5 6.5.6.6 IRQ—Bit 10 Reserved—Bits 9–4 JTAG—Bit 3 Reserved—Bits 2–0 This bit controls the pull-up resistors on the IRQA pin. This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This bit controls the pull-up resistors on the TRST, TMS, and TDI pins. This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.7 CLKO Select Register (SIM_CLKOSR) The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are for test purposes only, and are subject to significant unspecified latencies at high frequencies. The upper four bits of the GPIOB register can function as GPIO, Quad Decoder #0 signals, or as additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed to operate as peripheral outputs, then the choice between Quad Decoder #0 and additional clock outputs is made here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as Quad Decoder #0. This can be changed by altering PHASE0 through INDEX shown in Figure 6-9. The CLKOUT pin is not bonded out in the device. Instead, it is offered only as a pad for die-level testing. Base + $A Read Write RESET 15 0 14 0 13 0 12 0 11 0 10 0 9 8 7 6 HOME 0 5 CLK DIS 1 4 3 2 CLKOSEL 1 0 PHSA PHSB INDEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-9 CLKO Select Register (SIM_CLKOSR) 6.5.7.1 6.5.7.2 • • Reserved—Bits 15–10 PHASEA0 (PHSA)—Bit 9 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 0 = Peripheral output function of GPIOB[7] is defined to be PHASEA0 1 = Peripheral output function of GPIOB[7] is defined to be the oscillator clock (MSTR_OSC, see Figure 3-4) 6.5.7.3 • • PHASEB0 (PHSB)—Bit 8 0 = Peripheral output function of GPIOB[6] is defined to be PHASEB0 1 = Peripheral output function of GPIOB[6] is defined to be SYS_CLK2 56F8323 Technical Data, Rev. 17 90 Freescale Semiconductor Preliminary Register Descriptions 6.5.7.4 • • INDEX0 (INDEX)—Bit 7 0 = Peripheral output function of GPIOB[5] is defined to be INDEX0 1 = Peripheral output function of GPIOB[5] is defined to be SYS_CLK 6.5.7.5 • • HOME0 (HOME)—Bit 6 0 = Peripheral output function of GPIOB[4] is defined to be HOME0 1 = Peripheral output function of GPIOB[4] is defined to be the prescaler clock (FREF, see Figure 3-4) 6.5.7.6 • • Clockout Disable (CLKDIS)—Bit 5 0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL 1 = CLKOUT is tri-stated 6.5.7.7 • • • • • • • • • • • • • • • • • CLockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO pin. 00000 = SYS_CLK (from ROCS - DEFAULT) 00001 = Reserved for factory test—56800E clock 00010 = Reserved for factory test—XRAM clock 00011 = Reserved for factory test—PFLASH odd clock 00100 = Reserved for factory test—PFLASH even clock 00101 = Reserved for factory test—BFLASH clock 00110 = Reserved for factory test—DFLASH clock 00111 = MSTR_OSC Oscillator output 01000 = Fout (from OCCS) 01001 = Reserved for factory test—IPB clock 01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL) 01011 = Reserved for factory test—Prescaler clock (from OCCS) 01100 = Reserved for factory test—Postscaler clock (from OCCS) 01101 = Reserved for factory test—SYS_CLK2 (from OCCS) 01110 = Reserved for factory test—SYS_CLK_DIV2 01111 = Reserved for factory test—SYS_CLK_D 10000 = ADCA clock 6.5.8 SIM GPIO Peripheral Select Register (SIM_GPS) All of the peripheral pins on the 56F8323 and 56F8123 share their I/O with GPIO ports. To select peripheral or GPIO control, program the GPIOx_PER register. When SPI 0 and SCI 1, Quad Timer C and SCI 0, or PWMA and SPI 1 are multiplexed, there are two possible peripherals as well as the GPIO functionality available for control of the I/O. The SIM_GPS register is used to determine which peripheral has control. The default peripherals are SPI 0, Quad Timer C, and PWMA. Note: PWM is NOT available in the 56F8123 device. As shown in Figure 6-10, the GPIO has the final control over the pin function. SIM_GPS simply decides which peripheral will be routed to the I/O. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 91 GPIOX_PER Register GPIO Controlled 0 I/O Pad Control 1 SIM_GPS Register 0 Quad Timer Controlled SCI Controlled 1 Figure 6-10 Overall Control of Pads Using SIM_GPS Control Base + $B Read Write RESET 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 C6 6 C5 0 5 B1 0 4 B0 0 3 A5 0 2 A4 0 1 A3 0 0 A2 0 0 0 0 0 0 0 0 0 0 Figure 6-11 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 6.5.8.2 • • Reserved—Bits 15–8 GPIOC6 (C6)—Bit 7 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This bit selects the alternate function for GPIOC6. 0 = TC0 (default) 1 = TXD0 6.5.8.3 • • GPIOC5 (C5)—Bit 6 This bit selects the alternate function for GPIOC5. 0 = TC1 (default) 1 = RXD0 6.5.8.4 • • GPIOB1 (B1)—Bit 5 This bit selects the alternate function for GPIOB1. 0 = MISO0 (default) 1 = RXD1 56F8323 Technical Data, Rev. 17 92 Freescale Semiconductor Preliminary Register Descriptions 6.5.8.5 • • GPIOB0 (B0)—Bit 4 This bit selects the alternate function for GPIOB0. 0 = SS0 (default) 1 = TXD1 6.5.8.6 • • GPIOA5 (A5)—Bit 3 This bit selects the alternate function for GPIOA5. 0 = PWMA5 1 = SCLK1 6.5.8.7 • • GPIOA4 (A4)—Bit 2 This bit selects the alternate function for GPIOA4. 0 = PWMA4 1 = MOS1 6.5.8.8 • • GPIOA3 (A3)—Bit 1 This bit selects the alternate function for GPIOA3. 0 = PWMA3 1 = MISO1 6.5.8.9 • • GPIOA2 (A2)—Bit 0 This bit selects the alternate function for GPIOA2. 0 = PWMA2 1 = SS1 6.5.9 Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip. Base + $C Read Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 14 1 13 ADCA 12 CAN 11 1 10 DEC0 9 1 8 TMRC 7 1 6 TMRA 5 4 3 SPI1 2 SPI0 1 1 0 PWMA SCI 1 SCI 0 Figure 6-12 Peripheral Clock Enable Register (SIM_PCE) 6.5.9.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 93 6.5.9.2 • • Analog-to-Digital Converter A Enable (ADCA)—Bit 13 Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.3 • • FlexCAN Enable (CAN)—Bit 12 Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.4 6.5.9.5 • • Reserved—Bit 11 Decoder 0 Enable (DEC0)—Bit 10 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.6 6.5.9.7 • • Reserved—Bit 9 Quad Timer C Enable (TMRC)—Bit 8 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 6.5.9.9 • • Reserved—Bit 7 Quad Timer A Enable (TMRA)—Bit 6 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.10 • • Serial Communications Interface 1 Enable (SCI1)—Bit 5 Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 56F8323 Technical Data, Rev. 17 94 Freescale Semiconductor Preliminary Register Descriptions 6.5.9.11 • • Serial Communications Interface 0 Enable (SCI0)—Bit 4 Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.12 • • Serial Peripheral Interface 1 Enable (SPI1)—Bit 3 Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.13 • • Serial Peripheral Interface 0 Enable (SPI0)—Bit 2 Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 6.5.9.15 • • Reserved—Bit 1 Pulse Width Modulator A Enable (PWMA)—Bit 0 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL) The I/O Short Address Location registers are used to specify the memory referenced via the I/O short address mode. The I/O short address mode allows the instruction to specify the lower six bits of address; the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure 6-13. Note: If this register is set ot something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 95 “Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction Instruction Portion 16 Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24-Bit for Short I/O Address Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents prior to returning from interrupt. Note: Note: The default value of this register set points to the EOnCE registers. The pipeline delay between setting this register set and using short I/O addressing with the new value is five cycles. Base + $D Read Write RESET 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 0 ISAL[23:22] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-14 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. Base + $E Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISAL[21:6] Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL) 56F8323 Technical Data, Rev. 17 96 Freescale Semiconductor Preliminary Clock Generation Overview 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.6 Clock Generation Overview The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible means to manage power consumption. Power utilization can be minimized in several ways. In the OCCS, the relaxation oscillator, crystal oscillator, and PLL may be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused. Clock enables provide the means to disable individual clocks. Some peripherals provide further controls to disable unused subfunctions. Refer to Part 3 On-Chip Clock Synthesis (OCCS), and the 56F8300 Peripheral User Manual for further details. The memory, peripheral and core clocks all operate at the same frequency (60MHz max). 6.7 Power-Down Modes The 56F8323/56F8123 operate in one of three power-down modes, as shown in Table 6-2. Table 6-2 Clock Operation in Power-Down Modes Mode Run Wait Core Clocks Active Core and memory clocks disabled Peripheral Clocks Active Active Description Device is fully functional Peripherals are active and can produce interrupts if they have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation. Typically used for power-conscious applications. The only possible recoveries from Stop mode are: 1. CAN traffic (1st message will be lost) 2. Non-clocked interrupts (IRQA) 3. COP reset 4. External reset 5. Power-on reset Stop System clocks continue to be generated in the SIM, but most are gated prior to reaching memory, core and peripherals. All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz. Refer to the PCE register in Part 6.5.9 and ADC power modes. Power is a function of the system frequency, which can be controlled through the OCCS. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 97 6.8 Stop and Wait Mode Disable Function Permanent Disable D Q D-FLOP C Reprogrammable Disable 56800E STOP_DIS D Q D-FLOP Clock Select Reset CR Note: Wait disable circuit is similar Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E system clock must be set equal to the prescaler output. Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those instructions, write to the SIM control register (SIM_CONTROL) described in Part 6.5.1. This procedure can be on either a permanent or temporary basis. Permanently assigned applications last only until their next reset. 6.9 Resets The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within the SIM itself, by writing to the SIM_CONTROL register, and the COP reset. Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced to permit proper operation of the device. A POR reset is declared when reset is removed and any of the three voltage detectors (1.8V POR, 2.2V core voltage, or 2.7V I/O voltage) indicate a low supply voltage condition. POR will continue to be asserted until all voltage detectors indicate a stable supply is available (note that as power is removed POR is not declared until the 1.8V core voltage threshold is reached.) A POR reset is then extended for 64 clock cycles to permit stabilization of the clock source, followed by a 32 clock window in which SIM clocking is initiated. It is then followed by a 32 clock window in which peripherals are released to implement Flash security, and, finally, followed by a 32 clock window in which the core is initialized. After completion of the described reset sequence, application code will begin execution. Resets may be asserted asynchronously, but are always released internally on a rising edge of the system clock. 56F8323 Technical Data, Rev. 17 98 Freescale Semiconductor Preliminary Operation with Security Enabled Part 7 Security Features The 56F8323/56F8123 offer security features intended to prevent unauthorized users from reading the contents of the Flash memory (FM) array. The Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array. However, part of the security must lie with the user’s code. An extreme example would be user’s code that dumps the contents of the internal program, as this code would defeat the purpose of security. At the same time, the user may also wish to put a “backdoor” in his program. As an example, the user downloads a security key through the SCI, allowing access to a programming routine that updates parameters stored in another section of the Flash. 7.1 Operation with Security Enabled Once the user has programmed the Flash with his application code, the device can be secured by programming the security bytes located in the FM configuration field, which occupies a portion of the FM array. These non-volatile bytes will keep the part secured through reset and through power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module specification, the device will disable the EOnCE interface, preventing access to internal code. Normal program execurtion is otherwise unaffected. 7.2 Flash Access Blocking Mechanisms The 56F8323/56F8123 have several operating functional and test modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be compromised and read without explicit user permission. Methods to block these are outlined in the next subsections. 7.2.1 • • Forced Operating Mode Selection Unsecured Mode Secure Mode (EOnCE disabled) At boot time, the SIM determines in which functional modes the device will operate. These are: When Flash security is enabled as described in the Flash Memory module specification, the device will disable the EOnCE debug interface. 7.2.2 Disabling EOnCE Access On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability and access to the ID register. Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled. The 56800E core has an input which disables reading of internal memory via the JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security bytes. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 99 7.2.3 Flash Lockout Recovery If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory configuration (.cfg) files. Add, or uncomment the following configuration command: unlock_flash_on_connect 1 For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual. The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control the period of the clock used for timed events in the FM erase algorithm. This register must be set with appropriate values before the lockout sequence can begin. Refer to the 56F8300 Peripheral User Manual for more details on setting this register value. The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values. Flash Memory SYS_CLK 2 input clock 7 FMCLKD 7 DIVIDER FMCLKDIV JTAG FMERASE 7 Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. 56F8323 Technical Data, Rev. 17 100 Freescale Semiconductor Preliminary Flash Access Blocking Mechanisms EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8=FM_CLKDIV[6]=0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively. 150[kHz] ( < SYS_CLK (2) (DIV + 1) )< 200[kHz] EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8=FM_CLKDIV[6]=1. Using the following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of 181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively. 150[kHz] ( < SYS_CLK (2)(8) (DIV + 1) )< 200[kHz] Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User Manual. Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured operation. 7.2.4 Product Analysis The recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows backdoor key access must be set. An alternative method for performing analysis on a secured microcontroller would be to mass-erase and reprogram the Flash with the original code, but to modify the security bytes. To insure that a customer does not inadvertently lock himself out of the device during programming, it is recommended that he program the backdoor access key first, his application code second and the security bytes within the FM configuration field last. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 101 Part 8 General Purpose Input/Output (GPIO) 8.1 Introduction This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. This information supercedes the generic information in the 56F8300 Peripheral User Manual. 8.2 Configuration There are three GPIO ports defined on the 56F8323/56F8123. The width of each port and the associated peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is shown in Table 8-3. Table 8-1 56F8323 GPIO Ports Configuration GPIO Port Port Width 12 8 7 Available Pins in 56F8323 12 8 7 Peripheral Function Reset Function A B C PWM, SPI 1 SPI 0, DEC 0, TMRA, SCI 1 XTAL, EXTAL, CAN, TMRC, SCI 0 PWM SPI 0, DEC 0 XTAL, EXTAL, CAN, TMRC Table 8-2 56F8123 GPIO Ports Configuration GPIO Port Port Width 12 8 7 Available Pins in 56F8123 12 8 7 Peripheral Function Reset Function A B C SPI 1 SPI 0, SCI 1, TMRA XTAL, EXTAL, TMRC, SCI 0 Must be reconfigured SPI 0; other pins must be reconfigured XTAL, EXTAL, TMRC; other pins must be reconfigured Note: Pins in italics are NOT available in the 56F8123 device. 56F8323 Technical Data, Rev. 17 102 Freescale Semiconductor Preliminary Configuration Table 8-3 GPIO External Signals Map GPIO Function GPIOA0 GPIOA1 GPIOA2 Peripheral Function PWMA0 PWMA1 PWMA2 / SSI 3 4 7 Package Pin Notes PWM is NOT available in 56F8123 PWM is NOT available in 56F8123 SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis PWM is NOT available in 56F8123 SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis PWM is NOT available in 56F8123 SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis PWM is NOT available in 56F8123 SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis PWM is NOT available in 56F8123 GPIOA3 PWMA3 / MISO1 8 GPIOA4 PWMA4 / MOSI1 9 GPIOA5 PWMA5 / SCLK1 10 GPIOA6 GPIOA7 GPIOA8 GPIOA9 GPIOA10 GPIOA11 GPIOB0 GPIOB1 GPIOB2 GPIOB3 GPIOB4 FAULTA0 FAULTA1 FAULTA2 ISA0 ISA0 ISA2 SS0 / TXD1 MISO0 / RXD1 MOSI0 SCLK0 HOME0 / TA3 13 14 15 16 18 19 21 22 24 25 49 Quad Decoder 0 register DECCR is used to select between Decoder 0 and Timer A Quad Decoder is NOT available in 56F8123 Quad Decoder 0 register DECCR is used to select between Decoder 0 and Timer A Quad Decoder is NOT available in 56F8123 Quad Decoder 0 register DECCR is used to select between Decoder 0 and Timer A Quad Decoder is NOT available in 56F8123 SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis SIM register SIM_GPS is used to select between SPI1 and PWMA on a pin-by-pin basis GPIOB5 INDEX0 / TA2 50 GPIOB6 PHASEB0 / TA1 51 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 103 Table 8-3 GPIO External Signals Map (Continued) GPIO Function GPIOB7 Peripheral Function PHASEA0 / TA0 Package Pin 52 Notes Quad Decoder 0 register DECCR is used to select between Decoder 0 and Timer A Quad Decoder is NOT available in 56F8123 Pull-ups default to disabled Pull-ups default to disabled CAN is NOT available in 56F8123 CAN is NOT available in 56F8123 GPIOC0 GPIOC1 GPIOC2 GPIOC3 GPIOC4 GPIOC5 GPIOC6 EXTAL XTAL CAN_RX CAN_TX TC3 TC1 / RXD0 TC0 / TXD0 46 47 61 62 63 64 1 SIM register SIM_GPS is used to select between Timer C and SCI0 on a pin-by-pin basis SIM register SIM_GPS is used to select between Timer C and SCI0 on a pin-by-pin basis 8.3 Memory Maps The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based on this and the default function of each of the GPIO pins, the reset values of the GPIOX_PUR and GPIOX_PER registers change from port to port. Tables 4-21 through 4-23 define the actual reset values of these registers. Part 9 Joint Test Action Group (JTAG) 9.1 JTAG Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. 56F8323 Technical Data, Rev. 17 104 Freescale Semiconductor Preliminary General Characteristics Part 10 Specifications 10.1 General Characteristics The 56F8323/56F8123 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage. Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Note: All specifications meet both Automotive and Industrial requirements unless individual specifications are listed. Note: The 56F8123 device is guaranteed to 40MHz and specified to meet Industrial requirements only. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 105 Note: The 56F8123 device is specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8123 device. Table 10-1 Absolute Maximum Ratings (VSS = VSSA_ADC = 0) Characteristic Supply voltage ADC Supply Voltage Symbol VDD_IO VDDA_ADC, VREFH VDDA_OSC_PLL VDD_CORE VIN VINA VOUT VOUTOD TA TA TJ TJ TSTG TSTG OCR_DIS is High Pin Groups 1, 3, 4, 5 Pin Groups 7, 8 Pin Groups 1, 2, 3 Notes Min - 0.3 Max 4.0 4.0 Unit V V VREFH must be less than or equal to VDDA_ADC - 0.3 Oscillator / PLL Supply Voltage Internal Logic Core Supply Voltage Input Voltage (digital) Input Voltage (analog) Output Voltage - 0.3 - 0.3 -0.3 -0.3 -0.3 4.0 3.0 6.0 4.0 4.0 6.01 6.0 125 105 150 125 150 150 V V V V V Output Voltage (open drain) Ambient Temperature (Automotive) Ambient Temperature (Industrial) Junction Temperature (Automotive) Junction Temperature (Industrial) Storage Temperature (Automotive) Storage Temperature (Industrial) GPIO pins used in open drain mode -0.3 -40 -40 -40 -40 -55 -55 V °C °C °C °C °C °C 1. If corresponding GPIO pin is configured as open drain. Note: Pins in italics are NOT available in the 56F8123 device. Pin Group 1: TC0-1, TC3, FAULTA0-2, ISA0-2, SS0, MISO0, MOSI0, SCLK0, HOME0, INDEX0, PHASEA0, PHASEB0, CAN_RX, CAN_TX, GPIOC0-1 Pin Group 2: TDO Pin Group 3: PWMA0-5 Pin Group 4: RESET, TMS, TDI, TRST, IRQA Pin Group 5: TCK Pin Group 6: XTAL, EXTAL Pin Group 7: ANA0-7 Pin Group 8: OCR_DIS 56F8323 Technical Data, Rev. 17 106 Freescale Semiconductor Preliminary General Characteristics Table 10-2 56F8323/56F8123 ElectroStatic Discharge (ESD) Protection Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Change Device Model (CDM) Min 2000 200 500 Typ — — — Max — — — Unit V V V Table 10-3 Thermal Characteristics6 Value Characteristic Comments Symbol 64-pin LQFP Unit Notes Junction to ambient Natural Convection Junction to ambient (@1m/sec) Junction to ambient Natural Convection Junction to ambient (@1m/sec) Junction to case Junction to center of case I/O pin power dissipation Power dissipation Four layer board (2s2p) Four layer board (2s2p) RθJA RθJMA RθJMA (2s2p) RθJMA RθJC ΨJT P I/O PD 41 34 34 29 8 2 User-determined P D = (IDD x VDD + P I/O) (TJ - TA) / RθJA7 °C/W °C/W °C/W °C/W °C/W °C/W W W 2 2 1,2 1,2 3 4, 5 Maximum allowed PD PDMAX W 1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. 2. Junction-to-ambient thermal resistance, Theta-JA (RθJA ), was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. 3. Junction-to-case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. Thermal Characterization Parameter, Psi-JT (ΨJT ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to estimate junction temperature in steady-state customer environments. 5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. See Part 12.1 for more details on thermal design considerations. 7. TJ = Junction temperature TA = Ambient temperature 56F8323 Technical Data, Rev. 17 Freescale Semiconductor Preliminary 107 Note: The 56F8123 device is guaranteed to 40MHz and specified to meet Industrial requirements only; PWM, CAN and Quad Decoder are NOT available on the 56F8123 device. Table 10-4 Recommended Operating Conditions (VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL ) Characteristic Symbol VDD_IO VDDA_ADC, VREFH VDDA_OSC_PLL VDD_CORE FSYSCLK VIN VIHA VIHC VIHC VIL IOH IOL TA TA NF NF TR TA = -40°C to 125°C TA = -40°C to 105°C TJ