68HC05BD2

Freescale Semiconductor, Inc. HC05BD7GRS/H REV 2.0 68HC05BD7 68HC705BD7 68HC05BD2 Freescale Semiconductor, Inc... SPECIFICATION REV 2.0 (General Release) © January 20, 1998 Technical Operation Taiwan Taipei, Taiwan For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS SECTION 1 GENERAL DESCRIPTION .............................................. 1 Features......................................................................................1 Hardware Features................................................................1 Software Features .................................................................3 Signal Description.......................................................................7 VDD and VSS........................................................................7 IRQ/VPP................................................................................7 EXTAL, XTAL ........................................................................7 Crystal Oscillator..............................................................7 RESET ..................................................................................8 PA0-PA7................................................................................8 PB0-PB5................................................................................8 PC0*/PWM8*-PC1*/PWM9* ..................................................8 PC2/PWM10/ADC0- PC5/PWM13/ADC3 .............................8 PC6/PWM14/VSYNO, PC7/PWM15/HSYNO .......................8 PD0*/SDA*, PD1*/SCL* ........................................................8 PD2***/CLAMP, PD3*/SOG ..................................................8 PWM0**-PWM7** ..................................................................9 HSYNC, VSYNC ...................................................................9 Options .......................................................................................9 1.1 1.1.1 1.1.2 1.2 1.2.1 1.2.2 1.2.3 1.2.3.1 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.2.11 1.2.12 1.2.13 1.3 Freescale Semiconductor, Inc... SECTION 2 2.1 2.2 2.3 2.4 MEMORY ....................................................................... 11 COP ..........................................................................................15 ROM .........................................................................................15 EPROM.....................................................................................15 RAM..........................................................................................15 SECTION 3 CPU CORE..................................................................... 17 Registers...................................................................................17 Accumulator (A)...................................................................17 Index Register (X) ...............................................................18 Stack Pointer (SP)...............................................................18 Program Counter (PC) ........................................................18 Condition Code Register (CCR) ..........................................18 Half Carry Bit (H-Bit) ......................................................19 Interrupt Mask (I-Bit) ......................................................19 Negative Bit (N-Bit) ........................................................19 Zero Bit (Z-Bit) ...............................................................19 Carry/Borrow Bit (C-Bit) .................................................19 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.5.1 3.1.5.2 3.1.5.3 3.1.5.4 3.1.5.5 SECTION 4 4.1 4.2 4.3 INTERRUPTS................................................................. 21 CPU Interrupt Processing .........................................................21 Reset Interrupt Sequence.........................................................23 Software Interrupt (SWI) ...........................................................23 For More Information On This Product, Go to: www.freescale.com Page i Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Hardware Interrupts.................................................................. 23 External Interrupt (IRQ)....................................................... 23 VSYNC Interrupt ................................................................. 24 DDC12AB Interrupt ............................................................. 24 Multi-Function Timer Interrupt (MFT) .................................. 25 SECTION 5 5.1 5.2 5.2.1 5.2.2 5.2.3 RESETS..........................................................................27 External Reset (RESET) .......................................................... 27 Internal Resets ......................................................................... 27 Power-On Reset (POR) ...................................................... 27 Computer Operating Properly Reset (COPR)..................... 27 Illegal Address (ILADR) Reset ............................................ 28 Freescale Semiconductor, Inc... SECTION 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.7 OPERATING MODES ....................................................29 User Mode................................................................................ 29 SELF-CHECK MODE............................................................... 29 Bootstrap Mode ........................................................................ 29 Mode Entry ............................................................................... 29 EPROM Programming.............................................................. 30 Programming Sequence ..................................................... 30 Programming Control Register (PCR) ................................ 31 Low Power Modes.................................................................... 31 STOP Instruction................................................................. 31 WAIT Instruction ................................................................. 31 COP Watchdog Timer Considerations ..................................... 32 SECTION 7 7.1 7.2 7.3 7.4 7.5 7.6 INPUT/OUTPUT PORTS ................................................33 Port A ....................................................................................... 33 Port B ....................................................................................... 33 Port C ....................................................................................... 33 Port D ....................................................................................... 33 Input/Output Programming ....................................................... 34 Port C and D Configuration Register........................................ 35 SECTION 8 8.1 8.2 PULSE WIDTH MODULATION......................................37 Operation of 8-Bit PWM ........................................................... 37 Open-Drain Option Register..................................................... 38 SECTION 9 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 DDC12AB INTERFACE .................................................39 Introduction............................................................................... 39 DDC12AB Features.................................................................. 39 Registers .................................................................................. 40 DDC Address Register (DADR) .......................................... 40 DDC Control Register (DCR) .............................................. 40 DDC Master Control Register (DMCR) ............................... 41 DDC Status Register (DSR)................................................ 43 DDC Data Transmit Register (DDTR)................................. 44 Page ii For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 9.3.6 9.4 9.5 DDC Data Receive Register (DDRR)..................................44 Data Sequence .........................................................................45 Program Algorithm....................................................................45 SECTION 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 SYNC PROCESSOR...................................................... 49 Introduction ...............................................................................49 Functional Blocks......................................................................49 Polarity Detection ................................................................49 Sync Signal Counters..........................................................49 Polarity Controlled HSYNO/VSYNO Outputs ......................49 CLAMP Pulse Output ..........................................................50 Registers...................................................................................51 Sync Processor Control and Status Register (SPCSR) ......51 Sync Processor Input/Output Control Register (SPIOCR) ..52 Vertical Frequency Registers (VFRs)..................................53 Hsync Frequency Registers (HFRs)....................................54 System Operation .....................................................................54 Freescale Semiconductor, Inc... SECTION 11 11.1 11.2 11.2.1 11.2.2 MULTI-FUNCTION TIMER............................................. 57 Introduction ...............................................................................57 Register ....................................................................................57 Multi-function Timer Control/status Register .......................57 MFT Timer Counter Register...............................................59 SECTION 12 12.1 12.2 12.2.1 12.3 12.3.1 12.3.2 12.4 A/D CONVERTER.......................................................... 61 Introduction ...............................................................................61 Input..........................................................................................61 ADC0-ADC3 ........................................................................61 Registers...................................................................................62 ADC Control/status Register ...............................................62 ADC Channel Register ........................................................62 Program Example .....................................................................63 SECTION 13 13.1 13.2 13.3 13.4 13.5 13.5.1 13.5.2 13.6 ELECTRICAL SPECIFICATIONS.................................. 65 Maximum Ratings .....................................................................65 Thermal Characteristics............................................................65 DC Electrical Characteristics ....................................................66 Control Timing ..........................................................................67 DDC12AB TIMING....................................................................68 DDC12AB Interface Input Signal Timing .............................68 DDC12AB Interface Output Signal Timing ..........................68 HSYNC/VSYNC Input Timing ...................................................69 SECTION 14 14.1 14.2 14.3 MECHANICAL SPECIFICATIONS ................................ 71 Introduction ...............................................................................71 40-Pin DIP Package (Case 711-03) .........................................71 42-Pin SDIP Package (Case 858-01) .......................................71 For More Information On This Product, Go to: www.freescale.com Page iii Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 SECTION 15 APPLICATION DIAGRAM .............................................73 Freescale Semiconductor, Inc... Page iv For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION LIST OF FIGURES Figure 1-1: MC68HC05BD7 Block Diagram .....................................................................4 Figure 1-2: MC68HC05BD7/BD2 40-Pin DIP Pin Assignment .........................................5 Figure 1-3: MC68HC05BD7/BD2 42-Pin SDIP Pin Assignment.......................................6 Figure 1-4: Oscillator Connections ...................................................................................7 Figure 2-1: The 16K Memory Map of the MC68HC05BD7.............................................11 Figure 2-2: MC68HC05BD7 I/O Register $00-$0F.........................................................12 Figure 2-3: MC68HC05BD7 I/O Register $10-$1F.........................................................13 Figure 2-4: MC68HC05BD7 I/O Register $20-$2F.........................................................14 Figure 3-1: MC68HC05 Programming Model .................................................................17 Figure 4-1: Interrupt Processing Flowchart ....................................................................22 Figure 4-2: External Interrupt..........................................................................................24 Figure 6-1: Mode Entry Diagram ....................................................................................30 Figure 6-2: WAIT Flowcharts..........................................................................................32 Figure 7-1: Port I/O Circuitry...........................................................................................34 Figure 8-1: PWM Data Register .....................................................................................37 Figure 8-2: Relationship Between 5-Bit PWM and 3-Bit BRM........................................38 Figure 8-3: PWM Open-Drain Option Register...............................................................38 Figure 9-1: Software Flowchart of Slave Mode Interrupt Routine...................................47 Figure 9-2: Software Flowchart in Master mode: (a) Mode setup. (b) Interrupt routine..48 Figure 10-1: CLAMP output waveform ...........................................................................50 Figure 12-1: Structure of A/D Converter.........................................................................61 Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Page v Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 Freescale Semiconductor, Inc... Page vi For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION LIST OF TABLES Table 4-1: Vector Address for Interrupts and Reset .......................................................21 Table 6-1: Mode Select Summary ..................................................................................30 Table 7-1: I/O Pin Functions...........................................................................................35 Table 9-1: Pre-scaler of Master Clock Baudrate ............................................................42 Table 11-1: COP Reset Rates and RTI Rates................................................................59 Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Page vii Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 Freescale Semiconductor, Inc... THIS PAGE INTENTIONALLY LEFT BLANK Page viii For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION SECTION 1 GENERAL DESCRIPTION The MC68HC05BD7 HCMOS microcontroller is a member of the M68HC05 Family of lowcost single-chip microcontrollers. It is particularly suitable as multi-sync computer monitor controller. This 8-bit microcontroller unit (MCU) contains an on-chip oscillator, CPU, RAM, ROM, DDC12AB module, parallel I/O, Pulse Width Modulator, Multi-Function Timer, 6-bit ADC, and SYNC Processor. 1.1 1.1.1 Features Hardware Features • • • • • • • • • HC05 Core Low cost, HCMOS technology 40-pin DIP and 42-pin SDIP packages 256 Bytes of RAM for HC05BD2 Freescale Semiconductor, Inc... 5.75K-Bytes of User ROM for HC05BD2 11.5K-Bytes of User EPROM for HC705BD7 • • • • • • † DDC †† I2C-bus is a standard defined by VESA. is a proprietary Philips interface bus. SECTION 1: GENERAL DESCRIPTION For More Information On This Product, Go to: www.freescale.com PR 16 x 8-bit PWM channels: Two 8-bit PWM channels have +12V opendrain outputs: 8 dedicated 8-bit PWM channels have +5V open-drain output options 6-bit ADC with 4 selectable input channels Multi-Function Timer (MFT) with Periodic Interrupt Sync Signal Processor module for processing horizontal, vertical, composite, and SOG SYNC signals; frequency counting; polarity detection; polarity controlled HSYNO and VSYNO or extracted VSYNC outputs, and CLAMP pulse output DDC12AB† module contains DDC1 hardware and multi-master I2C†† hardware for DDC2AB protocol Software maskable Edge-Sensitive or Edge and Level-Sensitive External Interrupt EL 26 Bidirectional I/O lines: 14 dedicated and 12 multiplexed I/O lines. 4 of the 14 dedicated I/O lines and 6 of the 12 multiplexed I/O lines have max. +12V or +5V open-drain output buffers IM 11.75K-Bytes of User ROM for HC05BD7 IN 384 Bytes of RAM for HC05BD7HC705BD7 A Page 1 R Y Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 • • • COP watchdog Reset Power-On Reset Power Saving WAIT Mode; STOP Mode not implemented Freescale Semiconductor, Inc... PR EL SECTION 1: GENERAL DESCRIPTION Page 2 For More Information On This Product, Go to: www.freescale.com IM IN A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 1.1.2 • • • • • • • • • Software Features Similar to MC6800 8 X 8 unsigned multiply instruction Efficient use of program space Versatile interrupt handling Software programmable external interrupt options True bit manipulation Addressing modes with indexed addressing for tables Efficient instruction set Memory mapped I/O Upward software compatible with the MC146805 CMOS family Freescale Semiconductor, Inc... • SECTION 1: GENERAL DESCRIPTION For More Information On This Product, Go to: www.freescale.com PR EL IM IN A Page 3 R Y Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 PA0 PA1 PA2 PA3 PA4 PA5 PORT A REG DATA DIR REG VDD VSS EXTAL XTAL CORE TIMER (COP) RESET IRQ/VPP PWM0** PWM1** Pulse Width Modulation (PWM) PWM2** PWM3** PWM4** PWM5** PWM6** OSCILLATOR AND DIVIDE BY 2 Freescale Semiconductor, Inc... PA6 PA7 Y R CPU CONTROL 68HC05 CPU ALU 6-bit ADC PWM7** PB1 PB2* PB3* PB4* PB5* PORT B REG DATA DIR REG IN A ACCUM DDC12AB SP DDC12AB PD0*/SDA* PD1*/SCL* PD2***/CLAMP PD3*/SOG DATA PORT DIR D REG REG RAM SYNC PROCESSOR HSYNC VSYNC PB0 CPU REGISTERS INDEX REG PC0*/PWM8* PWM/ADC/HVPROCESSOR PC1*/PWM9* PC2/PWM10/ADC0 PC3/PWM11/ADC1 PC4/PWM12/ADC2 PC5/PWM13/ADC3 PR PORT DATA C DIR REG REG EL PC6/PWM14/VSYNO PC7/PWM15/HSYNO 5.75K-bytes ROM for HC05BD2 11.75K-bytes ROM for HC05BD7 11.5K-bytes EPROM for HC705BD7 IM 0 0 0 0 0 0 0 0 1 1 STK PTR PROGRAM COUNTER COND CODE REG 1 1 1 H I N Z C 256 bytes for HC05BD2 384 bytes for HC05BD7 384 bytes for HC705BD7 ***: +5V open-drain **: +5V open-drain option *: +12V open-drain IRQ/VPP: VPP valid for HC705 version only, not used for HC05 version Figure 1-1: MC68HC05BD7 Block Diagram SECTION 1: GENERAL DESCRIPTION Page 4 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION PWM2** PWM1** PWM0** RESET VDD VSS XTAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 VSYNC HSYNC PWM3** PWM4** PWM5** PWM6** PWM7** PC7/PWM15/HSYNO PC6/PWM14/VSYNO PC5/PWM13/ADC3 PC4/PWM12/ADC2 PC3/PWM11/ADC1 PC2/PWM10/ADC0 PC1*/PWM9* PC0*/PWM8* PD1*/SCL* PD0*/SDA* PA0 PA1 PA2 Freescale Semiconductor, Inc... PB5* PB4* PB3* PB2* PB1 PB0 IRQ/VPP PA7 PA6 PA5 PA4 PA3 MC68HC05BD7 40-PIN DIP IN IM EL PR **: +5V open-drain option *: +12V open-drain IRQ/VPP: VPP valid for HC705 version only, not used for HC05 version Figure 1-2: MC68HC05BD7/BD2 40-Pin DIP Pin Assignment SECTION 1: GENERAL DESCRIPTION For More Information On This Product, Go to: www.freescale.com A R 31 30 29 28 27 26 25 24 23 22 21 Y EXTAL Page 5 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 PWM2** PWM1** PWM0** RESET VDD PD3*/SOG VSS XTAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 34 VSYNC HSYNC PWM3** PWM4** PWM5** PD2***/CLAMP PWM6** PWM7** Freescale Semiconductor, Inc... PB5* PB4* PB3* PB2* PB1 PB0 IRQ/VPP PA7 PA6 PA5 PA4 PA3 MC68HC05BD7 42-PIN SDIP 33 32 31 30 29 28 27 26 25 24 23 22 A IN IM EL 21 Figure 1-3: MC68HC05BD7/BD2 42-Pin SDIP Pin Assignment PR ***: +5V open-drain option **: +5V open-drain option *: +12V open-drain IRQ/VPP: VPP valid for HC705 version only, not used for HC05 version SECTION 1: GENERAL DESCRIPTION Page 6 For More Information On This Product, Go to: www.freescale.com R Y PA0 PA1 PA2 EXTAL PC7/PWM15/HSYNO PC6/PWM14/VSYNO PC5/PWM13/ADC3 PC4/PWM12/ADC2 PC3/PWM11/ADC1 PC2/PWM10/ADC0 PC1*/PWM9* PC0*/PWM8* PD1*/SCL* PD0*/SDA* Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 1.2 1.2.1 Signal Description VDD and VSS VDD is the positive supply pin and VSS is the ground pin. 1.2.2 IRQ/VPP This pin has two functions. While in user mode, this pin serves as IRQ, a general purpose interrupt input which is software programmable for two choices of interrupt triggering sensitivity. These options are: 1) negative edge-sensitive triggering only, or 2) both negative edge-sensitive and level-sensitive triggering. In the latter case, either type of input to the IRQ pin will produce the interrupt. This interrupt can be inhibited by setting the INHIRQ bit in the MFT register. While in bootstrap mode, this pin is used as VPP pin for HC705 version. It is used to supply high voltage needed for programming the user EPROM. Freescale Semiconductor, Inc... 1.2.3 EXTAL, XTAL 2. An external clock signal as shown in Figure 1-4(b) The frequency, fOSC, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP. 1.2.3.1 Crystal Oscillator PR The circuit in shows Figure 1-4(a) a typical oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. An internal start-up resistor of approximately 2 MΩ is provided between EXTAL and XTAL for the crystal type oscillator. MCU EL IM IN A 1. A crystal as shown in Figure 1-4(a) EXTAL XTAL (a) Crystal or Ceramic Resonator Connections 36 pF 36 pF R MCU EXTAL The EXTAL and XTAL pins are the connections for the on-chip oscillator. The EXTAL, and XTAL pins can accept the following sets of components: unconnected Y XTAL External Clock (b) External Clock Source Connection Figure 1-4: Oscillator Connections SECTION 1: GENERAL DESCRIPTION For More Information On This Product, Go to: www.freescale.com Page 7 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 1.2.4 RESET This active low input-only pin is used to reset the MCU to a known start-up state. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See SECTION 5 for more details. 1.2.5 PA0-PA7 These eight I/O lines comprise Port A. The state of any pin is software programmable and all Port A lines are configured as inputs during Reset. See SECTION 7 for a detailed description of I/O programming. 1.2.6 PB0-PB5 Freescale Semiconductor, Inc... 1.2.8 PC2/PWM10/ADC0- PC5/PWM13/ADC3 These four pins can be selected as general purpose I/O of port C, PWM or ADC input channel 0-2. See SECTION 7 for how to configure the pins. Also see SECTION 8 and SECTION 12 for a detailed description of these modules. 1.2.9 PC6/PWM14/VSYNO, PC7/PWM15/HSYNO 1.2.10 PD0*/SDA*, PD1*/SCL* These pins are either general purpose I/O pins of port D or the data line (SDA) and clock line (SCL) of DDC12AB. These two pins are open-drain pins. See SECTION 7 for how to configure the pins. See SECTION 9 for a detailed description. 1.2.11 PD2***/CLAMP, PD3*/SOG The PD2*** is +5V open-drain general purpose I/O pin and the PD3* is +12V open-drain general purpose I/O pin. The PD2 pin could become the CLAMP pulse push-pull output to Pre-AMP IC and the PD3 pin could become the SOG digital input of the Sync Processor when the corresponding enable bit in SPIOCR register is set. These two pins will not be bonded out in 40-pin DIP package. PR These two pins can be selected as general purpose I/O of port C, PWM or sync signal outputs. See SECTION 7 for how to configure the pins. Also see SECTION 8 and SECTION 10 for a detailed description of these modules. EL IM Page 8 For More Information On This Product, Go to: www.freescale.com IN These two +12V open-drain pins are either 8-bit PWM channels 8 to 9 outputs or general purpose I/O port C. The state of any pin is software programmable and all Port C lines are configured as inputs during Reset. See SECTION 7 for a detailed description of I/O programming. SECTION 1: GENERAL DESCRIPTION A R 1.2.7 PC0*/PWM8*-PC1*/PWM9* Y These six I/O lines comprise Port B. The state of any pin is software programmable and all Port B lines are configured as inputs during Reset. PB2 to PB5 are +12V open-drain pins. See SECTION 7 for a detailed description of I/O programming. Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 1.2.12 PWM0**-PWM7** These pins are dedicated for 8-bit PWM channels 0 to 7, which have +5V open-drain software options. See SECTION 8 for a detailed description. 1.2.13 HSYNC, VSYNC These two input pins are for video sync signals input from the host computer. The signals will be used for video mode detection and output to HSYNO and VSYNO. The host computer can also send a composite sync signal to the HSYNC input. This composite signal will be separated internally. The polarity of the input signals can be either positive or negative. These two pins contain internal Schmitt triggers as part of their inputs to improve noise immunity. See SECTION 10 for a detail description. 1.3 Options Freescale Semiconductor, Inc... SECTION 1: GENERAL DESCRIPTION For More Information On This Product, Go to: www.freescale.com PR EL IM IN A MC68HC05BD7 provides an option for IRQ interrupt edge only sensitivity or edge and level sensitivity and one option register for individual PWM channels 0 to 7 to be programmed as open-drain type output. The IRQ option is selected by setting the appropriate bit in the MFTCSR register at address $0008 and the PWM open-drain option register is located at address $0012. R Y Page 9 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 Freescale Semiconductor, Inc... PR EL SECTION 1: GENERAL DESCRIPTION Page 10 For More Information On This Product, Go to: www.freescale.com IM IN A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION SECTION 2 MEMORY The MC68HC05BD7 has a 16K byte memory map, consisting of user ROM/EPROM, RAM, Self-Check/Bootstrap ROM, and I/O as shown in Figure 2-1. $0000 $0030 I/O 48 Bytes Freescale Semiconductor, Inc... $00C0 $0100 $01B0 Unused $0E00 480 Bytes Bootstrap ROM for HC705BD7 Unused in HC05BD2/HC05BD7 $1000 PR $2800 $3E00 $3F00 224 Bytes Self-Check ROM for HC05BD2/HC05BD7 Unused in HC705BD7 $3FE0 $3FF0 $3FFF Self-Check/Bootstrap Vectors 16 Bytes User Vectors 16 Bytes Figure 2-1: The 16K Memory Map of the MC68HC05BD7 SECTION 2: MEMORY For More Information On This Product, Go to: www.freescale.com EL $0FE0 IM User ROM 5.57K-bytes for HC05BD2 11.75K-bytes for HC05BD7 User EPROM 11.5K-bytes for HC705BD7 IN A Page 11 R Stack RAM 64 Bytes 256 Bytes for HC05BD2 384 Bytes for HC05BD7/HC705BD7 Y Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 READ WRITE R W R W R PC7 W R W R W R W R W R W R TOF W RTIF DDRC7 DDRC6 DDRC5 DDRB5 DDRB4 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 ADDR REGISTER 7 6 5 4 3 2 1 0 $0000 PORT A DATA PORTA PORT B DATA PORTB PORT C DATA PORTC PORT D DATA PORTD PORT A DATA DIRECTION DDRA PORT B DATA DIRECTION DDRB PORT C DATA DIRECTION DDRC PORT D DATA DIRECTION DDRD MFT CTRL/STATUS REG MFTCSR MFT TIMER COUNTER REG MFTCR CONFIGURATION REG 1 CR1 CONFIGURATION REG 2 CR2 SP CONTROL & STATUS SPCSR $0001 $0002 $0003 PD3 PD2 PD1 PD0 $0004 Freescale Semiconductor, Inc... $0005 DDRB3 Y ADC0 VF3 VF2 HFH2 DDRB2 DDRB1 DDRB0 $0006 DDRC4 R DDRC3 DDRD3 IRQN ADC1 VINVO VF11 HFH3 DDRC2 DDRC1 DDRC0 A RTIE ADC2 COMP VF12 VF4 HFH4 $0007 $0008 DDRD2 DDRD1 DDRD0 IN ADC3 VSIF 0 0 VF5 HFH5 TOFIE INHIRQ RT1 RT0 R MFTCR7 MFTCR6 MFTCR5 MFTCR4 MFTCR3 MFTCR2 MFTCR1 MFTCR0 $0009 R W R W R $000A IM W PWM15 PWM14 PWM13 PWM12 PWM11 PWM10 PWM9 PWM8 EL $000B HSYNO VSYNO VSIE VOF VEDGE SCL VPOL SDA HPOL $000C HINVO VF10 W R $000D PR VERT FREQUENCY HIGH REG VFHR VERT FREQUENCY LOW REG VFLR HOR FREQUENCY HIGH REG HFHR VF9 VF8 W R W R W HOVER HFH6 HFH1 HFH0 VF7 VF6 VF1 VF0 $000E $000F UNIMPLEMENTED RESERVED Figure 2-2: MC68HC05BD7 I/O Register $00-$0F SECTION 2: MEMORY Page 12 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION READ WRITE R W R VSYNCS HSYNCS W R W R W $0014 ADC CONTROL/STATUS REG R RESULT W AD5 AD4 AD3 AD2 AD1 AD0 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 COINV SOGIN CLAMP BPOR SOUT ADDR REGISTER 7 0 6 0 5 0 4 HFL4 3 HFL3 2 HFL2 1 HFL1 0 HFL0 $0010 HOR FREQUENCY LOW REG HFLR SP IO CONTROL REG SPIOCR PWM OPEN-DRAIN OPTION REGISTER UNIMPLEMENTED $0011 $0012 7PWMO 6PWMO 5PWMO 4PWMO 3PWMO 2PWMO 1PWMO 0PWMO $0013 Freescale Semiconductor, Inc... Y ALIF NAKIF BB $0015 ADC CHANNEL REGISTER R W CHSL1 CHSL0 $0016 R MAST DAD4 RW DTD4 DRD4 DDC MASTER CONTROL REG DMCR DDC ADDRESS REGISTER DADR DDC CONTROL REGISTER DCR DDC STATUS REGISTER DSR DDC DATA TRANSMIT REG DDTR DDC DATA RECEIVE REG DDRR UNIMPLEMENTED R W R DAD7 W R W R W R DEN RXIF DAD6 DIEN TXIF MRW BR2 BR1 BR0 A DAD5 MATCH DTD5 DRD5 $0017 DAD3 DAD2 DAD1 EXTAD $0018 IN TXAK RXAK SCLIEN DDC1EN SCLIF TXBE RXBF $0019 IM DTD7 $001A DTD6 DRD6 DTD3 DRD3 DTD2 DRD2 DTD1 DRD1 DTD0 DRD0 W R $001C $001D PR RESERVED FOR EPROM CONTROL PCR UNIMPLEMENTED EL W R W R $001B DRD7 ELAT PGM W R W R W $001E $001F RESERVED UNIMPLEMENTED RESERVED Figure 2-3: MC68HC05BD7 I/O Register $10-$1F SECTION 2: MEMORY For More Information On This Product, Go to: www.freescale.com Page 13 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 READ WRITE R 0PWM4 0PWM3 0PWM2 0PWM1 0PWM0 W R W R W R W R W R W R W R W R W R W R W R W R 4PWM4 4PWM3 4PWM2 4PWM1 4PWM0 4BRM2 4BRM1 4BRM0 3PWM4 3PWM3 3PWM2 3PWM1 3PWM0 3BRM2 3BRM1 3BRM0 2PWM4 2PWM3 2PWM2 2PWM1 2PWM0 2BRM2 2BRM1 2BRM0 1PWM4 1PWM3 1PWM2 1PWM1 1PWM0 1BRM2 1BRM1 1BRM0 0BRM2 0BRM1 0BRM0 ADDR REGISTER 7 6 5 4 3 2 1 0 $0020 PULSE WIDTH MODULATOR 0PWM PULSE WIDTH MODULATOR 1PWM PULSE WIDTH MODULATOR 2PWM PULSE WIDTH MODULATOR 3PWM PULSE WIDTH MODULATOR 4PWM PULSE WIDTH MODULATOR 5PWM PULSE WIDTH MODULATOR 6PWM PULSE WIDTH MODULATOR 7PWM PULSE WIDTH MODULATOR 8PWM PULSE WIDTH MODULATOR 9PWM PULSE WIDTH MODULATOR 10PWM PULSE WIDTH MODULATOR 11PWM PULSE WIDTH MODULATOR 12PWM PULSE WIDTH MODULATOR 13PWM PULSE WIDTH MODULATOR 14PWM PULSE WIDTH MODULATOR 15PWM $0021 $0022 $0023 $0024 Freescale Semiconductor, Inc... $0025 5PWM4 5PWM3 5PWM2 5PWM1 5PWM0 Y 5BRM2 6BRM2 7BRM2 8BRM2 9BRM2 5BRM1 5BRM0 $0026 6PWM4 6PWM3 6PWM2 6PWM1 6PWM0 R 6BRM1 6BRM0 $0027 7PWM4 7PWM3 7PWM2 7PWM1 7PWM0 A 7BRM1 7BRM0 $0028 8PWM4 8PWM3 8PWM2 8PWM1 8PWM0 IN 8BRM1 8BRM0 $0029 9PWM4 9PWM3 9PWM2 9PWM1 9PWM0 9BRM1 9BRM0 $002A 10PWM4 10PWM3 10PWM2 10PWM1 10PWM0 10BRM2 10BRM1 10BRM0 $002C $002D PR $002E $002F EL W R W R W R W $002B 11PWM4 11PWM3 11PWM2 11PWM1 11PWM0 11BRM2 11BRM1 11BRM0 12PWM4 12PWM3 12PWM2 12PWM1 12PWM0 12BRM2 12BRM1 12BRM0 13PWM4 13PWM3 13PWM2 13PWM1 13PWM0 13BRM2 13BRM1 13BRM0 14PWM4 14PWM3 14PWM2 14PWM1 14PWM0 14BRM2 14BRM1 14BRM0 15PWM4 15PWM3 15PWM2 15PWM1 15PWM0 15BRM2 15BRM1 15BRM0 IM UNIMPLEMENTED RESERVED Figure 2-4: MC68HC05BD7 I/O Register $20-$2F SECTION 2: MEMORY Page 14 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 2.1 COP The COP time-out is prevented by writing a ‘0’ to bit 0 of address $3FF0. See SECTION 11 for detail. 2.2 ROM For MC68HC05BD7, the user ROM consists of 11.75K bytes of ROM from $1000 through $3EFF and 16 bytes of user vectors from $3FF0 through $3FFF. For MC68HC05BD2, the user ROM consists of 5.75K bytes of ROM from $2800 through $3EFF and 16 bytes of user vectors from $3FF0 through $3FFF. The Self-Check ROM is located from $3F00 through $3FE0 and Self-Check vectors are located from $3FE0 through $3FEF. 2.3 EPROM Freescale Semiconductor, Inc... 2.4 RAM The user RAM consists of 384 bytes from $0030 to $01AF for HC05BD7/HC705BD7. User RAM consists of 256 bytes from $30 to $12F for HC05BD2. The stack pointer can access 64 bytes of RAM from $00FF to $00C0. See Section 3.1.3, Stack Pointer (SP). NOTE: Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. SECTION 2: MEMORY For More Information On This Product, Go to: www.freescale.com PR EL IM IN A Page 15 R For MC68HC705BD7, the user EPROM consists of 11.5K bytes of EPROM from $1000 through $3DFF and 16 bytes of user vectors from $3FF0 through $3FFF. The Bootstrap ROM is located from $0E00 through $0FDF and Bootstrap vectors are located from $3FE0 through $3FEF, at the same location as Self-Check vectors. Y Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 Freescale Semiconductor, Inc... THIS PAGE INTENTIONALLY LEFT BLANK PR EL SECTION 2: MEMORY Page 16 For More Information On This Product, Go to: www.freescale.com IM IN A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION SECTION 3 CPU CORE The MC68HC05BD7 has a 16K memory map. Therefore it uses only the lower 14 bits of the address bus. In the following discussion the upper 2 bits of the address bus can be ignored. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other instructions and registers behave as described in this chapter. 3.1 Registers Freescale Semiconductor, Inc... 7 A 6 5 1 1 1 ZERO BIT CARRY BIT R 4 3 2 1 0 A IN 8 0 1 1 ACCUMULATOR 0 0 0 0 0 IM 15 14 13 12 11 10 0 9 INDEX REGISTER Y I N The MCU contains five registers which are hard-wired within the CPU and are not part of the memory map. These five registers are shown in Figure 3-1 and are described in the following paragraphs. X 0 STACK POINTER SP EL PROGRAM COUNTER PC CONDITION CODE REGISTER H Z C CC PR 3.1.1 Accumulator (A) SECTION 3: CPU CORE HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT Figure 3-1: MC68HC05 Programming Model The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is not affected by a reset of the device. For More Information On This Product, Go to: www.freescale.com Page 17 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 3.1.2 Index Register (X) The index register shown in Figure 3-1 is an 8-bit register that can perform two functions: • • Indexed addressing Temporary storage In indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU finds the operand address by adding the index register content to an 8-bit immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand address by adding the index register content to a 16-bit immediate value. The index register can also serve as an auxiliary accumulator for temporary storage. The index register is not affected by a reset of the device. Freescale Semiconductor, Inc... 3.1.3 Stack Pointer (SP) 3.1.4 Program Counter (PC) Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.1.5 Condition Code Register (CCR) The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be individually tested by a program, and specific actions can be taken as a result of their states. The condition code register should be thought of as having three additional upper bits that are always ones. Only the interrupt mask is affected by a reset of the device. The following paragraphs explain the functions of the lower five bits of the condition code register. SECTION 3: CPU CORE Page 18 For More Information On This Product, Go to: www.freescale.com PR The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64K bytes the unimplemented upper address lines are ignored. The program counter contains the address of the next instruction or operand to be fetched. EL When accessing memory, the ten most significant bits are permanently set to 0000000011. The six least significant register bits are appended to these ten fixed bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 ($40) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack and an interrupt uses five locations. IM IN The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64K bytes the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer is set to $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 3.1.5.1 Half Carry Bit (H-Bit) When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded decimal (BCD) arithmetic operations. 3.1.5.2 Interrupt Mask (I-Bit) When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt mask is cleared. Freescale Semiconductor, Inc... 3.1.5.3 Negative Bit (N-Bit) The negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (Bit 7 of the result was a logical one.) The negative bit can also be used to check an often tested flag by assigning the flag to bit 7 of a register or memory location. Loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the flag. 3.1.5.4 Zero Bit (Z-Bit) 3.1.5.5 Carry/Borrow Bit (C-Bit) SECTION 3: CPU CORE For More Information On This Product, Go to: www.freescale.com PR The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction. EL The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. IM IN A R Page 19 Y A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), or WAIT instructions. Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 Freescale Semiconductor, Inc... THIS PAGE INTENTIONALLY LEFT BLANK PR EL SECTION 3: CPU CORE Page 20 For More Information On This Product, Go to: www.freescale.com IM IN A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION SECTION 4 4.1 CPU Interrupt Processing INTERRUPTS Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I-bit in the CCR is cleared) and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs the processor completes the current instruction, then stacks the current CPU register states, sets the I-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. Freescale Semiconductor, Inc... Table 4-1: Vector Address for Interrupts and Reset Register N/A N/A N/A SPCSR DMCR DSR Flag N/A N/A N/A VSIF TXIF RXIF ALIF NAKIF SCLIF TOF RTIF N/A N/A IM IN When an interrupt is to be processed the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $3FF0 thru $3FFF as defined in Table 4-1. A Interrupts CPU Int RESET SWI IRQ SP DDC12AB EL PR Reset Software External Interrupt VSINT DDC12AB interrupt R MFT N/A N/A MFTCSR N/A N/A Timer Overflow Real Time Interrupt N/A N/A An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt processing. SECTION 4: INTERRUPTS For More Information On This Product, Go to: www.freescale.com Y Vector Adds. $3FFE-$3FFF $3FFC-$3FFD $3FFA-$3FFB $3FF8-$3FF9 $3FF6-$3FF7 $3FF4-$3FF5 $3FF2-$3FF3 $3FF0-$3FF1 Page 21 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 From RESET Y Is I-Bit Set? N IRQ External Interrupt? N V Sync Interrupt? N DDC12AB Interrupt? N MFT Interrupt? N Y Clear IRQ Latch Y Freescale Semiconductor, Inc... Y Y EL Y Y IM PC -> (SP,SP-1) X -> (SP-2) A -> (SP-3) CC -> (SP-4) Set I-Bit in CCR Load Interrupt Vectors to PC Restore Registers from Stack CC, A, X, PC PR Fetch Next Instruction SWI Instruction? N RTI Instruction? N Execute Instruction Figure 4-1: Interrupt Processing Flowchart SECTION 4: INTERRUPTS Page 22 For More Information On This Product, Go to: www.freescale.com IN A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 4.2 Reset Interrupt Sequence The RESET function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner. A low level input on the RESET pin or an internally generated reset signal causes the program to vector to its starting address which is specified by the contents of $3FFE and $3FFF. The I-bit in the condition code register is also set. The MCU is configured to a known state during this type of reset as described in SECTION 5. 4.3 Software Interrupt (SWI) Freescale Semiconductor, Inc... 4.4.1 External Interrupt (IRQ) If the IRQ option is negative edge sensitive triggering (IRQN=1), a negative edge occurs at the IRQ pin and a cleared interrupt mask bit of the condition code register will cause an EXTERNAL INTERRUPT to occur. If the MCU has finished with the interrupt service routine, but the IRQ pin has not returned back to high, no further interrupt will be generated. The interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) only. If the negative edge occurs while the interrupt mask bit is set, the interrupt signal will be latched, and interrupt will occur as soon as the interrupt mask bit is cleared. The latch will be cleared by RESET or cleared automatically during fetch of the EXTERNAL INTERRUPT vectors. Therefore, one (and only one) external interrupt edge could be latched while the interrupt mask bit is set. If the INHIRQ bit in the MFT register is set, no IRQ interrupt can be generated. The service routine address is specified by the contents of $3FFA and $3FFB. Figure 4-2 shows the two methods for the interrupt line (IRQ) to be recognized by the processor. The first method is single pulses on the interrupt line spaced far apart enough to be serviced. The minimum time between pulses is a function of the number of cycles required to execute SECTION 4: INTERRUPTS For More Information On This Product, Go to: www.freescale.com PR If the IRQ option is edge and level sensitive triggering (IRQN=0), a low level at the IRQ pin and a cleared interrupt mask bit of the condition code register will cause an EXTERNAL INTERRUPT to occur. If the MCU has finished with the interrupt service routine, but the IRQ pin is still low, the EXTERNAL INTERRUPT will start again. In fact, the MCU will keep on servicing the EXTERNAL INTERRUPT as long as the IRQ pin is low. If the IRQ pin goes low for a while and resumes to high (a negative pulse) before the interrupt mask bit is cleared, the MCU will not recognize there was an interrupt request, and no interrupt will occur after the interrupt mask bit is cleared. EL IM IN All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables the hardware interrupts. There are four types of hardware interrupts which are explained in the following sections. A R 4.4 Hardware Interrupts Y The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), the SWI instruction executes after interrupts which were pending before the SWI was fetched, or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of $3FFC and $3FFD. Page 23 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The second configuration shows several interrupt line “wire-ANDed” to perform the interrupts at the processor. Thus, if after servicing one interrupt and the interrupt line remains low, then the next interrupt is recognized. NOTE: IRQN is located at bit 3 of the Multi-function Timer Register at $0008, and is cleared by reset. Edge-sensitive Trigger Condition IRQ t ILIH t ILIL Freescale Semiconductor, Inc... IRQ1 t ILIH IN VSYNC Interrupt DDC12AB Interrupt IRQn IRQ (MCU) 4.4.2 The VSYNC interrupt is generated when a specific edge of VSYNC input is detected as described in SECTION 10. The interrupt enable bit, VSIE, for the VSYNC interrupt is located at bit 7 of SYNC Processor Control and Status Register (SPCSR) at $000C. The Ibit in the CCR must be cleared in order for the VSYNC interrupt to be enabled. This interrupt will vector to the interrupt service routine located at the address specified by the contents of $3FF8 and $3FF9. The VSYNC Interrupt Flag (VSIF) must be cleared by writing ’0’ to it in the interrupt routine. 4.4.3 The DDC12AB interrupt is generated by the DDC12AB circuit as described in SECTION 9. The interrupt enable bit for the DDC12AB interrupt is located at bit 6 of DDC12AB Control Register (DCR) at $0018. The I-bit in the CCR must be cleared in order for the DDC12AB interrupt to be enabled. This interrupt will vector to the interrupt service routine located at the address specified by the contents of $3FF6 and $3FF7. PR EL Figure 4-2: External Interrupt IM SECTION 4: INTERRUPTS For More Information On This Product, Go to: www.freescale.com Page 24 A R Level-sensitive Trigger Condition If after servicing an interrupt, the IRQ remains low, then the next interrupt is recognized. Normally used with pull-up resistor for Wire-Ored connection Y The minimum pulse width tILIH is one internal bus period. The period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 cycles Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 4.4.4 Multi-Function Timer Interrupt (MFT) There are two different Multi-Function Timer (MFT) interrupt flags that will cause an interrupt whenever they are set and enabled. The interrupt flags and enable bits are located in the MFT Control and Status Register. Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of $3FF4 and $3FF5. See Section SECTION 11, MULTI-FUNCTION TIMER for more informations on MFT interrupts. Freescale Semiconductor, Inc... SECTION 4: INTERRUPTS For More Information On This Product, Go to: www.freescale.com PR EL IM IN A Page 25 R Y Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 Freescale Semiconductor, Inc... THIS PAGE INTENTIONALLY LEFT BLANK PR EL SECTION 4: INTERRUPTS Page 26 For More Information On This Product, Go to: www.freescale.com IM IN A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION SECTION 5 The MCU can be reset from four sources—1 external and 3 internal: • • • • External RESET pin Power-On-Reset (POR) Computer Operating Properly Watchdog Reset (COPR) Illegal Address Reset (ILADR) RESETS 5.1 External Reset (RESET) Freescale Semiconductor, Inc... 5.2 Internal Resets The three internally generated resets are the initial power-on reset, the COP Watchdog Timer reset, and the illegal address reset 5.2.1 The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power-on condition and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4065 internal processor bus clock cycles (PH2) after the oscillator becomes active. The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of this 4065 cycles delay, the RST signal will remain in the reset condition until the other reset condition(s) end. 5.2.2 Computer Operating Properly Reset (COPR) The internal COPR reset is generated automatically (if enabled) by a time-out of the COP Watchdog Timer. This time-out occurs if the counter in the COP Watchdog Timer is not reset (cleared) within a specific time by a program reset sequence. Refer to SECTION 11 for more information on this time-out feature. SECTION 5: RESETS For More Information On This Product, Go to: www.freescale.com PR Power-On Reset (POR) EL IM NOTE: Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified. IN The RESET pin is the only external reset source. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the RST signal and reset the CPU and peripherals. Termination of the external RESET input can alter the operating mode of the MCU. A R Y Page 27 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 5.2.3 Illegal Address (ILADR) Reset The MCU monitors all opcode fetches. If an illegal address is accessed during an opcode fetch, an internal reset is generated. Illegal address space consists of all unused locations within the memory space and the I/O registers. (See Figure 2-1 : The 16K Memory Map of the MC68HC05BD7.) Because the internal reset signal is used, the MCU comes out of an ILADR Reset in the same operating mode it was in when the opcode was fetched. The ILADR Reset is disabled in Test (Non User) Mode. Freescale Semiconductor, Inc... PR EL SECTION 5: RESETS Page 28 For More Information On This Product, Go to: www.freescale.com IM IN A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION SECTION 6 OPERATING MODES The HC05BD7/HC05BD2 has the following operating modes: single-chip mode (SCM) and self-check mode. The HC705BD7 has the following operating modes: User mode and bootstrap mode. 6.1 User Mode In this mode, all address and data bus activity occurs within the MCU so no external pins are required for these functions. Freescale Semiconductor, Inc... 6.2 SELF-CHECK MODE 6.4 Mode Entry The mode entry is done at the rising edge of the RESET pin. Once the device enters one of the operating modes, the mode can only be changed by an external reset. SECTION 6: OPERATING MODES For More Information On This Product, Go to: www.freescale.com PR At the rising edge of the RESET pin, the device latches the states of IRQ and PB5 pins and places itself in the specified mode. While the RESET pin is low, all pins are configured as Single Chip Mode. The following table shows the states of IRQ and PB5 pins for each mode entry. EL IM In this mode, the reset vector is fetched from the 480-byte internal bootstrap ROM at $0E00:$0FDF. The bootstrap ROM contains a small program which reads a program into internal RAM and then passes control to execute EPROM programming. IN 6.3 Bootstrap Mode A In this mode, the reset vector is fetched from the 240-byte internal self-check ROM at $3F00:$3FEF. The self-check ROM contains a self-check program to test the functions of internal modules. R Y Page 29 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 Table 6-1: Mode Select Summary MODE USER MODE SELF CHECK/BOOTSTRAP VTST = 1.8 x VDD RESET IRQ L or H VTST PB5 X H RESET Single Chip Mode H L VTST Freescale Semiconductor, Inc... Y R H = VDD L = VSS IRQ H L H L PB5 VTST = 1.8 x VDD 6.5 EPROM Programming The 11.5K bytes of USER EPROM is positioned at $1000 through $3DFF with the vector space from $3FF0 to $3FFF. The erased state of EPROM is read as $FF and EPROM power is supplied from VPP and VDD pins. The Programming Control Register (PCR) is provided for the EPROM programming. The function of EPROM depends on the device operating mode. Please contact Motorola for Programming boards availability. 6.5.1 Programming Sequence - Set the ELAT bit - Write the data to the address to be programmed - Set the PGM bit - Delay for the appropriate amount of time - Clear the PGM and the ELAT bit The EPROM programming is as follows: The last item may be done on a single CPU write. It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but it should remain between VDD and VSS during normal operation. PR In the User Mode, ELAT and PGM bits in the PCR are available for the user read/write and the remaining test bits become read only bits. EL IM Page 30 For More Information On This Product, Go to: www.freescale.com IN Figure 6-1: Mode Entry Diagram A SECTION 6: OPERATING MODES Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 6.5.2 Programming Control Register (PCR) Program control register is provided for EPROM programming the device. 7 R 6 5 4 3 2 1 0 PCR $001D ELAT W 0 0 0 0 0 0 0 PGM reset ⇒ 0 Freescale Semiconductor, Inc... 6.6.1 Since the execution of a normal STOP instruction results in the stoppage of clocks to all modules, including the COP Watchdog Timer, this instruction is hence not implemented in its usual way to make COP Watchdog Timer meaningful in monitor applications. Execution of the STOP instruction will be the same as that of the NOP instruction. Hence, I bit in the Condition Code Register will not be cleared. 6.6.2 WAIT Instruction In the WAIT Mode the internal processor clock is halted, suspending all processor and internal bus activity. Other Internal clocks remain active, permitting interrupts to be generated from the Multi-Function Timer, or a reset to be generated from the COP Watchdog Timer. The Timer may be used to generate a periodic exit from the WAIT Mode. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code Register, so that any hardware interrupt can wake up the MCU. All other registers, memory, and input/output lines remain in their previous states. SECTION 6: OPERATING MODES For More Information On This Product, Go to: www.freescale.com PR STOP Instruction EL The MC68HC05BD7 has ONLY ONE low-power operational mode. The WAIT instruction provides the only mode that reduces the power required for the MCU by stopping CPU internal clock. The WAIT instruction is not normally used if the COP Watchdog Timer is enabled. The STOP instruction is not implemented in its normal sense. The STOP instruction will be interpreted as the NOP instruction by the CPU if it is ever encountered. The flow of the WAIT mode is shown in Figure 6-2. IM 6.6 Low Power Modes IN PGM—EPROM Program Command 0 - Programming power to EPROM array is switched off. 1 - Programming power to EPROM array is switched on. A R ELAT—EPROM Latch Control 0 - EPROM address and data bus configured for normal read. 1 - EPROM address and data bus configured for programming (writes to EPROM cause address and data to be latched). EPROM is in programming mode and can not be read. This bit is not writable to 1 when no VPP voltage is applied to the VPP pin. Y Page 31 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 6.7 COP Watchdog Timer Considerations The COP Watchdog Timer is always enable in MC68HC05BD7. It will reset the MCU when it times out. For a system that must have intentional uses of the WAIT Mode, care must be taken to prevent such situations from happening during normal operations by arranging timely interrupts to reset the COP Watchdog timer. WAIT External Oscillator Active, and Internal Timer Clock Active Freescale Semiconductor, Inc... Stop Internal Processor Clock, Clear I-Bit in CCR Y External RESET? N IM EL PR Page 32 Y Y Restart Internal Processor Clock 1.Fetch Reset Vector or 2.Service Interrupt a.Stack b.Set I-Bit c.Vector to Interrupt Routine Figure 6-2: WAIT Flowcharts For More Information On This Product, Go to: www.freescale.com IN Y Internal COP RESET? N External H/W Interrupt? N Internal Interrupt? N A SECTION 6: OPERATING MODES R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION SECTION 7 INPUT/OUTPUT PORTS In the User Mode there are 26 bidirectional I/O lines arranged as 4 I/O ports (Port A, B, C, and D). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs). Also, if enabled by software, Port C and D will have additional functions as PWM outputs, DDC I/O and Sync Signal Processor outputs. 7.1 Port A Freescale Semiconductor, Inc... 7.2 Port B Port C is an 8-bit bidirectional port which shares pins with PWM, Sync Processor, and ADC subsystem. See SECTION 8 for a detailed description of PWM, SECTION 10 for a detailed description of SYNC Processor, and SECTION 12 for a detailed description of ADC. These pins are configured as PWM outputs when the corresponding bits in the CONFIGURATION REGISTER 1 are set. PC6 and PC7 are configured to VSYNO and HSYNO outputs when the corresponding bits in the CONFIGURATION REGISTER 2 are set. And PC2 to PC5 are configured as ADC input channels as the corresponding bit in the CONFIGURATION REGISTER 2 are set. If there is any confliction between the two configuration registers, the CONFIGURATION REGISTER 2 has higher priority. The Port C data register is at $02 and the data direction register (DDR) is at $06. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port to output mode. 7.4 Port D is a 4-bit bidirectional port. PD0 and PD1 shares their pins with DDC12AB subsystem. See SECTION 9 for a detailed description of DDC12AB. These two pins are configured to the corresponding functions when the corresponding bits in the CONFIGURATION REGISTER 2 are set. They have open-drain output and hysteresis input level to improve noise immunity. PD2 is a +5V open-drain general I/O pin which SECTION 7: INPUT/OUTPUT PORTS For More Information On This Product, Go to: www.freescale.com PR Port D EL 7.3 Port C IM Port B is a 6-bit bidirectional port which does not share any of its pins with other subsystems. PB2 to PB5 are +12V open-drain port pins. The Port B data register is at $01 and the data direction register (DDR) is at $05. Reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. IN A R Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The Port A data register is at $00 and the data direction register (DDR) is at $04. Reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Y Page 33 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 shares its pin with the CLAMP output. See SECTION 10 for the description of CLAMP signal. It becomes the CLAMP output when the CLAMP bit in SPIOCR register is set. PD3 is a +12V open-drain I/O pin which shares its pin with the SOG input. Also see SECTION 10 for the description of SOG input. It is configured as SOG input when the SOG bit in SPIOCR register is set. The Port D data register is at $03 and the data direction register (DDR) is at $07. Reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. 7.5 Input/Output Programming Freescale Semiconductor, Inc... Read/Write DDR Data Direction Register Bit Write Data EL Data Register Bit IM IN OUTPUT I/O PIN Internal HC05 Data Bus PR Read Data Reset (RST) Figure 7-1: Port I/O Circuitry SECTION 7: INPUT/OUTPUT PORTS Page 34 For More Information On This Product, Go to: www.freescale.com A During Reset, all DDRs are cleared, which configure all port pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. See Figure 7-1 and . R Y Bidirectional port lines may be programmed as an input or an output under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set. A pin is configured as an input if its corresponding DDR bit is cleared. Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION Table 7-1: I/O Pin Functions R/W 0 0 1 1 DDR 0 1 0 1 I/O Pin Functions The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in output mode. The output data latch is read. NOTE: Freescale Semiconductor, Inc... A “glitch” can be generated on an I/O pin when changing it from an input to an output unless the data register is first pre-conditioned to the desired state before changing the corresponding DDR bit from a zero to a one. 7 R 6 IM 5 IN 4 Port C and Port D are shared with PWM, ADC, DDC12AB, and SYNC Processor. The configuration registers at $0A and $0B are used to configure those I/O pins. They are default to zero after poWer-on reset. Setting these bits will set the corresponding pins to the corresponding functions. For example, setting SCL and SDA bits of register $0B will configure Port D pins 1 and 0 as DDC12AB pins, regardless of DDR1 and DDR0 settings. A 3 0 3 0 R PWM11 ADC1 7.6 Port C and D Configuration Register Y 2 1 0 PWM10 PWM9 PWM8 0 2 0 1 0 0 ADC0 SCL SDA 0 0 0 PWM15 W 0 7 EL PWM14 0 6 VSYNO 0 CR1 $000A PWM13 PWM12 reset ⇒ 0 5 0 4 CR2 $000B PR R HSYNO W 0 ADC3 ADC2 reset ⇒ 0 0 When any PWM8-PWM15 bits of CR1 register are set, the corresponding pins of port C become the PWM output if the corresponding bits in CR2 register are clear. When the pin is defined as PWM channel, it become an output only pin. When any ADC3-ADC0 bits of the CR2 register are set, the corresponding pins of port C become the ADC input channels. When HSYNO or VSYNO is set, the PC2 or PC3 becomes the output of HSYNC or VSYNC accordingly, see SECTION 10 for the detail description of HSYNO and VSYNO outputs. When SCL and SDA bits of the CR2 register are set, the DDC12AB use these two pins as clock and data pins. In summary, the configuration in the CR2 register has higher priority than in the CR1 register. SECTION 7: INPUT/OUTPUT PORTS For More Information On This Product, Go to: www.freescale.com Page 35 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 Freescale Semiconductor, Inc... THIS PAGE INTENTIONALLY LEFT BLANK PR EL SECTION 7: INPUT/OUTPUT PORTS Page 36 For More Information On This Product, Go to: www.freescale.com IM IN A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION SECTION 8 PULSE WIDTH MODULATION There are 16 PWM channels. Channel 0 to channel 7 are dedicated PWM channels with 5V open-drain option. Channel 8 to channel 15 are shared with ports C under the control of the corresponding configuration register. The channel 8 and channel 9 are 12V opendrain outputs. 8.1 Operation of 8-Bit PWM Freescale Semiconductor, Inc... 7 R EL 6 IM 5 Combining the 5-bit PWM together with the 3-bit BRM, the average duty cycle at the output will be (M+N/8)/32, where M is the content of the 5-bit PWM portion, and N is the content of the 3-bit BRM portion. Using this mechanism, a true 8-bit resolution PWM type DAC with reasonably high repetition rate can be obtained. IN 4 The 3-bit BRM will generate a number of narrow pulses which are equally distributed among an 8-PWM-cycle frame. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. An example of the waveform is shown in Figure 8-2. A 3 0 R 0PWM0 Each 8-Bit PWM channel is composed of an 8-bit register which contains a 5-bit PWM in MSB portion and a 3-bit binary rate multiplier (BRM) in LSB portion. There are 16 data registers as shown in Figure 8-1 located from $20 to $2F. The value programmed in the 5bit PWM portion will determine the pulse length of the output. The clock to the 5-bit PWM portion is the MCU clock and the repetition rate of the output is hence 62.5 KHz at 2 MHz MCU clock. Y 2 0BRM2 0 1 0 PWMR $20-$2F PR 0PWM4 0PWM3 0PWM2 0PWM1 0BRM1 0BRM0 W reset ⇒ 0 0 0 0 0 0 Figure 8-1: PWM Data Register The value of each PWM Data Register is continuously compared with the content of an internal counter to determine the state of each PWM channel output pin. Double buffering is not used in this PWM design. SECTION 8: PULSE WIDTH MODULATION For More Information On This Product, Go to: www.freescale.com Page 37 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 M = $00 M = $01 M = $0F M = $1F 32 T Narrow pulse possibly inserted by the BRM Freescale Semiconductor, Inc... T = 1 MCU Clock Period (0.5 µs if MCU clock = 2 MHz) N XX1 X1X 1XX 4 2, 6 Figure 8-2: Relationship Between 5-Bit PWM and 3-Bit BRM 8.2 Open-Drain Option Register PR This PWM Open-Drain option Register contains 8 bits which are programmed to change the output drive of individual PWM channel from channel 0 to channel 7 to be open-drain type. This register is located at $0012 7 6 5 4 3 2 1 0 R PWMOR $12 7PWMO W 0 6PWMO EL 5PWMO IM 1, 3, 5, 7 4PWMO IN 3PWMO 2PWMO 1PWMO 0PWMO 0 0 0 0 0 reset ⇒ 0 0 Figure 8-3: PWM Open-Drain Option Register When any bit in this register is one, the corresponding PWM channel output becomes +5V open-drain type. When the bit is zero, the corresponding PWM channel has push-pull output. All eight bits are clear upon reset. SECTION 8: PULSE WIDTH MODULATION Page 38 For More Information On This Product, Go to: www.freescale.com A PWM cycles in which narrow pulses are inserted in an 8-cycle frame R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION SECTION 9 9.1 Introduction DDC12AB INTERFACE Freescale Semiconductor, Inc... 9.2 • • • • • • • • • • • DDC12AB Features SECTION 9: DDC12AB INTERFACE For More Information On This Product, Go to: www.freescale.com PR DDC1 hardware Fully compatible with multi-master IIC Bus standard Software controllable acknowledge bit generation Interrupt driven byte by byte data transfer Calling address identification interrupt Auto detection of RW bit and switching of transmit or receive mode accordingly Detection of START, repeated START, and STOP signals Auto generation of START and STOP condition in master mode Arbitration loss detection and No-ACK awareness in master mode Master clock generator with 8 selectable baud rates Automatic recognition of the received acknowledge bit EL This DDC12AB module uses the SCL clock line and the SDA data line to communicate with external DDC host or IIC interface. These two pins are shared with PD0 and PD1 port pins. The outputs of SDA and SCL pins are all open-drain type. It means no clamping diode connected between the pin and internal VDD. The maximum data rate typically is 100K bps. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. IM IN This module not only can be applied in DDC12AB communication, but also can be used as one typical command reception serial bus for factory setup and alignment purpose. It also provides the flexibility of hooking additional devices to an existing system in future expansion without adding extra hardware. A R This DDC12AB Interface Module is mainly used for monitor to show its identification information to video controller. It contains DDC1 hardware and a two-wire, bidirectional serial bus which is fully compatible with multi-master IIC bus protocol to support DDC2AB interface. In DDC1 type of communication, the module is in transmit mode. For DDC2AB protocol, the module can be either in transmit mode or in receive mode upon host’s commands. When DDC1 hardware is enabled, the loaded data is serially clocked out to SDA line by the rising edge of VSYNC input signal continuously. If DDC2 protocol is selected, the module will act as a standard IIC module, and will response only when it is addressed or in master mode. During DDC1 communication, the falling transition in the SCL line can be detected to interrupt cpu for mode switching. Y Page 39 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 9.3 Registers There are six different registers used in the DDC12AB module and the internal configuration of these registers is discussed in the following paragraphs. 9.3.1 DDC Address Register (DADR) 7 R 6 5 4 3 2 1 0 DADR $0017 DAD7 W reset 1 DAD6 DAD5 DAD4 DAD3 DAD2 DAD1 EXTAD 0 1 0 0 0 0 0 DAD7-DAD1 Bit 7-Bit 1 Freescale Semiconductor, Inc... 9.3.2 DDC Control Register (DCR) R DCR $0018 PR 7 EL 6 5 IM 4 IN 3 X 0 A TXAK EXTAD Bit 0 These 7 bits can be the DDC2 interface’s own specific slave address in slave mode or the calling address when in master mode. So the program must update it as the calling address while entering the master mode and restore its own slave address after the master mode is quitted. This register is cleared as $A0 upon reset. The EXTAD bit is set to expand the calling address of this module. When it is one, the module will acknowledge the general call address $00 and the address comparison circuit will only compare the 4 MSB bits in the DADR register. For example, the DADR contains $A1, that means EXTAD is enabled and the calling address is $A0, therefore, the module can acknowledge the calling address of $00 and $A0 to $AF. When it is clear, the module will only acknowledge to the specific address which is stored in the DADR register. It is clear upon reset. R 2 SCLIEN 0 Y 1 0 DEN DIEN DDC1EN W reset ⇒ 0 0 X 0 X The DCR provides five control bits. DCR is cleared upon reset. DEN Bit 7 If the DDC module ENable bit (DEN) is set, the DDC module is enabled. If the DEN is clear, the interface is disabled and all flags will restore its power-on default states. Reset clears this bit. DIEN Bit 6 If the DDC Interrupt ENable bit (DIEN) is set, the interrupt occurs provided the TXIF or RXIF in the status register is set or the ALIF or NAKIF in the DMCR register is set and the I-bit in the Condition Code Register is cleared. If DIEN is cleared, the interrupt of TXIF, RXIF, ALIF, and NAKIF are all disabled. Reset clears this bit. SECTION 9: DDC12AB INTERFACE Page 40 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION TXAK Bit 3 If the transmit acknowledge enable bit (TXAK) is cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving 8 data bits. When TXAK is set, no acknowledge signal will be generated at the 9th clock (i.e., acknowledge bit = 1). Reset clears this bit. If the SCL Interrupt ENable bit (SCLIEN) is set, the interrupt occurs provided the SCLIF in the status register is set and the I-bit in the Condition Code Register is cleared. If SCLIEN is cleared, the interrupt of SCLIF is disabled. Reset clears this bit. When DDC1 protocol ENable (DDC1EN) is set, the VSYNC input will be selected as clock input of DDC module. Its rising edge will continuously clock out the data in the shift register. No calling address comparison is performed. The RW bit in the status register will be fixed to be one. If this bit is clear, the SCLIF bit in the status register is also cleared. Reset clears this bit. SCLIEN Bit 2 DDC1EN Bit 1 Freescale Semiconductor, Inc... 7 R 6 5 4 A 3 MRW 0 9.3.3 DDC Master Control Register (DMCR) R Y 2 BR2 0 1 0 DMCR $0016 ALIF W 0 NAKIF BB IN MAST BR1 BR0 reset ⇒ 0 IM 0 0 0 0 The DMCR contains two interrupt flags, one bus status flag, two master mode control bits, and three baudrate select bits. ALIF Bit 7 The Arbitration Loss Interrupt Flag is set when software attempt to set MAST but the BB has been set by detecting the start condition on the lines or when the DDC12AB module is transmitting a ’one’ to SDA line but detected a ’zero’ from SDA line in master mode, which is so called arbitration loss. This bit can generate an interrupt request to cpu when the DIEN bit in DCR register is set and I-bit in the Condition Code Register is clear. This bit is cleared by writing ’0’ to it or by reset. NAKIF Bit 6 The No AcKnowledge Interrupt Flag is only set in master mode when there is no acknowledge bit detected after one data byte or calling address is transferred. This bit can generate an interrupt request to cpu when the DIEN bit in DCR register is set and I-bit in the Condition Code Register is clear. This bit is cleared by writing ’0’ to it or by reset. BB Bit 5 The Bus Busy Flag is set after a start condition is detected, and is reset when a stop condition is detected. This bit can supplement the software in initiating the master mode protocol. Reset clears this bit. SECTION 9: DDC12AB INTERFACE For More Information On This Product, Go to: www.freescale.com PR EL Page 41 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 MAST Bit 4 If the software set the MASTer control bit, the module will generate a start condition to the SDA and SCL lines and send out the calling address which is stored in the DADR register. But if the ALIF flag is set when arbitration loss occurs on the lines, the module will discard the master mode by clearing the MAST bit and release both SDA and SCL lines immediately. This bit can also be cleared by writing zero to it or when the NAKIF is set. When the MAST bit is cleared either by NAKIF set or by software, not by ALIF set, the module will generate the stop condition to the lines after the current byte transmission is done. Reset clears this bit. This MRW bit will be transmitted out as the bit 0 of the calling address when the module sets the MAST bit to enter the master mode. It will also determine the transfer direction of the following data bytes. When it is one, the module is in master receive mode. When it is zero, the module is in master transmit mode. Reset clears this bit. The three Baud Rate select bits will select one of eight clock rates as the master clock when the module is in master mode. The serial clock frequency is equal to the CPU clock divided by the divider shown in following table. For the CPU clock will be halted while program executes the WAIT instruction, program must not enter WAIT mode when the DDC12AB module is in Master mode in order not to hang up the communication on the lines. These bits are cleared upon reset. MRW Bit 3 Freescale Semiconductor, Inc... BR2-BR0 Bit 2-Bit 0 EL PR Page 42 IM 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 BR2:BR1:BR0 IN Table 9-1: Pre-scaler of Master Clock Baudrate SECTION 9: DDC12AB INTERFACE For More Information On This Product, Go to: www.freescale.com A 20 40 80 R DIVIDER 160 320 640 1280 2560 Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION 9.3.4 DDC Status Register (DSR) This status register is readable only. All bits are cleared upon reset except bit 3 (RXAK) and bit 1 (TXBE). 7 R RXIF 6 TXIF 5 MATCH 4 SRW 3 RXAK 2 SCLIF 1 TXBE 0 RXBF DSR $0019 W 0 0 0 0 1 0 1 0 reset ⇒ RXIF Bit 7 TXIF Bit 6 MATCH Bit 5 SRW Bit 4 RXAK Bit 3 SCLIF Bit 2 The data Receive Interrupt Flag (RXIF) is set after the DDRR is loaded with a newly received data. Once the DDRR is loaded with received data, no more received data can be loaded to the DDRR register. The only way to release the DDRR register for loading next received data is that software reads the data from the DDRR register to clear RXBF flag. This bit is cleared by writing ’0’ to it or when the DEN is disabled. The data Transmit Interrupt Flag is set before the data of the DDTR register is downloaded to the shift register. It is software’s responsibility to fill the DDTR register with new data when this bit is set. This bit is cleared by writing ’0’ to it or when the DEN is disabled. The MATCH flag is set when the received data in the DDRR register is an calling address which matches with the address or its extended addresses (EXTAD=1) specified in the DADR register. The Slave RW bit will indicate the data direction of DDC protocol. It is updated after the calling address is received in the DDC2 protocol. When it is one, the master will read the data from DDC module, so the module is in transmit mode. When it is zero, the master will send data to the DDC module, the module is in receive mode. When DDC1EN is set, the SRW bit will be one. The reset state of it is zero. If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8 data bits transmission on the bus. If RXAK is high, it indicates no acknowledge signal has been detected at the 9th clock. Then the module will release the SDA line for the master to generate ’stop’ or ’repeated start’ condition. It is set upon reset. This SCLIF flag is set by the falling edge of SCL line only when DDC1EN is enabled. This bit is cleared by writing zero to it, clearing DDC1EN bit or when the DEN is disable. Freescale Semiconductor, Inc... SECTION 9: DDC12AB INTERFACE For More Information On This Product, Go to: www.freescale.com PR EL IM IN A R Y Page 43 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 TXBE Bit 1 The Transmit Buffer Empty (TXBE) flag indicates the status of the DDTR register. When the cpu writes the data into the DDTR register, the TXBE flag will be cleared. And it will be set again after the data of the DDTR register has been loaded to the shift register. It is default to be set when the DEN is disable and will be cleared by writing data to the DDTR register when the DEN is enabled. The Receive Buffer Full (RXBF) flag indicates the status of the DDRR register. When the cpu reads the data from the DDRR register, the RXBF flag will be cleared. And it will be set after the data or matched address is transferred from the shift register to the DDRR register. It is cleared when DEN is disabled or DDRR register is read when DEN is enabled. RXBF Bit 0 Freescale Semiconductor, Inc... 7 R 6 5 4 3 Y 2 9.3.5 DDC Data Transmit Register (DDTR) 1 0 W 1 1 1 1 The data written into this register after DEN is enabled will be automatically downloaded to the shift register when the module detects the calling address is matched and the bit 0 of the received data is one or when the data in the shift register has been transmitted with received acknowledge bit, RXAK=0. So if the program doesn’t write the data into the DDTR register (TXBE is cleared) before the matched calling address is detected, the module will pull down the SCL line. If the cpu write a data to the DDTR register, then the written data will be downloaded to the shift register immediately and the module will release the SCL line, then the TXBE is set again and the TXIF flag is set to generate another interrupt request for data. So the cpu may need to write the next data to the DDTR register to clear TXBE flag and for the auto downloading of data to the shift register after the data in the shift register is transmitted over again with RXAK=0. If the master receiver doesn’t acknowledge the transmitted data, RXAK=1, the module will release the SDA line for master to generate ’stop’ or ’repeated start’ conditions. The data stored in the DDTR register will not be downloaded to the shift register until next calling from master (TXBE remains unchanged). 9.3.6 DDC Data Receive Register (DDRR) 7 R DRD7 6 DRD6 5 DRD5 4 DRD4 3 DRD3 2 DRD2 1 DRD1 0 DRD0 DDRR $001B W 0 0 0 0 0 0 0 0 reset ⇒ The DDC Data Receive Register (DDRR) contains the last received data when the MATCH flag is zero or the calling address from master when the MATCH flag is one. The DDRR register will be updated after a data byte is received and the RXBF is zero. It is a read-only register. The read operation of this register will clear the RXBF flag. After the RXBF flag is SECTION 9: DDC12AB INTERFACE Page 44 For More Information On This Product, Go to: www.freescale.com PR EL IM IN reset ⇒ A 1 DDTR $001A DTD7 DTD6 DTD5 DTD4 DTD3 R DTD2 1 DTD1 DTD0 1 1 Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION cleared, the register can load the received data again and set the RXIF flag to generate interrupt request for reading the newly received data. 9.4 Data Sequence a) Master Transmit mode START Address 0 ACK TX Data1 ACK TX DataN NAK STOP TXBE=0 MAST=1 MRW=0 TXIF=1 TXBE=1 TXIF=1 TXBE=1 NAKIF=1 MAST=0 TXBE=0 Freescale Semiconductor, Inc... RXBF=0 MAST=1 A RXIF=1 RXBF=1 ACK R START Address 1 ACK RX Data1 Y b) Master Receive mode ACK RX DataN NAK STOP c) Slave Transmit mode START Address 1 TX Data1 IN ACK TXIF=1 TXBE=1 ACK RXIF=1 RXBF=1 RXIF=1 RXBF=1 NAKIF=1 MAST=0 TX DataN NAK STOP TXBE=0 RXBF=0 d) Slave Receive mode TXBE=0 RXBF=0 PR START Address 0 EL IM RXIF=1 RXBF=1 TXiF=1 TXBE=1 MATCH=1 SRW=1 ACK RX Data1 RX DataN NAK STOP RXIF=1 RXBF=1 MATCH=1 SRW=0 RXIF=1 RXBF=1 9.5 Program Algorithm The Figure 9-1 shows the algorithm of slave mode interrupt routine of DDC12B protocol. The Figure 9-2 shows the algorithm of master mode setup and interrupt service routine. When the DDC module detects an arbitration loss in master mode, it will release both SDA and SCL lines immediately. But if there is no further "stop condition" detected, the module will be hanged up. So it is recommended to have time-out software to recover from such ill condition. The software can start the time-out counter by looking at the BB (Bus Busy) in the bit 5 of DMCR and reset the counter when the completion of one byte transmission. If the time-out occurred, program can clear DEN bit to release the bus, and then set DEN bit SECTION 9: DDC12AB INTERFACE For More Information On This Product, Go to: www.freescale.com Page 45 Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 and DDC1EN bit to clear BB flag (This is the only way to clear BB flag by software while the module is hanged up due to no "stop condition" received). The program can resume IIC master mode after clearing the BB flag and DDC1EN bit. Freescale Semiconductor, Inc... PR EL SECTION 9: DDC12AB INTERFACE Page 46 For More Information On This Product, Go to: www.freescale.com IM IN A R Y Freescale Semiconductor, Inc. MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION Interrupt Y SCLIF =1? N TXIF =1? Y Clear TXIF Write Data to DDTR Freescale Semiconductor, Inc... A Y N RTI Clear RXIF Read Data from DDRR Clr DDC1EN Clr SCLIEN Clr SCLIF Y RXIF =1? IM N MATCH =1? EL PR Write TXAK for Next Byte Receive IN Address received SRW =1? Y TXBE =1? N Y Write Data to DDTR Figure 9-1: Software Flowchart of Slave Mode Interrupt Routine SECTION 9: DDC12AB INTERFACE For More Information On This Product, Go to: www.freescale.com R N Page 47 Y N Freescale Inc. GENERAL RELEASE SPECIFICATION Semiconductor, MC68HC05BD7 Rev. 2.0 RESET Interrupt Y ALIF =1? BB =1? N Y Clr NAKIF N NAKIF =1? N Y Clear ALIF Set "Failure" flag for retry *restore DADR Freescale Semiconductor, Inc... MRW =1? N A Y Y RTI Y Read MRW