68HC05P9A_1

Freescale Semiconductor, Inc. HC05P9AGRS/D REV 2.0 68HC05P9A SPECIFICATION Freescale Semiconductor, Inc... (General Release) AR CH IVE DB YF For More Information On This Product, Go to: www.freescale.com RE ES CA LE CSIC MCU Design Group Oak Hill, Texas SE MIC © December 18, 1995 ON DU CT OR , IN C.2 006 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... AR CH IVE DB YF For More Information On This Product, Go to: www.freescale.com RE ES CA LE SE MIC ON DU CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS SECTION 1 GENERAL DESCRIPTION 1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.6 Freescale Semiconductor, Inc... Rev. 2.0 For More Information On This Product, Go to: www.freescale.com AR CH 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 3.5 Accumulator (A) .............................................................................................. 3-1 Index Register (X) ........................................................................................... 3-1 Condition Code Register (CCR) ...................................................................... 3-1 H — Half Carry ........................................................................................... 3-1 I — Interrupt ................................................................................................ 3-2 N — Negative ............................................................................................. 3-2 Z — Zero ..................................................................................................... 3-2 C — Carry/Borrow ...................................................................................... 3-2 Stack Pointer (SP) ........................................................................................... 3-2 Program Counter (PC) .................................................................................... 3-3 IVE DB YF RE SECTION 3 CENTRAL PROCESSING UNIT ES CA 2.1 2.2 2.3 ROM ................................................................................................................ 2-3 ROM Security Feature .................................................................................... 2-3 RAM ................................................................................................................ 2-3 LE SE SECTION 2 MEMORY MIC Features .......................................................................................................... 1-1 Mask Options .................................................................................................. 1-2 MCU Structure ................................................................................................ 1-3 Pin Assignments ............................................................................................. 1-4 Signal Description ........................................................................................... 1-4 VDD and VSS ............................................................................................... 1-4 IRQ ............................................................................................................. 1-4 OSC1 and OSC2 ........................................................................................ 1-5 RESET ........................................................................................................ 1-5 TCMP .......................................................................................................... 1-5 PA0 through PA7 ........................................................................................ 1-5 SDO/PB5, SDI/PB6, and SCK/PB7 ............................................................ 1-6 PC0 through PC7 ........................................................................................ 1-6 PD5 and TCAP/PD7 ................................................................................... 1-6 Input/Output Programming .............................................................................. 1-6 ON DU CT OR , IN C.2 006 Section Title Page iii Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS SECTION 4 INTERRUPTS 4.1 4.2 4.3 4.4 4.5 Hardware Controlled Interrupt Sequence ........................................................ 4-2 Timer Interrupt ................................................................................................. 4-3 External Interrupt ............................................................................................. 4-4 Optional External Interrupts (PA0-PA7) ........................................................... 4-6 Software Interrupt (SWI) ................................................................................. 4-6 SECTION 5 RESETS Freescale Semiconductor, Inc... SECTION 6 LOW POWER MODES 6.1 6.2 6.3 6.2 STOP Instruction.............................................................................................. 6-1 Stop Mode ....................................................................................................... 6-1 Halt Mode......................................................................................................... 6-2 WAIT Instruction............................................................................................... 6-2 SECTION 7 SIMPLE SERIAL INPUT/OUTPUT PORT 7.1 Signal Format .................................................................................................. 7-1 7.1.1 Serial Clock (SCK) ...................................................................................... 7-1 7.1.2 Serial Data Out (SDO) ................................................................................ 7-2 7.1.3 Serial Data In (SDI) ..................................................................................... 7-2 7.2 SIOP Registers ............................................................................................... 7-3 7.2.1 SIOP Control Register (SCR) ..................................................................... 7-3 7.2.2 SIOP Status Register (SSR) ....................................................................... 7-4 7.2.3 SIOP Data Register (SDR) ......................................................................... 7-5 IVE DB YF RE ES CA 8.1 8.2 8.3 8.4 8.5 Counter ........................................................................................................... 8-2 Output Compare Register ............................................................................... 8-3 Input Capture Register .................................................................................... 8-4 Timer Control Register (TCR) $12 .................................................................. 8-5 Timer Status Register (TSR) $13 .................................................................... 8-6 AR CH LE SE SECTION 8 TIMER MIC ON 5.1 5.2 5.3 Power-On Reset (POR) .................................................................................. 5-1 RESET Pin ...................................................................................................... 5-1 Computer Operating Properly (COP) Reset .................................................... 5-1 DU CT OR , IN C.2 006 Section Title Page iv For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS 8.6 8.7 Timer During Wait Mode ................................................................................. 8-7 Timer During Stop Mode ................................................................................. 8-7 SECTION 9 COMPUTER OPERATING PROPERLY (COP) 9.1 9.2 9.3 Resetting The COP ......................................................................................... 9-1 COP During Wait Mode ................................................................................... 9-1 COP During Stop Mode .................................................................................. 9-1 SECTION 10 ANALOG-TO-DIGITAL (A/D) CONVERTER Freescale Semiconductor, Inc... Rev. 2.0 For More Information On This Product, Go to: www.freescale.com AR 12.1 Addressing Modes ........................................................................................ 12-1 12.1.1 Inherent ..................................................................................................... 12-1 12.1.2 Immediate ................................................................................................. 12-2 12.1.3 Direct ........................................................................................................ 12-2 12.1.4 Extended ................................................................................................... 12-2 12.1.5 Indexed, No Offset .................................................................................... 12-2 12.1.6 Indexed, 8-Bit Offset ................................................................................. 12-2 12.1.7 Indexed, 16-Bit Offset ............................................................................... 12-3 12.1.8 Relative ..................................................................................................... 12-3 12.2 Instruction Types ........................................................................................... 12-4 12.2.1 Register/Memory Instructions ................................................................... 12-4 12.2.3 Read-Modify-Write Instructions ................................................................ 12-5 12.2.4 Jump/Branch Instructions ......................................................................... 12-5 12.2.5 Bit Manipulation Instructions ..................................................................... 12-7 12.2.6 Control Instructions ................................................................................... 12-7 12.3 Instruction Set Summary ............................................................................... 12-8 CH IVE DB YF RE ES CA SECTION 12 INSTRUCTION SET LE SECTION 11 SELF-CHECK MODE SE MIC 10.1 10.2 10.3 10.4 10.5 Conversion Process ....................................................................................... 10-1 A/D Status and Control Register (ADSCR) .................................................... 10-2 A/D Data Register (ADDR)............................................................................. 10-3 A/D Converter During Wait Mode................................................................... 10-4 A/D Converter During Stop or Halt Mode....................................................... 10-4 ON DU CT OR , IN C.2 006 Section Title Page v Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS SECTION 13 ELECTRICAL SPECIFICATIONS 13.1 13.2 13.3 13.4 13.4 13.5 Maximum Ratings ......................................................................................... 13-1 Thermal Characteristics ................................................................................ 13-1 DC Electrical Characteristics ......................................................................... 13-2 A/D Converter Characteristics........................................................................ 13-4 SIOP Timing................................................................................................... 13-5 Control Timing................................................................................................ 13-6 SECTION 14 MECHANICAL SPECIFICATIONS Freescale Semiconductor, Inc... SECTION 15 ORDERING INFORMATION 15.1 15.2 15.3 15.4 MCU Ordering Forms .................................................................................... 15-1 Application Program Media ........................................................................... 15-2 ROM Program Verification ............................................................................ 15-3 ROM Verification Units (RVUs) ..................................................................... 15-3 AR CH IVE DB YF RE ES CA LE SE MIC ON 14.1 14.2 28-Pin Plastic Dual In-Line Package (Case 710-02) ..................................... 14-1 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) ................ 14-2 DU CT OR , IN C.2 006 Section Title Page vi For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION LIST OF FIGURES 1-1 1-2 1-3 1-4 2-1 2-2 4-1 4-2 5-1 6-1 7-1 7-2 7-3 7-4 7-5 8-1 8-2 8-3 10-1 10-2 11-1 13-1 13-2 13-3 13-4 13-5 Block Diagram ........................................................................................... 1-3 Pin Assignments ........................................................................................ 1-4 Port A Pullup Option .................................................................................. 1-5 I/O Circuitry ................................................................................................ 1-7 Memory Map .............................................................................................. 2-1 I/O Registers for the MC68HC05P9A ........................................................ 2-2 Hardware Interrupt Flowchart .................................................................... 4-3 IRQ Function Block Diagram ...................................................................... 4-4 Power-On Reset and RESET .................................................................... 5-2 Freescale Semiconductor, Inc... Self-Check Circuit .................................................................................... 12-2 SIOP Timing Diagram .............................................................................. 13-5 STOP Recovery Timing ........................................................................... 13-7 External Interrupt Timing ......................................................................... 13-7 Power-On Reset Timing .......................................................................... 13-8 External Reset Timing ............................................................................. 13-8 Rev. 2.0 For More Information On This Product, Go to: www.freescale.com AR CH IVE DB YF RE ES A/D Status and Control Register (ADSCR)............................................... 10-2 A/D Data Register (ADDR) ....................................................................... 10-3 CA Timer Block Diagram ................................................................................. 8-2 Timer Control Register ............................................................................... 8-5 Timer Status Register ................................................................................ 8-6 LE SE SIOP Block Diagram .................................................................................. 7-1 Serial I/O Port Timing ................................................................................ 7-2 SIOP Control Register ............................................................................... 7-3 SIOP Status Register ................................................................................. 7-4 SIOP Data Register ................................................................................... 7-5 MIC ON STOP/WAIT Flowcharts ............................................................................. 6-3 DU CT OR , IN C.2 006 Figure Title Page vii Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA LE SE MIC ON DU CT OR , IN C.2 006 viii For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION LIST OF TABLES 1-1 4-1 I/O Pin Functions ............................................................................................. 1-7 Vector Address for Interrupts and Reset ......................................................... 4-2 10-1 A/D Input Selection ........................................................................................ 10-3 11-1 Self-Check Results ........................................................................................ 11-1 12-1 12-2 12-3 12-4 12-5 12-6 12-7 13-1 13-2 13-3 13-4 13-5 13-6 13-7 Register/Memory Instructions ....................................................................... 12-4 Read-Modify-Write Instructions ..................................................................... 12-5 Jump and Branch Instructions ....................................................................... 12-6 Bit Manipulation Instructions ......................................................................... 12-7 Control Instructions ....................................................................................... 12-7 Instruction Set Summary ............................................................................... 12-8 Opcode Map ................................................................................................ 12-14 DC Electrical Characteristics (VDD = 5 V) ..................................................... 13-2 DC Electrical Characteristics (VDD = 3.3 V) .................................................. 13-3 A/D Converter Characeristics......................................................................... 13-4 SIOP Timing (VDD = 5 V) .............................................................................. 13-5 SIOP Timing (VDD = 3.3 V) ........................................................................... 13-5 Control Timing (VDD = 5 V) ........................................................................... 13-6 Control Timing (VDD = 3.3 V) ........................................................................ 13-6 Freescale Semiconductor, Inc... Rev. 2.0 For More Information On This Product, Go to: www.freescale.com AR CH IVE DB YF RE ES CA LE SE MIC ON DU CT OR , IN C.2 006 Table Title Page ix Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA LE SE MIC ON DU CT OR , IN C.2 006 x For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 1 GENERAL DESCRIPTION Freescale Semiconductor, Inc... 1.1 Features • • • • • • • • • • • • • • Low Cost HC05 Core 28-Pin Package On-Chip Oscillator with RC or Crystal/Ceramic Resonator Mask Options 2112 Bytes of User ROM Including 16 User Vector Locations ROM Security Feature 20 Bidirectional I/O Lines, One Input-Only Line Mask Programmable Keyscan (Pullups and Interrupt) on Eight Port Pins (PA0 through PA7) Two Port Pins with High Current Drive Capability (PC0, PC1) User Mode AR Four-Channel 8-Bit A/D Converter Self-Check Mode CH IVE DB YF 16-Bit Timer Rev. 2.0 For More Information On This Product, Go to: www.freescale.com RE 128 Bytes of On-Chip RAM ES CA GENERAL DESCRIPTION 1-1 LE SE MIC ON DU The MC68HC05P9A is a 28-pin device based on the MC68HC05P9. The memory map includes 2112 bytes of user ROM and 128 bytes of RAM. The MCU has two 8-bit input/output (I/O) ports, A and C. Port B has three I/O pins and port D has two pins, one that is I/O and the other input only. The MC68HC05P9A includes a four-channel 8-bit analog-to-digital (A/D) converter, a simple serial I/O peripheral (SIOP), and an on-chip mask programmable computer operating properly (COP) watchdog circuit. CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION • • • • • 1.2 Power-Saving Stop and Wait Modes Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger Mask Option Simple Serial Input/Output Port Mask Option Selectable Watchdog Timer (COP) Mask Options Freescale Semiconductor, Inc... • • • • • • CLOCK (RC or Crystal) IRQ (Edge-Sensitive Only or Edge- and Level-Sensitive) SIOP (MSB or LSB First) Keyscan Pullups and Interrupts on Port A (Enable/Disable by Pin). Stop Instruction (Option to Convert to Halt) All mask options and the user ROM are programmed on the 04E layer in fabrication. RE ES CA LE SE COP Watchdog Timer (Enable/Disable) Negative true signals like RESET and IRQ will be denoted with an overline. AR CH IVE DB YF GENERAL DESCRIPTION 1-2 For More Information On This Product, Go to: www.freescale.com MIC ON NOTE DU There are 13 mask options on the MC68HC05P9A: CT OR , IN C.2 006 STOP Conversion to Halt Mode (Mask Option) MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.3 MCU Structure OSC1 OSC2 INTERNAL PROCESSOR OSCILLATOR AND DIVIDE CLOCK BY 2 TCMP TIMER SYSTEM PORT D I/O LINES TCAP/PD7 Freescale Semiconductor, Inc... PORT D REGISTER DATA DIR REGISTER CT OR , IN C.2 006 COP SYSTEM RESET IRQ Figure 1-1 shows the structure of the MC68HC05P9A. PD5 DATA DIRECTION REGISTER PC0 PC1 PORT C REGISTER PC2 PC3/AN3 PC4/AN2 PC5/AN1 PC6/AN0 PC7/VRH PORT C I/O LINES ACCUMULATOR DATA DIRECTION REGISTER PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PORT A REGISTER PORT A I/O LINES A/D CONVERTER INDEX REGISTER CONDITION CODE REGISTER STACK POINTER ON DU CPU CONTROL AN3 AN2 AN1 AN0 VRH MIC 128 X 8 RAM CPU DATA DIR REG PORT B I/O LINES SDO/PB5 SDI/PB6 SCK/PB7 PORT B REG SDI SCK YF DB AR CH IVE Rev. 2.0 For More Information On This Product, Go to: www.freescale.com RE ES SDO 2112 X 8 USER ROM 240 X 8 SELFCHECK Figure 1-1. Block Diagram CA SERIAL I/O PORT (SIOP) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW LE SE ALU GENERAL DESCRIPTION 1-3 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.4 Pin Assignments RESET IRQ PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 SDO/PB5 SDI/PB6 SCK/PB7 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Freescale Semiconductor, Inc... DU 22 21 ON MIC SE 1.5.2 IRQ AR This pin has a mask option that provides two different choices of interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to SECTION 3 CENTRAL PROCESSING UNIT for more detail. CH IVE DB 1.5.1 V and V DD SS Power is supplied to the microcontroller through VDD and VSS. VDD is the power supply and VSS is ground. YF RE The following paragraphs provide a description of the signals. ES 1.5 Signal Description CA Figure 1-2. Pin Assignments GENERAL DESCRIPTION 1-4 For More Information On This Product, Go to: www.freescale.com LE CT OR , IN C.2 006 28 VDD 27 26 25 24 23 OSC1 OSC2 TCAP/PD7 PD5 PC0 PC1 PC2 PC3/AN3 PC4/AN2 PC5/AN1 PC6/AN0 PC7/VRH TCMP 20 19 18 17 16 15 The MC68HC05P9A pin assignments are shown in Figure 1-2. MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.5.3 OSC1 and OSC2 1.5.4 RESET Freescale Semiconductor, Inc... This active low pin is used to reset the MCU to a known start-up state by pulling RESET low. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. 1.5.5 TCMP YF VDD RE ES Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000, and the data direction register is at $0004. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Port A has mask option enabled pullup devices and interrupt capability by pin. For a detailed description of I/O programming, refer to 1.6 Input/Output Programming. CA VDD LE Mask Option DDR Bit SE 1.5.6 PA0 through PA7 MIC This pin provides an output for the output compare feature of the on-chip timer system. ON DU IRQ Schmitt Trigger PA0 IVE DB Normal Port Circuitry To Interrupt Logic From all other Port A pins AR CH Figure 1-3. Port A Pullup Option GENERAL DESCRIPTION Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 1-5 CT OR , IN C.2 006 These pins provide control input for an on-chip clock oscillator circuit. A crystal, a ceramic resonator, a resistor/capacitor combination, or an external signal connects to these pins and provides a system clock. A mask option selects either a crystal/ceramic resonator or a resistor/capacitor as the frequency determining element. The oscillator frequency is two times the internal bus rate. Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.5.7 SDO/PB5, SDI/PB6, and SCK/PB7 1.5.8 PC0 through PC2, PC3/AN3, PC4/AN2, PC5/AN1, PC6/AN0, PC7/VRH Freescale Semiconductor, Inc... 1.5.9 PD5 and TCAP/PD7 AR Port D is a 2-bit port. PD5 is I/O and TCAP/PD7 is input-only shared with the timer input capture. The address of the port D data register is $0003 and the data direction register is at address $0007. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. The TCAP/PD7 pin controls the input capture feature for the on-chip programmable timer. This pin can be read at any time even if the TCAP function is enabled. CH IVE DB YF RE The address of the port C data register is $0002 and the data direction register is at address $0006. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Two of the port C pins, PC0 and PC1, have a higher current drive capability. See SECTION 13 ELECTRICAL SPECIFICATIONS. ES CA GENERAL DESCRIPTION 1-6 For More Information On This Product, Go to: www.freescale.com LE When the A/D converter is enabled, PC7 becomes VRH, and PC6–PC3 become AN0–AN3 (analog inputs 0–3). The values of CH1 and CH0 in the A/D status and control register (ADSCR) select one of the four pins as the input to the A/D converter. When the A/D converter is enabled a digital read of port C gives a logical zero from the selected analog input pin. A digital read of port C’s remaining pins gives their correct digital values. VRH is the positive (high) reference voltage for the A/D converter. VSS is the negative (low) reference voltage. A reset turns off the A/D converter and configures port C as a general-purpose I/O port. See SECTION 10 ANALOG-TO-DIGITAL (A/D) CONVERTER. SE MIC ON DU Port C, as an 8-bit shared function port, shares five of its pins with the A/D converter. When the A/D converter is not enabled, PC7–PC0 form an 8-bit general-purpose bidirectional I/O port. The contents of data direction register C (DDRC) determine whether each pin is an input or an output. CT OR , IN C.2 006 Port B is a 3-bit bidirectional port. These pins are shared with the SIOP subsystem. Refer to SECTION 7 SIMPLE SERIAL INPUT/OUTPUT PORT for a detailed description of the SIOP. The address of the port B data register is $0001 and the data direction register is at address $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.6 Input/Output Programming Freescale Semiconductor, Inc... At power-on or reset, all DDRs are cleared, which configures all pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. For further information, see Table 1-1 and Figure 1-4. Table 1-1. I/O Pin Functions R/W 0 0 1 1 DDR 0 1 0 1 ON The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The I/O pin is in an output mode. The output data latch is read. R/W is an internal signal. Data Direction Register Bit DB Internal HC05 Connections YF RE ES CA LE SE The state of the I/O pin is read. MIC DU CT OR , IN C.2 006 I/O Pin Function Output Input I/O Port pins may be programmed as inputs or outputs under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each I/O port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logic zero. Latched Output Data Bit I/O Pin AR CH IVE Input Reg Bit Figure 1-4. I/O Circuitry GENERAL DESCRIPTION Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 1-7 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA GENERAL DESCRIPTION 1-8 For More Information On This Product, Go to: www.freescale.com LE SE MIC ON DU CT OR , IN C.2 006 MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 2 MEMORY The MC68HC05P9A has an eight Kbyte memory map, consisting of user ROM, user RAM, self-check ROM, and I/O. See Figure 2-1 and Figure 2-2. Freescale Semiconductor, Inc... $0000 $0020 I/O 32 Bytes DU User ROM (Page Zero) 48 Bytes Unused (48 Bytes) $0050 $0080 ON MIC $0100 RAM 128 Bytes SE ↑ Stack 64 Bytes 0256 RE $900 ES CA LE User ROM 2048 Bytes YF Unused 5632 Bytes DB IVE $1F00 Self-Check ROM 240 Bytes Self-Check Vectors User Vectors 16 Bytes CH $1FE0 $1FF0 $1FFF AR Figure 2-1. Memory Map MEMORY Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 2-1 CT OR , IN C.2 006 0000 0032 0080 0128 2304 7936 8160 8176 8191 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7 6 5 CT OR , IN C.2 006 4 3 ADDRESS $0000 to $001F $00 PORT A DATA $01 PORT B DATA $02 PORT C DATA $03 PORT D DATA $04 PORT A DDR $05 PORT B DDR $06 PORT C DDR DATA 2 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 Freescale Semiconductor, Inc... $07 PORT D DDR $08 UNUSED $09 UNUSED $0A SERIAL CTRL $0B SERIAL STAT $0C SERIAL DATA $0D UNUSED $0E UNUSED $0F UNUSED $10 UNUSED $11 UNUSED $12 TIMER CONTROL $13 TIMER STATUS $14 CAPTURE HIGH $15 CAPTURE LOW $16 COMPARE HIGH $17 COMPARE LOW $18 COUNTER HIGH $19 COUNTER LOW $1A DUAL TM HIGH $1B DUAL TM LOW $1C UNUSED $1D ADDR $1E ADSCR 0 0 0 0 0 0 0 0 SPF SPE DCOL 0 0 ON DU MSTR 0 0 0 0 0 0 0 0 0 ICIE ICF CA OCIE OCF LE TOIE TOF 0 0 SE MIC 0 0 0 0 IEDG 0 OLVL 0 AR CH CCF ADRC IVE DB YF ADON RE ES 0 0 0 CH1 CH0 $1F RESERVED Figure 2-2. I/O Registers for the MC68HC05P9A MEMORY 2-2 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 2.1 ROM 2.2 ROM Security Feature A security feature has been incorporated into the MC68HC05P9A to help prevent external reading of code in the ROM. Placing unique customer code at ROM locations $0028-$002F aids in keeping customer developed software proprietary. Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA MEMORY Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 2-3 LE Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. SE MIC ON The user RAM consists of 128 bytes of a shared stack area. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. NOTE DU 2.3 RAM CT OR , IN C.2 006 The user ROM consists of 48 bytes of page zero ROM from $0020 to $004F, 2048 bytes of ROM from $0100 to $08FF, and 16 bytes of user vectors from $1FF0 to $1FFF. The self-check ROM and vectors are located from $1F00 to $1FEF. Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA MEMORY 2-4 For More Information On This Product, Go to: www.freescale.com LE SE MIC ON DU CT OR , IN C.2 006 MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 3 CENTRAL PROCESSING UNIT This section describes the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor, Inc... 3.1 Accumulator (A) 7 ON LE SE MIC A X CCR H I N Z C DU The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 0 3.2 Index Register (X) The index register is an 8-bit register used for the indexed addressing value to create an effective address. The index register also may be used as a temporary storage area. 7 CA 3.3 Condition Code Register (CCR) The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. 3.3.1 H — Half Carry This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. AR CH IVE DB YF Rev. 2.0 For More Information On This Product, Go to: www.freescale.com RE ES CENTRAL PROCESSING UNIT 3-1 CT OR , IN C.2 006 0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.3.2 I — Interrupt 3.3.3 N — Negative When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Freescale Semiconductor, Inc... 3.3.4 Z — Zero When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. 3.3.5 C — Carry/Borrow 3.4 Stack Pointer (SP) CH 12 IVE When accessing memory, the seven most significant bits are permanently set to 0000011. These seven bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. DB YF RE ES The stack pointer contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. CA LE 7 SE When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates. MIC ON DU CT OR , IN C.2 006 When this bit is set, timer and external interrupts are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. 0 1 SP 0 0 0 0 0 1 AR CENTRAL PROCESSING UNIT 3-2 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.5 Program Counter (PC) 12 CT OR , IN C.2 006 The program counter is a 13-bit register that contains the address of the next byte to be fetched. 0 PC NOTE Freescale Semiconductor, Inc... AR CH IVE DB YF Rev. 2.0 For More Information On This Product, Go to: www.freescale.com RE ES CENTRAL PROCESSING UNIT 3-3 CA LE SE MIC ON DU The HC05 CPU core is capable of addressing a 64 Kbyte memory map. For this implementation, however, the addressing registers are limited to an 8 Kbyte memory map. Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CENTRAL PROCESSING UNIT 3-4 For More Information On This Product, Go to: www.freescale.com CA LE SE MIC ON DU CT OR , IN C.2 006 MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 4 INTERRUPTS The MCU can be interrupted four different ways: the two maskable hardware interrupts (IRQ and timer), the non-maskable software interrupt instruction (SWI), and by the optional external asynchronous interrupt on each port A pin (enabled by pullup mask option). Freescale Semiconductor, Inc... SE AR CH IVE DB YF RE ES CA Rev. 2.0 The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I bit clear) and if the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. Table 4-1 lists vector addresses for all interrupts including reset. LE INTERRUPTS 4-1 For More Information On This Product, Go to: www.freescale.com MIC Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. ON Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume. NOTE DU CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 4-1. Vector Address for Interrupts and Reset Register N/A N/A N/A TSR TSR TSR Flag Name N/A N/A N/A ICF OCF TOF Reset Interrupts CT OR , IN C.2 006 RESET SWI IRQ TIMER TIMER TIMER CPU Interrupt Vector Address $1FFE-$1FFF $1FFC-$1FFD $1FFA-$1FFB $1FF8-$1FF9 $1FF8-$1FF9 $1FF8-$1FF9 Software External Interrupt Timer Input Capture Timer Output Capture Timer Overflow Freescale Semiconductor, Inc... 4.1 Hardware Controlled Interrupt Sequence AR CH IVE DB YF 3. WAIT or HALT — The WAIT or HALT instruction causes all processor clocks to stop, but leaves the timer clock running. This rest state of the processor can be cleared by reset, an external interrupt (IRQ), or timer interrupt. These individual interrupts have no special wait vectors. See 6.1.2 Halt Mode. RE ES 2. STOP — The STOP instruction causes the oscillator to be turned off and the processor to "sleep" until an external interrupt (IRQ) or reset occurs.See 6.1.1 Stop Mode. CA LE 1. RESET — A low input on the RESET input pin causes the program to vector to its starting address, which is specified by the contents of memory locations $1FFE and $1FFF. The I bit in the condition code register also is set. Much of the MCU is configured to a known state during this type of reset as described in SECTION 5 RESETS. SE INTERRUPTS 4-2 For More Information On This Product, Go to: www.freescale.com MIC The following three functions (RESET, STOP, and WAIT) are not interrupts in the strictest sense. However, they are acted upon in a similar manner. Flowcharts for hardware interrupts are shown in Figure 4-1, and for STOP and WAIT in Figure 61. A discussion is provided below. ON DU MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Y Is I Bit Set N IRQ External Interrupt N Timer Internal Interrupt Y Freescale Semiconductor, Inc... Clear IRQ Request Latch Y N Fetch Next Instruction MIC ON Stack PC, X, A, CC SE DU ES CA Execute Instruction LE 4.2 Timer Interrupt Three different timer interrupt flags cause a timer interrupt when they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1FF8 and $1FF9. AR CH IVE DB Figure 4-1. Hardware Interrupt Flowchart YF RE INTERRUPTS Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 4-3 CT OR , IN C.2 006 Set I Bit Load PC From: IRQ: $1FFA-$1FFB Timer: $1FF8-$1FF9 Complete Interrupt Routine and Execute RTI From RESET Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 4.3 External Interrupt NOTE Freescale Semiconductor, Inc... When the edge- and level-sensitive mask option is selected, the voltage applied to the IRQ pin must return to the high state before the RTI instruction in the interrupt service routine is executed to avoid the processor re-entering the IRQ service routine. IRQ PIN ES CA LE SE MIC ON The internal interrupt latch is cleared nine PH2 clock cycles after the interrupt is recognized (after location $1FFA is read). Therefore, another external interrupt pulse can be latched during the IRQ service routine. NOTE DU CT OR , IN C.2 006 IRQ LATCH R The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector flipflop is latched on the falling edge of IRQ. If either the output from the internal edge detector flip-flops or the level on the IRQ pin is low, a request is synchronized to the CPU to generate the IRQ interrupt. If the edge-sensitive only mask 0ption is selected, the output of the internal edge detector flip-flop is sampled and the input level on the IRQ pin is ignored. The interrupt service routine address is specified by the contents of memory locations $1FFA and $1FFB. A block diagram of the IRQ function is shown in Figure 4-2. YF PA0 DDRA0 PA0 IRQ INHIBIT (MASK OPTION) RE TO BIH & BIL INSTRUCTION SENSING VDD DB IRQ VECTOR FETCH AR MASK OPTION (IRQ LEVEL) CH IVE PA7 DDRA7 PA7 IRQ INHIBIT (MASK OPTION) TO IRQ PROCESSING IN CPU RST Figure 4-2. IRQ Function Block Diagram INTERRUPTS MC68HC05P9A Rev. 2.0 4-4 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the IRQ pin or a port A pin if port A interrupts have been enabled. If edge-only sensitivity is chosen by a mask option, only the IRQ latch output can activate a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases: 1. Falling edge on the IRQ pin with all enabled port A interrupt pins at a high level. Freescale Semiconductor, Inc... 1. Low level on the IRQ pin. 3. Low level on any enabled port A interrupt pin. 4. Falling edge on any enabled port A interrupt pin with all enabled port A interrupt pins on the IRQ pin at a high level. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $1FFA and $1FFB. The IRQ latch is automatically cleared by entering the interrupt service routine. AR CH IVE DB YF RE ES CA Rev. 2.0 For More Information On This Product, Go to: www.freescale.com LE 2. Falling edge on the IRQ pin with all enabled port A interrupt pins at a high level. SE INTERRUPTS 4-5 MIC If level sensitivity is chosen, the active high state of the IRQ input can also activate an IRQ request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases: ON DU 2. Falling edge on any enabled port A interrupt pin with all other enabled port A interrupt pins and the IRQ pin at a high level. CT OR , IN C.2 006 The IRQ pin is one source of an IRQ interrupt and a mask option can also enable the port A pins (PA0 thru PA7) to act as other IRQ interrupt sources. These sources are all combined into a single ORing function to be latched by the IRQ latch. Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 4.4 Optional External Interrupts (PA0-PA7) NOTE Freescale Semiconductor, Inc... 4.5 Software Interrupt (SWI) AR CH IVE DB YF RE The SWI is an executable instruction and a non-maskable interrupt. It is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI executes after interrupts which were pending when the SWI was fetched but before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD. ES CA LE SE INTERRUPTS MIC If enabled, the PA0 thru PA7 pins will cause an IRQ interrupt only if these individual pins are configured as inputs. ON NOTE DU The BIH and BIL instructions apply to the output of the logic OR function of the enabled PA0 thru PA7 interrupt pins and the IRQ pin. The BIH and BIL instructions do not exclusively test the state of the IRQ pin. CT OR , IN C.2 006 The IRQ interrupt can be triggered by the inputs on the PA0 thru PA7 port pins if enabled by individual mask options. With pullup enabled, each port A pin can activate the IRQ interrupt function and the interrupt operation will be the same as for inputs to the IRQ pin. Once enabled by mask option, each individual port A pin can be disabled as an interrupt source if its corresponding DDR bit is configured for output mode. 4-6 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 5 RESETS The MCU can be reset three ways: by the initial power-on reset function, by an active low input to the RESET pin, and by a computer operating properly (COP) watchdog-timer timeout. Freescale Semiconductor, Inc... 5.1 Power-On Reset (POR) 5.3 Computer Operating Properly (COP) Reset The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU. Because the internal RESET signal is used, the MCU comes out of a COP reset in the same operating mode it was in when the COP time-out was generated. The COP reset function is enabled or disabled by a mask option. AR CH Refer to SECTION 9 COMPUTER OPERATING PROPERLY (COP) for more information on the COP. IVE DB YF RE ES CA The MCU is reset when a logic zero is applied to the RESET input for a period of one and one-half machine cycles (tcyc). Rev. 2.0 For More Information On This Product, Go to: www.freescale.com LE 5.2 RESET Pin SE There is a 4064 internal processor clock cycle (tcyc) oscillator stabilization delay after the oscillator becomes active. If the RESET pin is low at the end of this 4064cycle delay, the MCU will remain in the reset condition until RESET goes high. MIC RESETS 5-1 ON An internal reset is generated on power-up to allow the internal clock generator to stabilize. The power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. DU CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION t VDDR V V DD DD Threshold (1-2 V Typical) OSC1 2 t OXOV 4064 t cyc t cyc Freescale Semiconductor, Inc... Internal 1 Clock Internal Address 1 Bus 1FFE 1FFF New PC DU CT OR , IN C.2 006 1FFE 1FFE 1FFE 1FFE 1FFF New PC RESET SE MIC Internal Data 1 Bus New PCH New PCL Op Code ON PCH PCL PCL Op PCH Code t RL 3 AR CH IVE DB YF RESETS 5-2 For More Information On This Product, Go to: www.freescale.com RE ES Figure 5-1. Power-On Reset and RESET CA NOTES: 1. Internal timing signal and bus information not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. LE MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 6 LOW POWER MODES Freescale Semiconductor, Inc... 6.1 STOP Instruction 6.1.1 Stop Mode IVE DB The MCU can be brought out of the stop mode only by an IRQ external interrupt or an externally generated RESET. When exiting the stop mode, the internal oscillator will resume after a 4064 PH2 clock cycle oscillator stabilization delay. NOTE Execution of the STOP instruction without conversion to halt (via mask option) will cause the oscillator to stop, and therefore disable the COP watchdog timer. If the COP watchdog timer is used, the stop mode should be changed to the halt mode by selecting the appropriate mask option. LOW POWER MODES Rev. 2.0 For More Information On This Product, Go to: www.freescale.com AR CH YF Execution of the STOP instruction without conversion to halt places the MCU in its lowest power consumption mode. In the stop mode the internal oscillator is turned off, halting all internal processing, including the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the condition code register so that the IRQ external interrupt is enabled. All other registers and memory remain unaltered. All input/output lines remain unchanged. RE ES CA LE The STOP instruction can result in one of two modes of operation, depending on the stop conversion mask option. If the stop conversion is not chosen, the STOP instruction will behave like a normal STOP instruction in the MC68HC05 Family and place the MCU in the stop mode. If the stop conversion is chosen, the STOP instruction will behave like a WAIT instruction (with the exception of a variable delay at startup) and place the MCU in the halt mode. SE MIC ON DU The MC68HC05P9A is capable of running in a low-power mode in each of its configurations. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the onchip oscillator. The STOP and WAIT instructions are not normally used if the COP watchdog timer is enabled. The stop conversion mask option is used to modify the behavior of the STOP instruction from stop mode to halt mode. The flow of the stop, halt, and wait modes is shown in Figure 6-1. CT OR , IN C.2 006 6-1 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 6.1.2 Halt Mode In halt mode the PH2 clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated from the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the condition code register enabling the IRQ external interrupt. All other registers, memory, and input/output lines remain in their previous states. Freescale Semiconductor, Inc... AR If the 16-bit timer interrupt is enabled, it will cause the processor to exit the wait mode and resume normal operation. The 16-bit timer may be used to generate a periodic exit from the wait mode. The wait mode may also be exited when an IRQ external interrupt or RESET occurs. CH IVE The WAIT instruction places the MCU in a low-power mode, which consumes more power than the stop mode. In wait mode, the PH2 clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer and reset to be generated from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the condition code register enabling the IRQ external interrupt. All other registers, memory, and input/output lines remain in their previous state. DB YF RE ES 6.2 WAIT Instruction CA LOW POWER MODES LE The halt mode is not intended for normal use. This feature is provided to keep the COP watchdog timer active in the event a STOP instruction is inadvertently executed. SE MIC If the 16-bit timer interrupt is enabled, the processor will exit the halt mode and resume normal operation. The halt mode can also be exited when an IRQ external interrupt or external RESET occurs. When exiting the halt mode, the PH2 clock will resume after a delay of one to 4064 PH2 clock cycles. This varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization delay timer (a feature of the stop mode), which has been free-running (a feature of the wait mode). ON NOTE DU CT OR , IN C.2 006 Execution of the STOP instruction with the conversion to halt places the MCU in this low-power mode. Halt mode consumes the same amount of power as wait mode. (Both halt and wait modes consume more power than stop mode.) 6-2 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION STOP TO HALT MASK N Y EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE STOP EXTERNAL OSCILLATOR, STOP INTERNAL TIMER CLOCK, RESET STARTUP DELAY STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR CT OR , IN C.2 006 N N N N STOP HALT WAIT EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE Freescale Semiconductor, Inc... STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR Y EXTERNAL RESET? STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR DU ON EXTERNAL RESET? N IRQ EXTERNAL INTERRUPT? N Y Y IRQ EXTERNAL INTERRUPT? Y EXTERNAL RESET? N MIC Y Y TIMER INTERNAL INTERRUPT? Y IRQ EXTERNAL INTERRUPT? N RESTART EXTERNAL OSCILLATOR, RESTART STABILIZATION DELAY SE LE Y COP INTERNAL RESET? Y TIMER INTERNAL INTERRUPT? N CA Y END OF STABILIZATION DELAY? N Y ES COP INTERNAL RESET? N RESTART INTERNAL PROCESSOR CLOCK IVE AR CH Rev. 2.0 DB YF Figure 6-1. STOP/WAIT Flowcharts RE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT a. STACK b. SET I BIT c. VECTOR TO INTERRUPT ROUTINE LOW POWER MODES 6-3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA LOW POWER MODES 6-4 For More Information On This Product, Go to: www.freescale.com LE SE MIC ON DU CT OR , IN C.2 006 MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 7 SIMPLE SERIAL INPUT/OUTPUT PORT This device includes a simple synchronous serial I/O port. The SIOP is a three wire master/slave system including serial clock (SCK), serial data input (SDI), and serial data output (SDO). A mask programmable option determines whether the SIOP is MSB or LSB first. Freescale Semiconductor, Inc... DU RQ D C RESET CT OR , IN C.2 006 SDO ON SCK SDI 8-BIT SHIFT REGISTER SE 7.1 Signal Format 7.1.1 Serial Clock (SCK) The following paragraphs describe the SIOP signal format. AR The state of SCK between transmissions and prior to enabling the SIOP must be logic one. The first falling edge of SCK signals the beginning of a transmission. At this time, the first bit of received data is accepted at the SDI pin and the first bit of transmitted data is presented at the SDO pin. Data is captured at the SDI pin on the rising edge of SCK. Subsequent falling edges shift the data and accept or present the next bit. The transmission is ended upon the eighth rising edge of SCK. The maximum frequency of SCK in slave mode is equal to E (bus clock) divided by four. That is, for a 4-MHz oscillator input, E becomes 2 MHz and the maximum SCK frequency is 0.5 MHz. There is no minimum SCK frequency. CH IVE Rev. 2.0 For More Information On This Product, Go to: www.freescale.com DB YF RE SIMPLE SERIAL INPUT/OUTPUT PORT 7-1 ES CA Figure 7-1. SIOP Block Diagram LE DATA BUS MIC MSB/LSB MASK OPTION Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.1.2 Serial Data Out (SDO) Freescale Semiconductor, Inc... 7.1.3 Serial Data In (SDI) SCK SDO SDI ES BIT 1 CA BIT 2 BIT 3 LE SE The SDI pin becomes an input as soon as the SIOP is enabled. New data may be presented to the SDI pin on the falling edge of SCK. Valid data must be present at least 100 ns before the rising edge of the clock and remain valid for 100 ns after the edge. MIC ON DU A mask programmable option will be included to allow data to be transmitted in either MSB first format or LSB first format. In either case, the state of the SDO pin always will reflect the value of the first bit received on the previous transmission if there was one. Prior to enabling the SIOP, PB5 can be initialized to determine the beginning state if necessary. While the SIOP is enabled, PB5 can not be used as a standard output since that pin is coupled to the last stage of the serial shift register. On the first falling edge of SCK, the first data bit to be shifted out is presented to the output pin. CT OR , IN C.2 006 BIT 7 BIT 3 BIT 7 In master mode, the format is identical except that the SCK pin is an output and the shift clock now originates internally. The master mode transmission frequency is fixed at E/4. BIT 8 RE BIT 1 BIT 2 BIT 8 AR SIMPLE SERIAL INPUT/OUTPUT PORT 7-2 For More Information On This Product, Go to: www.freescale.com CH IVE DB YF Figure 7-2. Serial I/O Port Timing MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.2 SIOP Registers 7.2.1 SIOP Control Register (SCR) This register is located at address $000A and contains two bits. $0A RESET: 0 0 SPE 0 0 0 MSTR 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Figure 7-3. SIOP Control Register AR CH IVE Rev. 2.0 For More Information On This Product, Go to: www.freescale.com DB MSTR — Master Mode When set, this bit configures the SIOP for master mode. This means that the transmission is initiated by a write to the data register and the SCK pin becomes an output providing a synchronous data clock at a fixed rate of E (bus clock) divided by four. While the device is in master mode, the SDO and SDI pins do not change function. These pins behave exactly as they would in slave mode. Reset clears this bit and configures the SIOP for slave operation. MSTR may be set at any time regardless of the state of SPE. Clearing MSTR will abort any transmission in progress. YF RE SIMPLE SERIAL INPUT/OUTPUT PORT 7-3 ES CA SPE — Serial Peripheral Enable When set, this bit enables the serial I/O port and initializes the port B DDR such that PB5 (SDO) is output, PB6 (SDI) is input and PB7 (SCK) is input (slave mode only). The port B DDR can be altered subsequently as the application requires and the port B data register (except for PB5) can be manipulated as usual. However, these actions could affect the transmitted or received data. When SPE is cleared, port B reverts to standard parallel I/O without affecting the port B data register or DDR. SPE is readable and writable any time but clearing SPE while a transmission is in progress will abort the transmission, reset the bit counter, and return port B to its normal I/O function. Reset clears this bit. LE SE MIC ON DU CT OR , IN C.2 006 0 0 The following paragraphs describe the SIOP registers. Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.2.2 SIOP Status Register (SSR) $0B RESET: SPIF 0 DCOL 0 0 0 0 0 CT OR , IN C.2 006 0 0 0 0 This register is located at address $000B and contains only two bits. 0 0 0 0 Figure 7-4. SIOP Status Register Freescale Semiconductor, Inc... AR CH IVE DB YF RE SIMPLE SERIAL INPUT/OUTPUT PORT 7-4 For More Information On This Product, Go to: www.freescale.com ES DCOL is cleared by reading the status register with SPIF set followed by a read or write of the data register. If the last part of the clearing sequence is done after another transmission has been started, DCOL will be set again. If the DCOL bit is set and the SPIF is not set, clearing the DCOL requires turning the SIOP off then turning it back on. Reset also clears this bit. CA LE SE DCOL — Data Collision This is a read-only status bit which indicates that an invalid access to the data register has been made. This can occur any time after the first falling edge of SCK and before SPIF is set. A read or write of the data register during this time will result in invalid data being transmitted or received. MIC ON SPIF — Serial Peripheral Interface Flag This bit is set upon occurrence of the last rising clock edge and indicates that a data transfer has taken place. It has no effect on any further transmissions and can be ignored without problem. SPIF is cleared by reading the SSR with SPIF set followed by a read or write of the serial data register. If it is cleared before the last edge of the next byte, it will be set again. Reset clears this bit. DU MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.2.3 SIOP Data Register (SDR) $0C RESET: U U U U CT OR , IN C.2 006 U U This register is located at address $000C and is both the transmit and receive data register. This system is not double buffered and any write to this register will destroy the previous contents. The SDR can be read at any time, but if a transmission is in progress the results may be ambiguous. Writes to the SDR while a transmission is in progress can cause invalid data to be transmitted and/or received. This register can be read and written only when the SIOP is enabled (SPE=1). U U Freescale Semiconductor, Inc... Figure 7-5. SIOP Data Register AR CH IVE Rev. 2.0 For More Information On This Product, Go to: www.freescale.com DB YF RE SIMPLE SERIAL INPUT/OUTPUT PORT 7-5 ES CA LE SE MIC ON DU Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF RE SIMPLE SERIAL INPUT/OUTPUT PORT 7-6 For More Information On This Product, Go to: www.freescale.com ES CA LE SE MIC ON DU CT OR , IN C.2 006 MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 8 TIMER Freescale Semiconductor, Inc... The timer consists of a 16-bit, software-programmable counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from several microseconds to many seconds. Refer to Figure 8-1 for a timer block diagram. Each specific functional segment (capability) is represented by two registers. These registers contain the high and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte also is accessed. SE AR CH IVE DB YF RE ES CA LE Rev. 2.0 The I bit in the CCR should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. MIC TIMER 8-1 For More Information On This Product, Go to: www.freescale.com ON NOTE DU CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION High Byte Low Byte Internal Processor Clock 8-Bit Buffer /4 $16 $17 Output Compare Register High Byte 16-Bit Free Running Counter Counter Alternate Register Low Byte $18 $19 $1A $1B Freescale Semiconductor, Inc... DU Output Compare Circuit Overflow Detect Circuit ON ICF OCF TOF $13 MIC Timer Status Reg. SE Timer Control ICIE OCIE TOIE IEDG OLVL Reg. $12 Interrupt Circuit CT OR , IN C.2 006 High Low Byte Byte Input Capture Register $14 $15 Edge Detect Circuit Output Level Reg. DQ CLK C RESET Output Edge Level Input (TCMP) (TCAP) Internal Bus The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1A-$1B (counter alternate register). A read from only the least significant byte (LSB) of the free-running counter ($19, $1B) receives the count value at the time of the read. If a read of the free-running counter or counter alternate register first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several AR CH IVE The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. DB YF RE 8.1 Counter ES TIMER CA Figure 8-1. Timer Block Diagram LE 8-2 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The counter alternate register differs from the counter register in one respect: Aread of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF. The free-running counter is configured to $FFFC during reset and is always a read-only register. During a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator start-up delay. Because the free-running counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also be enabled when counter rollover occurs by setting its interrupt enable bit (TOIE). Freescale Semiconductor, Inc... The processor can write to either byte of the output compare register without affecting the other byte. The output level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF) is set or clear. TIMER Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 8-3 AR CH After a processor write cycle to the output compare register containing the MSB ($16), the output compare function is inhibited until the LSB ($17) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. IVE DB YF The output compare register contents are compared with the contents of the freerunning counter continually, and if a match is found, the corresponding output compare flag (OCF) bit is set and the corresponding output level (OLVL) bit is clocked to an output level register. The output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OCIE) is set. RE ES CA The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register is used for several purposes, such as indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. LE SE MIC 8.2 Output Compare Register ON DU CT OR , IN C.2 006 times. This buffer is accessed when reading the free-running counter or counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB also must be read to complete the sequence. Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8.3 Input Capture Register The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA TIMER 8-4 For More Information On This Product, Go to: www.freescale.com LE A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. SE MIC After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. ON The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. DU CT OR , IN C.2 006 Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture register. MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8.4 Timer Control Register (TCR) $12 $12 RESET: ICIE 0 OCIE 0 TOIE 0 0 0 CT OR , IN C.2 006 0 0 0 0 The TCR is a read/write register containing five control bits. Three bits control interrupts associated with the timer status register flags ICF, OCF, and TOF. IEDG 0 OLVL 0 Figure 8-2. Timer Control Register ICIE — Input Capture Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled Freescale Semiconductor, Inc... AR CH IVE DB Bits 2, 3, and 4 — Not used Always read zero YF OLVL — Output Level Value of output level is clocked into output level register by the next successful output compare and will appear on the TCMP pin 1 = High output 0 = Low output RE ES CA IEDG — Input Edge Value of input edge determines which level transition on TCAP pin will trigger free-running counter transfer to the input capture register 1 = Positive edge 0 = Negative edge Reset does not affect the IEDG bit (U=unaffected). LE Rev. 2.0 For More Information On This Product, Go to: www.freescale.com SE MIC TOIE — Timer Overflow Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TIMER 8-5 ON OCIE — Output Compare Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled DU Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8.5 Timer Status Register (TSR) $13 $13 RESET: ICF U OCF U TOF U 0 0 CT OR , IN C.2 006 0 0 0 0 The TSR is a read-only register containing three status flag bits. 0 0 0 0 Figure 8-3. Timer Status Register Freescale Semiconductor, Inc... ICF — Input Capture Flag 1 = Flag set when selected polarity edge is sensed by input capture edge detector 0 = Flag cleared when TSR and input capture low register ($15) are accessed OCF — Output Compare Flag 1 = Flag set when output compare register contents match the freerunning counter contents 0 = Flag cleared when TSR and output compare low register ($17) are accessed TOF — Timer Overflow Flag 1 = Flag set when free-running counter transition from $FFFF to $0000 occurs 0 = Flag cleared when TSR and counter low register ($19) are accessed The counter alternate register at address $1A and $1B contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. AR CH 2. The LSB of the free-running counter is read but not for the purpose of servicing the flag. IVE 1. The timer status register is read or written when TOF is set, and DB A problem can occur when using the timer overflow function and reading the freerunning counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: YF RE Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit. ES CA TIMER Bits 0-4 — Not used Always read zero LE SE MIC ON DU 8-6 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8.6 Timer During Wait or Halt Mode 8.7 Timer During Stop Mode Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA TIMER Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 8-7 LE SE MIC ON In the stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. If RESET is used, the counter is forced to $FFFC. During stop, if at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags wake up the MCU, but when the MCU does wake up, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. If RESET is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. DU CT OR , IN C.2 006 The CPU clock halts during the wait or halt mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA TIMER 8-8 For More Information On This Product, Go to: www.freescale.com LE SE MIC ON DU CT OR , IN C.2 006 MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 9 COMPUTER OPERATING PROPERLY (COP) This device includes a watchdog COP feature as a mask option. The COP is implemented with an 18-bit ripple counter. This provides a timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP should timeout, a system reset will occur and the device will be re-initialized in the same fashion as a power-on reset (POR) or external reset. 9.1 Resetting The COP Freescale Semiconductor, Inc... 9.2 COP During Wait or Halt Mode 9.3 COP During Stop Mode IVE DB Stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will be reset after the 4064 cycles of delay after stop mode. If an IRQ is used to exit stop mode, the COP counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program. YF RE ES CA The COP will continue to operate normally during wait or halt mode. The software should pull the device out of wait or halt mode periodically and reset the COP by writing a logic zero to the COPR bit to prevent a COP reset. LE SE NOTE AR The halt mode is not intended for normal use. This feature is provided to keep the COP watchdog timer active in the event a STOP instruction is inadvertently executed. CH COMPUTER OPERATING PROPERLY (COP) Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 9-1 MIC Preventing a COP reset is done by writing a zero to the COPR bit. This action will reset the counter and begin the timeout period again. The COPR bit is bit 0 of address $1FF0. A read of address $1FF0 will access the user-defined ROM data at that location. ON DU CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF COMPUTER OPERATING PROPERLY (COP) 9-2 For More Information On This Product, Go to: www.freescale.com RE ES CA LE SE MIC ON DU CT OR , IN C.2 006 MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 10 ANALOG-TO-DIGITAL (A/D) CONVERTER This section describes the four-channel, 8-bit, multiplexed input, successiveapproximation A/D converter. Freescale Semiconductor, Inc... 10.1 Conversion Process AR CH IVE Rev. 2.0 For More Information On This Product, Go to: www.freescale.com DB YF Pins PC6–PC3 are the four inputs to the multiplexer. Each channel of conversion takes 32 internal clock cycles, and the clock frequency must be equal to or greater than 1 MHz. If the internal clock frequency is less than 1 MHz, the A/D internal RC oscillator (nominally 1.5 MHz) must be used for the A/D conversion clock. Make this selection by setting the ADRC bit in the A/D status and control register to logical one. ANALOG-TO-DIGITAL (A/D) CONVERTER 10-1 RE ES CA An analog input voltage equal to VRH converts to digital $FF; an input voltage greater than VRH converts to $FF with no overflow. An analog input voltage equal to VSS converts to digital $00. For ratiometric conversions, the source of each analog input should use VRH as the supply voltage and be referenced to VSS. LE SE A multiplexer selects one of four analog input channels (AN3, AN2, AN1, or AN0) for sampling. A comparator successively compares the output of an internal digital-to-analog (D/A) converter to the sampled analog input. Control logic changes the D/A converter input one bit at a time, starting with the most significant bit (MSB), until the D/A converter output matches the sampled analog input. The conversion is monotonic and has no missing codes. MIC ON DU The A/D conversion process is ratiometric, using two reference voltages, VRH and VSS. Conversion accuracy is guaranteed only if VRH is equal to VDD. CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.2 A/D Status and Control Register (ADSCR) $001E RESET: CCF 0 ADRC 0 ADON 0 0 0 CT OR , IN C.2 006 0 0 0 0 The A/D status and control register contains a status flag and four writable control bits. CH1 0 CH0 0 Figure 10-1. A/D Status and Control Register (ADSCR) CCF — Conversion Complete Flag This read-only bit is automatically set when an analog-to-digital conversion is complete, and a new result can be read from the A/D data register. CCF is automatically cleared when a new conversion begins or when either the A/D status and control register or the A/D data register is accessed. Writing to or reading the A/D status and control register or the A/D data register starts a new conversion sequence. Data from the previous conversion is overwritten regardless of the state of the CCF bit. While CCF is a logical zero, the requested A/D result is not yet available in the A/D data register. ADRC — A/D RC Oscillator Control When the RC oscillator is turned on, it requires a time (tADRC) to stabilize, and results can be inaccurate during this time. If the internal clock rate is above 1 MHz, the ARDC bit should be cleared. 1 = Internal RC oscillator drives A/D converter 0 = Internal clock drives A/D converter When the internal RC oscillator is being used as the A/D converter clock, two limitations apply: 1. Because of the frequency tolerance of the RC oscillator and its asynchronism with the internal clock, the conversion complete flag (CCF) must be used to determine when a conversion sequence has been completed. 2. The conversion process runs at the nominal 1.5 MHz rate, but the conversion results must be transferred to the A/D data register synchronously with the internal clock; therefore, the conversion process is limited to a maximum of one channel every internal clock cycle. ADON — A/D On When the A/D is turned on, it requires a time (tADON) for the current sources to stabilize. During this time, results can be inaccurate. 1 = A/D converter enabled 0 = A/D converter disabled Bits 4–2 — Not Used These bits are not used and read logical zero out of reset. Logical zeros must be written to these bits when writing the A/D status and control register. ANALOG-TO-DIGITAL (A/D) CONVERTER 10-2 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA LE SE MIC ON DU Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION CH1–CH0 — Channel Select Table 10-1. A/D Input Selection CH1:CH0 00 01 10 Input Selected AN0, Port C Bit 6 AN1, Port C Bit 5 AN2, Port C Bit 4 AN3, Port C Bit 3 Freescale Semiconductor, Inc... 11 10.3 A/D Data Register (ADDR) $001D RESET: Bit 7 RE 6 ES The A/D data register is a read-only register that contains the result of the most recent A/D conversion. This register is updated each time the conversion complete flag (CCF) is set in the A/D status and control register. 5 4 3 2 1 Bit 0 10.4 A/D Converter During Wait Mode The A/D converter continues to operate normally while the MCU is in wait mode. If the A/D converter is not being used, clear the ADON and ADRC bits in the A/D status and control register to decrease power consumption during wait mode. AR CH IVE Rev. 2.0 For More Information On This Product, Go to: www.freescale.com DB YF A/D DATA REGISTER NOT AFFECTED BY RESET Figure 10-2. A/D Data Register (ADDR) ANALOG-TO-DIGITAL (A/D) CONVERTER 10-3 CA LE SE Performing a digital read of a port C pin that is selected as an analog input returns a logical zero. MIC Using one of the port C pins as the A/D converter input does not affect the ability to use the remaining port C pins as digital inputs. ON To prevent excess power dissipation, do not use a port C pin as an analog input and a digital input at the same time. DU CT OR , IN C.2 006 These bits select one of the four A/D inputs (AN3, AN2, AN1, or AN0) for conversion. Refer to Table 10-1). Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.5 A/D Converter During Stop or Halt Mode Freescale Semiconductor, Inc... AR CH IVE DB YF ANALOG-TO-DIGITAL (A/D) CONVERTER 10-4 For More Information On This Product, Go to: www.freescale.com RE ES CA LE SE MIC ON DU CT OR , IN C.2 006 Stop or halt mode disables the comparator and charge pump and aborts any conversion in progress or pending. When the MCU leaves stop mode, the built-in delay for oscillator startup allows enough time for the A/D circuits to stabilize. Therefore, no software delays are needed after exiting from stop mode. When the MCU leaves halt mode, a software delay is needed since the MCU may exit from halt mode after only one internal clock cycle. MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 11 SELF-CHECK MODE The self-check program resides at mask ROM locations $1F00 to $1FEF. This program is designed to check the part’s functionality with a minimum of support hardware. The COP subsystem is disabled in the self-check mode so that routines that feed the COP do not exist in the self-check program. Freescale Semiconductor, Inc... 0 0 0 1 1 0 1 1 0 0 CA PC2 PC1 LE Table 11-1. Self-Check Results PC0 1 0 1 0 1 Bad I/O Bad RAM Bad Timer Bad ROM Bad Serial Good Device Bad Device SE REMARKS 0 indicates LED is on; 1 indicates LED is off. AR CH IVE DB YF RE Flashing All Others Rev. 2.0 For More Information On This Product, Go to: www.freescale.com ES SELF-CHECK MODE 11-1 MIC The self-check mode is entered on the rising edge of RESET if the IRQ pin is driven to double the supply voltage and the TCAP/PD7 pin is at logic one. RESET must be held low for 4064 cycles after POR or for a time tRL for any other reset. After reset, the I/O, RAM, ROM, timer, and SIOP are tested. Self-check results (using LED’s as monitors) are shown in Table 11-1. It is not recommended that the user code use any of the self-check code. The self-check code is subject to change at any time to improve testability or manufacturability. ON DU CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10 KΩ 4.7 KΩ 1 µf RESET IRQ PA7 PA6 PA5 PA4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CT OR , IN C.2 006 VDD VTST VDD 28 27 VDD 10 KΩ OSC1 OSC2 26 25 24 23 22 21 20 19 18 17 16 15 4 MHz TCAP/PD7 TCMP PD5 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 10 MΩ 20 pF 20 pF Freescale Semiconductor, Inc... PA3 PA2 PA1 PA0 SDO/PB5 SDI/PB6 SCK/PB7 VSS SE MIC ON DU Figure 11-1. Self-Check Circuit AR CH IVE DB YF RE ES CA VDD = 5.0 V VTST = 10.0 V LE 470 Ω VDD 10 KΩ SELF-CHECK MODE 11-2 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 12 INSTRUCTION SET This section describes the M68HC05P9A addressing modes and instruction types. Freescale Semiconductor, Inc... 12.1 Addressing Modes • • • • • • • Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative 12.1.1 Inherent AR CH IVE Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long. DB YF RE ES Rev. 2.0 For More Information On This Product, Go to: www.freescale.com CA INSTRUCTION SET 12-1 LE SE MIC • Inherent ON The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are the following: DU CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.1.2 Immediate 12.1.3 Direct Freescale Semiconductor, Inc... 12.1.4 Extended Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. 12.1.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can access locations $0000–$01FE. AR CH IVE DB YF Indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the conditional address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF. RE ES 12.1.5 Indexed, No Offset CA INSTRUCTION SET LE When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. SE Extended instructions use only three bytes to access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. MIC ON DU Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. CT OR , IN C.2 006 Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 12-2 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.1.7 Indexed, 16-Bit Offset Freescale Semiconductor, Inc... 12.1.8 Relative AR CH IVE DB YF When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. RE ES Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. Rev. 2.0 For More Information On This Product, Go to: www.freescale.com CA LE INSTRUCTION SET 12-3 SE MIC As with direct and extended addressing the Motorola assembler determines the shortest form of indexed addressing. ON Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. DU Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. CT OR , IN C.2 006 Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.2 Instruction Types • • • • • Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions Freescale Semiconductor, Inc... Table 12-1. Register/Memory Instructions Instruction SE MIC Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 12-1 lists the register/memory instructions. ON DU 12.2.1 Register/Memory Instructions Add Memory Byte to Accumulator AND Memory Byte with Accumulator LE Add Memory Byte and Carry Bit to Accumulator CT OR , IN C.2 006 Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB The MCU instructions fall into the following five categories: Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte AR CH IVE DB Multiply Load Index Register with Memory Byte OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator YF RE ES Bit Test Accumulator CA INSTRUCTION SET 12-4 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.2.2 Read-Modify-Write Instructions Table 12-2. Read-Modify-Write Instructions Instruction Mnemonic ASL Freescale Semiconductor, Inc... Arithmetic Shift Left Arithmetic Shift Right Clear Bit in Memory Set Bit in Memory Clear DU ON Decrement Increment Logical Shift Left MIC Complement (One’s Complement) SE Negate (Two’s Complement) Rotate Left through Carry Bit LE Logical Shift Right CA Test for Negative or Zero ES Rotate Right through Carry Bit Bit test and branch instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These three-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding the AR CH IVE Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump to subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions use relative addressing. DB YF 12.2.3 Jump/Branch Instructions RE INSTRUCTION SET Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 12-5 CT OR , IN C.2 006 These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST) is an exception to the read-modify-write sequence because it does not write a replacement value. Table 12-2 lists the read-modify-write instructions. ASR BCLR BSET CLR COM DEC INC LSL LSR NEG ROL ROR TST Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Freescale Semiconductor, Inc... Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower DU ON MIC SE Branch if Interrupt Mask Clear Branch if Minus LE Branch if Lower or Same CA Branch if Interrupt Mask Set Branch if Not Equal ES Branch Always RE Branch if Plus Branch if Bit Clear Branch Never YF DB Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine IVE AR CH INSTRUCTION SET 12-6 For More Information On This Product, Go to: www.freescale.com CT OR , IN C.2 006 Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 12-3 lists the jump and branch instructions. MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.2.4 Bit Manipulation Instructions Table 12-4. Bit Manipulation Instructions Instruction Mnemonic BCLR Freescale Semiconductor, Inc... Clear Bit Branch if Bit Clear Branch if Bit Set Set Bit DU MIC ON 12.2.5 Control Instructions Table 12-5. Control Instructions LE Clear Carry Bit CA Instruction SE These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 12-5, use inherent addressing. Clear Interrupt Mask ES Reset Stack Pointer RE No Operation YF Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin DB IVE Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts CH AR INSTRUCTION SET Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 12-7 CT OR , IN C.2 006 BSET CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Bit manipulation instructions use direct addressing. Table 12-4 lists these instructions. BRCLR BRSET Mnemonic Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.3 Instruction Set Summary Table 12-6. Instruction Set Summary Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel CT OR , IN C.2 006 Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Opcode Operation Description HINZC Freescale Semiconductor, Inc... Add with Carry A ← (A) + (M) + (C) ¤—¤ ¤ ¤ DU IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL A9 ii B9 dd C9 hh ll D9 ee ff E9 ff F9 AB ii BB dd CB hh ll DB ee ff EB ff FB A4 ii B4 dd C4 hh ll D4 ee ff E4 ff F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 dd Add without Carry A ← (A) + (M) ON ¤—¤ ¤ ¤ MIC SE Logical AND A ← (A) ∧ (M) —— ¤ ¤— LE Arithmetic Shift Left (Same as LSL) CA C 0 b0 —— ¤ ¤ ¤ ES b7 ff dd RE Arithmetic Shift Right C b7 b0 —— ¤ ¤ ¤ DB Branch if Carry Bit Clear YF ff PC ← (PC) + 2 + rel ? C = 0 ————— rr dd dd dd dd dd dd dd dd rr rr BCLR n opr Clear Bit n Mn ← 0 AR BCS rel BEQ rel Branch if Carry Bit Set (Same as BLO) Branch if Equal CH DIR (b0) DIR (b1) DIR (b2) DIR (b3) ————— DIR (b4) DIR (b5) DIR (b6) DIR (b7) ————— ————— REL REL IVE PC ← (PC) + 2 + rel ? C = 1 PC ← (PC) + 2 + rel ? Z = 1 INSTRUCTION SET 12-8 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Cycles 2 3 4 5 4 3 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form BHCC rel BHCS rel BHI rel BHS rel Operation Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Description PC ← (PC) + 2 + rel ? H = 0 PC ← (PC) + 2 + rel ? H = 1 CT OR , IN C.2 006 HINZC ————— ————— REL REL REL REL REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL 28 29 22 24 2F 2E rr rr rr rr rr rr PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — — PC ← (PC) + 2 + rel ? C = 0 ————— Freescale Semiconductor, Inc... BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel PC ← (PC) + 2 + rel ? IRQ = 1 ————— ————— DU PC ← (PC) + 2 + rel ? IRQ = 0 Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — PC ← (PC) + 2 + rel ? I = 0 SE Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? C = 1 MIC Bit Test Accumulator with Memory Byte (A) ∧ (M) —— ¤ ¤— A5 ii B5 dd C5 hh ll D5 ee ff E5 ff F5 p 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 00 02 04 06 08 0A 0C 0E 21 rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr ON ————— LE ————— ————— ————— ————— ————— ————— CA PC ← (PC) + 2 + rel ? N = 1 PC ← (PC) + 2 + rel ? I = 1 ES PC ← (PC) + 2 + rel ? Z = 0 PC ← (PC) + 2 + rel ? 1 = 1 RE PC ← (PC) + 2 + rel ? N = 0 IVE DB BRCLR n opr rel Branch if bit n clear PC ← (PC) + 2 + rel ? Mn = 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ———— ¤ DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ———— ¤ DIR (b4) DIR (b5) DIR (b6) DIR (b7) ————— REL YF CH BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 AR BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 INSTRUCTION SET Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 12-9 Cycles 3 3 3 3 3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form Operation Description CT OR , IN C.2 006 HINZC BSET n opr Set Bit n Mn ← 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ————— DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd Freescale Semiconductor, Inc... BSR rel Branch to Subroutine Clear Carry Bit Clear Interrupt Mask CLC CLI CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X C←0 I←0 DU PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel ————— REL AD rr ———— 0 — 0 ——— INH INH DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX 98 9A 3F 4F 5F 6F 7F dd Clear Byte MIC M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 ON —— 0 1 — ff CA LE Compare Accumulator with Memory Byte (A) – (M) —— ¤ ¤ ¤ A1 ii B1 dd C1 hh ll D1 ee ff E1 ff F1 33 43 53 63 73 dd ES Complement Byte (One’s Complement) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) SE —— ¤ ¤1 ff RE YF Compare Index Register with Memory Byte (X) – (M) —— ¤ ¤1 DB A3 ii B3 dd C3 hh ll D3 ee ff E3 ff F3 3A 4A 5A 6A 7A dd IVE Decrement Byte M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 —— ¤ ¤— ff AR EXCLUSIVE OR Accumulator with Memory Byte A ← (A) ⊕ (M) —— ¤ ¤— A8 ii B8 dd C8 hh ll D8 ee ff E8 ff F8 CH INSTRUCTION SET 12-10 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Cycles 5 5 5 5 5 5 5 5 6 2 2 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Operation Description M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 CT OR , IN C.2 006 HINZC Increment Byte —— ¤ ¤— DIR INH INH IX1 IX DIR EXT IX2 IX1 IX 3C 4C 5C 6C 7C dd ff Unconditional Jump PC ← Jump Address ————— Freescale Semiconductor, Inc... DU BC C dd C hh ll D ee ff ff C EC FC BD C dd D hh ll D ee ff ff D ED FD A6 ii B6 dd C6 hh ll D6 ee ff E6 ff F6 AE ii BE dd CE hh ll DE ee ff EE ff FE 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D ii dd YF LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP RE ES LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LE LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X MIC JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Conditional Address ————— DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH ON Load Accumulator with Memory Byte SE A ← (M) —— ¤ ¤— Load Index Register with Memory Byte CA X ← (M) —— ¤ ¤— Logical Shift Left (Same as ASL) C b7 b0 0 —— ¤ ¤ ¤ ff dd DB Logical Shift Right 0 b7 b0 C —— 0 ¤ ¤ IVE ff Unsigned Multiply X : A ← (X) × (A) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) 0 ——— 0 11 5 3 3 6 5 2 AR Negate Byte (Two’s Complement) CH —— ¤ ¤ ¤ ff No Operation ————— INSTRUCTION SET Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 12-11 Cycles 5 3 3 6 5 2 3 4 3 2 5 6 7 6 5 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP Operation Description CT OR , IN C.2 006 HINZC Logical OR Accumulator with Memory A ← (A) ∨ (M) —— ¤ ¤— IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH AA ii BA dd CA hh ll DA ee ff EA ff FA 39 49 59 69 79 36 46 56 66 76 9C dd Freescale Semiconductor, Inc... Rotate Byte Left through Carry Bit C b7 —— ¤ ¤ ¤ b0 ff dd DU b7 ON Rotate Byte Right through Carry Bit C —— ¤ ¤ ¤ b0 ff RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X LE Return from Subroutine SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) SE RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) MIC Reset Stack Pointer SP ← $00FF ————— ¤¤ ¤ ¤ ¤ INH 80 INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX A2 ii B2 dd C2 hh ll D2 ee ff E2 ff F2 99 9B B7 dd C7 hh ll D7 ee ff E7 ff F7 8E BF dd CF hh ll DF ee ff EF ff FF 2 3 4 5 4 3 2 2 4 5 6 5 4 2 4 5 6 5 4 RE ES Subtract Memory Byte and Carry Bit from Accumulator CA A ← (A) – (M) – (C) —— ¤ ¤ ¤ Set Carry Bit C←1 I←1 ———— 1 — 1 ——— Set Interrupt Mask CH Store Index Register In Memory IVE Stop Oscillator and Enable IRQ Pin DB Store Accumulator in Memory YF M ← (A) —— ¤ ¤— — 0 ——— M ← (X) —— ¤ ¤— AR INSTRUCTION SET 12-12 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Cycles 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 2 6 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Operation Description CT OR , IN C.2 006 HINZC Subtract Memory Byte from Accumulator A ← (A) – (M) —— ¤ ¤ ¤ IMM DIR EXT IX2 IX1 IX A0 ii B0 dd C0 hh ll D0 ee ff E0 ff F0 Freescale Semiconductor, Inc... SWI Software Interrupt TAX TST opr TSTA TSTX TST opr,X TST ,X TXA MIC Transfer Accumulator to Index Register X ← (A) ON DU PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) — 1 ——— SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte ————— INH 83 10 INH DIR INH INH IX1 IX INH 97 3D 4D 5D 6D 7D 9F dd SE Test Memory Byte for Negative or Zero (M) – $00 ————— ff LE Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts A ← (X) ————— CA WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n — ¤ ——— opr PC PCH PCL REL rel rr SP X Z # ∧ ∨ ⊕ () –( ) ← ? : ¤ — INH 8F AR CH Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit ES Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Loaded with If Concatenated with Set or cleared Not affected IVE DB YF RE INSTRUCTION SET Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 12-13 Cycles 2 3 4 5 4 3 2 4 3 3 5 4 2 2 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc... 12-14 Table 12-7. Opcode Map Read-Modify-Write Control Register/Memory IMM DIR EXT IX2 D E 5 4 4 Bit Manipulation Branch REL DIR INH INH IX1 6 7 8 9 9 2 3 5 6 3 DIR IX INH INH A B C SUB EXT 3 4 IX2 2 5 DIR IX1 F 2 3 4 5 3 5 3 IX MSB LSB 3 MSB LSB BRA REL 2 3 INH 6 DIR 1 INH 1 INH 2 IX1 1 IX 1 2 IMM 2 2 DIR 3 3 0 NEG RTS 1 INH 11 2 IMM 2 2 DIR 3 3 EXT 3 4 1 NEGA CMP SBC 2 3 6 5 10 IMM 2 2 DIR 3 3 EXT 3 4 5 5 0 NEGX CMP SBC CPX DIR 3 3 AR NEG CMP SBC CPX EXT 3 4 BRSET0 BRN REL 3 BSET0 CMP IX2 2 5 NEG RTI SUB SUB SUB SUB IX1 1 4 SUB IX 3 3 1 BHI REL 3 5 INH 3 1 BRCLR0 MUL COMX INH 2 3 INH IX1 1 6 IX 1 5 2 IMM 2 2 CH CMP SBC IX2 2 5 DIR 2 5 DIR 2 5 0 CMP IX1 1 4 IX 3 BCLR0 3 DIR 2 5 IVE DB COM DIR 1 5 INH 1 3 DIR 2 5 1 SBC IX1 1 4 2 BLS REL 2 3 BRSET1 COMA LSRX INH 2 IX IX1 1 2 IMM 2 2 DIR 3 3 BSET1 COM LSR BIT 2 IMM 2 2 SBC IX 3 3 DIR 2 5 DIR 2 5 2 CPX IX2 2 5 3 COM LSR BIT DIR 3 3 BRCLR1 BCC REL 2 3 REL 3 5 3 3 6 5 DIR 1 INH 1 BCLR1 LSR LSRA AND AND AND 3 DIR 2 5 DIR 2 5 YF SWI CPX CPX IX1 1 4 CPX IX 3 4 BCS/BLO BNE REL 2 3 IX 5 2 DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 2 BRSET2 BSET2 RE ES CA ROR ASR IX1 1 6 IX 5 INH 2 1 3 AND EXT 3 4 IX2 2 5 AND IX1 1 4 AND IX 3 3 DIR 2 5 DIR 2 5 4 BIT EXT 3 4 5 ROR ASR DIR 1 5 INH 1 3 INH 2 3 BRCLR2 RORA ASRA ASL/LSL IX 5 1 BCLR2 RORX ASRX CLC SEC IX 5 1 INH 2 2 BIT IX2 2 5 BIT IX1 1 4 BIT IX 3 3 DIR 2 5 DIR 2 5 6 ROR TAX LDA BEQ REL 2 3 BRSET3 ASR BSET3 LE LDA 5 LDA DIR 3 4 EXT 3 5 LDA IX2 2 6 LDA IX1 1 5 LDA IX 4 3 DIR 2 5 DIR 2 5 SE IMM 2 6 STA 2 2 DIR 3 3 7 BHCC REL 2 3 DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 BRCLR3 ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ROL DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 BCLR3 STA EXT 3 4 STA IX2 2 5 STA IX1 1 4 STA IX 3 3 DIR 2 5 INH 2 2 DIR 2 5 MIC ON EOR IMM 2 2 7 EOR ADC EOR EOR EOR EOR INSTRUCTION SET BHCS REL 2 3 8 ROLA DECA INH 1 IX INH 2 IX1 1 BRSET4 ROLX DECX DEC DEC 1 BSET4 ROL ROL 3 DIR 2 5 DIR 2 5 9 BPL REL 2 3 DIR 1 BRCLR4 DEC BCLR4 DU IMM 2 2 DIR 3 3 EXT 3 4 IX2 2 5 IX1 1 4 IX 3 8 ADC ADC ADC ADC ADC DIR 3 3 EXT 3 4 IX2 2 5 IX1 1 4 IX 3 3 DIR 2 5 DIR 2 5 9 CLI INH 2 2 A BMI REL 3 5 3 3 6 5 BRSET5 BSET5 ORA IMM 2 2 ORA SEI 1 INH 2 2 ORA ADD IMM 2 ORA ORA ORA 3 DIR 2 5 DIR 2 5 DIR 3 3 EXT 3 4 IX2 2 5 IX1 1 4 IX 3 A ADD RSP ADD ADD ADD ADD DIR 3 2 EXT 3 3 IX2 2 4 IX1 1 3 IX 2 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com BMC REL 2 3 DIR 1 4 INH 1 3 INH 2 3 IX1 1 5 B INC TST DIR 1 INH 1 INH 2 BRCLR5 INCA TSTA TSTX TST IX1 1 BCLR5 INCX INC INC IX 4 3 DIR 2 5 DIR 2 5 B JMP 1 2 INH 2 6 C BMS REL 2 3 BRSET6 BSET6 JMP NOP IX 2 1 INH 2 JMP BSR REL 2 2 JMP JMP 3 DIR 2 5 DIR 2 5 CT OR , IN C.2 006 DIR 3 5 EXT 3 6 IX2 2 7 IX1 1 6 IX 5 C JSR DIR 3 3 D BIL REL 3 5 3 3 BRCLR6 BCLR6 TST STOP 1 6 5 INH 2 JSR EXT 3 4 JSR IX2 2 5 JSR IX1 1 4 JSR IX 3 3 DIR 2 5 DIR 2 5 D LDX 2 2 IMM 2 E BIH REL 2 DIR 1 INH 1 BRSET7 CLR CLRA CLRX INH 2 BSET7 LDX DIR 3 4 LDX EXT 3 5 LDX IX2 2 6 LDX IX1 1 5 LDX IX 4 3 DIR 2 5 DIR 2 5 E CLR IX1 1 F BRCLR7 BCLR7 CLR IX 1 WAIT INH 1 TXA INH 2 STX DIR 3 STX EXT 3 STX IX2 2 STX IX1 1 STX IX 3 DIR 2 DIR 2 F MSB LSB LSB of Opcode in Hexadecimal 0 3 0 MSB of Opcode in Hexadecimal 5 Number of Cycles BRSET0 Opcode Mnemonic DIR Number of Bytes/Addressing Mode MC68HC05P9A Rev. 2.0 REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset INH = Inherent IMM = Immediate DIR = Direct EXT = Extended Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 13 ELECTRICAL SPECIFICATIONS 13.1 Maximum Ratings (Voltages referenced to VSS Rating CT OR , IN C.2 006 Symbol VDD VIN Value Unit V V V mA Freescale Semiconductor, Inc... Supply Voltage Input Voltage Self-Check Modes (IRQ Pin Only) Current Drain Per Pin Excluding VDD and VSS Operating Temperature Range 68HC05P9AP (Standard) 68HC05P9ACP (Extended) 68HC05P9AVP (Automotive) 68HC05P9AMP (Automotive) Storage Temperature Range -0.3 to +7.0 DU VSS -0.3 to VDD +0.3 VSS -0.3 to 2 x VDD +0.3 25 TL to TH 0 to +70 -40 to +85 -40 to +105 -40 to +125 -65 to +150 VIN I ON MIC TA °C Characteristic YF 13.2 Thermal Characteristics RE ES This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either VSS or VDD). CA LE SE Tstg °C Symbol θJA Value 60 71 Unit °C/W AR CH ELECTRICAL SPECIFICATIONS Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 13-1 IVE DB Thermal Resistance Plastic DIP Plastic SOIC Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.3 DC Electrical Characteristics Characteristic Output Voltage ILOAD = 10.0 µA ILOAD = -10.0 µA Output High Voltage (ILOAD = -0.8 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5, TCMP (ILOAD = -5.0 mA) PC0-PC1 Output Low Voltage (ILOAD = 1.6 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5, TCMP (ILOAD = 15 mA) PC0-PC1 Input High Voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7, IRQ, RESET, OSC1 Input Low Voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7, IRQ, RESET, OSC1 Supply Current Run (A/D Enabled) Wait (A/D Enabled) Wait (A/D Disabled)/Halt Stop 25°C 0°C to +70°C -40°C to +85°C -40°C to +105°C -40°C to +125°C I/O Ports Hi-Z Leakage Current PA0-PA7, PB5-PB7, PC0-PC2, PD5 A/D Ports Hi-Z Leakage Current PC3–PC7 Input Current RESET, IRQ, OSC1, TCAP/PD7 I/O Ports Switch Resistance (Pullup Enabled PA0-PA7) Capacitance Ports (as Input or Output) RESET, IRQ Symbol VOL VOH VOH VOH VOL VOL VIH CT OR , IN C.2 006 Min Table 13-1. DC Electrical Characteristics (VDD = 5 V) (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted) Typ — — — — Max 0.1 — — — 0.4 0.4 VDD Unit V — VDD-0.1 VDD-0.8 VDD-0.8 — — V — — — V Freescale Semiconductor, Inc... DU 0.7 × VDD V ON VIL VSS — 0.2 × VDD V MIC — — — — — — — — — — — TBD 3.3 1.7 1.0 2 — — — — — — — 15 TBD TBD TBD 5 TBD TBD TBD 100 ± 10 ±1 ±1 TBD mA mA mA µA µA µA µA µA µA µA µA kΩ IDD LE CA ES SE IIL IOZ IIN RPTA COUT CIN YF RE — — — — 12 8 pF AR CH NOTES: 1. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range, 25°C. 3. Wait IDD: Only timer system active. 4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source (fosc= 4.2 MHz), all inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD -0.2 V. 6. Wait IDD is affected linearly by the OSC2 capacitance. IVE DB ELECTRICAL SPECIFICATIONS 13-2 For More Information On This Product, Go to: www.freescale.com MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 13-2. DC Electrical Characteristics (VDD = 3.3 V) (VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted) Characteristic Output Voltage ILOAD = 10.0 µA ILOAD = -10.0 µA Output High Voltage (ILOAD = -0.2 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5, TCMP (ILOAD = -1.5 mA) PC0-PC1 Output Low Voltage (ILOAD = 0.4 mA) PA0-PA7, PB5-PB7, PC2-PC7, PD5, TCMP (ILOAD = 6.0 mA) PC0-PC1 Symbol VOL VOH VOH VOH VOL VOL VIH CT OR , IN C.2 006 Min Typ — — — — Max 0.1 — — — 0.3 0.3 VDD Unit V — VDD-0.1 VDD-0.3 VDD-0.3 — — V — — V Freescale Semiconductor, Inc... I/O Ports Hi-Z Leakage Current PA0-PA7, PB5-PB7, PC0-PC2, PD5 A/D Ports Hi-Z Leakage Current PC3–PC7 Input Current RESET, IRQ, OSC1, TCAP/PD7 I/O Ports Switch Resistance (Pullup Enabled PA0-PA7) Capacitance Ports (as Input or Output) RESET, IRQ LE Supply Current Run (A/D Enabled) Wait (A/D Enabled) Wait (A/D Disabled)/Halt Stop 25°C 0°C to +70°C -40°C to +85°C -40°C to +105°C -40°C to +125°C ON Input Low Voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7, IRQ, RESET, OSC1 DU Input High Voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7, IRQ, RESET, OSC1 0.7 × VDD — V VIL VSS — 0.2 × VDD V MIC — — — — — — — — — — — TBD 1.2 0.8 0.4 1 — — — — — — — 25 TBD TBD TBD 3 TBD TBD TBD 70 ±10 ±1 ±1 TBD mA mA mA µA µA µA µA µA µA µA µA kΩ IDD SE IIL IOZ IIN RPTA COUT CIN RE ES CA AR CH IVE NOTES: 1. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range, 25°C. 3. Wait IDD: Only timer system active. 4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source (fosc= 2.0 MHz), all inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD -0.2 V. 6. Wait IDD is affected linearly by the OSC2 capacitance. DB Rev. 2.0 For More Information On This Product, Go to: www.freescale.com YF — — — — 12 8 pF ELECTRICAL SPECIFICATIONS 13-3 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.4 A/D Converter Characteristics Characteristic Resolution Absolute Accuracy (4.0 V > VRH > VDD) CT OR , IN C.2 006 Min 8 Table 13-3. A/D Converter Characteristics Max 8 ±1–1/2 VRH VDD 32 32 100 01 FF 12 12 12 VRH ±1 ±1 Unit Bit LSB V (See Note 1) Conversion Range — VRH Conversion Time (Includes Sampling Time) External Clock (XTAL) Internal RC Oscillator (ADRC = 1) Power-Up Time VSS VSS 32 — — tAD µs µs Hex Hex tAD µs pF V µA Freescale Semiconductor, Inc... Monotonicity Zero Input Reading (Vin = 0 V) Full-Scale Reading (Vin = VRH) Sample Acquisition Time (see Note 2) External Clock (XTAL) Internal RC Oscillator (ADRC = 1) Input Capacitance PC3/AN3–PC6/AN0 Analog Input Voltage Input Leakage (see Note 4) AN0–AN3 VRH Inherent (Within Total Error) DU 00 FF 12 — — VSS — — AR CH IVE DB YF RE ELECTRICAL SPECIFICATIONS 13-4 For More Information On This Product, Go to: www.freescale.com ES CA NOTES: 1. A/D accuracy may decrease proportionately as VRH is reduced below 4.0 V. 2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling. 3. tAD = tcyc if clock source is MCU. 4. The external system error caused by input leakage current is approximately equal to the product of R source and input current. LE SE MIC ON MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.5 SIOP Timing (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted) Num. Operating Frequency Master Slave 1 2 3 Cycle Time Master Slave Clock (SCK) Low Time SDO Data Valid Time SDO Hold Time SDI Setup Time SDI Hold Time Characteristic Symbol fop(m) fop(s) Min Max 0.25 0.25 4.0 — — 200 — — — Unit fop CT OR , IN C.2 006 0.25 dc 4.0 4.0 tcyc(m) tcyc(s) tcyc tv ts tho th Table 13-4. SIOP Timing (VDD = 5 V) tcyc ns ns ns ns ns 932 — 0 Freescale Semiconductor, Inc... 4 5 6 DU 100 100 NOTE: fop = 2.1 MHz maximum Num. Operating Frequency Master Slave 1 2 3 4 5 6 Cycle Time Master Slave Clock (SCK) Low Time SDO Data Valid Time SDO Hold Time SDI Setup Time SDI Hold Time Characteristic MIC (VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted) Symbol fop(m) fop(s) tcyc(m) tcyc(s) tcyc tv tho ts th Min 0.25 dc 4.0 4.0 1980 — 0 200 200 Max 0.25 0.25 4.0 — — 400 — — — Unit fop Table 13-5. SIOP Timing (VDD = 3.3 V) LE SE ON tcyc ns ns ns ns ns NOTE: fop = 1.0 MHz maximum YF RE 1 2 BIT 0 BIT 1 4 SCK DB ES CA SDO IVE BIT 6 BIT 7 6 3 CH SDI BIT 0 BIT 1 BIT 6 5 BIT 7 AR Figure 13-1. SIOP Timing Diagram ELECTRICAL SPECIFICATIONS Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 13-5 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.6 Control Timing (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted Characteristic Frequency of Operation Crystal Option External Clock Option Internal Operating Frequency Crystal (fosc ÷ 2) External Clock (fosc ÷ 2) Cycle Time Symbol fosc Min — dc — dc Max 4.2 4.2 2.1 2.1 — 100 100 — — — — 5 100 Unit MHz Table 13-6. Control Timing (VDD = 5 V) CT OR , IN C.2 006 fop MHz ns ms ms tcyc ns tcyc ns µs µs tcyc 480 — — Freescale Semiconductor, Inc... Crystal Oscillator Startup Time Stop Recovery Startup Time (Crystal Oscillator) RESET Pulse Width Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width RC Oscillator Stabilization Time A/D On Current Stabilization Time tOXOV tILCH tRL tILIH tILIL DU 1.5 125 * 90 — — ON MIC LE SE tOH, tOL tRCON tADON *The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc. (VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted Frequency of Operation Crystal Option External Clock Option Internal Operating Frequency Crystal (fosc ÷ 2) External Clock (fosc ÷ 2) Cycle Time Crystal Oscillator Startup Time Table 13-7. Control Timing (VDD = 3.3 V) CA Characteristic Symbol fosc Min — dc — dc 1000 — — 1.5 250 * 200 Max 2.0 2.0 1.0 1.0 — 100 100 — — — — Unit MHz ES RE fop tcyc tOXOV tILCH tRL tILIH tILIL tOH, tOL MHz ns ms ms tcyc ns tcyc ns Stop Recovery Startup Time (Crystal Oscillator) Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width *The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc. AR CH ELECTRICAL SPECIFICATIONS 13-6 For More Information On This Product, Go to: www.freescale.com IVE DB RESET Pulse Width, Excluding Powerup YF MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION t RL RESET IRQ 2 t ILIH 4064 t cyc Freescale Semiconductor, Inc... IRQ 3 INTERNAL CLOCK INTERNAL ADDRESS BUS ON DU CT OR , IN C.2 006 1FFE 1FFE 1FFE 1FFF 4 RESET OR INTERRUPT VECTOR FETCH Edge - Sensit ive Trigger Condition The minimum pulse width (t ILIH ) is either 125 ns (V DD = 5 V) or 250 ns (VDD = 3 V). The period t ILIL should not be less than the number of t cyc cycles it takes to execute the interr upt service routine plus 19 t cyc cycles. Level - Sensitive Trigger Condition If after ser vicing an interrupt the IRQ remains low, then the next interrupt is recognized. NORMALLY USED WITH WIRE–ORed CONNECTION OSC 1 1FFE 1FFE Figure 13-2. STOP Recovery Timing IRQ (PIN) IRQ1 • • • IRQn AR RQ (MCU) CH IVE DB Rev. 2.0 For More Information On This Product, Go to: www.freescale.com YF t ILIH Figure 13-3. External Interrupt Timing ELECTRICAL SPECIFICATIONS 13-7 RE t ILIH t ILIL ES CA LE NOTES: 1. Represents the internal clocking of the OSC1 pin. 2. IRQ pin edge–sensitive mask option. 3. IRQ pin level– and edge–sensitive mask option. 4. RESET vector address shown for timing example. SE MIC Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION VDD VDD THRESHOLD (TYPICALLY 1-2 V) SC1 PIN 4064 t cyc Freescale Semiconductor, Inc... INTERNAL CLOCK INTERNAL ADDRESS BUS INTERNAL DATA BUS 1FFE 1FFE 1FFE DU CT OR , IN C.2 006 1FFE 1FFE 1FFE 1FFF NEW PCH NEW PCL 1FFE 1FFF NEW PC NEW PC NEW PCH NEW PCL DUMMY OP CODE t VDDR Figure 13-4. Power-On Reset Timing NTERNAL DDRESS BUS NTERNAL DATA BUS 1FFE RE ES 1FFE 1FFE NTERNAL CLOCK AR CH NOTES: 1. Internal clock, internal address bus, and internal data bus signals are not available externally. 2. The next rising edge of the internal processor clock after the rising edge of RESET initiates the reset sequence. IVE RESET DB YF t RL Figure 13-5. External Reset Timing ELECTRICAL SPECIFICATIONS 13-8 For More Information On This Product, Go to: www.freescale.com CA LE SE NOTES: 1. Internal clock, internal address bus, and internal data bus signals are not available externally. 2. An internal POR reset is triggered as V rises through a threshold (typically 1-2 V). DD MIC ON MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 14 MECHANICAL SPECIFICATIONS This section describes the dimensions of the dual in-line package (DIP) and small outline integrated circuit (SOIC) MCU packages. Freescale Semiconductor, Inc... 14.1 28-Pin Plastic Dual In-Line Package (Case 710-02) DU 28 15 B 1 14 MIC ON CT OR , IN C.2 006 J DIM A B C D F G H J K L M N NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0° 15° 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0° 15° 0.020 0.040 SE M A N C L H G F D K SEATING PLANE AR CH IVE MECHANICAL SPECIFICATIONS Rev. 2.0 For More Information On This Product, Go to: www.freescale.com 14-1 DB YF RE ES CA LE Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 14.2 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) -A28 15 14X -B1 14 P 0.010 (0.25) 28X D 0.010 (0.25) M T A S B S R X 45° -T26X CT OR , IN C.2 006 M B M M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8° 0° 10.05 10.55 0.75 0.25 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 8° 0° 0.395 0.415 0.010 0.029 C G K -TSEATING PLANE Freescale Semiconductor, Inc... F DU AR CH IVE DB YF RE ES CA LE SE MIC ON J MECHANICAL SPECIFICATIONS 14-2 For More Information On This Product, Go to: www.freescale.com MC68HC0P9A Rev. 2.0 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 15 ORDERING INFORMATION This section contains instructions for ordering custom-masked ROM MCUs. 15.1 MCU Ordering Forms Freescale Semiconductor, Inc... • • • AR CH IVE DB YF Rev. 2.0 For More Information On This Product, Go to: www.freescale.com RE ES The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After making the connection, type bbs in lower-case letters. Then press the return key to start the BBS software. CA ORDERING INFORMATION 15-1 LE Customer’s application program on one of the media listed in 15.2 Application Program Media SE A copy of the customer specification if the customer specification deviates from the Motorola specification for the MCU MIC A current MCU ordering form that is completely filled out (Contact your Motorola sales office for assistance.) ON DU To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Motorola representative. Submit the following items when ordering MCUs: CT OR , IN C.2 006 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 15.2 Application Program Media • • • Macintosh®1 3 1/2-inch diskette (double-sided 800K or double-sided high-density 1.4M) MS-DOS®2 or PC-DOSTM3 3 1/2-inch diskette (double-sided 720K or double-sided high-density 1.44M) MS-DOS® or PC-DOSTM 5 1/4-inch diskette (double-sided doubledensity 360K or double-sided high-density 1.2M) Freescale Semiconductor, Inc... Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with the following information: • • • • • • • Customer name Customer part number Project or product name File name of object code Date Name of operating system that formatted diskette Formatted capacity of diskette YF On diskettes, the application program must be in Motorola’s S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. RE ES CA LE DB NOTE ORDERING INFORMATION 1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. MC68HC05P9A Rev. 2.0 15-2 For More Information On This Product, Go to: www.freescale.com AR Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all non-user ROM locations or leave all non-user ROM locations blank. Refer to the current MCU ordering form for additional requirements. Motorola may request pattern resubmission if non-user areas contain any non-zero code. CH IVE SE MIC ON DU CT OR , IN C.2 006 Please deliver the application program to Motorola in one of the following media: Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION In addition to the object code, a file containing the source code can be included. Motorola keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the file name of the source code. 15.3 ROM Program Verification Freescale Semiconductor, Inc... AR After receiving the signed listing verify form, Motorola manufactures a custom photographic mask. The mask contains the customer’s application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Motorola then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer’s user ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Motorola Quality Assurance. CH IVE DB YF 15.4 ROM Verification Units (RVUs) Rev. 2.0 For More Information On This Product, Go to: www.freescale.com RE ES Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Motorola. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask. CA To aid the customer in checking the listing verify file, Motorola will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. ORDERING INFORMATION 15-3 LE SE MIC Motorola inputs the customer’s application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain non-user ROM code, such as self-check code. Motorola sends the customer a computer printout of the listing verify file along with a listing verify form. ON DU The primary use for the on-chip ROM is to hold the customer’s application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. CT OR , IN C.2 006 If the memory map has two user ROM areas with the same address, then write the two areas in separate files on the diskette. Label the diskette with both file names. Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Freescale Semiconductor, Inc... AR CH IVE DB YF RE ES CA ORDERING INFORMATION 15-4 For More Information On This Product, Go to: www.freescale.com LE SE MIC ON DU CT OR , IN C.2 006 MC68HC05P9A Rev. 2.0 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... AR CH IVE DB YF For More Information On This Product, Go to: www.freescale.com RE ES CA LE SE MIC ON DU CT OR , IN C.2 006 Freescale Semiconductor, Inc. AR CH Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064, Japan 0120 191014 +81 2666 8080 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Freescale Semiconductor, Inc... LE CA IVE DB YF RE ES SE Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. MIC ON DU CT OR , IN C.2 006 Motorola, Inc., 1995 For More Information On This Product, Go to: www.freescale.com HC05P9AGRS/D