68HC705RC17

Freescale Semiconductor, Inc. HC705RC17GRS/D REV. 2.0 Freescale Semiconductor, Inc... General Release Specification CSIC MCU Design Center Austin, Texas For More Information On This Product, Go to: www.freescale.com NON-DISCLOSURE May 20, 1997 AGREEMENT 68HC705RC17 REQUIRED Freescale Semiconductor, Inc. General Release Specifiation REQUIRED Freescale Semiconductor, Inc... AGREEMENT NON-DISCLOSURE Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. General Release Specification For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . 15 Freescale Semiconductor, Inc... Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 31 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Section 6. Low-Power Modes . . . . . . . . . . . . . . . . . . . . 51 Section 7. Parallel Input/Output (I/O) . . . . . . . . . . . . . . 55 Section 8. Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Section 9. Carrier Modulator Transmitter (CMT) . . . . . . 65 Section 10. Phase-Locked Loop (PLL) Synthesizer . . . . 83 Section 11. EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 97 Section 13. Electrical Specifications . . . . . . . . . . . . . . 115 Section 14. Mechanical Specifications . . . . . . . . . . . 121 Section 15. Ordering Information . . . . . . . . . . . . . . . . 123 MC68HC705RC17 — Rev. 2.0 List of Sections For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. List of Sections REQUIRED NON-DISCLOSURE General Release Specification List of Sections For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Freescale Semiconductor, Inc... 1.3 1.4 Section 2. Memory 2.1 2.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3.1 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.2 EPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.3 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.3.4 Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.4 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 MC68HC705RC17 — Rev. 2.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 1.5 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.2 IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . .20 1.5.3 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.5 LPRST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.6 IRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.7 Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.8 Port B (PB0–PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.9 Port C (PC0–PC1 and PC4–PC7). . . . . . . . . . . . . . . . . . . .22 1.5.10 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.11 VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AGREEMENT 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 REQUIRED Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 3. Central Processor Unit (CPU) 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Freescale Semiconductor, Inc... AGREEMENT Section 4. Interrupts 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 External Interrupt (IRQ/Port B Keyscan). . . . . . . . . . . . . . . . . .41 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Carrier Modulator Transmitter Interrupt (CMT) . . . . . . . . . . . . .42 Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 NON-DISCLOSURE Section 5. Resets 5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Low-Power External Reset (LPRST) . . . . . . . . . . . . . . . . . . . .48 5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.5.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .49 5.5.2.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Table of Contents 5.5.2.2 5.5.2.3 5.5.2.4 5.5.3 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49 COP Watchdog Timer Considerations . . . . . . . . . . . . . . .50 Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Section 6. Low-Power Modes 6.1 6.2 6.3 6.4 6.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Low-Power Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Freescale Semiconductor, Inc... Section 7. Parallel Input/Output (I/O) 7.1 7.2 7.3 7.4 7.5 7.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Input/Output (I/O) Programming . . . . . . . . . . . . . . . . . . . . . . . .57 Section 8. Core Timer 8.1 8.2 8.3 8.4 8.5 8.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .61 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .63 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .63 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Section 9. Carrier Modulator Transmitter (CMT) 9.1 9.2 9.3 MC68HC705RC17 — Rev. 2.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Table of Contents REQUIRED 9.4 Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 9.4.1 Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 9.4.2 Carrier Generator Data Registers . . . . . . . . . . . . . . . . . . . .70 9.5 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9.5.1 Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 9.5.2 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 9.5.3 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .76 9.5.3.1 End-of-Cycle (EOC) Interrupt. . . . . . . . . . . . . . . . . . . . . .77 9.5.3.2 Modulator Control and Status Register . . . . . . . . . . . . . .78 9.5.4 Modulator Period Data Registers . . . . . . . . . . . . . . . . . . . .81 Freescale Semiconductor, Inc... AGREEMENT Section 10. Phase-Locked Loop (PLL) Synthesizer 10.1 10.2 10.3 10.4 10.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .85 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .87 Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Section 11. EPROM 11.1 11.2 11.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 NON-DISCLOSURE 11.4 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.4.1 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.4.2 Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.4.3 Mask Option Registers (MOR1 and MOR2) . . . . . . . . . . . .94 Section 12. Instruction Set 12.1 12.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Table of Contents 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Freescale Semiconductor, Inc... 12.5 12.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Section 13. Electrical Specifications 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . .118 DC Electrical Characteristics (3.3 Vdc). . . . . . . . . . . . . . . . . .119 Control Timing (3.3 Vdc and 5.0 Vdc). . . . . . . . . . . . . . . . . . .120 Section 14. Mechanical Specifications 14.1 14.2 14.3 14.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 28-Pin Plastic Dual In-Line Package (Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 MC68HC705RC17 — Rev. 2.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT 12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .102 12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .103 12.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .104 12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .106 12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 REQUIRED Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 15. Ordering Information 15.1 15.2 15.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 NON-DISCLOSURE General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 List of Figure Figure 1-1 1-2 1-3 1-4 2-1 2-2 3-1 3-2 4-1 4-2 5-1 5-2 6-1 6-2 7-1 7-2 8-1 8-2 8-3 9-1 9-2 Title Page Freescale Semiconductor, Inc... MC68HC705RC17 Memory Map . . . . . . . . . . . . . . . . . . . . .26 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .40 IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .41 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Reset and POR Timing Diagram . . . . . . . . . . . . . . . . . . . . .47 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .52 Stop/Wait Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Port B Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .60 Core Timer Control and Status Register (CTCSR) . . . . . . .61 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . .63 Carrier Modulator Transmitter Module Block Diagram . . . . .67 Carrier Generator Block Diagram . . . . . . . . . . . . . . . . . . . . .68 MC68HC705RC17 — Rev. 2.0 List of Figure For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT MC68HC705RC17 Block Diagram . . . . . . . . . . . . . . . . . . . .17 28-Pin SOIC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 28-Pin PDIP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 REQUIRED Freescale Semiconductor, Inc. List of Figure REQUIRED Figure 9-3 9-4 9-5 9-6 9-7 9-8 Title Page Freescale Semiconductor, Inc... AGREEMENT Carrier Data Register (CHR1, CLR1, CHR2, and CLR2) . . . . . . . . . . . . . . . . . .70 Modulator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .73 CMT Operation in Time Mode . . . . . . . . . . . . . . . . . . . . . . .74 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .76 Modulator Control and Status Register (MCSR) . . . . . . . . .78 Modulator Data Registers (MDR1, MDR2, and MDR3) . . . . . . . . . . . . . . . . . . . . . .81 PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Phase-Locked Loop Control Register (PLLCR) . . . . . . . . . .85 Programmer Interface to Host . . . . . . . . . . . . . . . . . . . . . . .90 Programming Register (PROG) . . . . . . . . . . . . . . . . . . . . . .91 MC68HC705RC17 Bootloader Flowchart . . . . . . . . . . . . . .92 MC68HC705RC17 Programming Circuit . . . . . . . . . . . . . . .93 Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . .94 Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . .94 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 NON-DISCLOSURE General Release Specification List of Figure For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 List of Tables Table 4-1 Title Page Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . .38 COP Watchdog Timer Recommendations . . . . . . . . . . . . . . .50 I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 RTI and COP Rates at 4.096-MHz Oscillator . . . . . . . . . . . . .62 PS1 and PS0 Speed Selects with 32.768-kHz Crystal. . . . . .86 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .102 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .103 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .105 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .106 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Freescale Semiconductor, Inc... 5-1 7-1 8-1 10-1 11-1 12-1 12-2 12-3 12-4 12-5 12-6 12-7 15-1 MC68HC705RC17 — Rev. 2.0 List of Tables For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. List of Tables REQUIRED NON-DISCLOSURE General Release Specification List of Tables For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Freescale Semiconductor, Inc... 1.3 1.4 1.2 Introduction The MC68HC705RC17 is a general-purpose, low-cost addition to the M68HC05 Family of microcontroller units (MCUs) and is suitable for remote control applications. It contains the HC05 central processing unit (CPU) core, including the 14-stage core timer with real-time interrupt (RTI), computer operating properly (COP) watchdog systems, and a programmable phase-lock loop (PLL) synthesizer. On-chip peripherals include a carrier modulator transmitter. The 16-Kbyte memory map has 15,936 bytes of user EPROM, 340 bytes of boot ROM, and 352 bytes of RAM. There are 18 input-output (I/O) lines (eight having keyscan logic and pullups) and a low-power reset pin. MC68HC705RC17 — Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 1.5 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.2 IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . .20 1.5.3 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.5 LPRST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.6 IRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.7 Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.8 Port B (PB0–PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.9 Port C (PC0–PC1 and PC4–PC7). . . . . . . . . . . . . . . . . . . .22 1.5.10 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.11 VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED The MC68HC705RC17 is available in 28-pin small outline integrated circuit (SOIC) or plastic dual in-line package (PDIP) packages. Four additional I/O lines are available for bond out in higher pin count packages. NOTE: Consult the factory for availability of higher pin count packages. 1.3 Features Features of the MC68HC705RC17 include: • • • • • • • • • • Low Cost HC05 Core 28-Pin SOIC or DIP Packages On-Chip Oscillator with 32.768-kHz Crystal/Ceramic Resonator Phase-Locked Loop (PLL) Synthesizer with Programmable Speed 15,936 Bytes of User ROM 64 Bytes of Burn-In ROM 352 Bytes of On-Chip RAM 14-Stage Core Timer with Real-Time Interrupt (RTI) and Computer Operating Properly (COP) Watchdog Circuits Carrier Modulator Transmitter Supporting Baseband, Pulse Length Modulator (PLM), and Frequency Shift Keying (FSK) Protocols Low-Power Reset Pin 18 Bidirectional I/O Lines (Four Additional I/O Lines Available for Bond Out in Higher Pin Count Packages) Programmable Pullups and Interrupt on Eight Port Pins (PB0–PB7) High-Current Infrared (IR) Drive Pin High-Current Port Pin (PC0) NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT • • • • • General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Description Features XFC VDDSYN OSC2 OSC1 VDD VSS PHASE LOCK LOOP IRQEN ÷2 INTERNAL PROCESSOR CLOCK CARRIER MODULATOR TRANSMITTER IRO PC0 DATA DIRECTION REGISTER PC1 PC4* PC5* PC6* PC7* Freescale Semiconductor, Inc... PORT C COP SYSTEM RTI SYSTEM CORE TIMER SYSTEM RESET LPRST CPU CONTROL M68HC05 CPU CPU REGISTERS IRQEN 0 IRQ 00 0 0 0 0 1 1 ACCUMULATOR INDEX REGISTER STACK POINTER ALU PA0 DATA DIRECTION REGISTER PA1 PA2 PORT A PA3 PA4 PA5 PA6 PROGRAM COUNTER 11 1H I NZ C CONDITION CODE REGISTER PB0 RAM — 352 BYTES DATA DIRECTION REGISTER PB1 KEYSCAN PULLUPS PB2 PB3 PB4 PB5 PB6 PB7 EPROM — 15,936 BYTES BOOT ROM — 340 BYTES * Marked pins are available only in higher pin count (>28) packages. Figure 1-1. MC68HC705RC17 Block Diagram MC68HC705RC17 — Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE PA7 PORT B AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED • • Power-Saving Stop and Wait Modes Programmable Options: – COP Watchdog Timer – STOP Instruction Disable – Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger – Port B Pullups for Keyscan Illegal Address Reset ROM Security • • Freescale Semiconductor, Inc... AGREEMENT NOTE: A line over a signal name indicates an active-low signal. For example, RESET is active low. 1.4 Options The options on the MC68HC705RC17 are handled with 11 EPROM bits in two separate mask option register (MOR1 and MOR 2). These options are: • • • • Eight Port B Pullups IRQ Sensitivity COP Enable/Disable STOP Enable/Disable NON-DISCLOSURE The factory will program these options in the ROM versions of this device. 1.5 Signal Description Pinout for the 28-pin small outline integrated circuit (SOIC) package is shown in Figure 1-2. Pinout for the 28-pin plastic dual in-line (PDIP) package is shown in Figure 1-3. The signals are described in the following subsections. NOTE: Consult the factory for availability of higher pin count packages. General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Description Signal Description 1.5.1 VDD and VSS Power is supplied to the microcontroller’s digital circuits using these two pins. VDD is the positive supply and VSS is ground. PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OSC1 OSC2 VDD IRQ/VPP RESET IRO VSS LPRST XFC VDDSYN PC1 PC0 PA7 PA6 Freescale Semiconductor, Inc... PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 Figure 1-2. 28-Pin SOIC Pinout PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OSC1 OSC2 VDD IRQ/VPP RESET IRO VSS LPRST XFC VDDSYN PC1 PC0 PA7 PA6 Figure 1-3. 28-Pin PDIP Pinout MC68HC705RC17 — Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED 1.5.2 IRQ/VPP (Maskable Interrupt Request) This pin supplies the EPROM with the required programming voltage. In addition, this pin serves as the input for external interrupts. Triggering sensitivity is programmable using MOR1. The options are: 1. Negative edge-sensitive triggering only 2. Both negative edge-sensitive and level-sensitive triggering The MCU completes the current instruction before it responds to the interrupt request. When IRQ goes low for at least one tILIH, a logic 1 is latched internally to signify that an interrupt has been requested. When the MCU completes its current instruction, the interrupt latch is tested. If the interrupt latch contains a logic 1 and the interrupt mask bit (I bit) in the condition code register is clear, the MCU then begins the interrupt sequence. If the option is selected to include level-sensitive triggering, the IRQ input requires an external resistor to VDD for wired-OR operation. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Section 4. Interrupts for more detail. NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT 1.5.3 OSC1 and OSC2 These pins provide control input for an on-chip clock oscillator circuit. A crystal, a ceramic resonator, or an external signal connects to these pins to provide a system clock. The oscillator frequency is two times the internal bus rate. Figure 1-4 shows the recommended circuit when using a crystal. The crystal and components should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. A ceramic resonator may be used in place of the crystal in cost-sensitive applications. Figure 1-4 (a) shows the recommended circuit for using a ceramic resonator. The manufacturer of the particular ceramic resonator being considered should be consulted for specific information. General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Description Signal Description An external clock should be applied to the OSC1 input with the OSC2 pin not connected (see Figure 1-4 (b)). This setup can be used if the user does not want to run the CPU with a crystal. NOTE: The PLL design requires a 32.768-kHz external frequency for proper operation. MCU MCU Freescale Semiconductor, Inc... 10 MΩ UNCONNECTED < EXTERNAL CLOCK 30 pF 30 pF (a) Crystal/Ceramic Resonator Oscillator Connections (b) External Clock Source Connections Figure 1-4. Oscillator Connections 1.5.4 RESET This active-low pin is used to reset the MCU to a known startup state by pulling RESET low. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See Section 5. Resets. 1.5.5 LPRST The LPRST pin is an active-low pin and is used to put the MCU into lowpower reset mode. In low-power reset mode the MCU is held in reset with all processor clocks halted. See Section 5. Resets. MC68HC705RC17 — Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT OSC1 OSC2 OSC1 OSC2 REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED 1.5.6 IRO The IRO pin is the high-current source and sink output of the carrier modulator transmitter subsystem which is suitable for driving infrared (IR) LED biasing logic. See Section 9. Carrier Modulator Transmitter (CMT). 1.5.7 Port A (PA0–PA7) These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. For detailed information on I/O programming, see Section 7. Parallel Input/Output (I/O). Freescale Semiconductor, Inc... AGREEMENT 1.5.8 Port B (PB0–PB7) These eight I/O lines comprise port B. The state of any pin is software programmable and all port B lines are configured as inputs during power-on or reset. Each port B I/O line has a mask optionable pullup for keyscan. For detailed information on I/O programming, see Section 7. Parallel Input/Output (I/O). NON-DISCLOSURE 1.5.9 Port C (PC0–PC1 and PC4–PC7) These six I/O lines comprise port C. PC0 is a high-current pin. PC4 through PC7 are available only in higher pin count (>28) packages. The state of any pin is software programmable and all port C lines are configured as input during power-on or reset. For detailed information on I/O programming, see Section 7. Parallel Input/Output (I/O). NOTE: Only two bits of port C are bonded out in 28-pin packages for the MC68HC705RC17, although port C is truly a 6-bit port. Since pins PC4–PC7 are unbonded, software should include the code to set their respective data direction register locations to outputs to avoid floating inputs. General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Description Signal Description 1.5.10 XFC This pin provides a means for connecting an external filter capacitor to the synthesizer phase-locked loop filter. (For additional information concerning this capacitor, refer to Section 10. Phase-Locked Loop (PLL) Synthesizer.) 1.5.11 VDDSYN Freescale Semiconductor, Inc... NOTE: Any unused inputs, I/O ports, and no connects should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC705RC17 do not require termination, termination is recommended to reduce the possibility of static damage. MC68HC705RC17 — Rev. 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT This pin provides a separate power connection to the PLL synthesizer which should be at the same potential as VDD. REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED NON-DISCLOSURE General Release Specification General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 2. Memory 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Freescale Semiconductor, Inc... 2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3.1 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.2 EPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.3 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.3.4 Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.4 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.2 Introduction This section describes the organization of the on-chip memory. 2.3 Memory Map The MC68HC705RC17 has a 16-Kbyte memory map consisting of user EPROM, RAM, bootloader ROM, and input/output (I/O). Figure 2-1 is a memory map for the MC68HC705RC17. Figure 2-2 is a more detailed memory map of the I/O register section. MC68HC705RC17 — Rev. 2.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Memory REQUIRED I/O 32 BYTES BOOT ROM 144 BYTES RAM 16 BYTES STACK 64 BYTES BOOT ROM 112 BYTES RAM 15 BYTES $0000 $001F $0020 I/O 32 BYTES 0000 0031 0032 PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DATA DIRECTION REGISTER $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A RAM 160 BYTES $00B0 $00BF $00C0 $00FF $0100 $0170 $0171 $0180 STACK 64 BYTES RAM 128 BYTES 0191 0192 0255 0256 0383 0384 PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER RESERVED CORE TIMER CONTROL & STATUS REG. CORE TIMER COUNTER REGISTER RESERVED Freescale Semiconductor, Inc... AGREEMENT ....... BOOT ROM MOR1 MOR2 USER VECTORS 16 BYTES BOOT MODE MEMORY MAP $3FAF $3FB0 $3FEF $3FF0 $3FF1 BOOT ROM MOR1 MOR2 USER VECTORS 16 BYTES USER MODE MEMORY MAP 16303 16304 16368 16370 RESERVED CMT CHR1 CMT CLR1 CMT CHR2 CMT CLR2 CMT MCSR CMT MDR1 CMT MDR2 CMT MDR3 RESERVED PROGRAMMING REGISTER RESERVED UNUSED UNUSED CORE TIMER VECTOR (HIGH BYTE) CORE TIMER VECTOR (LOW BYTE) CMT VECTOR (HIGH BYTE) CMT VECTOR (LOW BYTE) IRQ/ PTB KEYSCAN PULLUPS VECTOR (HIGH BYTE) IRQ/PTB KEYSCAN PULLUPS VECTOR (LOW BYTE) SWI VECTOR (HIGH BYTE) SWI VECTOR (LOW BYTE) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE) $3FFF 16383 NON-DISCLOSURE $3FFB $3FFC $3FFD $3FFE $3FFF Figure 2-1. MC68HC705RC17 Memory Map General Release Specification Memory For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 ... $3FF5 $3FF6 $3FF7 $3FF8 $3FF9 $3FFA .. $1E $1F $3FF2 ....... $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 USER EPROM 15,920 BYTES USER EPROM 15,920 BYTES Freescale Semiconductor, Inc. Memory Memory Map Addr $00 $01 $02 $03 $04 $05 Register Name Port A Data Register Port B Data Register Port C Data Register Reserved Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register PLL Control Register Timer Control and Status Register Timer Counter Register Reserved Reserved Reserved Reserved Reserved Reserved CMT Timer CHR1 CMT Timer CLR1 CMT Timer CHR2 CMT Timer CLR2 CMT Timer MCSR CMT Timer MDR1 CMT Timer MDR2 CMT Timer MDR3 Bit 7 PA7 PB7 PC7 R DDRA7 DDRB7 DDRC7 0 CTOF D7 R R R R R R IROLN IROLP 0 0 EOC MB11 MB7 SB7 6 PA6 PB6 PC6 R DDRA6 DDRB6 DDRC6 BCS RTIF D6 R R R R R R CMTPOL 0 0 0 DIV2 MB10 MB6 SB6 5 PA5 PB5 PC5 R DDRA5 DDRB5 DDRC5 0 TOFE D5 R R R R R R PH5 PL5 SH5 SL5 EIMSK MB9 MB5 SB5 4 PA4 PB4 PC4 R DDRA4 DDRB4 DDRC4 BWC RTIE D4 R R R R R R PH4 PL4 SH4 SL4 EXSPC MB8 MB4 SB4 3 PA3 PB3 2 PA2 PB2 1 PA1 PB1 PC1 Bit 0 PA0 PB0 PC0 R DDRA0 DDRB0 DDRC0 PS0 RT0 D0 R R R R R R R DDRA3 DDRB3 R DDRA2 DDRB2 R DDRA1 DDRB1 DDRC1 Freescale Semiconductor, Inc... $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 PLLON TOFC D3 R R R R R R PH3 PL3 SH3 SL3 BASE SB11 MB3 SB3 VCOTST RTFC D2 R R R R R R PH2 PL2 SH2 SL2 MODE SB10 MB2 SB2 PS1 RT1 D1 R R R R R R PH1 PL1 SH1 SL1 IE SB9 MB1 SB1 PL0 SH0 SL0 MCGEN SB8 MB0 SB0 = Unimplemented R = Reserved Figure 2-2. I/O Registers (Sheet 1 of 2) MC68HC705RC17 — Rev. 2.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE PH0 AGREEMENT $06 REQUIRED Freescale Semiconductor, Inc. Memory REQUIRED Addr $18 $19 $1A $1B $1C $1D Register Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 7 R R R R R R R R 6 R R R R R R R R 5 R R R R R R R R 4 R R R R R R R R 3 R R R R R R R R 2 R R R R R R R R 1 R R R R R R R R Bit 0 R R R R R R R R Freescale Semiconductor, Inc... AGREEMENT $1E $1F R = Reserved Figure 2-2. I/O Registers (Sheet 2 of 2) 2.3.1 EPROM The user EPROM consists of 15,936 bytes of EPROM from $0180 to $3FAF and 14 bytes of user vectors from $3FF2 to $3FFF. The bootloader ROM and vectors are located from $0020 to $00AF and $0100 to $170 in boot mode only, and from $3FB0 to $3FEF in both boot mode and burn-in mode. Ten of the user vectors, $3FF6 thorough $3FFF, are dedicated to reset and interrupt vectors. The four remaining locations, $3FF2 through $3FF5, are general-purpose user EPROM locations. The mask option registers (MOR1 and MOR2) are located at $3FF0 and $3FF1. NON-DISCLOSURE 2.3.2 EPROM Security The MC68HC705RC17 contains special circuitry to prevent accessing the EPROM in non-user mode. Emulation will not be affected by this change. Security is controlled by a security bit in the MOR register. It is intended to be programmed while the users are programming their code. This will inhibit reading of the EPROM in all modes other than user mode. General Release Specification Memory For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Memory Input/Output Programming 2.3.3 RAM The user RAM consists of 352 bytes of a shared stack area. The RAM starts at address $0020 and ends at address $017F. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. NOTE: Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. Freescale Semiconductor, Inc... 2.3.4 Bootloader ROM Addresses $0020 to $00AF, $0100 to $0170, and $3FB0 to $3FEF are reserved ROM addresses that contain the instructions for the bootloader functions. (See Section 11. EPROM.) 2.4 Input/Output Programming In user mode, 18 lines are arranged as three 8-bit I/O ports. These ports are programmable as either inputs or outputs under software control of the data direction registers. For detailed information, refer to Section 7. Parallel Input/Output (I/O). MC68HC705RC17 — Rev. 2.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Memory REQUIRED NON-DISCLOSURE General Release Specification Memory For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 3. Central Processor Unit (CPU) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Freescale Semiconductor, Inc... 3.3 3.4 3.5 3.6 3.7 3.8 3.2 Introduction This section describes the registers of the MC68HC705RC17’s central processor unit (CPU). MC68HC705RC17 — Rev. 2.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Central Processor Unit (CPU) REQUIRED 3.3 CPU Registers The MCU contains five registers as shown in Figure 3-1. The interrupt stacking order is shown in Figure 3-2. 7 A 7 X 0 ACCUMULATOR 0 INDEX REGISTER 0 PC PROGRAM COUNTER 0 1 SP CCR H I N Z C CONDITION CODE REGISTER STACK POINTER Freescale Semiconductor, Inc... AGREEMENT 13 13 0 0 0 0 0 0 7 1 Figure 3-1. Programming Model 7 1 INCREASING MEMORY ADDRESSES R E T U R N 1 1 0 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL UNSTACK NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. STACK I N T E R R U P T NON-DISCLOSURE DECREASING MEMORY ADDRESSES Figure 3-2. Stacking Order General Release Specification Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Central Processor Unit (CPU) Accumulator 3.4 Accumulator The accumulator (A) is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 7 A 0 3.5 Index Register Freescale Semiconductor, Inc... The index register (X) is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area. 7 X 0 3.6 Condition Code Register The condition code register (CCR) is a 5-bit register in which the H, N, Z, and C bits are used to indicate the results of the instruction just executed, and the I bit is used to enable or disable interrupts. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. CCR H I N Z C Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the I bit is cleared. MC68HC705RC17 — Rev. 2.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Central Processor Unit (CPU) REQUIRED Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/Borrow (C) Freescale Semiconductor, Inc... AGREEMENT When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates. 3.7 Stack Pointer The stack pointer (SP) contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the eight most significant bits are permanently set to 00000011. These eight bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 13 0 0 0 0 0 0 7 1 1 SP 0 NON-DISCLOSURE General Release Specification Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Central Processor Unit (CPU) Program Counter 3.8 Program Counter The program counter (PC) is a 13-bit register that contains the address of the next byte to be fetched. 13 PC 0 NOTE: Freescale Semiconductor, Inc... MC68HC705RC17 — Rev. 2.0 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT The HC05 CPU core is capable of addressing 16-bit locations. For this implementation, however, the addressing registers are limited to a 16Kbyte memory map. REQUIRED Freescale Semiconductor, Inc. Central Processor Unit (CPU) REQUIRED NON-DISCLOSURE General Release Specification Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 4. Interrupts 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 External Interrupt (IRQ/Port B Keyscan). . . . . . . . . . . . . . . . . .41 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Carrier Modulator Transmitter Interrupt (CMT) . . . . . . . . . . . . .42 Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Freescale Semiconductor, Inc... 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 The MCU can be interrupted four different ways: 1. Non-maskable software interrupt instruction (SWI) 2. External asynchronous interrupt (IRQ/port B keyscan) 3. Internal carrier modulator transmitter interrupt 4. Internal core timer interrupt MC68HC705RC17 — Rev. 2.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 4.2 Introduction AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED 4.3 CPU Interrupt Processing Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I bit in the CCR is clear) and the corresponding interrupt enable bit is set, the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs, the processor completes the current instruction, stacks the current CPU register state, sets the I bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. When an interrupt is to be processed, the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $3FF6 through $3FFF as defined in Table 4-1. Table 4-1. Vector Address for Interrupts and Reset Register N/A N/A N/A MCSR CTCSR Flag Name N/A N/A N/A EOC CTOF, RTIF Reset Software Interrupt External Interrupts* End-of-Cycle Interrupt Real-Time Interrupt Core Timer Overflow Interrupt CPU Interrupt RESET SWI IRQ CMT CORE TIMER Vector Address $3FFE–$3FFF $3FFC–$3FFD $3FFA–$3FFB $3FF8–$3FF9 $3FF6–$3FF7 NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT *External interrupts include IRQ and port B keyscan sources. General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Interrupts Reset Interrupt Sequence The M68HC05 CPU does not support interruptible instructions. The maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. Latency = (Longest instruction execution time + 10) x tcyc seconds An return from interrupt (RTI) instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occurs during interrupt processing. Freescale Semiconductor, Inc... 4.4 Reset Interrupt Sequence The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low-level input on the RESET pin or an internally generated RST signal causes the program to vector to its starting address, which is specified by the contents of memory locations $3FFE and $3FFF. The I bit in the condition code register is also set. The MCU is configured to a known state during this type of reset. 4.5 Software Interrupt (SWI) The SWI is an executable instruction and a nonmaskable interrupt since it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), the SWI instruction executes after interrupts that were pending before the SWI was fetched or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD. MC68HC705RC17 — Rev. 2.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED FROM RESET Y I BIT IN CCR SET? N IRQ/ PORT B KEYSCAN EXTERNAL INTERRUPTS? N INTERNAL CMT INTERRUPT? N INTERNAL CORE TIMER INTERRUPT? N Y Y Y EIMSK CLEAR? N Y CLEAR IRQ REQUEST LATCH. Freescale Semiconductor, Inc... AGREEMENT STACK PC, X, A, CCR. FETCH NEXT INSTRUCTION. NON-DISCLOSURE SET I BIT IN CC REGISTER. SWI INSTRUCTION ? N Y RTI INSTRUCTION ? N RESTORE REGISTERS FROM STACK: CCR, A, X, PC. EXECUTE INSTRUCTION. Y LOAD PC FROM APPROPRIATE VECTOR. Figure 4-1. Interrupt Processing Flowchart General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Interrupts Hardware Interrupts 4.6 Hardware Interrupts All hardware interrupts except RESET are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. The three types of hardware interrupts are explained in the following sections. 4.7 External Interrupt (IRQ/Port B Keyscan) Freescale Semiconductor, Inc... NOTE: The BIH and BIL instructions will apply to the level on the IRQ pin itself and to the output of the logic OR function with the port B IRQ interrupts. The states of the individual port B pins can be checked by reading the appropriate port B pins as inputs. The IRQ pin is one source of an external interrupt. All port B pins (PB0 through PB7) act as other external interrupt sources if the pullup/interrupt feature is enabled as specified by the user. EIMSK IRQ PIN PORT B INTERRUPT/KEYSCAN IRQ VECTOR FETCH VDD IRQ LATCH R TO IRQ PROCESSING IN CPU RST LEVEL (MOR1 OPTION) Figure 4-2. IRQ Function Block Diagram MC68HC705RC17 — Rev. 2.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE TO BIH & BIL INSTRUCTION SENSING AGREEMENT The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown in Figure 4-2. REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED When edge sensitivity is selected for the IRQ interrupt, it is sensitive to these cases: 1. Falling edge on the IRQ pin 2. Falling edge on any port B pin with pullup/interrupt enabled When edge and level sensitivity is selected for the IRQ interrupt, it is sensitive to these cases: 1. Low level on the IRQ pin Freescale Semiconductor, Inc... AGREEMENT 2. Falling edge on the IRQ pin 3. Falling edge or low level on any port B pin with pullup/interrupt enabled External interrupts also can be masked by setting the EIMSK bit in the MSCR register of the IR remote timer. See 9.5.4 Modulator Period Data Registers for details. 4.8 External Interrupt Timing If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of the IRQ source. It is then synchronized internally and serviced as specified by the contents of $3FFA and $3FFB. Either a level-sensitive and edge-sensitive trigger or an edge-sensitiveonly trigger is available via the mask programmable option for the IRQ pin. NON-DISCLOSURE 4.9 Carrier Modulator Transmitter Interrupt (CMT) A CMT interrupt occurs when the end-of-cycle flag (EOC) and the endof-cycle interrupt enable (EOCIE) bits are set in the modulator control and status register (MCSR). This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $3FF8 and $3FF9. General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Interrupts Core Timer Interrupt 4.10 Core Timer Interrupt This timer can create two types of interrupts. A timer overflow interrupt occurs whenever the 8-bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real-time interrupt occurs whenever the programmed time elapses and the enable bit RTIE is set. Either of these interrupts vectors to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF6 and $3FF7. Freescale Semiconductor, Inc... MC68HC705RC17 — Rev. 2.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED NON-DISCLOSURE General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 5. Resets 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Low-Power External Reset (LPRST) . . . . . . . . . . . . . . . . . . . .48 Freescale Semiconductor, Inc... 5.3 5.4 5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.5.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .49 5.5.2.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.5.2.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.5.2.3 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.5.2.4 COP Watchdog Timer Considerations . . . . . . . . . . . . . . .50 5.5.3 Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 The MCU can be reset from five sources: two external inputs and three internal restart conditions. The RESET and LPRST pins are inputs as shown in Figure 5-1. All the internal peripheral modules will be reset by the internal reset signal (RST). Refer to Figure 5-2 for reset timing detail. MC68HC705RC17 — Rev. 2.0 Resets For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 5.2 Introduction AGREEMENT REQUIRED Freescale Semiconductor, Inc. Resets REQUIRED 5.3 External Reset (RESET) The RESET pin is one of the two external sources of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active-low input will generate the RST signal and reset the CPU and peripherals. Termination of the external RESET input or the internal COP watchdog reset are the only reset sources that can alter the operating mode of the MCU. Freescale Semiconductor, Inc... AGREEMENT NOTE: Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified. IRQ D LATCH RESET R CLOCKED TO IRQ LOGIC MODE SELECT NON-DISCLOSURE OSC DATA ADDRESS LPRST COP WATCHDOG (COPR) CPU S D LATCH PH2 TO OTHER PERIPHERALS VDD POWER-ON RESET (POR) ILLEGAL ADDRESS (ILLADDR) RST ADDRESS Figure 5-1. Reset Block Diagram General Release Specification Resets For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc... V DD > VPOR 4 0V MC68HC705RC17 — Rev. 2.0 t CYC 3FFE 3FFF NEW PC NEW PC 3FFE 3FFE 3FFE 3FFE 3FFF NEW PC NEW PC NEW PCH NEW PCL OP CODE PCH t RL 3 PCL OP CODE OSC12 4064 tCYC INTERNAL PROCESSOR CLOCK1 INTERNAL ADDRESS BUS1 INTERNAL DATA BUS1 Freescale Semiconductor, Inc. Resets For More Information On This Product, Go to: www.freescale.com RESET NOTES: 1. Internal timing signal and bus information are not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. 4. VDD must fall to a level lower than VPOR to be recognized as a power-on reset. 5. The LPRST pin resets the CPU like the RESET pin. However, 4064 POR cycles are executed first, before the reset vector address appears on the internal address bus. (See 5.3 External Reset (RESET).) General Release Specification Resets External Reset (RESET) Figure 5-2. Reset and POR Timing Diagram NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Resets REQUIRED 5.4 Low-Power External Reset (LPRST) The LPRST pin is one of the two external sources of a reset. This external reset occurs whenever the LPRST pin is pulled below the lower threshold and remains in reset until the LPRST pin rises. This active-low input will, in addition to generating the RST signal and resetting the CPU and peripherals, halt all internal processor clocks. The MCU will remain in this low-power reset condition as long as a logic 0 remains on LPRST. When a logic 1 is applied to LPRST, processor clocks will be re-enabled with the MCU remaining in reset until the 4064 internal processor clock cycle (tcyc) oscillator stabilization delay is completed. If any other reset function is active at the end of this 4064-cycle delay, the RST signal remains in the reset condition until the other reset condition(s) end. Freescale Semiconductor, Inc... AGREEMENT 5.5 Internal Resets The three internally generated resets are the initial power-on reset function, the COP watchdog timer reset, and the illegal address detector. Termination of the external reset input, external LPRST input, or the internal COP watchdog timer are the only reset sources that can alter the operating mode of the MCU. The other internal resets do not have any effect on the mode of operation when their reset state ends. NON-DISCLOSURE 5.5.1 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor bus clock cycles (PH2) after the oscillator becomes active. The POR generates the RST signal that resets the CPU. If any other reset function is active at the end of this 4064-cycle delay, the RST signal remains in the reset condition until the other reset condition(s) ends. General Release Specification Resets For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Resets Internal Resets 5.5.2 Computer Operating Properly Reset (COPR) The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to time out, an internal reset is generated to reset the MCU. Regardless of an internal or external reset, the MCU comes out of a COP reset according to the standard rules of mode selection. The COP reset function is enabled or disabled by a mask option and is verified during production testing. 5.5.2.1 Resetting the COP Writing a 0 to the COP bit prevents a COP reset. This action resets the counter and begins the time out period again. The COP bit is bit 0 of address $3FF0. A read of address $3FF0 returns user data programmed at that location. 5.5.2.2 COP During Wait Mode The COP continues to operate normally during wait mode. The software should pull the device out of wait mode periodically and reset the COP by writing to the COPF bit to prevent a COP reset. 5.5.2.3 COP During Stop Mode When the stop enable mask option is selected, stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. When stop is executed, the COP counter will hold its current state. If a reset is used to exit stop mode, the COP counter is reset and held until 4064 POR cycles are completed at which time counting will begin. If an external IRQ is used to exit stop mode, the COP counter does not wait for the completion of the 4064 POR cycles but does count these cycles. Therefore, it is recommended that the COP is fed before executing the STOP instruction. Freescale Semiconductor, Inc... MC68HC705RC17 — Rev. 2.0 Resets For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Resets REQUIRED 5.5.2.4 COP Watchdog Timer Considerations The COP watchdog timer is active in all modes of operation if enabled by a mask option. If the COP watchdog timer is selected by a mask option, any execution of the STOP instruction (either intentionally or inadvertently due to the CPU being disturbed) causes the oscillator to halt and prevents the COP watchdog timer from timing out. If the COP watchdog timer is selected by a mask option, the COP resets the MCU when it times out. Therefore, it is recommended that the COP watchdog be disabled for a system that must have intentional uses of the wait mode for periods longer than the COP time out period. The recommended interactions and considerations for the COP watchdog timer, STOP instruction, and WAIT instruction are summarized in Table 5-1. Table 5-1. COP Watchdog Timer Recommendations IF the Following Conditions Exist: Wait Time Wait Time Less than COP Time Out Wait Time More than COP Time Out Any Length Wait Time Freescale Semiconductor, Inc... AGREEMENT THEN the COP Watchdog Timer Should Be: Enable or Disable COP by Mask Option Disable COP by Mask Option Disable COP by Mask Option NON-DISCLOSURE 5.5.3 Illegal Address An illegal address reset is generated when the CPU attempts to fetch an instruction from I/O address space ($0000 to $001F). General Release Specification Resets For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 6. Low-Power Modes 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Low-Power Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Freescale Semiconductor, Inc... 6.3 6.4 6.5 6.2 Introduction This section describes the low-power modes. 6.3 Stop Mode The STOP instruction places the MCU in its lowest power-consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation. During the stop mode, the CTCSR ($08) bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is cleared. The I bit in the CCR is cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of stop mode only by an external interrupt or RESET. Refer to Figure 6-1. NOTE: If an external interrupt is pending when stop mode is entered, then stop mode will be exited immediately. MC68HC705RC17 — Rev. 2.0 Low-Power Modes For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Low-Power Modes REQUIRED OSC11 tRL RESET IRQ2 tLIH IRQ3 tILCH 4064 tCYC Freescale Semiconductor, Inc... AGREEMENT INTERNAL CLOCK INTERNAL ADDRESS BUS 3FFE 3FFE 3FFE 3FFE 3FFF NOTES: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask option RESET OR INTERRUPT VECTOR FETCH Figure 6-1. Stop Recovery Timing Diagram NOTE: NON-DISCLOSURE The EIMSK bit of the carrier modulator transmitter MCSR (modulator control and status register) is not cleared automatically by the execution of a STOP instruction. Care should be taken to clear this bit before entering stop mode. 6.4 Wait Mode The WAIT instruction places the MCU in a low power-consumption mode, but wait mode consumes more power than stop mode. All CPU action is suspended, but the core timer, the oscillator, and any enabled module remain active. Any interrupt or reset will cause the MCU to exit wait mode. The user must shut off subsystems to reduce power consumption. Wait current specifications assume CPU operation only and do not include current consumption by any other subsystems. General Release Specification Low-Power Modes For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Low-Power Modes Wait Mode During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous states. The timer may be enabled to allow a periodic exit from wait mode. NOTE: For minimum current consumption, the phase-locked loop (PLL) should be disabled or turned off before entering wait mode. STOP WAIT Freescale Semiconductor, Inc... STOP OSCILLATOR AND ALL CLOCKS. CLEAR I BIT. OSCILLATOR ACTIVE. IR TIMER CLOCK ACTIVE. CORE TIMER CLOCK ACTIVE. PROCESSOR CLOCKS STOPPED. N LPRST OR RESET? Y LPRST OR RESET? Y N N EXTERNAL INTERRUPT (PTB KEYSCAN PULLUPS) (IRQ)? Y EXTERNAL INTERRUPT N (PTB KEYSCAN PULLUPS) (IRQ)? Y IR TIMER INTERNAL Y INTERRUPT? Y TURN ON OSCILLATOR. WAIT FOR TIME DELAY TO STABILIZE. RESTART PROCESSOR CLOCK. CORE TIMER INTERNAL INTERRUPT? Y N 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE Figure 6-2. Stop/Wait Flowchart MC68HC705RC17 — Rev. 2.0 Low-Power Modes For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE N AGREEMENT REQUIRED Freescale Semiconductor, Inc. Low-Power Modes REQUIRED 6.5 Low-Power Reset Low-power reset mode is entered when a logic 0 is detected on the LPRST pin. When in this mode (as long as LPRST is held low), the MCU is held in reset and all internal clocks are halted. Applying a logic 1 to LPRST will cause the part to exit low-power reset mode and begin counting out the 4064-cycle oscillator stabilization period. Once this time has elapsed, the MCU will begin operation from the reset vectors ($3FFE–$3FFF). NON-DISCLOSURE General Release Specification Low-Power Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 7. Parallel Input/Output (I/O) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Input/Output (I/O) Programming . . . . . . . . . . . . . . . . . . . . . . . .57 Freescale Semiconductor, Inc... 7.3 7.4 7.5 7.6 7.2 Introduction In user mode, 18 lines are arranged as one 2-bit and two 8-bit I/O ports. These ports are programmable as either inputs or outputs under software control of the data direction registers. Four extra I/O ports are available on higher pin count packages. Consult factory for availability. MC68HC705RC17 — Rev. 2.0 Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE NOTE: To avoid a glitch on the output pins, write data to the I/O port data register before writing a 1 to the corresponding data direction register. AGREEMENT REQUIRED Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED 7.3 Port A Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000 and the data direction register (DDR) is at $0004. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. Freescale Semiconductor, Inc... AGREEMENT 7.4 Port B Port B is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The address of the port B data register is $0001 and the data direction register (DDR) is at address $0005. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. Each of the port B pins has a mask programmable pullup device that can be enabled. When the pullup device is enabled, this pin will also become an interrupt pin. The edge or edge and level sensitivity of the IRQ pin will also pertain to the enabled port B pins. Care needs to be taken when using port B pins that have the pullup enabled. Before switching from an output to an input, the data should be preconditioned to a logic 1 or the I bit should be set in the condition code register to prevent an interrupt from occurring. NON-DISCLOSURE NOTE: When a port B pin is configured as an output, its corresponding keyscan interrupt is disabled, regardless of its mask option. VDD VDD DISABLED MASK OPTION (PB7PU) DDR BIT ENABLED PB7 NORMAL PORT CIRCUITRY AS SHOWN IN FIGURE 7-2 IRQEN IRQ TO INTERRUPT LOGIC FROM ALL OTHER PORT B PINS Figure 7-1. Port B Pullup Option General Release Specification Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Port C 7.5 Port C Port C is a 6-bit bidirectional port (PC0–PC1 and PC4–PC7) which does not share any of its pins with other subsystems. The port C data register is at $0002 and the data direction register (DDR) is at $0006. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. Port C pins PC4 through PC7 are available only in higher pin count (>28 pin) packages. Freescale Semiconductor, Inc... 7.6 Input/Output (I/O) Programming Port pins may be programmed as inputs or outputs under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each I/O port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0. At power-on or reset, all DDRs are cleared, which configures all pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. MC68HC705RC17 — Rev. 2.0 Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT NOTE: Only two bits of port C are bonded out in 28-pin packages for the MC68HC05RC17, although port C is truly a 6-bit port. Since pins PC4–PC7 are unbonded, software should include the code to set their respective data direction register locations to outputs to avoid floating inputs. REQUIRED Freescale Semiconductor, Inc. Parallel Input/Output (I/O) REQUIRED Table 7-1. I/O Pin Functions R/W 0 0 1 1 DDR 0 1 0 1 I/O Pin Functions The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in an output mode. The output data latch is read. Freescale Semiconductor, Inc... AGREEMENT DATA DIRECTION REGISTER BIT INTERNAL HC05 CONNECTIONS LATCHED OUTPUT DATA BIT OUTPUT I/O PIN INPUT REG BIT NON-DISCLOSURE INPUT I/O Figure 7-2. I/O Circuitry General Release Specification Parallel Input/Output (I/O) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 8. Core Timer 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .61 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .63 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .63 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Freescale Semiconductor, Inc... 8.3 8.4 8.5 8.6 8.2 Introduction The core timer for this device is a 14-stage multifunctional ripple counter. Features include timer overflow, power-on reset (POR), real-time interrupt (RTI), and COP watchdog timer. As seen in Figure 8-1, the internal peripheral clock is divided by four, and then drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the core timer counter register (CTCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt rate of the internal peripheral clock(E)/1024. This point is then followed by three more stages, with the resulting clock (E/4096) driving the realtime interrupt circuit (RTI). The RTI circuit consists of three divider stages with a one-of-four selector. The output of the RTI circuit is further divided by eight to drive the mask optional COP watchdog timer circuit. The RTI rate selector bits and the RTI and CTOF enable bits and flags are located in the timer control and status register at location $08. MC68HC705RC17 — Rev. 2.0 Core Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Core Timer REQUIRED INTERNAL BUS COP CLEAR 8 8 CTCR $09 CORE TIMER COUNTER REGISTER (CTCR) INTERNAL PERIPHERAL CLOCK (E) E ÷ 22 E ÷ 210 ÷4 E ÷ 212 POR Freescale Semiconductor, Inc... AGREEMENT 5-BIT COUNTER E ÷ 215 E ÷ 214 E ÷ 213 E ÷ 212 TCBP RTI SELECT CIRCUIT OVERFLOW DETECT CIRCUIT RTIOUT CTCSR CTOF RTIF TOFE RTIE TOFC RTFC RT1 RT0 TIMER CONTROL & $08 STATUS REGISTER NON-DISCLOSURE INTERRUPT CIRCUIT COP WATCHDOG TIMER (÷8) 23 TO INTERRUPT LOGIC TO RESET LOGIC Figure 8-1. Core Timer Block Diagram General Release Specification Core Timer For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Core Timer Core Timer Control and Status Register 8.3 Core Timer Control and Status Register The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real-time interrupt rate select bits. Figure 8-2 shows the value of each bit in the CTCSR when coming out of reset. Address: $0008 Bit 7 Read: CTOF 6 RTIF TOFE Write: Reset: 0 0 0 0 RTIE TOFC 0 RTFC 0 1 1 5 4 3 0 2 0 1 RT1 Bit 0 RT0 Freescale Semiconductor, Inc... = Unimplemented Figure 8-2. Core Timer Control and Status Register (CTCSR) CTOF — Core Timer Overflow CTOF is a read-only status bit set when the 8-bit ripple counter rolls over from $FF to $00. Clearing the CTOF is done by writing a 1 to TOFC. Writing to this bit has no effect. Reset clears CTOF. RTIF — Real-Time Interrupt Flag The real-time interrupt circuit consists of a 3-stage divider and a oneof-four selector. The clock frequency that drives the RTI circuit is E/212 (or E ÷ 4096) with three additional divider stages, giving a maximum interrupt period of 16 milliseconds at a bus rate of 2.024 MHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (one-of-four selection) stage goes active. Clearing the RTIF is done by writing a 1 to RTFC. Writing has no effect on this bit. Reset clears RTIF. TOFE — Timer Overflow Enable When this bit is set, a CPU interrupt request is generated when the CTOF bit is set. Reset clears this bit. RTIE — Real-Time Interrupt Enable When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset clears this bit. MC68HC705RC17 — Rev. 2.0 Core Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Core Timer REQUIRED TOFC — Timer Overflow Flag Clear When a 1 is written to this bit, CTOF is cleared. Writing a 0 has no effect on the CTOF bit. This bit always reads as 0. RTFC — Real-Time Interrupt Flag Clear When a 1 is written to this bit, RTIF is cleared. Writing a 0 has no effect on the RTIF bit. This bit always reads as 0. RT1 and RT0 — Real-Time Interrupt Rate Select Freescale Semiconductor, Inc... AGREEMENT These two bits select one of four taps from the real-time interrupt circuit. Refer to Table 8-1. Reset sets these two bits which selects the lowest periodic rate and gives the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the time out period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing RTI taps. Table 8-1. RTI and COP Rates at 4.096-MHz Oscillator RTI Rate 2.048-MHz Bus 2 ms 4 ms 8 ms 16 ms 212 ÷ E 213 ÷ E 214 ÷ E 215 ÷ E RT1 and RT0 00 01 10 11 Minimum COP Rates 2.048-MHz Bus (215–212)/E (216–213)/E (217–214)/E (218–215)/E 14 ms 28 ms 56 ms 112 ms NON-DISCLOSURE General Release Specification MC68HC705RC17 — Rev. 2.0 Core Timer For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Core Timer Core Timer Counter Register 8.4 Core Timer Counter Register The timer counter register is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked by the CPU clock (E/4) and can be used for various functions, including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location, thereby simulating a 16-bit (or more) counter. Address: $0009 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 Bit 0 D0 Freescale Semiconductor, Inc... = Unimplemented Figure 8-3. Core Timer Counter Register (CTCR) The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 cycles, the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer starts counting up from zero and normal device operation begins. When RESET is asserted any time during operation (other than POR and low-power reset), the counter chain is cleared. 8.5 Computer Operating Properly (COP) Reset The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 8-1. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP time out or clearing the COP is accomplished by writing a 0 to bit 0 of address $3FF0. When the COP is cleared, only the final divide-by-eight stage (output of the RTI) is cleared. MC68HC705RC17 — Rev. 2.0 Core Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Core Timer REQUIRED If the COP watchdog timer is allowed to time out, an internal reset is generated to reset the MCU. The COP remains enabled after execution of the WAIT instruction and all associated operations apply. If the STOP instruction is disabled, execution of STOP instruction causes the CPU to execute a no operation (NOP) instruction. In addition, the COP is prohibited from being held in reset. This prevents a device lock-up condition. This COP’s objective is to make it impossible for this device to become stuck or locked-up and to be sure the COP is able to rescue the part from any situation where it might entrap itself in abnormal or unintended behavior. This function is a mask option. Freescale Semiconductor, Inc... AGREEMENT 8.6 Timer During Wait Mode The CPU clock halts during wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. The COP is always enabled while in user mode. NON-DISCLOSURE General Release Specification Core Timer For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 9. Carrier Modulator Transmitter (CMT) 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Freescale Semiconductor, Inc... 9.3 9.4 Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 9.4.1 Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 9.4.2 Carrier Generator Data Registers . . . . . . . . . . . . . . . . . . . .70 9.5 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9.5.1 Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 9.5.2 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 9.5.3 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .76 9.5.3.1 End-of-Cycle (EOC) Interrupt. . . . . . . . . . . . . . . . . . . . . .77 9.5.3.2 Modulator Control and Status Register . . . . . . . . . . . . . .78 9.5.4 Modulator Period Data Registers . . . . . . . . . . . . . . . . . . . .81 9.2 Introduction The carrier modulator transmitter (CMT) module provides a means to generate the protocol timing and carrier signals for a wide variety of encoding schemes. It incorporates hardware to off-load the critical and/or lengthy timing requirements associated with code generation from the CPU, releasing much of its bandwidth to handle other tasks such as code data generation, data decompression, or keyboard scanning. The CMT does not include dedicated hardware configurations for specific protocols but is intended to be sufficiently programmable in its function to handle the timing requirements of most protocols with MC68HC705RC17 — Rev. 2.0 Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) REQUIRED minimal CPU intervention. When disabled, certain CMT registers can be used to change the state of the infrared out pin (IRO) directly. This feature allows for the generation of future protocols not readily producible by the current architecture. 9.3 Overview The module consists of carrier generator, modulator, and transmitter output blocks. The block diagram is shown in Figure 9-1. The carrier generator has a resolution of 500 ns with a 2-MHz oscillator. The user may independently define the high and low times of the carrier signal to determine both period and duty cycle. The carrier generator can generate signals with periods between 1 µs (1 MHz) and 64 µs (15.6 kHz) in steps of 500 ns. The possible duty cycle options will depend upon the number of counts required to complete the carrier period. For example, a 400-kHz signal has a period of 2.5 µs and will therefore require 5 x 500 ns counts to generate. These counts may be split between high and low times so the duty cycles available will be 20% (one high, four low), 40% (two high, three low), 60% (three high, two low) and 80% (four high, one low). For lower frequency signals with larger periods, higher resolution (as a percentage of the total period) duty cycles are possible. The carrier generator may select between two sets of high and low times. When operating in normal mode (subsequently referred to as time mode), just one set will be used. When operating in FSK (frequency shift key) mode, the generator will toggle between the two sets when instructed to do so by the modulator, allowing the user to dynamically switch between two carrier frequencies without CPU intervention. When the BASE bit in the modulator control and status register (MCSR) is set, the carrier output to the modulator is held high continuously to allow for the generation of baseband protocols. See 9.4 Carrier Generator. The modulator provides a simple method to control protocol timing. The modulator has a resolution of 4 µs with a 2-MHz oscillator. It can count system clocks to provide real-time control or it can count carrier clocks for self-clocked protocols. It can either gate the carrier onto the NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT General Release Specification Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) Overview PRIMARY/SECONDARY SELECT MODE BASE fOSC CARRIER GENERATOR CARRIER OUT MODULATOR OUT MODULATOR TRANSMITTER OUTPUT IRO PIN Freescale Semiconductor, Inc... EOC INTERRUPT ENABLE EOC FLAG MODULATOR/ CARRIER ENABLE fOSC ÷ 2 CPU INTERFACE DB AB EOC INTERRUPT Figure 9-1. Carrier Modulator Transmitter Module Block Diagram modulator output (TIME), control the logic level of the modulator output (baseband) or directly route the carrier to the modulator output while providing a signal to switch the carrier generator between high/low time register buffers (FSK). See 9.5 Modulator. The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated on to the IRO pin when the modulator/carrier generator is enabled. Otherwise, the IRO pin is controlled by the state of the IRO latch, which is directly accessible to the CPU by means of bit 7 of the carrier generator data registers CHR1 and CLR1. The IRO latch can be written to on either edge of the internal bus clock (fosc/2), allowing for IR waveforms which have a resolution of twice the bus clock frequency (fosc). See 9.4.2 Carrier Generator Data Registers. MC68HC705RC17 — Rev. 2.0 Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) REQUIRED 9.4 Carrier Generator The carrier signal is generated by counting a predetermined number of input clocks (500 ns for a 2-MHz oscillator) for both the carrier high time and the carrier low time. The period is determined by the total number of clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted. The high and low time values are user programmable and are held in two registers. An alternate set of high/low count values is held in another set of registers to allow the generation of dual frequency FSK (frequency shift keying) protocols without CPU intervention. The MCGEN bit in the MCSR must be set and the BASE bit in the MCSR must be cleared to enable carrier generator clocks. The block diagram is shown in Figure 9-2. Freescale Semiconductor, Inc... AGREEMENT SECONDARY HIGH COUNT REGISTER PRIMARY HIGH COUNT REGISTER COUNT REGISTER SELECT CONTROL =? fOSC CLOCK AND OUTPUT CONTROL MODE NON-DISCLOSURE BASE MODULATOR/ CARRIER GENERATOR ENABLE CLK CLR 6-BIT UP COUNTER PRIMARY/ SECONDARY SELECT CARRIER OUT =? SECONDARY LOW COUNT REGISTER PRIMARY LOW COUNT REGISTER Figure 9-2. Carrier Generator Block Diagram General Release Specification Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) Carrier Generator 9.4.1 Time Counter The high/low time counter is a 6-bit up counter. After each increment, the contents of the counter are compared with the appropriate high or low count value register. When this value is reached, the counter is reset and the compare is redirected to the other count value register. Assuming that the high time count compare register is currently active, a valid compare will cause the carrier output to be driven low. The counter will continue to increment and when reaching the value stored in the selected low count value register, it will be cleared and will cause the carrier output to be driven high. The cycle repeats, automatically generating a periodic signal which is directed to the modulator. The lowest frequency (maximum period) and highest frequency (minimum period) which can be generated are. fmin = fosc ÷ (2 x (26 – 1)) Hz fmax = fosc ÷ (2 x 1) Hz In the general case, the carrier generator output frequency is: fout = fosc ÷ (Highcount + Lowcount) Hz Where: 0 < Highcount < 64 and 0 < Lowcount < 64 Freescale Semiconductor, Inc... NOTE: These equations assume the DIV2 bit (bit 6) of the MCSR is clear. When the DIV2 bit is set, the carrier generator frequency will be half of what is shown in these equations. The duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. As the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts required to generate the desired carrier period. Highcount Duty Cycle = --------------------------------------------------------------Highcount + Lowcount MC68HC705RC17 — Rev. 2.0 Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) REQUIRED 9.4.2 Carrier Generator Data Registers The carrier generator contains two, 7-bit data registers: primary high time (CHR1), primary low time (CLR1); and two, 6-bit data registers: secondary high time (CHR2) and secondary low time (CLR2). Bit 7 of CHR1 and CHR2 is used to read and write the IRO latch. CHR1 Address: $0010 Bit 7 6 CMTPOL 0 5 PH5 U 4 PH4 U 3 PH3 U 2 PH2 U 1 PH1 U Bit 0 PH0 U Freescale Semiconductor, Inc... AGREEMENT Read: IROLN Write: Reset: 0 U = Unaffected CLR1 Address: $0011 Bit 7 Read: IROLP Write: Reset: 0 U = Unaffected CHR2 Address: $0012 Bit 7 Read: 0 Write: Reset: 0 U = Unaffected CLR2 Address: $0013 Bit 7 Read: 0 Write: Reset: 0 U = Unaffected 0 U U U U U U 0 SL5 SL4 SL3 SL2 SL1 SL0 6 5 4 3 2 1 Bit 0 0 U U U U U U 0 SH5 SH4 SH3 SH2 SH1 SH0 6 5 4 3 2 1 Bit 0 0 U U U U U U 0 PL5 PL4 PL3 PL2 PL1 PL0 6 5 4 3 2 1 Bit 0 NON-DISCLOSURE Figure 9-3. Carrier Data Register (CHR1, CLR1, CHR2, and CLR2) General Release Specification Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) Carrier Generator PH0–PH5 and PL0–PL5 — Primary Carrier High and Low Time Data Values When selected, these bits contain the number of input clocks required to generate the carrier high and low time periods. When operating in time mode (see 9.5.1 Time Mode), this register pair is always selected. When operating in FSK mode (see 9.5.2 FSK Mode), this register pair and the secondary register pair are alternately selected under control of the modulator. The primary carrier high and low time values are undefined out of reset. These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious results. Freescale Semiconductor, Inc... NOTE: Writing to CHR1 to update PH0–PH5 or to CLR1 to update PL0–PL5 will also update the IRO latch. When MCGEN (bit 0 in the MCSR) is clear, the IRO latch value appears on the IRO output pin. Care should be taken that bit 7 of the data to be written to CHR1 or CHL1 should contain the desired state of the IRO latch. SH0–SH5 and SL0–SL5 — Secondary Carrier High and Low Time Data Values When selected, these bits contain the number of input clocks required to generate the carrier high and low time periods. When operating in time mode (see 9.5.1 Time Mode), this register pair is never selected. When operating in FSK mode (see 9.5.2 FSK Mode), this register pair and the secondary register pair are alternately selected under control of the modulator. The secondary carrier high and low time values are undefined out of reset. These bits must be written to nonzero values before the carrier generator is enabled when operating in FSK mode. IROLN and IROLP — IRO Latch Control Reading IROLN or IROLP reads the state of the IRO latch. Writing IROLN updates the IRO latch with the data being written on the negative edge of the internal processor clock (fosc/2). Writing IROLP updates the IRO latch on the positive edge of the internal processor clock; for example, one fosc period later. The IRO latch is clear out of reset. MC68HC705RC17 — Rev. 2.0 Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) REQUIRED NOTE: Writing to CHR1 to update IROLN or to CLR1 to update IROLP will also update the primary carrier high and low data values. Care should be taken that bits 5–0 of the data to be written to CHR1 or CHL1 should contain the desired values for the primary carrier high or low data. 9.5 Modulator The modulator consists of a 12-bit down counter with underflow detection which is loaded from the modulation mark period from the mark buffer register, MBUFF. When this counter underflows, the modulator gate is closed and a 12-bit comparator is enabled which continually compares the logical complement of the contents of the (still) decrementing counter with the contents of the modulation space period register, SREG. When a match is obtained, the modulator control gate is opened again. Should SREG = 0, the match will be immediate and no space period will be generated (for instance, for FSK protocols which require successive bursts of different frequencies). When the match occurs, the counter is reloaded with the contents of MBUFF, SREG is reloaded with the contents of its buffer, SBUFF, and the cycle repeats. The MCGEN bit in the MCSR must be set to enable the modulator timer. The 12-bit MBUFF and SBUFF registers are accessed through three 8bit modulator period registers, MDR1, MDR2, and MDR3. The modulator can operate in two modes, time or FSK. In time mode the modulator counts clocks derived from the system oscillator and modulates a single-carrier frequency or no carrier (baseband). In FSK mode, the modulator counts carrier periods and instructs the carrier generator to alternate between two carrier frequencies whenever a modulation period (mark + space counts) expires. NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT General Release Specification Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) Modulator 12 BITS 0 MBUFF ÷8 CLOCK CONTROL 13-BIT DOWN COUNTER * COUNTER 12 LOAD MBUFF/SBUFF . =? SYSTEM CONTROL PRIMARY/SECONDARY SELECT MODULATOR GATE MODULATOR OUT . CARRIER OUT fOSC Freescale Semiconductor, Inc... SREG * EXTENDED SPACE EOC FLAG SET 12 MODULATOR/ CARRIER GENERATOR ENABLE EOC FLAG SBUFF 12 BITS MODULATOR CONTROL/STATUS REGISTER EOC INTERRUPT ENABLE MODE BASE * DENOTES HIDDEN REGISTER DIV2 Figure 9-4. Modulator Block Diagram 9.5.1 Time Mode When the modulator operates in time mode, the modulation mark and space periods consist of zero or an integer number of fosc ÷ 8 clocks (= 250 kHz @ 2 MHz osc). This provides a modulator resolution of 4 µs and a maximum mark and space periods of about 16 ms (each). However, to prevent carrier glitches which could affect carrier spectral purity, the modulator control gate and carrier clock are synchronized. The carrier signal is activated when the modulator gate opens. The modulator gate can only close when the carrier signal is low. (The output logic level during space periods is low). If the carrier generator is in baseband mode (BASE bit in MCSR is high), the modulator output will be at a logic 1 for the duration of the mark period and at a logic 0 for the duration of a space period. See Figure 9-5. MC68HC705RC17 — Rev. 2.0 Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED MS BIT Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) REQUIRED The mark and space time equations are: ( MBUFF + 1 ) × 8 t mark = --------------------------------------------- sec s f osc SBUFF × 8 t space = ----------------------------- sec s f osc Setting the DIV2 bit in the MCSR will double mark and space times. Freescale Semiconductor, Inc... AGREEMENT fOSC ÷ 8 CARRIER FREQUENCY MODULATOR GATE MARK SPACE MARK SPACE MARK NON-DISCLOSURE TIME MODE OUTPUT BASEBAND OUTPUT Figure 9-5. CMT Operation in Time Mode General Release Specification Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) Modulator 9.5.2 FSK Mode When the modulator operates in FSK mode, the modulation mark and space periods consist of an integer number of carrier clocks (space period can be zero). When the mark period expires, the space period is transparently started (as in time mode); however, in FSK mode the carrier switches between data registers in preparation for the next mark period. The carrier generator toggles between primary and secondary data register values whenever the modulator mark period expires. The space period provides an interpulse gap (no carrier), but if SBUFF = 0, then the modulator and carrier generator will switch between carrier frequencies without a gap or any carrier glitches (zero space). Using timing data for carrier burst and interpulse gap length calculated by the CPU, FSK mode automatically can generate a phase-coherent, dual-frequency FSK signal with programmable burst and interburst gaps. The mark and space time equations for FSK mode are: MBUFF + 1 t mark = ------------------------------- sec s f cg SBUFF t space = -------------------- sec s f cg Where fcg is the frequency output from the carrier generator, setting the DIV2 bit in the MCSR will double mark and space times. Freescale Semiconductor, Inc... MC68HC705RC17 — Rev. 2.0 Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) REQUIRED 9.5.3 Extended Space Operation In either time or FSK mode, the space period can be made longer than the maximum possible value of SBUFF. Setting the EXSPC bit in the MCSR will force the modulator to treat the next modulation period (beginning with the next load of MBUFF/SBUFF) as a space period equal in length to the mark and space counts combined. Subsequent modulation periods will consist entirely of these extended space periods with no mark periods. Clearing EXSPC will return the modulator to standard operation at the beginning of the next modulation period. To calculate the length of an extended space in time mode, use the equation: texspace = ((SBUFF1)+(MBUFF2+1+SBUFF2) +... (MBUFFn+1+SBUFFn)) x 8 fosc secs Freescale Semiconductor, Inc... AGREEMENT Where the subscripts 1, 2, ... n refer to the modulation periods that elapsed while the EXSPC bit was set. Similarly, to calculate the length of an extended space in FSK mode, use the equation: texspace = ((SBUFF1)+(MBUFF2+1+SBUFF2)+... (MBUFFn+1+SBUFFn)) fcg secs NON-DISCLOSURE Where fcg is the frequency output from the carrier generator. For an example of extended space operation, see Figure 9-6. NOTE: The EXSPC feature can be used to emulate a zero mark event. SET EXSPC CLEAR EXSPC Figure 9-6. Extended Space Operation General Release Specification Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) Modulator 9.5.3.1 End-of-Cycle (EOC) Interrupt At the end of each cycle (when the counter is reloaded from MBUFF), the end-of-cycle (EOC) flag is set. If the interrupt enable bit was previously set, an interrupt will also be issued to the CPU. The EOC interrupt provides a means for the user to reload new mark/space values into the MBUFF and SBUFF registers. As the EOC interrupt is coincident with reloading the counter, MBUFF does not require additional buffering and may be updated with a new value for the next period from within the EOC interrupt service routine (ISR). To allow both mark and space period values to be updated from within the same ISR, SREG is buffered by SBUFF. The contents written to SBUFF are transferred to the active register SREG at the end of every cycle irrespective of the state of the EOC flag. The EOC flag is cleared by a read of the modulator control and status register (MCSR) followed by an access of MDR2 or MDR3. The EOC flag must be cleared within the ISR to prevent another interrupt being generated after exiting the ISR. If the EOC interrupt is not being used (IE = 0), the EOC flag need not be cleared. Freescale Semiconductor, Inc... MC68HC705RC17 — Rev. 2.0 Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) REQUIRED 9.5.3.2 Modulator Control and Status Register The modulator control and status register (MCSR) contains the modulator and carrier generator enable (MCGEN), interrupt enable (IE), mode select (MODE), baseband enable (BASE), extended space (EXSPC), and external interrupt mask (EIMSK) control bits, divide-bytwo prescaler (DIV2) bit, and the end of cycle (EOC) status bit. Address: $0014 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 EOC DIV2 EIMSK EXSPC BASE MODE IE MCGEN 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... AGREEMENT = Unimplemented Figure 9-7. Modulator Control and Status Register (MCSR) EOC — End-Of-Cycle Status Flag 1 = End of modulator cycle (counter = SBUFF) has occurred 0 = Current modulation cycle in progress EOC is set when a match occurs between the contents of the space period register, SREG, and the down counter. This is recognized as the end of the modulation cycle. At this time, the counter is initialized with the (possibly new) contents of the mark period buffer, MBUFF, and the space period register, SREG, is loaded with the (possibly new) contents of the space period buffer, SBUFF. This flag is cleared by a read of the MCSR followed by an access of MDR2 or MDR3. The EOC flag is cleared by reset. DIV2 — Divide-by-two prescaler 1 = Divide-by-two prescaler enabled 0 = Divide-by-two prescaler disabled The divide-by-two prescaler causes the CMT to be clocked at the bus rate when enabled; 2 x the bus rate when disabled (fosc). This bit is not double buffered and so should not be set during a transmission. NON-DISCLOSURE General Release Specification Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) Modulator EIMSK — External Interrupt Mask 1 = IRQ and keyscan interrupts masked 0 = IRQ and keyscan interrupts enabled The external interrupt mask bit is used to mask IRQ and keyscan interrupts. This bit is cleared by reset. EXSPC — Extended Space Enable 1 = Extended space enabled 0 = Extended space disabled Freescale Semiconductor, Inc... BASE — Baseband Enable 1 = Baseband enabled 0 = Baseband disabled When set, the BASE bit disables the carrier generator and forces the carrier output high for generation of baseband protocols. When BASE is clear, the carrier generator is enabled and the carrier output toggles at the frequency determined by values stored in the carrier data registers. See 9.5.1 Time Mode. This bit is cleared by reset. This bit is not double buffered and should not be written to during a transmission. MODE — Mode Select 1 = CMT operates in FSK mode. 0 = CMT operates in time mode. For a description of CMT operation in time mode, see 9.5.1 Time Mode. For a description of CMT operation in FSK mode, see 9.5.2 FSK Mode. This bit is cleared by reset. This bit is not double buffered and should not be written to during a transmission. IE — Interrupt Enable 1 = CPU interrupt enabled 0 = CPU interrupt disabled A CPU interrupt will be requested when EOC is set if IE was previously set. If IE is clear, EOC will not request a CPU interrupt. MC68HC705RC17 — Rev. 2.0 Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT For a description of the extended space enable bit, see 9.5.3 Extended Space Operation. This bit is cleared by reset. REQUIRED Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) REQUIRED MCGEN — Modulator and Carrier Generator Enable 1 = Modulator and carrier generator enabled 0 = Modulator and carrier generator disabled Setting MCGEN will initialize the carrier generator and modulator and will enable all clocks. Once enabled, the carrier generator and modulator will function continuously. When MCGEN is cleared, the current modulator cycle will be allowed to expire before all carrier and modulator clocks are disabled (to save power) and the modulator output is forced low. The user should initialize all data and control registers before enabling the system to prevent spurious operation. This bit is cleared by reset. NON-DISCLOSURE General Release Specification Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) Modulator 9.5.4 Modulator Period Data Registers The 12-bit MBUFF and SBUFF registers are accessed through three 8bit registers, MDR1, MDR2, and MDR3. MDR2 and MDR3 contain the least significant eight bits of MBUFF and SBUFF respectively. MDR1 contains the two most significant nibbles of MBUFF and SBUFF. In many applications, periods greater than those obtained by eight bits will not be required. Splitting the registers up in this manner allows the user to clear MDR1 and generate 8-bit periods with just two data writes. Freescale Semiconductor, Inc... MDR1 Address: $0015 Bit 7 6 MB10 5 MB9 4 MB8 3 SB11 2 SB10 1 SB9 Bit 0 SB8 Read: MB11 Write: Reset: MDR2 Address: $0016 Bit 7 Read: MB7 Write: Reset: MDR3 Address: $0017 Bit 7 Read: SB7 Write: Reset: Unaffected by Reset SB6 SB5 SB4 SB3 SB2 SB1 SB0 6 5 4 3 2 1 Bit 0 Unaffected by Reset MB6 MB5 MB4 MB3 MB2 MB1 MB0 6 5 4 3 2 1 Bit 0 Unaffected by Reset Figure 9-8. Modulator Data Registers (MDR1, MDR2, and MDR3) MC68HC705RC17 — Rev. 2.0 Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Carrier Modulator Transmitter (CMT) REQUIRED NON-DISCLOSURE General Release Specification Carrier Modulator Transmitter (CMT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 10. Phase-Locked Loop (PLL) Synthesizer 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .85 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .87 Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Freescale Semiconductor, Inc... 10.3 10.4 10.5 10.2 Introduction The phase-locked loop (PLL) consists of a variable bandwidth loop filter, a voltage controlled oscillator (VCO), a feedback frequency divider, and a digital phase detector. The PLL requires an external loop filter capacitor (typically 0.1 µF) connected between XFC and VDDSYN. This capacitor should be located as close to the chip as possible to minimize noise. VDDSYN is the supply source for the PLL and should be bypassed to minimize noise. The VDDSYN bypass cap should be as close as possible to the chip. VDDSYN should be at the same potential as VDD. The phase detector compares the frequency and phase of the feedback frequency (tFB) and the crystal oscillator reference frequency (tREF) and generates the output, PCOMP, as shown in Figure 10-1. The output waveform is then integrated and amplified. The resultant dc voltage is applied to the voltage controlled oscillator. The output of the VCO is divided by a variable frequency divider of 128, 64, 32, or 16 to provide the feedback frequency for the phase detector. MC68HC705RC17 — Rev. 2.0 Phase-Locked Loop (PLL) Synthesizer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesizer REQUIRED VDDSYN 0.1 µF OSC1 t REF CRYSTAL OSCILLATOR PCOMP 0.1 µF XFC PLLOUT TO CLOCK GENERATION CIRCUITRY PHASE DETECT LOOP FILTER VCO CLOCK SELECT BCS tFB FREQUENCY DIVIDER Freescale Semiconductor, Inc... AGREEMENT PS1 PS0 Figure 10-1. PLL Circuit To change PLL frequencies, follow this 6-step procedure: 1. Clear BCS to enable the low frequency bus rate 2. Clear PLLON to disable the PLL and select manual high bandwidth 3. Select the speed using PS1 and PS0 4. Set PLLON to enable the PLL 5. Wait a time of 90% tPLLS for the PLL frequency to stabilize and select manual low bandwidth, wait another 10% tPLLS NON-DISCLOSURE NOTE: Typically, tPLLS equals 10 ms. 6. Set BCS to switch to the high-frequency bus rate The user cannot switch among the high speeds with the BCS bit set. Following the procedure above will prevent possible bursts of high frequency operation during the re-configuration of the PLL. Whenever the PLL is first enabled, the wide bandwidth mode is used. This enables the PLL frequency to ramp up quickly. When the output frequency is near the desired frequency, the filter is switched to the narrow bandwidth mode to make the final frequency more stable. General Release Specification Phase-Locked Loop (PLL) Synthesizer For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesizer Phase-Locked Loop Control Register 10.3 Phase-Locked Loop Control Register This read/write register contains the control bits that select the PLL frequency and enable/disable the synthesizer. Address: $0007 Bit 7 Read: 0 BCS 0 0 0 BWC 0 PLLON 1 VCOTST 1 PS1 0 PS0 1 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Write: Reset: 0 Figure 10-2. Phase-Locked Loop Control Register (PLLCR) BCS — Bus Clock Select When this bit is set, the output of the PLL is used to generate the internal processor clock. When clear, the internal bus clock is driven by the crystal (OSC1÷2). Once BCS has been changed, it may take up to 1.5 OSC1 cycles + 1.5 PLLOUT cycles to make the transition. During the transition, the clock select output will be held low and all CPU and timer activity will cease until the transition is complete. Before setting BCS, allow at least a time of tPLLS after PLLON is set. This bit should not be set unless the PLLON bit is already set on a previous instruction. Reset clears this bit. BWC — Bandwidth Control This bit selects high bandwidth control when set and low bandwidth control when clear. The low bandwidth driver is always enabled, so this bit determines whether the high bandwidth driver is on or off. When the PLL is turned on, the BWC bit should be set to 1 for a time 90% tPLLS to allow the PLL time to acquire a frequency close to the desired frequency. The BWC bit should then be cleared and software should delay for a time, 10% tPLLS, to allow the PLL time to make the final adjustments. The PLL clock cannot be used (BCS bit set). Although it is NOT prohibited in hardware, the BCS bit should not be set unless the BWC bit is cleared and the proper delay times have been followed. The PLL will generate a lower jitter clock when the BWC bit is cleared. Reset clears this bit. MC68HC705RC17 — Rev. 2.0 Phase-Locked Loop (PLL) Synthesizer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesizer REQUIRED PLLON — PLL On This bit activates the synthesizer circuit without connecting it to the control circuit. This allows the synthesizer to stabilize before it can drive the CPU clocks. When this bit is cleared, the PLL is shut off and the BCS bit cannot be set. (Setting the BCS bit would engage the disabled PLL onto the bus). Reset sets this bit. NOTE: NOTE: For minimum current consumption, disable the PLL module before entering wait mode. The PLLON bit should not be cleared unless the BCS bit has been cleared on a previous write to the register. VCOTST — VCO Test Freescale Semiconductor, Inc... AGREEMENT NOTE: This bit is intended for use by Motorola. This bit cannot be cleared in user mode. PS1 and PS0 — PLL Synthesizer Speed Select These two bits select one of four taps from the PLL to drive the CPU clocks. These bits are used in conjunction with PLLON and BCS bits in the PLL control register. Reset clears PS1 and sets PS0, choosing a bus clock frequency of 524 kHz using an external crystal of 32.768 kHz. NON-DISCLOSURE CAUTION: This bit should not be modified if BCS and PLLON in the PLLCR are both at a logic high. Table 10-1. PS1 and PS0 Speed Selects with 32.768-kHz Crystal PS1 0 0 1 1 PS0 0 1 0 1 524 kHz 1.049 MHz 2.097 MHz 4.194 MHz Reset Condition For 3.0 V ≤ VDD ≤ 5.5 V Do Not Select CPU Bus Clock Frequency (fOP) General Release Specification Phase-Locked Loop (PLL) Synthesizer For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesizer Operation During Stop Mode NOTE: For the MC68HC705RC17, the 4.194-MHz bus clock frequency should not be selected. The 2.097-MHz bus clock frequency should not be selected when running the part below VDD = 3.0 V. 10.4 Operation During Stop Mode The PLL is switched to low-frequency bus rate and is turned off temporarily when STOP is executed. Coming out of stop mode with an external IRQ, the PLL is turned on with the same configuration it had before going into STOP with the exception of BCS which is reset. Otherwise, the PLL control register is in the reset condition. Freescale Semiconductor, Inc... 10.5 Noise Immunity The MCU should be insulated as much as possible from noise in the system. These steps are recommend to help prevent problems due to noise injection. 1. The application environment should be designed so that the MCU is not near signal traces which switch often, such as a clock signal. 2. The oscillator circuit for the MCU should be placed as close as possible to the OSC1 and OSC2 pins on the MCU. 3. To minimize noise, all power pins should be filtered by using bypass capacitors placed as close as possible to the MCU. See the application note Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers, available through the Motorola Literature Distribution Center, document number AN1050/D. MC68HC705RC17 — Rev. 2.0 Phase-Locked Loop (PLL) Synthesizer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesizer REQUIRED NON-DISCLOSURE General Release Specification Phase-Locked Loop (PLL) Synthesizer For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC705RC17 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC705RC17 Section 11. EPROM 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Freescale Semiconductor, Inc... 11.3 11.4 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.4.1 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.4.2 Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.4.3 Mask Option Registers (MOR1 and MOR2) . . . . . . . . . . . .94 11.2 Introduction This section describes erasable programmable read-only memory (EPROM) programming. 11.3 EPROM The user EPROM consists of 15,920 bytes of EPROM from $0180 to $3FAF and 14 bytes of user vectors from $3FF2 to $3FFF. The bootloader ROM and vectors are located from $0020 to $00AF, $0100 to $0170, and from $3FB0 to $3FEF. Ten of the user vectors, $3FF6–$3FFF, are dedicated to reset and interrupt vectors. The four remaining locations, $3FF2–$3FF5, are general-purpose user EPROM locations. The mask option registers (MOR1 and MOR2) are located at $3FF0 and $3FF1. MC68HC705RC17 — Rev. 3.0 EPROM For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. EPROM REQUIRED 11.4 Bootloader This program (contained in an on-chip boot ROM) handles copying of user code from an external EPROM into the on-chip EPROM. The bootloader function does not have to be done from an external EPROM, but can be done from a host. 11.4.1 Bootloader Functions Two pins are used to select the bootloader function. These pins are PC1 and PB5. PC1 is normally a SYNC pin, which is used to synchronize the MCU to an off-chip source that is driving EPROM data into the MCU. The programmer/host interface is shown in Figure 11-1. DATA READ CLK (OUT) Freescale Semiconductor, Inc... AGREEMENT SYNC (IN) DATA IN Figure 11-1. Programmer Interface to Host If an external EPROM is used, this pin (PC1) must be connected to VSS. PB5 is used to select between program/verify or verify-only modes. Two other pins, PB2 and IRO, are used to drive the VERF LED and the PROG LED respectively. The programming modes are shown in Table 11-1. Table 11-1. Bootloader Functions PC1 SYNC SYNC NON-DISCLOSURE PB5 1 0 Mode Program/Verify Verify Only A program flow for the bootloader software included in the MC68HC705RC17 boot ROM is shown in Figure 11-3. The bootloader programming board shown in Figure 11-4 uses an external 12-bit counter to address the memory device containing the code to be copied. General Release Specification EPROM For More Information On This Product, Go to: www.freescale.com MC68HC705RC17 — Rev. 3.0 Freescale Semiconductor, Inc. EPROM Bootloader This counter requires a clock and a reset function. The 12-bit counter can address up to 4 Kbytes of memory, which means that two port pins have to be used to address the extra memory space. NOTE: The user code must be a one-to-one correspondence with the internal EPROM addresses. 11.4.2 Programming Register Freescale Semiconductor, Inc... Address: $001E Bit 7 6 R 0 = Reserved 5 R 0 4 R 0 3 R 0 2 LATCH 0 1 R 0 Bit 0 EPGM 0 Read: R Write: Reset: 0 R LATCH — EPROM Latch Control READ: Any time WRITE: Any time 1 = EPROM address and data bus configured for programming. Causes address and data bus to be latched when a write to EPROM is done. EPROM cannot be read if LATCH = 1. 0 = EPROM address and data bus configured for normal reads EPGM — EPROM Program Control READ: Any time WRITE: Any time security is not set 1 = VPP switched on to the EPROM array. If LATCH = 1, EPGM switches programming power to the EPROM array. 0 = Programming power switched off the EPROM array MC68HC705RC17 — Rev. 3.0 EPROM For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE Figure 11-2. Programming Register (PROG) AGREEMENT This register is used to program the EPROM array. Only the LATCH and EPGM bits are available in user mode. To program a byte of EPROM, set LATCH, then write data to the desired address, then set EPGM for tEPGM. REQUIRED Freescale Semiconductor, Inc. EPROM REQUIRED BOOT YES DDRC