68HC805K3

Freescale Semiconductor, Inc. HC805K3GRS/D REV. 1.0 Freescale Semiconductor, Inc... General Release Specification April 19, 1996 NON-DISCLOSURE CSIC System Design Group Austin, Texas For More Information On This Product, Go to: www.freescale.com AGREEMENT 68HC805K3 REQUIRED NON-DISCLOSURE General Release Specification AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 List of Sections Table of Contents ............................................................... 5 List of Figures .................................................................. 11 Freescale Semiconductor, Inc... List of Tables .................................................................... 13 Section 1. General Description ....................................... 15 Section 2. Memory Map ................................................... 27 Section 3. Central Processing Unit Core ....................... 35 Section 4. Interrupts ........................................................ 39 Section 5. Resets ............................................................. 49 Section 6. Operational Modes ......................................... 53 Section 7. Parallel Input/Output ...................................... 59 Section 8. 8-Bit Timer ...................................................... 71 Section 9. Personality EEPROM ..................................... 79 Section 10. User Program EEPROM ............................... 89 Section 11. Instruction Set .............................................. 91 Section 12. Electrical Specifications ............................ 109 Section 13. Mechnical Specifications .......................... 115 Section 14. Ordering Information ................................. 117 MC68HC805K3 — Rev. 1.0 List of Sections For More Information On This Product, Go to: www.freescale.com 3 NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Release Specification REQUIRED NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT MC68HC805K3 — Rev. 1.0 4 List of Sections For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Freescale Semiconductor, Inc... 1.3 1.4 1.5 1.6 Section 2. Memory Map 2.1 2.2 2.3 2.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .32 MC68HC805K3 — Rev. 1.0 For More Information On This Product, Go to: www.freescale.com 5 NON-DISCLOSURE 1.7 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.7.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.7.2 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.7.2.1 2-Pin Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.7.2.2 2-Pin Ceramic Resonator Oscillator. . . . . . . . . . . . . . . . .22 1.7.2.3 2-Pin RC Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.7.2.4 3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.7.2.5 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.7.3 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.7.4 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . .24 1.7.5 PA0 through PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7.6 PB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7.7 PB1/OSC3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 AGREEMENT 1.2 REQUIRED Freescale Semiconductor, Inc. General Release Specification REQUIRED 2.5 2.6 User Electronically Erasable Programmable Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Mask Option Registers (MOR) $0012 and $0013. . . . . . . . . . .32 Section 3. Central Processing Unit Core 3.1 3.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Freescale Semiconductor, Inc... AGREEMENT 3.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.3.1 Stack Pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.3.2 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Section 4. Interrupts 4.1 4.2 4.3 4.4 4.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 NON-DISCLOSURE 4.6 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.6.1 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.6.2 IRQ Status/Control Register (ISCR) . . . . . . . . . . . . . . . . . .45 4.6.3 Port Interrupts (PA0–PA3). . . . . . . . . . . . . . . . . . . . . . . . . .46 4.6.4 Timer Interrupt (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Section 5. Resets 5.1 5.2 5.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .51 5.4.3 Illegal Address Reset (ILADR) . . . . . . . . . . . . . . . . . . . . . .51 MC68HC805K3 — Rev. 1.0 6 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Section 6. Operational Modes 6.1 6.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.3.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.3.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 6.3.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.3.4 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . .57 Freescale Semiconductor, Inc... Section 7. Parallel Input/Output 7.1 7.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 7.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.3.2 Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . .61 7.3.3 Port A Pulldown Inhibit Register . . . . . . . . . . . . . . . . . . . . .61 7.3.4 Port A LED Drive Capability . . . . . . . . . . . . . . . . . . . . . . . .62 7.3.5 Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .62 7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 7.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 7.4.2 Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . .65 7.4.3 Port B Pulldown Inhibit Register . . . . . . . . . . . . . . . . . . . . .65 7.4.4 Port B with 3-Pin RC Oscillator . . . . . . . . . . . . . . . . . . . . . .66 7.5 I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 7.5.1 Pin Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 7.5.2 Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.5.3 Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.5.4 I/O Pin Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.5.5 I/O Pin Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 MC68HC805K3 — Rev. 1.0 For More Information On This Product, Go to: www.freescale.com 7 NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Release Specification REQUIRED Section 8. 8-Bit Timer 8.1 8.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.3 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.3.1 Timer Counter Register (TCNTR) $09 . . . . . . . . . . . . . . . .73 8.3.2 Timer Status/Control Register (TSCR) $08. . . . . . . . . . . . .74 8.4 8.5 8.6 COP Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Operating During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 Operating During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .77 Freescale Semiconductor, Inc... AGREEMENT Section 9. Personality EEPROM 9.1 9.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3 PEEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.3.1 PEEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . .81 9.3.2 PEEPROM Status/Control Register (PESCR) . . . . . . . . . .82 9.4 9.5 PEEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 PEEPROM Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 NON-DISCLOSURE Section 10. User Program EEPROM 10.1 10.2 10.3 10.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 MC68HC805K3 — Rev. 1.0 8 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Section 11. Instruction Set 11.1 11.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Freescale Semiconductor, Inc... 11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 11.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . .96 11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .97 11.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .98 11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .100 11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .111 3.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .112 5.0 Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.0 Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 MC68HC805K3 — Rev. 1.0 For More Information On This Product, Go to: www.freescale.com 9 NON-DISCLOSURE Section 12. Electrical Specifications AGREEMENT 11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 REQUIRED Freescale Semiconductor, Inc. General Release Specification REQUIRED Section 13. Mechnical Specifications 13.1 13.2 13.3 13.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Dual-In-Line Package (Case 648) . . . . . . . . . . . . . . . . . . . . .116 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .116 Section 14. Ordering Information Freescale Semiconductor, Inc... AGREEMENT 14.1 14.2 14.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 NON-DISCLOSURE MC68HC805K3 — Rev. 1.0 10 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 List of Figures Figure 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 3-1 4-1 4-2 4-3 4-4 5-1 6-1 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 Title Page Freescale Semiconductor, Inc... MC68HC805K3 Single-Chip Mode Memory Map.................28 MC68HC805K3 I/O Registers Memory Map ........................29 MC68HC805K3 I/O Registers $0000–$000F .......................30 MC68HC805K3 I/O Registers $0010–$001F .......................31 Mask Option Register...........................................................32 M68HC05 Programming Model ............................................36 Interrupt Processing Flowchart.............................................41 Interrupt Stacking Order .......................................................42 IRQ Function Block Diagram................................................43 IRQ Status/Control Register.................................................45 Reset Block Diagram............................................................50 Stop/Halt/Wait Flowcharts ....................................................55 Port A I/O Circuitry ...............................................................60 Port A Pulldown Inhibit Register (PDRA) .............................62 Port B I/O Circuitry ...............................................................64 Port B Pulldown Inhibit Register (PDRB) .............................65 Timer Block Diagram............................................................72 Timer Counter Register ........................................................73 Timer Status/Control Register ..............................................74 COPR Watchdog Timer Location .........................................76 MC68HC805K3 — Rev. 1.0 For More Information On This Product, Go to: www.freescale.com 11 NON-DISCLOSURE AGREEMENT MC68HC805K3 Pin Assignments ........................................18 MC68HC805K3 Block Diagram ............................................19 Oscillator Connections .........................................................21 REQUIRED Freescale Semiconductor, Inc. General Release Specification REQUIRED Figure 9-1 9-2 9-3 Title Page Personality EEPROM Block Diagram...................................80 PEBSR Select Register........................................................81 PESCR Status/Control Register...........................................82 NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT MC68HC805K3 — Rev. 1.0 12 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 List of Tables Table 4-1 Title Page Vector Addresses for Interrupts and Reset ..........................40 Port A Pin Functions.............................................................68 PB0 Pin Functions................................................................68 PB1/OSC3 Pin Functions .....................................................69 RTI Rates and COP Reset Times ........................................75 Software to Read PEEPROM...............................................83 Register/Memory Instructions...............................................96 Read-Modify-Write Instructions ............................................97 Jump and Branch Instructions..............................................99 Bit Manipulation Instructions ..............................................100 Control Instructions ............................................................101 Instruction Set Summary ....................................................102 Opcode Map.......................................................................108 Freescale Semiconductor, Inc... 7-1 7-2 7-3 8-1 9-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 MC68HC805K3 — Rev. 1.0 For More Information On This Product, Go to: www.freescale.com 13 NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Release Specification REQUIRED NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT MC68HC805K3 — Rev. 1.0 14 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 1. General Description 1.1 Contents Freescale Semiconductor, Inc... 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.4 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.6 MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.7 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.7.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.7.2 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.7.2.1 2-Pin Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.7.2.2 2-Pin Ceramic Resonator Oscillator. . . . . . . . . . . . . . . . .22 1.7.2.3 2-Pin RC Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.7.2.4 3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.7.2.5 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.7.3 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.7.4 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . .24 1.7.5 PA0 through PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7.6 PB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.7.7 PB1/OSC3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.2 Introduction The low-cost MC68HC805K3 microcontroller is a member of the M68HC805 Family of microprocessors. This device has 64 bytes of user RAM, 128 bits of personality electronically erasable programmable ROM (PEEPROM), and 928 bytes of user EEPROM. This device is available in the 16-pin plastic dual in-line package (PDIP) and 16-pin small outline integrated circuit (SOIC) package. A functional block diagram of the MC68HC805K3 is shown in Figure 1-2. MC68HC805K3 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. General Release Specification 1.3 Features • • • • • Low-Cost HC05 Core 16-Pin PDIP or SOIC Package 928 Bytes of User EEPROM (Including Eight Bytes of User Vectors) 64 Bytes of User RAM 128 Bits of Personality EEPROM (Not Memory Mapped) Programmed using User Software or during User EEPROM Programming On-Chip Charge Pump for In-Circuit Programming of the Personality EEPROM at 3.0 to 5.5 Vdc. 8-Bit Free-Running Timer 4-Stage Selectable Real-Time Interrupt Generator 10 Bidirectional Input/Output (I/O) Lines Including: – 8 mA Sink Capability on Four I/O Pins (PA7–PA4) – Mask Option Register Bit for Software Programmable Pulldowns on All I/O Pins – Mask Option Register Bit for Port Interrupts on Four I/O Pins (PA3–PA0) (Keyboard Scan Feature) • • • IRQ Interrupt Hardware Mask, Flag Bit, and Request Bit Mask Option Register Bit for Sensitivity on IRQ Interrupt (Edgeand Level-Sensitive or Edge-Sensitive Only) On-Chip Oscillator (Mask Option Register Bits for Crystal/Ceramic Resonator Oscillator with Internal 2 MΩ Resistor, and 2-Pin or 3Pin Resistor Capacitor (RC) Oscillator) Mask Option Register Bit for Reduced Startup Delay Time with RC Oscillator Options Mask Option Register Bit for Computer Operating Properly (COP) Watchdog System Power-Saving Stop and Wait Mode Instructions Features Freescale Semiconductor, Inc... • • • • • • • MC68HC805K3 — Rev. 1.0 16 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Mask Option Register • • • • Mask Option Register Bit to Convert STOP Instruction to Halt Mode Illegal Address Reset Internal Steering Diode and Pullup Resistor on RESET Pin to VDD Internal RESET Pin Pulldown from COP Watchdog and ILADR NOTE: A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. Any reference to voltage, current, or frequency specified in the following sections refers to the nominal values. The exact values and their tolerance or limits are specified in Section 12. Electrical Specifications. Freescale Semiconductor, Inc... 1.4 Mask Option Register The MC68HC805K3 contains these nine programmable options: 1. COP Watchdog Timer (Enable or Disable) 2. IRQ Triggering (Edge-Sensitive or Edge- and Level-Sensitive) 3. Port A Interrupts (Enable or Disable) 4. Port Software Programmable Pulldowns (Enable or Disable) 5. STOP Instruction (Enable or Disable) 6. Oscillator Type (Crystal/Ceramic Resonator or RC) 7. RC Oscillator Type (2-Pin or 3-Pin) 8. RC Oscillator Startup Delay (4064 or 16 fOP Cycles) 9. User EEPROM and PEEP Security (Enable or Disable) NOTE: The startup delay of 16 fOP cycles and the crystal/ceramic resonator oscillator should not be selected together. MC68HC805K3 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com 17 Freescale Semiconductor, Inc. General Release Specification 1.5 Pin Assignments The MC68HC805K3 is available in 16-pin SOIC and PDIP packages. The pin assignments for these packages are shown in Figure 1-1. Pin Assignments RESET 1 16 OSC1 PB1/OSC3 2 15 OSC2 Freescale Semiconductor, Inc... IRQ 16-PIN PDIP PACKAGE PB0 3 14 VSS VDD PA7 4 13 PA0 5 12 PA1 6 11 PA6 PA2 7 10 PA5 PA3 8 9 PA4 RESET PB1/OCS3 PB0 IRQ PA0 PA1 PA2 PA3 1 16-PIN SOIC PACKAGE 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OSC1 OSC2 VSS VDD PA7 PA6 PA5 PA4 Figure 1-1. MC68HC805K3 Pin Assignments MC68HC805K3 — Rev. 1.0 18 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification MCU Structure 1.6 MCU Structure The overall block diagram of the MC68HC805K3 is shown in Figure 1-2. OSC 1 OSC 2 SELECTABLE OSCILLATOR ÷2 8-BIT TIMER SYSTEM Freescale Semiconductor, Inc... VSS VDD WATCHDOG & ILLEGAL ADDRESS DETECT RESET CPU CONTROL 68HC05 CPU ALU DATA DIRECTION REG ACCUM IRQ CPU REGISTERS INDEX REGISTER 0 0 0 0 0 0 0 0 1 1 1 STK PTR PROGRAM COUNTER COND CODE REGISTER 1 1 1 H I N Z C PORT B PB1/OSC3 PB0 PA7 * DATA DIRECTION REGISTER PA6 * PA5 * PORT A PA4 * PA3 ** PA2 ** PA1 ** PA0 ** SRAM — 64 BYTES ON-CHIP CHARGE PUMP USER EEPROM — 928 BYTES MASK OPTION REGISTER (MOR) — 10 BITS ON-CHIP CHARGE PUMP PERSONALITY EEPROM — 128 BITS * 8 mA Sink Capability ** IRQ Interrupt Capability Figure 1-2. MC68HC805K3 Block Diagram MC68HC805K3 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com 19 Freescale Semiconductor, Inc. General Release Specification 1.7 Functional Pin Description The following paragraphs give a description of the general function of each pin. Functional Pin Description 1.7.1 VDD and VSS Power is supplied to the MCU through VDD and VSS. VDD is the positive supply and VSS is ground. The MCU operates from a single power supply. Rapid signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with high-frequency characteristics that are positioned as close to the MCU as possible. Freescale Semiconductor, Inc... 1.7.2 OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the 2-pin on-chip oscillator. The OSC1 and OSC2 pins also can be used in conjunction with the PB1/OSC3 pin to create a more stable 3-pin RC oscillator. The OSC1, OSC2, and PB1/OSC3 pins can accept these sets of components: 1. A crystal, as shown in Figure 1-3(a) 2. A ceramic resonator, as shown in Figure 1-3(a) 3. An external resistor and capacitor using two pins, as shown in Figure 1-3(b) 4. An external resistor and capacitor using three pins, as shown in Figure 1-3(c) 5. An external clock signal, as shown in Figure 1-3(d) The frequency, fosc, of the oscillator or external clock source is divided by two to produce the internal operating frequency fop. The oscillator type is selected by two mask option register bits. MC68HC805K3 — Rev. 1.0 20 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Functional Pin Description 1.7.2.1 2-Pin Crystal Oscillator The circuit in Figure 1-3(a) shows a typical 2-pin oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’s recommendations should be followed, since the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately 2 MΩ is provided between OSC1 and OSC2 when the crystal/ceramic resonator oscillator option is used. Freescale Semiconductor, Inc... MCU 2 MΩ (MASK OPTION) OSC1 OSC2 OSC1 MCU OSC2 * Starting value only. Follow crystal 36 pF* 36 pF* supplier’s recommendations regarding component values that will provide reliable startup and maximum stability. R C (a) 2-Pin Crystal or Ceramic Resonator Connections (b) 2-Pin RC Oscillator Connections MCU MCU OSC1 OSC2 R PB1/OSC3 C OSC1 OSC2 UNCONNECTED EXTERNAL CLOCK (c) 3-Pin RC Oscillator Connections (d) External Clock Source Connection Figure 1-3. Oscillator Connections MC68HC805K3 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com 21 Freescale Semiconductor, Inc. General Release Specification Functional Pin Description 1.7.2.2 2-Pin Ceramic Resonator Oscillator In cost-sensitive applications, a ceramic resonator can be used instead of the crystal. The circuit in Figure 1-3(a) is for a ceramic resonator also. The resonator manufacturer’s recommendations should be followed, since the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately 2 MΩ is provided between OSC1 and OSC2 for the crystal/ceramic resonator oscillator mask option register bit. 1.7.2.3 2-Pin RC Oscillators The 2-pin RC oscillator configuration can be used for very low-cost applications. With this option, a resistor must be connected between the two oscillator pins and a capacitor must be connected from the OSC1 pin to VSS, as shown in Figure 1-3(b). The signal on the OSC2 pin is a square wave and the signal on the OSC1 pin approximates a triangular wave. The 2-pin RC oscillator is selected by programming bit 5 ("RC") of the mask option register located at $0012. Bit 6 ("Pin 3") should NOT be programmed when using the 2-pin oscillator. The 2-pin RC oscillator is optimized for operation at 500 kHz. This oscillator can be used at higher or lower frequencies with degraded accuracy over temperature, supply voltage, and/or device processing variations. The internal startup resistor of approximately 2 MΩ is not connected between OSC1 and OSC2 when the 2-pin RC oscillator mask option register bit is selected. Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 22 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Functional Pin Description 1.7.2.4 3-Pin RC Oscillator Another low cost, but more accurate, type of RC oscillator is the 3-pin configuration utilizing the PB1/OSC3 pin. With this option, a resistor must be connected between the OSC1 and OSC2 pins and a capacitor must be connected between the OSC1 and PB1/OSC3 pins, as shown in Figure 1-3(c). This 3-pin RC oscillator is more accurate than the 2-pin RC oscillator with respect to temperature, supply voltage, and/or device processing variations. The signal on the OSC2 and PB1/OSC3 pins is a square wave and the signal on the OSC1 pin approximates a triangular wave. Selection of the 3-bit RC oscillator requires programming two bits in the mask option register located at $0012. Bit 5 ("RC"), when programmed, enables the RC oscillator. Bit 6 ("Pin 3"), when programmed along with bit 5, selects the 3-pin oscillator configuration. The 3-pin RC oscillator is optimized for operation at 500 kHz. This oscillator can be used at higher or lower frequencies with degraded accuracy over temperature, supply voltage, and/or device processing variations. The internal startup resistor of approximately 2 MΩ is not connected between OSC1 and OSC2 when the 3-pin RC oscillator mask option register bit is selected. The typical external components for a 500kHz oscillator are a 20-kΩ resistor and a 25- to 30-pF capacitor. Freescale Semiconductor, Inc... NOTE: Capacitors used with the RC oscillators should have minimal leakage. Electrolytic or tantalum capacitors should not be used because they degrade the temperature performance of the oscillator due to excessive variation in their leakage. 1.7.2.5 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(d). This configuration is possible regardless of whether the oscillator is set up for crystal/ceramic resonator, 2-pin RC, or 3-pin RC operation. However, if the 3-pin RC oscillator is selected, the PB1/OSC3 pin also must be left unconnected. MC68HC805K3 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com 23 Freescale Semiconductor, Inc. General Release Specification 1.7.3 Reset (RESET) This pin can be used as an input to reset the MCU to a known startup state by pulling the pin to the low state. The RESET pin contains a steering diode to discharge any voltage on the pin to VDD when the power is removed. The RESET pin contains an internal pullup resistor to VDD of approximately 100 kΩ to allow the RESET pin to be left unconnected for low-power applications. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. Functional Pin Description Freescale Semiconductor, Inc... The RESET pin has an internal pulldown device that pulls the RESET pin low when there is an internal COP watchdog or an illegal address reset. Refer to Section 5. Resets. 1.7.4 Maskable Interrupt Request (IRQ) The IRQ input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function has a mask option register bit to select either negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If the option is selected to include level-sensitive triggering, the IRQ pin requires an external resistor to VDD if “wired-OR” operation is desired. If the IRQ pin is not used, it must be tied to the VDD supply. NOTE: Each of the PA0 through PA3 I/O pins can be connected through an OR gate to the IRQ interrupt function by a common mask option. This capability allows keyboard scan applications where the transitions or levels on the I/O pins behave the same as the IRQ pin, except that the logic level is inverted. The edge or level sensitivity selected by the mask option register bit for the IRQ pin also applies to the I/O pins ORed to create an IRQ signal. The IRQ pin contains an internal Schmitt trigger to improve noise immunity. For more details, see Section 4. Interrupts. MC68HC805K3 — Rev. 1.0 24 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Functional Pin Description 1.7.5 PA0 through PA7 These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. The four upper-order I/O pins (PA4 through PA7) are capable of sinking higher currents. The four lower-order I/O pins (PA0 through PA3) can be connected via an internal OR gate to the IRQ interrupt function by a mask option register bit. All the port A pins can have software programmable pulldown devices provided by another mask option bit. See Section 7. Parallel Input/Output for more details on the I/O ports. Freescale Semiconductor, Inc... 1.7.6 PB0 The state of the PB0 pin is software programmable and is configured as an input during power-on or reset. This pin can have a software programmable pulldown device provided by a mask option register bit. See Section 7. Parallel Input/Output for more details on the I/O ports. 1.7.7 PB1/OSC3 The state of the PB1/OSC3 pin is software programmable and is configured as an input during power-on or reset except when the 3-pin RC oscillator configuration is selected by a pair of mask option register bits. This pin can have a software programmable pulldown device provided by a mask option. See Section 7. Parallel Input/Output for more details on the I/O ports. MC68HC805K3 — Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com 25 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 26 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 2. Memory Map 2.1 Contents Freescale Semiconductor, Inc... 2.2 2.3 2.4 2.5 2.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .32 User Electronically Erasable Programmable Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Mask Option Registers (MOR) $0012 and $0013. . . . . . . . . . .32 MC68HC805K3 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com 27 Freescale Semiconductor, Inc. General Release Specification 2.2 Introduction The MC68HC805K3 has several input/output (I/O) features, 64 bytes of user read-only memory (RAM), 128 bits of personality user electronically erasable programmable read-only memory (PEEPROM), and 928 bytes of user EEPROM, which are all active in the single-chip mode as shown in Figure 2-1. Introduction $0000 Freescale Semiconductor, Inc... $001F $0020 I/O 32 BYTES SEE FIGURE 2-2 0000 0031 0032 USER EEPROM 160 BYTES $00BF $00C0 $00DF $00E0 $00FF $0100 0191 0192 0223 0224 0255 0256 USER RAM 64 BYTES STACK 32 BYTES USER EEPROM 760 BYTES * * $0100 TO $03F7 INCLUDES COP RESET ADDRESS TIMER VECTOR (HIGH BYTE) TIMER VECTOR (LOW BYTE) IRQ VECTOR (HIGH BYTE) $03F8 $03F9 $03FA $03FB $03FC $03FD $03FE $03FF $03F0 $03F7 $03F8 COP WATCHDOG TIMER 1008 1016 IRQ VECTOR (LOW BYTE) SWI VECTOR (HIGH BYTE) SWI VECTOR (LOW BYTE) RESET VECTOR (HIGH BYTE) USER VECTORS EEPROM 8 BYTES $03FF 1023 RESET VECTOR (LOW BYTE) Figure 2-1. MC68HC805K3 Single-Chip Mode Memory Map MC68HC805K3 — Rev. 1.0 28 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification I/O and Control Registers 2.3 I/O and Control Registers The I/O and status/control registers reside in locations $0000–$001F. The overall organization of these registers is shown in Figure 2-2. The bit assignments for each register are shown in Figure 2-3 and Figure 2-4. Reading unimplemented bits returns unknown states, and writing to unimplemented bits has no effect. Freescale Semiconductor, Inc... PORT A DATA REGISTER PORT B DATA REGISTER UNIMPLEMENTED (2) PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER UNIMPLEMENTED (2) TIMER STATUS & CONTROL REGISTER TIMER COUNTER REGISTER IRQ STATUS & CONTROL REGISTER UNIMPLEMENTED (3) PEEPROM BIT SELECT REGISTER PEEPROM STATUS & CONTROL REGISTER PORT A PULLDOWN REGISTER PORT B PULLDOWN REGISTER MOR REGISTER 1 MOR REGISTER 2 RESERVED UNIMPLEMENTED (10) RESERVED $0000 $0001 $0004 $0005 $0008 $0009 $000A $000E $000F $0010 $0011 $0012 $0013 $0014 $001F Figure 2-2. MC68HC805K3 I/O Registers Memory Map MC68HC805K3 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com 29 Freescale Semiconductor, Inc. General Release Specification I/O and Control Registers Addr $0000 $0001 $0002 $0003 Name Port A Data, PORTA Port B Data, PORTB Unimplemented Unimplemented Port A Data Direction, DDRA Port B Data Direction, DDRB Unimplemented Unimplemented Timer Status/Control, TSCR Timer Counter, TCNTR IRQ Status/Control, ISCR Unimplemented Unimplemented Unimplemented R/W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 PA7 0 6 PA6 0 5 PA5 0 4 PA4 0 3 PA3 0 2 PA2 0 1 PA1 PB1 Bit 0 PA0 PB0 Freescale Semiconductor, Inc... $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F DDRA7 0 DDRA6 0 DDRA5 0 DDRA4 0 DDRA3 0 DDRA2 0 DDRA1 DDRB1 DDRA0 DDRB0 TOF TCR7 RTIF TCR6 0 TOIE TCR5 0 RTIE TCR4 0 R 0 TOFR TCR3 IRFQ 0 RTIFR TCR2 0 RT1 TCR1 0 IRQR RT0 TCR0 0 IRQE Personality EEPROM Bit Select, R PEBSR W Personality EEPROM R Status/Control, PESCR W PEB7 PEDATA PEB6 PEB5 PEB4 PEB3 CPEN PEB2 CPCLK PDB1 0 PDB0 PEPCZF PEBULK PEPGM PEBYTE = Unimplemented R = Reserved Figure 2-3. MC68HC805K3 I/O Registers $0000–$000F MC68HC805K3 — Rev. 1.0 30 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification I/O and Control Registers Addr $0010 $0011 $0012 $0013 Name Port A Pulldown Inhibit, PDRA Port B Pulldown Inhibit, PDRB MOR1 Register MOR2 Register Reserved Unimplemented R/W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 PDIA7 6 PDIA6 5 PDIA5 4 PDIA4 3 PDIA3 2 PDIA2 1 PDIA1 PDIB1 Bit 0 PDIA0 PDIB0 COPEN SBIT0 RCSTD PIN3 RC SWAIT SWPDI PIRQ LEVIRQ SBIT1 Freescale Semiconductor, Inc... $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F R R R R R R R R Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Reserved R R R R R R R R = Unimplemented R = Reserved Figure 2-4. MC68HC805K3 I/O Registers $0010–$001F MC68HC805K3 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com 31 Freescale Semiconductor, Inc. General Release Specification Random-Access Memory (RAM) 2.4 Random-Access Memory (RAM) The total RAM consists of 64 bytes (including the stack) at locations $00C0 through $00FF. The stack pointer can access 32 locations from $00E0 to $00FF. The stack begins at address $00FF and proceeds down to $00E0. Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. Freescale Semiconductor, Inc... 2.5 User Electronically Erasable Programmable Read-Only Memory A total of 928 bytes of user EEPROM is on chip. This includes 160 bytes in page zero from locations $0020 through $00BF, 760 bytes of user EEPROM with locations $0100 through $03F7 for user program storage, and 8 bytes for user vectors at locations $03F8 through $03FF. 2.6 Mask Option Registers (MOR) $0012 and $0013 The mask option registers consist of 10 EEPROM bits located at $0012 and $0013. These registers hold the option bits for the interrupt sensitivity, COP enable/disable, enable pulldowns/interrupt on port A and port B, interrupts via the lower four bits of port A, STOP instruction as HALT, oscillator type, and security. When in the erased state, the EEPROM cells will read as logic zeros. These registers are refreshed at a rate of 1 ms (typical) using an internal ring oscillator. During STOP and MOR programming, the MOR1 and MOR2 will not be refreshed. $0012 Read: Write: $0013 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 RCSTD PIN3 RC HALT SWPDI PIRQ LEVIRQ COPEN SBIT1 SBIT0 = Unimplemented Figure 2-5. Mask Option Register MC68HC805K3 — Rev. 1.0 32 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Mask Option Registers (MOR) $0012 and $0013 COPEN — COP Enable/Disable READ: Any time WRITE: In user mode, writing has no effect. 1 = The COP is enabled 0 = The COP is disabled (erased state) LEVIRQ — Interrupt Request Option READ: Any time WRITE: In user mode, writing has no effect. 1 = The IRQ pin is edge and level sensitive 0 = The IRQ pin is edge sensitive (erased state) PIRQ — Port A IRQ Enable READ: Any time. WRITE: In user mode, writing has no effect. 1 = PA3 through PA0 enabled as external interrupt sources 0 = PA3 through PA0 not enabled as external interrupt sources (erased state) SWPDI — Software Pulldown Inhibit READ: Any time WRITE: In user mode, writing has no effect. 1 = The software pulldown is disabled 0 = The software pulldown is enabled (erased state) HALT — STOP Conversion to Halt Mode READ: Any time WRITE: In user mode, writing has no effect. 1 = The STOP instruction is converted to HALT instruction 0 = STOP instruction is not converted to HALT instruction (erased state) Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 Memory Map For More Information On This Product, Go to: www.freescale.com 33 Freescale Semiconductor, Inc. General Release Specification RC — RC Oscillator READ: Any time WRITE: In user mode, writing has no effect. 0 = Oscillator configured for external crystal, ceramic resonator, or clock source (erased state) 1 = Oscillator configured for external RC network PIN 3 — Three-Pin RC Oscillator READ: Any time. WRITE: In user mode, writing has no effect. 0 = Two-pin oscillator configured (erased state) 1 = Three-pin oscillator configured RCSTD — RC Oscillator Startup Delay READ: Any time. WRITE: In user mode, writing has no effect. 0 = POR and STOP recovery are 4064 fOP cycles. (erased state) 1 = POR and STOP recovery are 16 fOP cycles. SBIT1 and SBIT0 — Security Bits for User EEPROM and PEEP READ: Any time. WRITE: In user mode, writing has no effect. 00 01 = EEPROM and PEEP security enabled 10 11 = EEPROM and PEEP security disabled Mask Option Registers (MOR) $0012 and $0013 Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 34 Memory Map For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 3. Central Processing Unit Core 3.1 Contents Freescale Semiconductor, Inc... 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.3.1 Stack Pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.3.2 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 Introduction The MC68HC805K3 has a 1024-byte memory map. Therefore, it uses only the lower 10 bits of the address bus. In the following discussion, the upper six bits of the address bus can be ignored. Also, by using a mask option register bit, the STOP instruction can be converted from acting as the normal STOP instruction. The stack area also is reduced to 32 bytes due to the limited amount of RAM. Therefore, the stack pointer is reduced to only five bits, only decrements down to $00E0, and then wraps around to $00FF. All other instructions and registers behave as described in M6805 HMOS/M146805 CMOS Family User’s Manual (M6805UM/AD3). MC68HC805K3 — Rev. 1.0 Central Processing Unit Core For More Information On This Product, Go to: www.freescale.com 35 Freescale Semiconductor, Inc. General Release Specification 3.3 Registers The MCU contains five registers that are hard-wired within the CPU and are not part of the memory map. These five registers are shown in Figure 3-1. 7 6 5 4 3 2 1 0 A Registers ACCUMULATOR Freescale Semiconductor, Inc... 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 1 1 INDEX REGISTER X 1 STACK POINTER SP 0 0 0 0 0 0 PROGRAM COUNTER PC CONDITION CODE REGISTER 1 1 1 H I N Z C CC HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT ZERO BIT CARRY BIT Figure 3-1. M68HC05 Programming Model For a more complete description of the M68HC05 CPU functions, refer to M6805 HMOS, M146805 CMOS Family User’s Manual (M6805UM(AD3), HC05 Applications Guide (M68HC05AG/AD), or Understanding Small Microcontrollers (M68HC05TB/D). Any specific differences in the operation of all CPU registers or bits is described in the following sections. MC68HC805K3 — Rev. 1.0 36 Central Processing Unit Core For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Registers 3.3.1 Stack Pointer (SP) The stack pointer shown in Figure 3-1 is a 16-bit register internally. In devices with memory maps less than 64 Kbytes, the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. When accessing memory, the 11 most significant bits are permanently set to 00000000111. The five least significant register bits are appended to these 11 fixed bits to produce an address within the range of $00FF to $00E0. Subroutines and interrupts may use up to 32 ($20) locations. If 32 locations are exceeded, the stack pointer wraps around to $00FF and writes over the previously stored information. Freescale Semiconductor, Inc... 3.3.2 Program Counter (PC) The program counter shown in Figure 3-1 is a 16-bit register internally. The program counter contains the address of the next instruction or operand to be fetched. The six most significant bits of the program counter are ignored internally and appear as 000000 when stacked onto the RAM. MC68HC805K3 — Rev. 1.0 Central Processing Unit Core For More Information On This Product, Go to: www.freescale.com 37 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 38 Central Processing Unit Core For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 4. Interrupts 4.1 Contents Freescale Semiconductor, Inc... 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 IRQ Status/Control Register (ISCR) . . . . . . . . . . . . . . . . . .45 Port Interrupts (PA0–PA3). . . . . . . . . . . . . . . . . . . . . . . . . .46 Timer Interrupt (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . .47 4.2 Introduction The MCU can be interrupted four different ways: 1. Non-maskable software interrupt instruction (SWI) 2. External asynchronous interrupt (IRQ) 3. External interrupt via IRQ on PA0-PA3 (enabled by a mask option register bit) 4. Internal timer interrupt (TIMER) MC68HC805K3 — Rev. 1.0 Interrupts For More Information On This Product, Go to: www.freescale.com 39 Freescale Semiconductor, Inc. General Release Specification 4.3 CPU Interrupt Processing Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I bit in the CCR is clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs, the processor completes the current instruction, stacks the current CPU register states, sets the I bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location, shown in Table 4-1, is serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. When an interrupt is to be processed, the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $03F8 through $03FF as defined in Table 4-1. Table 4-1. Vector Addresses for Interrupts and Reset Register N/A N/A ISCR TSCR TSCR Flag Name N/A N/A IRQF TOF RTIF Interrupts Reset Software External Interrupt Timer Overflow Real Time Interrupt CPU Interrupts RESET SWI IRQ TIMER TIMER Vector Addresses $03FE-$03FF $03FC-$03FD $03FA-$03FB $03F8-$03F9 $03F8-$03F9 CPU Interrupt Processing Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 40 Interrupts For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification CPU Interrupt Processing An RTI instruction is used to signify when the interrupt software service routine is complete. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occurs during interrupt processing. Figure 4-2 shows the stacking and unstacking order into the RAM that is associated with an interrupt service routine. Freescale Semiconductor, Inc... FROM RESET Y IS I BIT SET? N IRQ EXTERNAL INTERRUPT? N TIMER INTERNAL INTERRUPT? N Y Y CLEAR IRQ REQUEST LATCH STACK PCL, PCH, X, A, CC FETCH NEXT INSTRUCTION SET I BIT IN CCR SWI INSTRUCTION ? N RTI INSTRUCTION ? N EXECUTE INSTRUCTION Y LOAD PC FROM: SWI: $03FC, $03FD IRQ: $03FA-$03FB TIMER: $03F8-$03F9 Y RESTORE REGISTERS FROM STACK CC, A, X, PCH, PCL Figure 4-1. Interrupt Processing Flowchart MC68HC805K3 — Rev. 1.0 Interrupts For More Information On This Product, Go to: www.freescale.com 41 Freescale Semiconductor, Inc. General Release Specification Reset Interrupt Sequence STACK I N T E R R U P T 1 1 1 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER R E T U R N DECREASING MEMORY ADDRESSES INCREASING MEMORY ADDRESSES 0 0 0 0 PCL 0 0 PCH Freescale Semiconductor, Inc... UNSTACK Figure 4-2. Interrupt Stacking Order 4.4 Reset Interrupt Sequence The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner. A low-level input on the RESET pin or an internally generated RST signal causes the program to vector to its starting address, which is specified by the contents of memory locations $03FE and $03FF. The I bit in the condition code register also is set. The MCU is configured to a known state during this type of reset, as described in Section 5. Resets. 4.5 Software Interrupt (SWI) The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), the SWI instruction executes after interrupts that were pending before the SWI was fetched or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $03FC and $03FD. MC68HC805K3 — Rev. 1.0 42 Interrupts For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Hardware Interrupts 4.6 Hardware Interrupts All hardware interrupts except RESET are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. The two types of hardware interrupts are explained in the following sections. 4.6.1 External Interrupt (IRQ) Freescale Semiconductor, Inc... The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown in Figure 4-3. The IRQ pin is one source of an IRQ interrupt, and a mask option register bit is available to enable the four lower order port A pins (PA0 through PA3) to act as other IRQ interrupt sources. All of these sources are combined into a single ORing function that is latched by the IRQ latch. The IRQ latch is set on the falling edge of the IRQ pin or on the rising edge of a PA0 through PA3 pin, if port A interrupts have been enabled by the mask option register bit. IRQ PIN PA0 PA1 PA2 PA3 PORT A IRQ MASK OPTION REGISTER BIT RST IRQR IRQ VECTOR FETCH IRQE IRQ SENSITIVITY MASK OPTION REGISTER BIT VDD LATCH TO BIH & BIL INSTRUCTION SENSING IRQF R TO IRQ PROCESSING IN CPU Figure 4-3. IRQ Function Block Diagram MC68HC805K3 — Rev. 1.0 Interrupts For More Information On This Product, Go to: www.freescale.com 43 Freescale Semiconductor, Inc. General Release Specification Hardware Interrupts If the mask option for edge-sensitive only IRQ is used, only the IRQ latch output can activate an IRQF flag which creates a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to these cases: • • If the port A interrupts are disabled by a mask option register bit, only a falling edge on the IRQ pin initiates an IRQ interrupt. If the port A interrupts are enabled by a mask option register bit, these conditions initiate an IRQ interrupt: – A falling edge on the IRQ pin with all the PA0 through PA3 pins at a low level – A rising edge on one PA0 through PA3 pin with all other PA0 through PA3 pins at a low level and the IRQ pin at a high level If the mask option register bit for edge- and level-sensitive IRQ is used, the active high state of the IRQ latch input also can activate an IRQF flag, which creates a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to these cases: • If the port A Interrupts are disabled by a mask option register bit, only these conditions initiate an IRQ interrupt: – A low level on the IRQ pin – Falling edge on the IRQ pin • If the port A interrupts are enabled by a mask option register bit, these conditions initiate an IRQ interrupt: – A low level on the IRQ pin with all the PA0 through PA3 pins at a low level. – Falling edge on the IRQ pin with all the PA0 through PA3 pins at a low level. – High level on any one of the PA0 through PA3 pins with the IRQ pin at a high level. – Rising edge on any PA0 through PA3 pin with all other PA0 through PA3 pins at a low level and the IRQ pin at a high level. Freescale Semiconductor, Inc... The IRQE enable bit controls whether an active IRQF flag can generate an IRQ interrupt sequence. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $03FA and $03FB. MC68HC805K3 — Rev. 1.0 44 Interrupts For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Hardware Interrupts Entering the interrupt service routine automatically clears the IRQ latch. The IRQ interrupt service routine also may clear the IRQ latch by writing a logic one to the IRQR acknowledge bit in the ISCR. As long as the output state of the IRQF flag bit is active, the CPU continuously re-enters the IRQ interrupt sequence following an RTI instruction until the active state is removed or the IRQE enable bit is cleared. 4.6.2 IRQ Status/Control Register (ISCR) Freescale Semiconductor, Inc... The IRQ interrupt function is controlled by the ISCR located at $000A as shown in Figure 4-4. All unused bits in the ISCR read as logic zeros. A reset clears the IRQF bit and sets the IRQE bit. $000A Read: IRQE Write: Reset: 1 0 0 R 0 R 0 = Reserved 0 IRQR 0 0 Bit 7 6 0 5 0 4 0 3 IRQF 2 0 1 0 Bit 0 0 = Unimplemented Figure 4-4. IRQ Status/Control Register IRQR — IRQ Interrupt Acknowledge The IRQR acknowledge bit clears an IRQ interrupt request by clearing the IRQ latch. If the IRQ latch is set again while in the IRQ service routine (before an RTI instruction is executed), the CPU reenters the IRQ interrupt service routine unless the IRQ latch is cleared. Writing a logic one to the IRQR acknowledge bit clears the IRQ latch. Writing a logic zero to the IRQR acknowledge bit has no effect on the IRQ latch. The IRQR acknowledge bit always reads as a logic zero. IRQF — IRQ Interrupt Request The IRQF flag bit indicates that an IRQ request is pending. Writing to the IRQF flag bit has no effect on it. The IRQF flag bit is cleared automatically when the IRQ vector is fetched and the service routine is entered. The IRQF flag bit also can be cleared by writing a logic one to the IRQR acknowledge bit to clear the IRQ latch and also condition MC68HC805K3 — Rev. 1.0 Interrupts For More Information On This Product, Go to: www.freescale.com 45 Freescale Semiconductor, Inc. General Release Specification Hardware Interrupts the external IRQ sources to be inactive if the edge- and level-sensitive mask option register bit is selected. In this way, any additional setting of the IRQF flag bit while in the service routine can be ignored by clearing the IRQF flag bit just before exiting the service routine. If the IRQF flag bit is set again while in the IRQ service routine, the CPU reenters the IRQ interrupt sequence unless the IRQF flag bit is cleared. The IRQF flag bit is cleared by reset. IRQE — IRQ Interrupt Enable Freescale Semiconductor, Inc... The IRQE bit enables or disables the IRQF flag bit to initiate an IRQ interrupt sequence. If the IRQE enable bit is set, the IRQF flag bit can generate an interrupt sequence. If the IRQE enable bit is cleared, the IRQF flag bit cannot generate an interrupt sequence. Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once the I bit is cleared. Execution of the STOP or WAIT instructions causes the IRQE bit to be set to allow the external IRQ to exit these modes. In addition, reset also sets the I bit, which masks all interrupt sources. NOTE: If the I bit is cleared, any instruction that sets the IRQE enable bit when the IRQF flag bit is already set initiates an IRQ interrupt sequence immediately after that instruction. 4.6.3 Port Interrupts (PA0–PA3) The IRQ interrupt also can be triggered by inputs to PA0 through PA3 port pins as described in 4.6.1 External Interrupt (IRQ) if the port interrupts mask option register bit is used. If enabled, the lower four bits of port A can activate the IRQ interrupt function and the interrupt operation is the same as the input to the IRQ pin. The mask option register bit allows all of these input pins to be ORed with the input present on the IRQ pin. All PA0 through PA3 pins must be selected as a group and as an additional IRQ interrupt source. All the port A interrupt sources also are controlled by the IRQE enable bit. NOTE: The BIH and BIL instructions apply only to the level on the IRQ pin itself and not to the output of the logic OR gate with PA0 through PA3 pins. The state of the individual port A pins can be checked by reading the appropriate port A pins as inputs. MC68HC805K3 — Rev. 1.0 46 Interrupts For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Hardware Interrupts NOTE: If port A interrupts are enabled, the state of PA0 through PA3 pins may cause an IRQ interrupt regardless of whether these pins are configured as inputs or outputs. (See Section 7. Parallel Input/Output.) 4.6.4 Timer Interrupt (TIMER) The timer interrupt is generated by the 8-bit timer when either a timer overflow or a real-time interrupt has occurred, as described in Section 8. 8-Bit Timer. The interrupt flags and enable bits for the timer interrupts are in the timer status/control register (TSCR) located at $0008. The I bit in the CCR must be clear for the timer interrupt to be enabled. Either of these two interrupts vector to the same interrupt service routine located at the address specified by the contents of memory locations $03F8 and $03F9. Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 Interrupts For More Information On This Product, Go to: www.freescale.com 47 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 48 Interrupts For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 5. Resets 5.1 Contents Freescale Semiconductor, Inc... 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.3 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .51 5.4.3 Illegal Address Reset (ILADR) . . . . . . . . . . . . . . . . . . . . . .51 5.2 Introduction The MCU can be reset from four sources: one external input and three internal restart conditions. The RESET pin is an input with a Schmitt trigger, as shown in Figure 5-1. All the internal peripheral modules that drive external pins are reset by the synchronous reset signal (RST) coming from a latch, which is synchronized to the PH2 bus clock and set by any of the four reset sources. NOTE: Activation of the RST signal generally is referred to as a reset of the device, unless otherwise specified. MC68HC805K3 — Rev. 1.0 Resets For More Information On This Product, Go to: www.freescale.com 49 Freescale Semiconductor, Inc. General Release Specification Resets VDD RESET OSC DATA ADDRESS COP WATCHDOG (COPR) POWER-ON RESET (POR) ILLEGAL ADDRESS (ILADR) CPU S LATCH PH2 RST TO OTHER PERIPHERALS Freescale Semiconductor, Inc... VDD ADDRESS Figure 5-1. Reset Block Diagram 5.3 External Reset (RESET) The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide noise immunity. This external reset occurs whenever the RESET pin is pulled low and remains in reset until the RESET pin rises to a logic one. This active low input generates the RST signal and resets the CPU and peripherals. 5.4 Internal Resets The three internally generated resets are the initial power-on reset function, the COP watchdog timer reset, and the illegal address detector reset. 5.4.1 Power-On Reset (POR) The internal POR is generated on power-up of the internal CPU to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (a “brown-out” condition). After the oscillator becomes active, a mask MC68HC805K3 — Rev. 1.0 50 Resets For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Resets option register bit selects an oscillator stabilization delay of 16 or 4064 cycles of the internal processor bus clock (PH2). The POR generates the RST signal that resets the CPU. If any other reset function is active at the end of this stabilization delay, the RST signal remains in the reset condition until the other reset condition(s) end(s). 5.4.2 Computer Operating Properly Reset (COPR) Freescale Semiconductor, Inc... A COP watchdog timer can be enabled by a mask option register bit. The internal COP reset (COPR) is generated automatically by a timeout of the COP watchdog timer. This timeout occurs if the counter in the COP watchdog timer is not reset (cleared) within a specific time by a user program reset sequence. Refer to 8.4 COP Watchdog Timer for more information on this timeout feature. The COPR generates the RST signal that resets the CPU and other peripherals. If any other reset function is active at the end of the COPR reset signal, the RST signal remains in the reset condition until the other reset condition(s) end(s). The COP Watchdog reset activates the internal pulldown device connected to the RESET pin for one cycle of the internal processor bus clock, PH2. 5.4.3 Illegal Address Reset (ILADR) The internal ILADR reset is generated when an instruction opcode fetch occurs from an address in the I/O address area ($0000 through $001F). The ILADR generates the RST signal that resets the CPU and other peripherals. If any other reset function is active at the end of the ILADR reset signal, the RST signal remains in the reset condition until the other reset condition(s) end(s). The ILADR reset activates the internal pulldown device connected to the RESET pin for one cycle of the internal processor bus clock, PH2. MC68HC805K3 — Rev. 1.0 Resets For More Information On This Product, Go to: www.freescale.com 51 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 52 Resets For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 6. Operational Modes 6.1 Contents Freescale Semiconductor, Inc... 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.3.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.3.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 6.3.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.3.4 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . .57 6.2 Introduction The MC68HC805K3 is capable of running in one of several operational modes to reduce power consumption. 6.3 Low-Power Modes The WAIT and STOP/HALT instructions provide two low-power operational modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The flow of the stop, halt and wait modes is shown in Figure 6-1. 6.3.1 Stop Mode The STOP instruction can result in one of two modes of operation depending on its mask option register bit. The mask option register bit can make the STOP instruction operate the same as the STOP instruction in other M68HC05 Family members and place the device in stop mode. Or the mask option register bit can make the STOP instruction behave like a WAIT instruction (except that the restart time involves a delay) and place the device in halt mode. MC68HC805K3 — Rev. 1.0 Operational Modes For More Information On This Product, Go to: www.freescale.com 53 Freescale Semiconductor, Inc. General Release Specification Low-Power Modes The mask option register bit enabling the execution of the STOP instruction places the MCU in its lowest power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including the COP watchdog timer. When the CPU enters stop mode, the interrupt flags (TOF and RTIF) and the interrupt enable bits (TOFE and RTIE) in the TSCR are cleared by internal hardware to remove any pending timer interrupt requests and to disable any further timer interrupts. Execution of the STOP instruction automatically clears the I bit in the condition code register and sets the IRQE enable bit in the IRQ status/control register so that the IRQ external interrupt is enabled. All other memory and registers, including the other bits in the TSCR, remain unaltered. The MCU can be brought out of stop mode only by an IRQ external interrupt, an IRQ from port A (if mask option register bit is enabled), or an externally generated RESET. When exiting stop mode, the internal oscillator resumes after an oscillator stabilization delay of either 16 or 4064 cycles (depending on mask option register bit state) of the internal processor clock. Freescale Semiconductor, Inc... NOTE: If enabled by a mask option register bit, the STOP instruction causes the oscillator to stop and, therefore, disable the COP watchdog timer. If the COP watchdog timer is used and the part is never intended to enter stop mode, the mask option register bit that should be used is the one that disables the STOP instruction and changes the stop mode to the halt mode. See 6.3.4 COP Watchdog Timer Considerations for more details. MC68HC805K3 — Rev. 1.0 54 Operational Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Low-Power Modes STOP WAIT MASK OPTION TO HALT? N=0 Y=1 HALT STOP EXTERNAL OSCILLATOR, STOP INTERNAL TIMER CLOCK, AND RESET STARTUP DELAY EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE Freescale Semiconductor, Inc... STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR, AND SET IRQE IN ISCR STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR, AND SET IRQE IN ISCR STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR, AND SET IIRQE IN ISCR EXTERNAL RESET? N IRQ EXTERNAL INTERRUPT? N Y Y EXTERNAL RESET? N Y EXTERNAL RESET? N Y Y IRQ EXTERNAL INTERRUPT? N Y IRQ EXTERNAL INTERRUPT? N RESTART EXTERNAL OSCILLATOR AND BEGIN STABILIZATION DELAY Y TIMER INTERNAL INTERRUPT? N Y TIMER INTERNAL INTERRUPT? N END OF STARTUP DELAY N Y RESTART INTERNAL PROCESSOR CLOCK 1.FETCH RESET VECTOR OR 2.SERVICE INTERRUPT a.STACK CPU STATE b.SET I BIT C. VECTOR TO INTERRUPT ROUTINE Figure 6-1. Stop/Halt/Wait Flowcharts MC68HC805K3 — Rev. 1.0 Operational Modes For More Information On This Product, Go to: www.freescale.com 55 Freescale Semiconductor, Inc. General Release Specification 6.3.2 Halt Mode Execution of the STOP instruction with a mask option register bit to disable the stop mode places the MCU in a low-power halt mode, which consumes more power than stop mode. In halt mode, the internal processor clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the COP watchdog timer. Execution of the STOP instruction in the halt mode automatically clears the I bit in the condition code register and sets the IRQE enable bit in the IRQ status/control register so that the IRQ external interrupt is enabled. All other registers, memory, and input/output lines remain in their previous states. If timer interrupts are enabled, a timer interrupt causes the processor to exit halt mode and resume normal operation. Halt mode also can be exited when an external IRQ or external RESET occurs. When exiting halt mode, the internal processor clock resumes after a variable delay. Depending on the mask option register bit state, the maximum oscillator stabilization delay is 16 or 4064 cycles of the internal processor clock. Using the mask option register bit to disable the STOP instruction prevents the STOP instruction from halting the oscillator or affecting the COP watchdog timer similar to wait mode. However, the recovery method introduces some startup delay in the processor clock. Low-Power Modes Freescale Semiconductor, Inc... NOTE: Halt mode is not intended for normal use, but is provided to keep the COP watchdog timer active if the STOP instruction opcode is executed inadvertently. MC68HC805K3 — Rev. 1.0 56 Operational Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Low-Power Modes 6.3.3 Wait Mode The WAIT instruction places the MCU in a low-power wait mode, which consumes more power than stop mode. In wait mode, the internal processor clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the condition code register and sets the IRQE enable bit in the IRQ status/control register so that the IRQ external interrupt is enabled. All other registers, memory, and input/output lines remain in their previous states. If timer interrupts are enabled, a timer interrupt causes the processor to exit wait mode and resume normal operation. Thus, the timer can be used to generate a periodic exit from wait mode. Wait mode also is exited when an external IRQ or RESET occurs. Freescale Semiconductor, Inc... 6.3.4 COP Watchdog Timer Considerations If the COP watchdog timer is enabled by the mask option register bit, any execution of the STOP instruction (either intentional or inadvertent due to the CPU being disturbed) causes the oscillator to halt and prevent the COP watchdog timer from timing out unless the STOP instruction is disabled by a mask option register bit. If the mask option register bit is selected to enable the COP watchdog timer, the COP resets the MCU when it times out. Therefore, it is recommended that the mask option register bit be selected to disable the COP watchdog for a system that must have intentional uses of the wait mode for periods longer than the COP timeout period. MC68HC805K3 — Rev. 1.0 Operational Modes For More Information On This Product, Go to: www.freescale.com 57 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 58 Operational Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 7. Parallel Input/Output 7.1 Contents Freescale Semiconductor, Inc... 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . .61 Port A Pulldown Inhibit Register . . . . . . . . . . . . . . . . . . . . .61 Port A LED Drive Capability . . . . . . . . . . . . . . . . . . . . . . . .62 Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . .65 Port B Pulldown Inhibit Register . . . . . . . . . . . . . . . . . . . . .65 Port B with 3-Pin RC Oscillator . . . . . . . . . . . . . . . . . . . . . .66 I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Pin Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 I/O Pin Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 I/O Pin Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 MC68HC805K3 — Rev. 1.0 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com 59 Freescale Semiconductor, Inc. General Release Specification 7.2 Introduction In single-chip mode, 10 bidirectional input/output (I/O) lines are arranged as one 8-bit I/O port (port A) and one 2-bit I/O port (port B). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs). All port A and port B I/O pins have individual software programmable pulldown devices enabled by a mask option register bit. Some port A pins also have the additional properties of sinking higher current or acting as additional IRQ interrupt input sources. One of the port B pins also may be used as an output for a 3-pin resistor capacitor (RC) oscillator option. Introduction Freescale Semiconductor, Inc... 7.3 Port A Port A is an 8-bit bidirectional port that shares four of its pins with the IRQ interrupt system, as shown in Figure 7-1. Each port A pin is controlled by the corresponding bits in a data direction register, a data register, and a pulldown register. READ $0004 WRITE $0004 VDD DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT I/O PIN WRITE $0000 READ $0000 WRITE $0010 INTERNAL HC05 DATA BUS PULLDOWN REGISTER BIT RESET (RST) MASK OPTION TO INHIBIT SOFTWARE PULLDOWNS TO IRQ INTERRUPT SYSTEM (BITS 0-3 ONLY) Figure 7-1. Port A I/O Circuitry MC68HC805K3 — Rev. 1.0 60 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Port A The port A DATA register is located at address $0000. The port A data direction register (DDRA) is located at address $0004. The port A pulldown register (PDRA) is located at address $0010. Reset clears both the DDRA and the PDRA. The port A data register is unaffected by reset. 7.3.1 Port A Data Register Each port A I/O pin has a corresponding bit in the port A data register. When a port A pin is programmed as an output, the state of the corresponding data register bit determines the state of the output pin. When a port A pin is programmed as an input, any read of the port A data register returns the logic state of the corresponding I/O pin, and any write to the port A data register is saved in the data register, but is not applied to the corresponding I/O pin. The port A data register is unaffected by reset. The port A data register is indeterminant after initial power-up. Freescale Semiconductor, Inc... 7.3.2 Port A Data Direction Register Each port A I/O pin may be programmed as an input by clearing the corresponding bit in the DDRA or programmed as an output by setting the corresponding bit in the DDRA. When a DDRA bit is set, the corresponding pulldown device is disabled. The DDRA can be accessed at address $0004. The DDRA is cleared by reset. 7.3.3 Port A Pulldown Inhibit Register All port A I/O pins have software programmable pulldown devices which may be enabled by a mask option register bit. If enabled by mask option register bit, the software programmable pulldowns are activated by clearing their corresponding bit in the PDRA or disabled by setting the corresponding bit in the PDRA. If disabled by a mask option register bit, all pulldowns are disabled. A pulldown on an I/O pin can be activated only if the I/O pin is programmed as an input. Any activated pulldowns on the port A pins are not affected by the VDD supply source to the drivers. MC68HC805K3 — Rev. 1.0 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com 61 Freescale Semiconductor, Inc. General Release Specification Port A The PDRA is a write-only register and any reads of location $0010 return undefined results. Since reset clears both the DDRA and the PDRA, all pins initialize as inputs with the pulldown devices active (if enabled by mask option register bit). $0010 Read: Write: PDIA7 0 PDIA6 0 PDIA5 0 PDIA4 0 PDIA3 0 PDIA2 0 PDIA1 0 PDIA0 0 Bit 7 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Reset: = Unimplemented Figure 7-2. Port A Pulldown Inhibit Register (PDRA) 7.3.4 Port A LED Drive Capability The outputs of port A pins 4 through 7 are capable of sinking high current for LED drive capability. 7.3.5 Port A I/O Pin Interrupts The inputs for the lower four bits of port A can be connected through an OR gate to the IRQ latched input to the CPU by a mask option register bit. When connected as an alternate source of an IRQ interrupt, the port A input pins behave the same as the IRQ pin itself, except that their active state is a logical one or a rising edge. The normal IRQ pin has an active state that is a logical zero or a falling edge depending on the mask option register bit. If the mask option register bit for edge- and level-sensitive interrupts and the mask option register bit for port A interrupts are both used, the presence of a logic one on any one of the lower four port A pins causes an IRQ interrupt request. If the mask option register bit for edgesensitive-only interrupts and the mask option register bit for port A interrupts are both used, the occurrence of a rising edge on any one of the PA0–PA3 pins causes an IRQ interrupt request, as long as the other PA0–PA3 pins are at a low level. As long as any one of the PA0 through PA3 IRQ inputs remains at a logic one level, or the IRQ remains at a MC68HC805K3 — Rev. 1.0 62 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Port B logic zero level, the other PA0–PA3 IRQ inputs are effectively ignored. Port interrupts will be generated with the above PA0–PA3 I/O state regardless of whether the port is configured as an input or output. NOTE: The BIH and BIL instructions apply only to the level on the IRQ pin itself, and not to the internal IRQ input to the CPU. Therefore, BIH and BIL cannot be used to test the state of the lower four port A input pins as a group. Each port A interrupt pin can be tested by reading the port A data register at $0000. Freescale Semiconductor, Inc... 7.4 Port B Port B is a 2-bit bidirectional port that shares one of its pins with the RC oscillator as shown in Figure 7-3. Each port B pin is controlled by the corresponding bits in a data direction register, a data register, and a pulldown register. The port B data register is located at address $0001. The port B data direction register (DDRB) is located at address $0005, and the port B pulldown register (PDRB) is located at address $0011. Reset clears both the DDRB and the PDRB. The port B data register is unaffected by reset. 7.4.1 Port B Data Register Each port B I/O pin has a corresponding bit in the port B data register. When a port B pin is programmed as an output, the state of the corresponding data register bit determines the state of the output pin. When a port B pin is programmed as an input, any read of the port B data register returns the logic state of the corresponding I/O pin, and any write to the port B data register is saved in the data register, but not applied to the corresponding I/O pin. Unused bits 2 through 7 are always read as logic zeros, and any write to these bits is ignored. The port B data register is unaffected by reset. The port B data register is indeterminant after initial power-up. MC68HC805K3 — Rev. 1.0 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com 63 Freescale Semiconductor, Inc. General Release Specification Port B READ $0005 VDD WRITE $0005 DATA DIRECTION REGISTER B FROM 3-PIN RC OSCILLATOR WRITE $0001 DATA REGISTER BIT OUTPUT PB1 OSC3 I/O PIN Freescale Semiconductor, Inc... READ $0001 WRITE $0011 PULLDOWN REGISTER BIT MASK OPTION FOR RC OSCILLATOR MASK OPTION FOR 3-PIN RC OSCILLATOR) READ $0005 WRITE $0005 DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT PB0 PIN WRITE $0001 READ $0001 WRITE $0011 INTERNAL HC05 DATA BUS PULLDOWN REGISTER BIT MASK OPTION TO INHIBIT SOFTWARE PULLDOWNS RESET (RST) Figure 7-3. Port B I/O Circuitry MC68HC805K3 — Rev. 1.0 64 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Port B 7.4.2 Port B Data Direction Register Each port B I/O pin may be programmed as an input by clearing the corresponding bit in the DDRB or programmed as an output by setting the corresponding bit in the DDRB. When a DDRB bit is set, the corresponding pulldown device is disabled. The DDRB can be accessed at address $0005. Unused bits 2 through 7 are always read as logic zeros, and any write to these bits is ignored. The DDRB is cleared by reset. Freescale Semiconductor, Inc... 7.4.3 Port B Pulldown Inhibit Register Each port B I/O pin has a software programmable pulldown device which can be enabled by a mask option register bit. If enabled by a mask option register bit, the software programmable pulldowns are activated by clearing the corresponding bit in the PDRB or disabled by setting the corresponding bit in the PDRB. If disabled by a mask option register bit, all pulldowns are disabled. A pulldown on an I/O pin can be activated only if the I/O pin is programmed as an input. The PDRB is a write-only register and any reads of location $0011 return undefined results. Since reset clears both the DDRB and the PDRB, all pins initialize as inputs with the pulldown devices active (if enabled by mask option register bit). $0011 Read: Write: Reset: = Unimplemented PDIB1 0 PDIB0 0 Bit 7 6 5 4 3 2 1 Bit 0 Figure 7-4. Port B Pulldown Inhibit Register (PDRB) MC68HC805K3 — Rev. 1.0 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com 65 Freescale Semiconductor, Inc. General Release Specification 7.4.4 Port B with 3-Pin RC Oscillator The PB1/OSC3 pin may be used as an output from a 3-pin RC oscillator when the mask option register bit for a 3-pin RC oscillator is used. In this case, the following conditions apply: • • The PB1 data register bit can be used as a read/write storage location without affecting the oscillator. PB1 is unaffected by reset. The DDRB1 data direction bit can be used as a read/write storage location without affecting the oscillator. DDRB1 is cleared by reset. The software programmable pulldown on PB1/OSC3 is disabled, regardless of the mask option register bit selection for the software programmable pulldowns or the state of PDRB1. I/O Port Programming Freescale Semiconductor, Inc... • 7.5 I/O Port Programming All I/O pins can be programmed as inputs or outputs, with or without pulldown devices. 7.5.1 Pin Data Direction The direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (DDR). A pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logic zero. The data direction bits DDRB0, DDRB1, and DDRA0 through DDRA7 are read/write bits that can be manipulated with read-modify-write instructions. At power-on or reset, all DDRs are cleared, which configures all port pins as inputs. If the mask option register bit for software programmable pulldowns is selected, all pins initially power-up with their software programmable pulldowns enabled. MC68HC805K3 — Rev. 1.0 66 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification I/O Port Programming 7.5.2 Output Pin When an I/O pin is programmed as an output pin, the state of the corresponding data register bit determines the state of the pin. The state of the data register bits can be altered by writing to address $0000 for port A and address $0001 for port B. Reads of the corresponding data register bit at address $0000 or $0001 return the state of the data register bit, not the state of the I/O pin itself. Therefore, bit manipulation is possible on all pins programmed as outputs. Freescale Semiconductor, Inc... All pins programmed as outputs have their pulldown devices disabled regardless of the selected mask option register bit for software programmable pulldowns or the state of their PDR bits. 7.5.3 Input Pin When an I/O pin is programmed as an input pin, the state of the pin can be determined by reading the corresponding data register bit. Any writes to the corresponding data register bit for an input pin is saved by the register bit, but not applied to the corresponding I/O pin until the pin is later programmed to be an output. If the corresponding bit in the pulldown register is clear (and the mask option register bit for software programmable pulldowns is selected), the input pin also has an activated pulldown device. Read-modify-write instructions, such as bit manipulation, should not be used on the pulldown registers, since they are write-only. 7.5.4 I/O Pin Transitions A “glitch” can be generated on an I/O pin when changing it from an input to an output unless the data register is first pre-conditioned to the desired state before changing the corresponding DDR bit from a zero to a one. MC68HC805K3 — Rev. 1.0 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com 67 Freescale Semiconductor, Inc. General Release Specification I/O Port Programming If the mask option register bit for software programmable pulldowns is selected, a floating input can be avoided by first clearing the pulldown register bit before changing the corresponding DDR from a one to a zero. This ensures that the pulldown device is activated on the pin as the I/O pin changes from a driven output to a pulled low input. 7.5.5 I/O Pin Truth Tables Every pin on port A and PB0 on port B may be programmed as an input or an output under software control, as shown in Table 7-1 and Table 7-2. All port I/O pins also may have software programmable pulldown devices selected by a mask option register bit. The PB1/OSC3 pin on port B also can be programmed as an input or an output under software control, but it has special considerations when selected by a mask option register bit as an output for the 3-pin RC oscillator, as shown in Table 7-3. Otherwise, PB1/OSC3 behaves the same as PB0. Table 7-1. Port A Pin Functions Software Prog. Pulldown Mask Option Register Bit* 1 1 0 0 0 0 I/O Pin Mode Access to PDRA at $0010 Read X X 0 0 1 1 0 1 0 1 0 1 IN, Hi-Z OUT IN, Pulldown OUT IN, Hi-Z OUT U U U U U U Write PDIA0–7 PDIA0–7 PDIA0–7 PDIA0–7 PDIA0–7 PDIA0–7 Access to DDRA at $0004 Read/Write DDRA0–7 DDRA0–7 DDRA0–7 DDRA0–7 DDRA0–7 DDRA0–7 Access to Data Register at $0000 Read I/O Pin PA0–7 I/O Pin PA0–7 I/O Pin PA0–7 Write X PA0–7 X PA0–7 X PA0–7 Freescale Semiconductor, Inc... PDIAx DDRAx NOTES: X is don’t care state U is an undefined state * 1 = pulldowns disabled 2 = pulldowns enabled MC68HC805K3 — Rev. 1.0 68 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification I/O Port Programming Table 7-2. PB0 Pin Functions Software Prog. Pulldown Mask Option Register Bit* 1 1 0 I/O Pin Mode Access to PDRB at $0011 Read X X 0 0 1 1 0 1 0 1 0 1 IN, Hi-Z OUT IN, Pulldown OUT IN, Hi-Z OUT U U U U U U Write PDIB0 PDIB0 PDIB0 PDIB0 PDIB0 PDIB0 Access to DDRB at $0005 Read/Write DDRB0 DDRB0 DDRB0 DDRB0 DDRB0 DDRB0 Access to Data Register at $0001 Read I/O Pin PB0 I/O Pin PB0 I/O Pin PB0 Write X PB0 X PB0 X PB0 PDIB0 DDRB0 Freescale Semiconductor, Inc... 0 0 0 NOTES: X is don’t care state U is an undefined state * 1 = pulldowns disabled 2 = pulldowns enabled Table 7-3. PB1/OSC3 Pin Functions Mask Option (3-Pin) 0 0 0 0 0 0 1 Software Prog. Pulldown Mask Option Register Bit* 0 0 0 0 0 0 X I/O Pin Mode Access to PDRB at $0011 Read 1 1 0 0 0 0 X 0 1 0 1 0 1 X IN, Hi-Z OUT IN, Pulldown OUT IN, Hi-Z OUT RC OSCOUT U U U U U U U Write PDIB1 PDIB1 PDIB1 PDIB1 PDIB1 PDIB1 PDIB1 Access to DDRB at $0005 Read/Write DDRB1 DDRB1 DDRB1 DDRB1 DDRB1 DDRB1 DDRB1 Access to Data Register at $0001 Read I/O Pin PB1 I/O Pin PB1 I/O Pin PB1 PB1 Write X PB1 X PB1 X PB1 PB1 PDIB1 DDRB1 NOTES: X is don’t care state U is an undefined state * 1 = pulldowns disabled 2 = pulldowns enabled MC68HC805K3 — Rev. 1.0 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com 69 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 70 Parallel Input/Output For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 8. 8-Bit Timer 8.1 Contents Freescale Semiconductor, Inc... 8.2 8.3 8.3.1 8.3.2 8.4 8.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Timer Counter Register (TCNTR) $09 . . . . . . . . . . . . . . . .73 Timer Status/Control Register (TSCR) $08. . . . . . . . . . . . .74 COP Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Operating During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76 8.2 Introduction The timer for this device is an 8-bit ripple counter. The features include timer overflow, power-on reset (POR), real time interrupt, and COP watchdog timer. This timer is powered down in the stop mode to reduce STOP IDD. As shown in Figure 8-1, the timer is driven by the timer clock, NTF1, divided by four (4). NTF1 has the same phase and frequency as the processor bus clock, PH2, but is not stopped by the wait or halt modes. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the timer counter register (TCNTR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of fOP/1024. Two additional stages produce the POR function at fOP/4064 or fOP/16, followed by two more stages, with the resulting clock (fOP/16,384) driving the real time interrupt (RTI) circuit. The RTI circuit consists of three divider stages with a one-of-four selector. The output of the RTI circuit is further divided by eight to drive the optional COP watchdog timer circuit, which can be enabled by a mask option register bit. The RTI rate selector bits, and the RTI and TOF enable bits and flags are located in the timer control and status register MC68HC805K3 — Rev. 1.0 8-Bit Timer For More Information On This Product, Go to: www.freescale.com 71 Freescale Semiconductor, Inc. General Release Specification 8.6 Operating During Wait Mode at location $08. The clock frequency that drives the RTI circuit is fOP/214 (or fOP/16384) with three additional divider stages giving a maximum interrupt period of fOP/217 (or fOP/131072). The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 or 16 cycles (depending on mask option register bit), the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer starts counting up from zero and normal device operation begins. If RESET is asserted at any time during operation, the counter chain is cleared. Freescale Semiconductor, Inc... MC68HC05 INTERNAL BUS 8 8 $09 TCNTR TIMER COUNTER REGISTER (TCNTR) TCNTR fOP/210 7-BIT COUNTER RESET POR TCBP OVERFLOW DETECT CIRCUIT RTI SELECT CIRCUIT MOR1,2 REFRESH fOP/22 ÷4 COPR CLEAR NTF1 INTERNAL TIMER CLOCK (fOP) $08 TSCR TIMER STATUS/CONTROL REGISTER TSCR TOF RTIF TOFE RTIE TOFR RTIFR RT1 RT0 ÷8 INTERRUPT CIRCUIT COP WATCHDOG TIMER TO INTERRUPT LOGIC TO RESET LOGIC Figure 8-1. Timer Block Diagram MC68HC805K3 — Rev. 1.0 72 8-Bit Timer For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Timer Registers 8.3 Timer Registers The 8-bit timer contains two registers: a timer counter register and a timer status/control register. 8.3.1 Timer Counter Register (TCNTR) $09 The timer counter register is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP divided by 4 and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location thereby simulating a 16-bit (or more) counter. The value of each bit of the TCNTR is shown below. This register is cleared by reset. $09 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 TCR7 6 TCR6 5 TCR5 4 TCR4 3 TCR3 2 TCR2 1 TCR1 Bit 0 TCR0 Freescale Semiconductor, Inc... = Unimplemented Figure 8-2. Timer Counter Register MC68HC805K3 — Rev. 1.0 8-Bit Timer For More Information On This Product, Go to: www.freescale.com 73 Freescale Semiconductor, Inc. General Release Specification Timer Registers 8.3.2 Timer Status/Control Register (TSCR) $08 The TSCR contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. Bit 2 and bit 3 are writeonly bits that read as logical zeros. Figure 8-3 shows the value of each bit in the TSCR following reset. $08 Read: Bit 7 TOF 6 RTIF TOIE RTIE TOFR 0 0 0 0 0 RTIFR 0 1 1 5 4 3 0 2 0 RT1 RT0 1 Bit 0 Freescale Semiconductor, Inc... Write: Reset: = Unimplemented Figure 8-3. Timer Status/Control Register TOF — Timer Overflow The TOF is a read-only flag bit that is set when the 8-bit ripple counter rolls over from $FF to $00. A timer interrupt request is generated if TOF is set when TOIE is also set. The TOF flag bit is reset by writing a logical one to the TOFR acknowledge bit. Writing to the TOF flag bit has no effect on its value. This bit is cleared by reset. RTIF — Real Time Interrupt Flag The RTIF is a read-only flag bit that is set when the output of the chosen (one-of-four selection) real time interrupt stage goes active. A timer interrupt request is generated if RTIF is set when RTIE is also set. The RTIF flag bit is reset by writing a logical one to the RTIFR acknowledge bit. Writing to the RTIF flag bit has no effect on its value. This bit is cleared by reset. TOIE — Timer Overflow Interrupt Enable The TOIE is an enable bit that allows generation of a timer interrupt. When the TOIE enable bit is set, the TIMER Interrupt is generated when the TOF flag bit is set. This bit is cleared by reset. MC68HC805K3 — Rev. 1.0 74 8-Bit Timer For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Timer Registers RTIE — Real Time Interrupt Enable The RTIE is an enable bit that allows the generation of a timer interrupt. When the RTIE enable bit is set and the RTIF flag bit is set, the timer interrupt is generated. The RTIE bit is cleared by reset. TOFR — Timer Overflow Acknowledge The TOFR is an acknowledge bit that resets the TOF flag bit. Writing a logical one to the TOFR clears the TOF flag bit. Reading the TOFR always returns a logical zero. This bit is unaffected by reset. Freescale Semiconductor, Inc... RTIFR — Real Time Interrupt Acknowledge The RTIFR is an acknowledge bit that resets the RTIF flag bit. Writing a logical one to the RTIFR clears the RTIF flag bit. Reading the RTIFR always returns a logical zero. This bit is unaffected by reset. RT1:RT0 — Real Time Interrupt Rate Select The RT0 and RT1 control bits select one-of-four taps for the real time interrupt circuit. Table 8-1 shows the available interrupt rates with several fOP values. Both the RT0 and RT1 control bits are set by reset, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the time-out period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF can be missed or an additional RTIF can be generated. To avoid problems, the COP should be cleared just prior to changing RTI taps. Table 8-1. RTI Rates and COP Reset Times RT1:RT0 RTI Rate fOP ÷ 214 fOP ÷ 215 fOP ÷ 216 fOP ÷ 217 RTI Period (fOP = 2 MHz) 8.2 ms 16.4 ms 32.8 ms 65.5 ms COP Timeout Period (± 1 RTI Period) 8 x RTI Period 8 x RTI Period 8 x RTI Period 8 x RTI Period Minimum COP Timeout Period fOP = 2 MHz) 57.3 ms 114.7 ms 229.4 ms 458.8 ms 0 0 1 1 0 1 0 1 MC68HC805K3 — Rev. 1.0 8-Bit Timer For More Information On This Product, Go to: www.freescale.com 75 Freescale Semiconductor, Inc. General Release Specification 8.4 COP Watchdog Timer The computer operating properly (COP) watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset times are listed in Table 8-1. If the COP circuit times out, an internal reset is generated and the reset vector is fetched. Preventing a COP time out is done by writing a logical zero to the COPC bit at address $03F0 as shown below. The COPR register is shared with a user EEPROM byte. This address location is not affected by any reset signals. Reading this location returns the user EEPROM byte. When the COPC is cleared, only the final four bits used to count eight RTI cycles are cleared. The COP watchdog timer can be enabled/disabled by a mask option register bit. $03F0 Read: Write: Reset: — — — — — — — Bit 7 6 5 4 3 2 1 Bit 0 COP Watchdog Timer Freescale Semiconductor, Inc... Reading $03F0 returns the contents of User EEPROM COPC 0 = Unimplemented Figure 8-4. COPR Watchdog Timer Location 8.5 Operating During Stop Mode The timer system is cleared when going into stop mode. When STOP is exited by an external interrupt or an external RESET, the internal oscillator resumes, followed by a 16 or 4064 cycle internal processor oscillator stabilization delay. The timer system counter is then cleared and operation resumes. If the STOP instruction is disabled by mask option register bit to create the halt mode, the effects on the timer are as described in 8.6 Operating During Wait Mode. MC68HC805K3 — Rev. 1.0 76 8-Bit Timer For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Operating During Wait Mode 8.6 Operating During Wait Mode The CPU clock halts during the wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt or custom periodic interrupt causes the processor to exit the wait mode. Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 8-Bit Timer For More Information On This Product, Go to: www.freescale.com 77 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 78 8-Bit Timer For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 9. Personality EEPROM 9.1 Contents Freescale Semiconductor, Inc... 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3 PEEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.3.1 PEEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . .81 9.3.2 PEEPROM Status/Control Register (PESCR) . . . . . . . . . .82 9.4 PEEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 9.2 Introduction The MC68HC805K3 contains a 128-bit personality EEPROM (PEEPROM) for storage of variables or user data. These 128 bits are provided as a simple EEPROM array and control logic that requires serial reading of the data. The PEEPROM may be accessed via software programmed into the user EEPROM through two registers that directly interface with the PEEPROM array. The actual implementation of the software varies depending on customer requirements. The PEEPROM array is arranged as 16 bytes (rows) with a separate column select for each bit (column) in a byte. The column select connects the bit to a single sense amplifier as shown in the block diagram of the PEEPROM module in Figure 9-1. An on-chip charge pump is provided to allow programming and erasure of the Personality EEPROM if the supply voltage to the VDD pin is at least 3.0 Vdc. NOTE: Programming and erasure of the personality EEPROM may only be performed if VDD > 3.0 Vdc. MC68HC805K3 — Rev. 1.0 Personality EEPROM For More Information On This Product, Go to: www.freescale.com 79 Freescale Semiconductor, Inc. General Release Specification 9.5 PEEPROM Read Access 86Introduction HC05 DATA BUS CPCLK VDD BUS CLOCK (PH2) ON-CHIP CHARGE PUMP MUX INTERNAL RING OSCILLATOR PERSONALITY EEPROM STATUS/CONTROL REGISTER CPEN PEPCZF PEDATA SINGLE SENSE AMP 8 Freescale Semiconductor, Inc... PEPGM/PEBYTE/PEBULK VPP SWITCH VPP SWITCH PERSONALITY EEPROM BIT SELECT REGISTER 0-2 8-TO-1 DECODE & MUX EACH ROW IS A BYTE 8 3-6 16-TO-1 DECODE & MUX 16 x 8 EEPROM ARRAY Figure 9-1. Personality EEPROM Block Diagram MC68HC805K3 — Rev. 1.0 80 Personality EEPROM For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification PEEPROM Registers 9.3 PEEPROM Registers Two register locations are used to support the EEPROM array. These are the bit select and status/control registers. 9.3.1 PEEPROM Bit Select Register (PEBSR) The PEEPROM bit select register is located at $000E and contains the enable signals for the rows and columns to access the bits in the EEPROM array. The placement of these bits is shown below. The output of this register is connected to two decoders, one for the array column and one for the array row. A byte in the PEEPROM is defined by the upper four bits in the 7-bit address in the PEBSR (PEB3 through PEB6) and the bit within that byte is defined by the lower three bits in the 7-bit address in the PEBSR (PEB0 through PEB2). The upper bit in the PEBSR (PEB7) may be used as a storage location. All of the bits in the PEBSR register are cleared by reset. Bit (Column in Byte (Row) of PEEPROM 0 3 PEB3 0 2 2 PEB2 0 1 1 PEB1 0 0 Bit 0 PEB0 0 Freescale Semiconductor, Inc... Byte (Row) of PEEPROM 3 $0E Read: PEB7 Write: Reset: 0 0 0 0 PEB6 PEB5 PEB4 Bit 7 6 2 5 1 4 Figure 9-2. PEBSR Select Register MC68HC805K3 — Rev. 1.0 Personality EEPROM For More Information On This Product, Go to: www.freescale.com 81 Freescale Semiconductor, Inc. General Release Specification PEEPROM Registers 9.3.2 PEEPROM Status/Control Register (PESCR) The PEEPROM Status/Control Register is located at $000F and contains 5 user bits, as shown in Figure 9-3. Bit 1 is unimplemented and always reads as a logic zero. The states of all bits except PEPCZF and PEDATA are cleared by reset. The PEPCZF is set by reset; and the state of the PEDATA bit following reset is dependent on the stored data in bit 0 of the PEEPROM array. $0F Bit 7 6 PEBULK Write: Reset: 1 0 5 4 3 CPEN 0 2 CPCLK 0 0 1 1 0 Bit 0 PEPCZF Freescale Semiconductor, Inc... Read: PEDATA PEPGM PEBYTE (DATA IN) 0 0 = Unimplemented Figure 9-3. PESCR Status/Control Register PEPCZF — PEEPROM Column Zero Flag The PEPCZF is a flag bit that is set to a logical one when the first column (COL0) of the EEPROM array is selected. If any other column is selected, the PEPCZF flag bit is cleared. This flag bit can be used to reduce the software code required to access one byte of the PEEPROM. The PEPCZF is set following a reset, since the first column is selected by the reset of the PEBSR. The software code given in Table 9-1 is suggested for reading one byte from the PEEPROM. MC68HC805K3 — Rev. 1.0 82 Personality EEPROM For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification PEEPROM Registers Table 9-1. Software to Read PEEPROM pebsr pescr ram equ equ equ lda sta clr peep_rd rol ror inc brclr $000e $000f $000c #$xy pebsr ram pescr ram pebsr 0,pescr,peep_rd ; xy is base addresses and should start on ; a first column (i.e., $00, $08, $10, $18, etc). ; clear ram location used for final result ; ; ; ; ; ; c = pedata (c = carry bit) ram = c go to next bit in array. care data here, loop until all bytes read peep_rd loop ends when PEPCZF = 1. At end of loop, ram contains one row of PEEP data. Freescale Semiconductor, Inc... CPCLK — Charge Pump Clock Source The CPCLK bit is a read/write bit that controls the source of the clock for the charge pump. When the CPCLK bit is set, the charge pump is driven by the PH2 bus clock. When the CPCLK bit is cleared, the charge pump is driven from an internal ring oscillator. The CPCLK bit is cleared when the device is in reset. In systems where the desired PH2 clock rate is below 1 MHz, the CPCLK bit should be cleared to enable the internal ring oscillator. Otherwise, the charge pump does not attain sufficient program/erase voltage because the clock source is too slow. CPEN — Charge Pump Enable The CPEN bit is a read/write bit to control the on-chip charge pump for programming and erasure of the Personality EEPROM. This charge pump is only intended for use at VDD supply voltages above 3.0 Vdc. The charge pump is activated when both the CPEN bit is set and one of the program or erase bits is also set (PEPGM, PEBYTE, or PBULK). The charge pump supplies the required programming voltage to the Personality EEPROM array. Once activated, and after startup time tCP, the charge pump continues to operate until all the program and erase bits are cleared. NOTE: If the personality EEPROM is read while the CPEN bit is set, the data is unknown. MC68HC805K3 — Rev. 1.0 Personality EEPROM For More Information On This Product, Go to: www.freescale.com 83 Freescale Semiconductor, Inc. General Release Specification PEEPROM Registers The charge pump must always be used to program or erase bits in the Personality EEPROM. The CPEN bit is cleared when the device is in reset. NOTE: Setting the CPEN bit can activate the charge pump. However, all the PEPGM, PEBYTE, PEBULK, and CPEN bits must be cleared to deactivate the charge pump. If the charge pump is left running, the overall device IDD current increases. PEBYTE — PEEPROM Byte Erase Freescale Semiconductor, Inc... The PEBYTE bit is a read/write bit to control the switches that apply the internally provided charge pump programming voltage to a row in the PEEPROM array that is to be erased. When the PEBYTE bit is set to a logical one, a logical zero is stored to all bits in the same row of the PEEPROM array, as specified by the upper four bits of the 7-bit address in the PEBSR. The PEBYTE bit should only be set if the PEPGM and PEBULK bits are cleared. If both the PEBYTE and PEBULK bits are set, the PEEPROM is bulk erased. The PEBYTE bit is cleared when the device is reset. PEPGM — PEEPROM Program Control The PEPGM bit is a read/write bit to control the switches that apply the internally provided charge pump programming voltage to the device in the PEEPROM array that is to be programmed. When the PEPGM bit is set to a logical one, a logical one is stored to the PEEPROM array element specified by the address in the PEBSR. Since the state of the PEPGM bit determines the state of the programmed bit in the PEEPROM array, the PEPGM bit is similar to a DATA IN bit. The PEPGM bit should be set only if the PEBYTE and PEBULK bits are cleared. The PEPGM bit is cleared when the device is reset. NOTE: Only one of the PEPGM, PEBYTE, or PEBULK bits should be set at any one time. MC68HC805K3 — Rev. 1.0 84 Personality EEPROM For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification PEEPROM Registers NOTE: Always clear the PEPGM bit before altering the addressing bits in the PEBSR. Otherwise, intermediate locations may be affected if the programming voltage is present. PEBULK — PEEPROM Bulk Erase The PEBULK bit is a read/write bit to control the switches that apply an internally provided programming voltage to all the bits in the PEEPROM array that are to be erased. When the PEBULK bit is set to a logical one, a logical zero is stored to all bits of the PEEPROM array regardless of the bit address specified in the PEBSR. The PEBULK bit should only be set if the PEBYTE and PEPGM bits are cleared. If both the PEBYTE and PEBULK bits are set, the personality EEPROM is bulk erased. The PEBULK bit is cleared when the device is reset. PEDATA — PEEPROM DATA The PEDATA bit is a read-only bit that reflects the state of the PEEPROM sense amplifier. The state of the PEDATA bit is only meaningful when the PEBYTE, PEPGM, PEBULK, and CPEN control bits are all zero. The state of the PEDATA bit following a reset is dependent on the stored data in bit 0 of the PEEPROM array. Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 Personality EEPROM For More Information On This Product, Go to: www.freescale.com 85 Freescale Semiconductor, Inc. General Release Specification 9.4 PEEPROM Programming The PEEPROM can be programmed using a Motorola programmer or in the user application if the VDD supply source is at least 3.0 Vdc. In the latter case, the programming software must be provided in the user EEPROM and use some external pins in either a serial or parallel method for data transfer and/or access. Each bit of the PEEPROM can be programmed as follows: 1. Write the desired bit location to be programmed into the PEBSR located at $000E. 2. Set the PEPGM and CPEN bits in the PESCR located at $000F. 3. Wait for a tEPGM time delay. 4. Clear the PEPGM and CPEN bits. The PEEPROM is then ready to be set up for another bit of data for programming. The programming of a PEEPROM bit only requires access of that bit through the PEBSR followed by setting the PEPGM and CPEN bits in the PESCR. Do not access any bits that are to be left unprogrammed (erased) until all the PEPGM, PEBYTE, PEBULK, and CPEN bits in the PESCR are cleared. Always clear the PEPGM, PEBYTE, PEBULK, and CPEN bits before altering the PEBSR register. PEEPROM Programming Freescale Semiconductor, Inc... 9.5 PEEPROM Read Access The contents of the PEEPROM are read by the following sequence: 1. Write the desired bit location to be read into the PEBSR located at $000E. 2. Read the state of the PEDATA bit in the PESCR located at $000F. 3. Store the state of the PEDATA bit into RAM or a register. 4. Select another bit by changing the PEBSR. 5. Continue reading and storing the PEDATA bit states until all the required PEEPROM data has been accessed. MC68HC805K3 — Rev. 1.0 86 Personality EEPROM For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification PEEPROM Read Access Reading the PEEPROM is easiest when each row in the PEEPROM array is mapped to contain one byte of data. Selecting a column zero bit selects the first bit in the row; and incrementing the PEEPROM bit select register (PEBSR) selects the next (column 1) bit from the same row. Incrementing the PEBSR seven more times selects the remaining bits of the row and carries over to select column zero of the next row, thereby setting the column zero flag, PEPCZF in the PESCR. The number of increments per row can be controlled by looping on a test of the PEPCZF flag bit. Freescale Semiconductor, Inc... The complete array can be easily accessed by starting with $7F for the PEBSR and decrementing the PEBSR after each access of the PEDATA bit. The decrement sequence can end when the contents of the PEBSR are zero. NOTE: One byte of data from the PEEPROM can be re-created in the PEBSR itself. This can be done if the read routine builds the 8-bit data byte in the index register or the accumulator and then transfers that result to the PEBSR when completed. Subsequent reads of the PEBSR quickly yield that retrieved data byte. MC68HC805K3 — Rev. 1.0 Personality EEPROM For More Information On This Product, Go to: www.freescale.com 87 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 88 Personality EEPROM For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 10. User Program EEPROM 10.1 Contents Freescale Semiconductor, Inc... 10.2 10.3 10.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 10.2 Introduction The user EEPROM consists of 920 bytes of user EEPROM from $0020 to $00BF and $0100 to $03F7, and 8 bytes of user vector EEPROM from $03F8 to $03FF. The COP reset address is located within the main EEPROM address space at $03F0. It may be used as a user EEPROM location and is included in the available user EEPROM space previously disclosed. 10.3 EEPROM Programming The MC68HC805K3 user EEPROM and MOR can only be programmed using the appropriate programming board available from Motorola. 10.4 EEPROM Security The MC68HC805K3 programmer allows the user to optionally select EEPROM security such that an attempt to enter any non-user operating mode will initiate an automatic bulk erasure of all EEPROM locations including the PEEP. Prior to programming the device, the array is also bulk erased automatically. MC68HC805K3 — Rev. 1.0 User Program EEPROM For More Information On This Product, Go to: www.freescale.com 89 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 90 User Program EEPROM For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 11. Instruction Set 11.1 Contents Freescale Semiconductor, Inc... 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 11.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . .96 11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .97 11.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .98 11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .100 11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 MC68HC805K3 — Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com 91 Freescale Semiconductor, Inc. General Release Specification 11.2 Introduction The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator. Introduction Freescale Semiconductor, Inc... 11.3 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: • • • • • • • • Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative MC68HC805K3 — Rev. 1.0 92 Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Addressing Modes 11.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 11.3.2 Immediate Freescale Semiconductor, Inc... Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 11.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. 11.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. MC68HC805K3 — Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com 93 Freescale Semiconductor, Inc. General Release Specification 11.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. Addressing Modes Freescale Semiconductor, Inc... 11.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 11.3.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. MC68HC805K3 — Rev. 1.0 94 Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Instruction Types 11.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. Freescale Semiconductor, Inc... When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 11.4 Instruction Types The MCU instructions fall into the following five categories: • • • • • Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions MC68HC805K3 — Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com 95 Freescale Semiconductor, Inc. General Release Specification 11.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 11-1. Register/Memory Instructions Instruction Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB Instruction Types Freescale Semiconductor, Inc... Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator MC68HC805K3 — Rev. 1.0 96 Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Instruction Types 11.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. Table 11-2. Read-Modify-Write Instructions Instruction Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2) Freescale Semiconductor, Inc... Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One’s Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two’s Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. MC68HC805K3 — Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com 97 Freescale Semiconductor, Inc. General Release Specification 11.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Instruction Types Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 98 Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Instruction Types Table 11-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR Freescale Semiconductor, Inc... Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine MC68HC805K3 — Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com 99 Freescale Semiconductor, Inc. General Release Specification 11.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 11-4. Bit Manipulation Instructions Instruction Mnemonic BCLR BRCLR BRSET BSET Instruction Types Freescale Semiconductor, Inc... Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set MC68HC805K3 — Rev. 1.0 100 Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification Instruction Types 11.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 11-5. Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT Freescale Semiconductor, Inc... No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts MC68HC805K3 — Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com 101 Freescale Semiconductor, Inc. General Release Specification 11.5 Instruction Set Summary Table 11-6. Instruction Set Summary Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel Instruction Set Summary Operation Description H I NZC Add with Carry A ← (A) + (M) + (C) ¤— ¤ ¤ ¤ Freescale Semiconductor, Inc... IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL ii A9 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 ii A4 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3 Add without Carry A ← (A) + (M) ¤— ¤ ¤ ¤ Logical AND A ← (A) ∧ (M) —— ¤ ¤— Arithmetic Shift Left (Same as LSL) C b7 b0 0 —— ¤ ¤ ¤ ff dd Arithmetic Shift Right b7 b0 C —— ¤ ¤ ¤ ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? C = 0 ————— BCLR n opr Clear Bit n Mn ← 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ————— DIR (b4) DIR (b5) DIR (b6) DIR (b7) ————— ————— ————— ————— ————— ————— REL REL REL REL REL REL BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same PC ← (PC) + 2 + rel ? C = 1 PC ← (PC) + 2 + rel ? Z = 1 PC ← (PC) + 2 + rel ? H = 0 PC ← (PC) + 2 + rel ? H = 1 PC ← (PC) + 2 + rel ? C ∨ Z = 0 PC ← (PC) + 2 + rel ? C = 0 MC68HC805K3 — Rev. 1.0 102 Instruction Set For More Information On This Product, Go to: www.freescale.com Cycles Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. General Release Specification Instruction Set Summary Table 11-6. Instruction Set Summary (Continued) Opcode Source Form BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operation Branch if IRQ Pin High Branch if IRQ Pin Low Description PC ← (PC) + 2 + rel ? IRQ = 1 PC ← (PC) + 2 + rel ? IRQ = 0 H I NZC ————— ————— REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL 2F 2E A5 B5 C5 D5 E5 F5 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr ii dd hh ll ee ff ff rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd Bit Test Accumulator with Memory Byte (A) ∧ (M) —— ¤ ¤— Freescale Semiconductor, Inc... Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC ← (PC) + 2 + rel ? C = 1 PC ← (PC) + 2 + rel ? C ∨ Z = 1 PC ← (PC) + 2 + rel ? I = 0 PC ← (PC) + 2 + rel ? N = 1 PC ← (PC) + 2 + rel ? I = 1 PC ← (PC) + 2 + rel ? Z = 0 PC ← (PC) + 2 + rel ? N = 0 PC ← (PC) + 2 + rel ? 1 = 1 ————— ————— ————— ————— ————— ————— ————— ————— BRCLR n opr rel Branch if Bit n Clear PC ← (PC) + 2 + rel ? Mn = 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ———— ¤ DIR (b4) DIR (b5) DIR (b6) DIR (b7) ————— REL BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ———— ¤ DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ————— DIR (b4) DIR (b5) DIR (b6) DIR (b7) BSET n opr Set Bit n Mn ← 1 BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel C←0 I←0 ————— REL AD rr CLC CLI Clear Carry Bit Clear Interrupt Mask ———— 0 — 0 ——— INH INH 98 9A MC68HC805K3 — Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com 103 Cycles 3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 2 2 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. General Release Specification Instruction Set Summary Table 11-6. Instruction Set Summary (Continued) Opcode Source Form CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Operation Description M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 H I NZC Clear Byte —— 0 1 — DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX 3F 4F 5F 6F 7F dd ff Freescale Semiconductor, Inc... Compare Accumulator with Memory Byte (A) – (M) —— ¤ ¤ ¤ ii A1 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5 Complement Byte (One’s Complement) M ← (M) = $FF – (M) A ← (A) = $FF – (A) X ← (X) = $FF – (X) M ← (M) = $FF – (M) M ← (M) = $FF – (M) —— ¤ ¤ 1 ff Compare Index Register with Memory Byte (X) – (M) —— ¤ ¤ ¤ ii A3 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5 Decrement Byte M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 —— ¤ ¤— ff EXCLUSIVE OR Accumulator with Memory Byte A ← (A) ⊕ (M) —— ¤ ¤— ii A8 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5 Increment Byte M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 —— ¤ ¤— ff Unconditional Jump PC ← Jump Address ————— BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2 MC68HC805K3 — Rev. 1.0 104 Instruction Set For More Information On This Product, Go to: www.freescale.com Cycles 5 3 3 6 5 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. General Release Specification Instruction Set Summary Table 11-6. Instruction Set Summary (Continued) Opcode Source Form JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X Operation Description H I NZC PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Effective Address Jump to Subroutine ————— DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 ii A6 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D AA BA CA DA EA FA 39 49 59 69 79 ii dd hh ll ee ff ff dd dd dd 5 3 3 6 5 5 3 3 6 5 11 5 3 3 6 5 2 2 3 4 5 4 3 5 3 3 6 5 Freescale Semiconductor, Inc... Load Accumulator with Memory Byte A ← (M) —— ¤ ¤— Load Index Register with Memory Byte X ← (M) —— ¤ ¤— Logical Shift Left (Same as ASL) C b7 b0 0 —— ¤ ¤ ¤ ff dd Logical Shift Right 0 b7 b0 C —— 0 ¤ ¤ ff Unsigned Multiply X : A ← (X) × (A) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) 0 ——— 0 Negate Byte (Two’s Complement) —— ¤ ¤ ¤ ff No Operation ————— Logical OR Accumulator with Memory A ← (A) ∨ (M) —— ¤ ¤— Rotate Byte Left through Carry Bit C b7 b0 —— ¤ ¤ ¤ ff MC68HC805K3 — Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com 105 Cycles Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. General Release Specification Instruction Set Summary Table 11-6. Instruction Set Summary (Continued) Opcode Source Form ROR opr RORA RORX ROR opr,X ROR ,X RSP Operation Description H I NZC Rotate Byte Right through Carry Bit b7 b0 C —— ¤ ¤ ¤ DIR INH INH IX1 IX INH 36 46 56 66 76 9C dd ff Reset Stack Pointer SP ← $00FF SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) ————— Freescale Semiconductor, Inc... RTI Return from Interrupt ¤ ¤ ¤ ¤ ¤ INH 80 RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Return from Subroutine ————— INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX 81 Subtract Memory Byte and Carry Bit from Accumulator A ← (A) – (M) – (C) —— ¤ ¤ ¤ ii A2 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B B7 C7 D7 E7 F7 8E BF CF DF EF FF dd hh ll ee ff ff dd hh ll ee ff ff 2 2 4 5 6 5 4 2 4 5 6 5 4 Set Carry Bit Set Interrupt Mask C←1 I←1 ———— 1 — 1 ——— Store Accumulator in Memory M ← (A) —— ¤ ¤— Stop Oscillator and Enable IRQ Pin — 0 ——— Store Index Register In Memory M ← (X) —— ¤ ¤— Subtract Memory Byte from Accumulator A ← (A) – (M) —— ¤ ¤ ¤ ii A0 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3 SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) — 1 ——— SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte X ← (A) ————— INH 83 10 TAX Transfer Accumulator to Index Register INH 97 MC68HC805K3 — Rev. 1.0 106 Instruction Set For More Information On This Product, Go to: www.freescale.com Cycles 5 3 3 6 5 2 9 6 2 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. General Release Specification Instruction Set Summary Table 11-6. Instruction Set Summary (Continued) Opcode Source Form TST opr TSTA TSTX TST opr,X TST ,X TXA Operation Description H I NZC Test Memory Byte for Negative or Zero (M) – $00 —— ¤ ¤— DIR INH INH IX1 IX INH INH 3D 4D 5D 6D 7D 9F 8F dd ff Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit A ← (X) ————— — 0——— Freescale Semiconductor, Inc... WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n 2 opr PC PCH PCL REL rel rr SP X Z # ∧ ∨ ⊕ () –( ) ← ? : ¤ — Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Loaded with If Concatenated with Set or cleared Not affected MC68HC805K3 — Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com 107 Cycles 4 3 3 5 4 2 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc... Table 11-7. Opcode Map Branch Register/Memory IMM IX F MSB LSB 108 Read-Modify-Write Control IX INH INH IX1 E 9 A B C D IX2 8 EXT 7 DIR DIR INH INH 5 6 4 3 IX1 REL 2 0 1 1 1 2 3 3 3 3 3 2 2 2 2 1 1 1 1 1 5 CLR 2 DIR 3 CLRX 1 INH 3 CLRA 1 INH 6 CLR 2 IX1 5 CLR 1 IX 2 2 2 2 2 2 2 3 3 3 3 3 3 3 2 TXA 1 INH MSB LSB 2 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 5 NEG 2 DIR 3 NEGX 1 INH 6 NEG 2 IX1 5 NEG 1 IX 2 2 2 10 SWI 1 INH 2 2 2 2 1 1 1 1 1 2 2 2 2 3 2 3 3 2 3 3 2 2 2 3 3 2 2 3 3 9 RTI 1 INH 6 RTS 1 INH 3 NEGA 1 INH Bit Manipulation DIR DIR MSB LSB 0 1 0 1 1 2 3 4 5 6 7 8 9 A B C D E F General Release 2 1 3 4 11 MUL INH 3 5 COM COMA 2 DIR 1 INH 3 5 LSR LSRA 2 DIR 1 INH 3 COMX 1 INH 3 LSRX 1 INH 6 COM 2 IX1 6 LSR 2 IX1 5 COM 1 IX 5 LSR 1 IX 5 6 2 SUB IMM 2 CMP IMM 2 SBC IMM 2 CPX IMM 2 AND IMM 2 BIT IMM 2 LDA IMM 7 8 Instruction Set Summary 9 A 5 ROR DIR 5 ASR 2 DIR 5 ASL/LSL 2 DIR 5 ROL 2 DIR 5 DEC 2 DIR 5 ROR IX 5 ASR 1 IX 5 ASL/LSL 1 IX 5 ROL 1 IX 5 DEC 1 IX 2 EOR IMM 2 ADC IMM 2 ORA IMM 2 ADD IMM 3 3 6 RORA ROR RORX INH 1 INH 2 IX1 3 3 6 ASRA ASR ASRX 1 INH 1 INH 2 IX1 3 3 6 ASLA/LSLA ASLX/LSLX ASL/LSL 1 INH 1 INH 2 IX1 3 3 6 ROLA ROL ROLX 1 INH 1 INH 2 IX1 3 3 6 DECA DEC DECX 1 INH 1 INH 2 IX1 B Freescale Semiconductor, Inc. Instruction Set For More Information On This Product, Go to: www.freescale.com 5 INC 2 DIR 4 TST 2 DIR 3 INCX 1 INH 3 TSTX 1 INH 6 INC 2 IX1 5 TST 2 IX1 5 INC 1 IX 4 TST 1 IX 3 INCA 1 INH 3 TSTA 1 INH 2 TAX INH 2 CLC INH 2 SEC INH 2 CLI INH 2 SEI INH 2 RSP INH 2 NOP INH 6 BSR REL 2 2 LDX 2 IMM 2 2 STOP INH 2 WAIT 1 INH C D E F 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS/BLO 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL 3 SUB DIR 3 CMP DIR 3 SBC DIR 3 CPX DIR 3 AND DIR 3 BIT DIR 3 LDA DIR 4 STA DIR 3 EOR DIR 3 ADC DIR 3 ORA DIR 3 ADD DIR 2 JMP DIR 5 JSR DIR 3 LDX DIR 4 STX DIR 4 SUB EXT 4 CMP EXT 4 SBC EXT 4 CPX EXT 4 AND EXT 4 BIT EXT 4 LDA EXT 5 STA EXT 4 EOR EXT 4 ADC EXT 4 ORA EXT 4 ADD EXT 3 JMP EXT 6 JSR EXT 4 LDX EXT 5 STX EXT 5 SUB IX2 5 CMP IX2 5 SBC IX2 5 CPX IX2 5 AND IX2 5 BIT IX2 5 LDA IX2 6 STA IX2 5 EOR IX2 5 ADC IX2 5 ORA IX2 5 ADD IX2 4 JMP IX2 7 JSR IX2 5 LDX IX2 6 STX IX2 5 BSET0 2 DIR 5 BCLR0 2 DIR 5 BSET1 2 DIR 5 BCLR1 2 DIR 5 BSET2 2 DIR 5 BCLR2 2 DIR 5 BSET3 2 DIR 5 BCLR3 2 DIR 5 BSET4 2 DIR 5 BCLR4 2 DIR 5 BSET5 2 DIR 5 BCLR5 2 DIR 5 BSET6 2 DIR 5 BCLR6 2 DIR 5 BSET7 2 DIR 5 BCLR7 2 DIR 4 SUB IX1 4 CMP IX1 4 SBC IX1 4 CPX IX1 4 AND IX1 4 BIT IX1 4 LDA IX1 5 STA IX1 4 EOR IX1 4 ADC IX1 4 ORA IX1 4 ADD IX1 3 JMP IX1 6 JSR IX1 4 LDX IX1 5 STX IX1 3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX 0 LSB of Opcode in Hexadecimal MSB of Opcode in Hexadecimal MC68HC805K3 — Rev. 1.0 REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset INH = Inherent IMM = Immediate DIR = Direct EXT = Extended 0 5 BRSET0 3 DIR Number of Cycles Opcode Mnemonic Number of Bytes/Addressing Mode Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 12. Electrical Specifications 12.1 Contents Freescale Semiconductor, Inc... 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .111 3.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .112 5.0 Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.0 Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 12.2 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD Rating Supply Voltage Input Voltage Storage Temperature Range Symbol VDD VIN TSTG Value –0.3 to + 7.0 VSS –0.3 to VDD + –0.3 –65 to + 150 Unit V V °C NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 12.5 5.0 Volt DC Electrical Characteristics1 and 12.6 3.0 Volt DC Electrical Characteristics1 for guaranteed operating conditions. MC68HC805K3 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com 109 Freescale Semiconductor, Inc. General Release Specification 12.3 Operating Range Characteristic Operating Temperature Range MC68HC805K3 (Standard) MC68HC805K3 (Extended) Supply Voltage Range for Internal Charge Pump Operation Symbol TA Value TL to TH 0 to +70 –40 to +85 3.0 to 5.5 Unit °C Operating Range VDDCP V Freescale Semiconductor, Inc... 12.4 Thermal Characteristics Characteristic Thermal Resistance PDIP SOIC Symbol θJA Value 100 140 Unit °C/W MC68HC805K3 — Rev. 1.0 110 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification 5.0 Volt DC Electrical Characteristics1 12.5 5.0 Volt DC Electrical Characteristics1 Characteristic Output High Voltage (ILOAD = –0.8 mA) PA7–PA0, PB1/OSC3, PB0 Output Low Voltage PA3–PA0, PB1/OSC3, PB0 (ILOAD = 1.6 mA) PA7–PA4 (ILOAD = 8.0 mA) Input High Voltage PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1 Symbol VOH VOL VIH VIL Min VDD –0.8 — — 0.7 x VDD VSS — — IDD — — — IIL IIL — 100 — — — 300 500 600 1 nA nA nA µA µA Typ — Max — Unit V — — — — 0.4 0.4 VDD 0.2 x VDD 5.0 3.0 V V V Freescale Semiconductor, Inc... Input Low Voltage PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1 Supply Current (fOP = 2 MHz, see Notes 4–8) Run Wait Stop 25 °C 0 °C to +70 °C (Standard) –40 °C to +85 °C (Extended) I/O Ports Hi-Z Leakage Current PA0–PA7, PB0–PB1 (Without Pulldowns Activated) Input Pulldown Current PA0–PA7, PB0–PB1 Input Current IRQ, OSC1 RESET (VIN = VIH) RESET (VIN = VIL) RESET, Internal Pulldown Device Capacitance Ports (As Input or Output) RESET, IRQ, OSC1, OSC2 Crystal/Ceramic Resonator Oscillator Mode Internal Resistor OSC1 to OSC2 — — mA mA 50 100 200 IIN IIN COUT CIN ROSC — — — 1.0 — — 1.0 — 15 50 4.0 — — 2.0 1 — — 8.0 12 8 3.0 µA mA pF MΩ NOTES: 1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 °C only. 4. Wait IDD: Only timer system active 5. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1, all inputs 0.2 Vdc from rail; no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 6. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc. 7. Stop IDD measured with OSC1 = VDD, RESET open 8. Wait IDD is affected linearly by the OSC2 capacitance. MC68HC805K3 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com 111 Freescale Semiconductor, Inc. General Release Specification 3.0 Volt DC Electrical Characteristics1 12.6 3.0 Volt DC Electrical Characteristics1 Characteristic Output High Voltage (ILOAD = –0.4 mA) PA7–PA0, PB1/OSC3, PB0 Output Low Voltage PA3–PA0, PB1/OSC3, PB0 (ILOAD = 0.4 mA) PA7–PA4 (ILOAD = 3.0 mA) Input High Voltage PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1 Symbol VOH Min VDD –0.3 Typ — Max — Unit V VOL VIH VIL — — 0.7 x VDD VSS — — — — — — 0.3 0.3 VDD 0.2 x VDD 2.0 0.75 200 275 300 1 V V V Freescale Semiconductor, Inc... Input Low Voltage PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1 Supply Current (fOP = 1 MHz, see Notes 4–8) Run Wait Stop 25 °C 0 °C to +70 °C (Standard) –40 °C to +85 °C (Extended) I/O Ports Hi-Z Leakage Current PA0–PA7, PB0–PB1 (Without Individual Pulldown Activated) Input Pulldown Current PA0–PA7, PB0–PB1 Input Current IRQ, OSC1 RESET (VIN = VIH) RESET (VIN = VIL) RESET, Internal Pulldown Device Capacitance Ports (As Input or Output) RESET, IRQ, OSC1, OSC2 Crystal/Ceramic Resonator Oscillator Mode Internal Resistor OSC1 to OSC2 — — 50 — — — mA mA nA nA nA µA µA IDD — — — IIL IIL — 25 50 100 IIN IIN COUT CIN ROSC — — — 0.2 — — 1.0 — 10 30 2.0 — — 2.0 1 — — 4.0 12 8 3.0 µA mA pF MΩ NOTES: 1. VDD = 3.0 Vdc ± 0.5 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise note 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 °C only. 4. Wait IDD: Only timer system active 5. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1, all inputs 0.2 Vdc from rail; no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 6. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc. 7. Stop IDD measured with OSC1 = VDD, RESET open 8. Wait IDD is affected linearly by the OSC2 capacitance. MC68HC805K3 — Rev. 1.0 112 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification 5.0 Volt Control Timing1 12.7 5.0 Volt Control Timing1 Characteristic Frequency of Operation 3-Pin RC Oscillator Option 2-Pin RC Oscillator Option Crystal Oscillator Option External Clock Source Internal Operating Frequency RC Oscillator (fOSC ÷ 2) Crystal Oscillator (fOSC ÷ 2) External Clock (fOSC ÷ 2) Cycle Time (1 ÷ fOP) RC Oscillator Stabilization Time Crystal Oscillator Startup Time (Crystal Oscillator Option) Stop Recovery Startup Time (Crystal Oscillator Option) RESET Pulse Width Low Timer Resolution (see Note 2) IRQ Interrupt Pulse Width Low (Edge-Triggered) IRQ Interrupt Pulse Period PA0 through PA3 Interrupt Pulse Width High (Edge-Triggered) PA0 through PA3 Interrupt Pulse Period OSC1 Pulse Width 2-Pin RC Oscillator Frequency Combined Stability (see Note 4) fOSC = 500 kHz 3-Pin RC Oscillator Frequency Combined Stability (see Note 4) fOSC = 500 kHz PEEPROM Bit Programming Time PEEPROM Byte Erase Time PEEPROM Bulk Erase Time PEEPROM Charge Pump Startup Time Symbol Min 0.1 0.1 0.5 DC 0.5 1.0 DC 500 — — — 1.5 4.0 125 Note 3 125 Note 3 90 — — — — — — Max 1.25 2.7 4.0 4.0 1.0 2.0 2.0 — 1 100 100 — — — — — — — ±35 ±25 10 10 30 1 Unit fOSC MHz fOP tCYC tRCON tOXON tILCH tRL tRESL tILIH tILIL tIHIL tIHIH t ∆fOSC ∆fOSC tEPGM tERBT tERBK tCP MHz Freescale Semiconductor, Inc... ns ms ms ms tCYC tCYC ns tCYC ns tCYC ns % % ms ms ms ms NOTES: 1.VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise note 2.The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3.The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC. 4.Effects of processing, temperature, and supply voltage (including tolerances of external 1% R and 2% C). MC68HC805K3 — Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com 113 Freescale Semiconductor, Inc. General Release Specification 12.8 3.0 Volt Control Timing1 Characteristic Frequency of Operation 3-Pin RC Oscillator Option 2-Pin RC Oscillator Option Crystal Oscillator Option External Clock Source Internal Operating Frequency RC Oscillator (fOSC ÷ 2) Crystal Oscillator (fOSC ÷ 2) External Clock (fOSC ÷ 2) Cycle Time (1 ÷ fOP) RC Oscillator Stabilization Time Crystal Oscillator Startup Time (Crystal Oscillator Option) Stop Recovery Startup Time (Crystal Oscillator Option) RESET Pulse Width Low Timer Resolution (see Note 2) IRQ Interrupt Pulse Width Low (Edge-Triggered) IRQ Interrupt Pulse Period PA0 through PA3 Interrupt Pulse Width High (Edge-Triggered) PA0 through PA3 Interrupt Pulse Period OSC1 Pulse Width 2-Pin RC Oscillator Frequency Combined Stability (see Note 4) fOSC = 500 kHz 3-Pin RC Oscillator Frequency Combined Stability (see Note 4) fOSC = 500 kHz Symbol Min 0.1 0.1 0.4 DC — — DC 2.0 — — — 1.5 4.0 125 Note 3 125 Note 3 90 — — Max 0.6 0.7 1.0 1.0 350 500 500 — 1 100 100 — — — — — — — ±35 ±15 Unit 3.0 Volt Control Timing1 fOSC MHz fOP tCYC tRCON tOXON tILCH tRL tRESL tILIH tILIL tIHIL tIHIH t ∆fOSC ∆fOSC kHz µs ms ms ms tCYC tCYC ns tCYC ns tCYC ns % % Freescale Semiconductor, Inc... NOTES: 1. VDD = 3.0 Vdc ± 0.5 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted 2. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC. 4. Effects of processing, temperature, and supply voltage (including tolerances of external 1% R and 2% C). MC68HC805K3 — Rev. 1.0 114 Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 13. Mechnical Specifications 13.1 Contents Freescale Semiconductor, Inc... 13.2 13.3 13.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Dual-In-Line Package (Case 648) . . . . . . . . . . . . . . . . . . . . .116 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .116 13.2 Introduction The MC68HC805K3 is available in the following packages: • • 648 — Plastic dual in-line package (PDIP) 751 — Small outline integrated circuit (SOIC) The following figures show the latest packages at the time of this publication. To make sure that you have the latest package specifications, contact one of the following: • • Local Motorola Sales Office Motorola Mfax – Phone 602-244-6609 – EMAIL rmfax0@email.sps.mot.com • Worldwide Web (wwweb) at http://design-net.com Follow Mfax or wwweb on-line instructions to retrieve the current mechanical specifications. MC68HC805K3 — Rev. 1.0 Mechnical Specifications For More Information On This Product, Go to: www.freescale.com 115 Freescale Semiconductor, Inc. General Release Specification Dual-In-Line Package (Case 648) 13.3 Dual-In-Line Package (Case 648) -A16 9 B 1 8 INCHES MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0° 10° 0.51 1.01 F DIM MIN MAX C S -TSEATING PLANE L Freescale Semiconductor, Inc... H G D 16 PL K J M 0.25 (0.010) M T A M A B C D F G H J K L M S 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0° 10° 0.020 0.040 13.4 Small Outline Integrated Circuit (Case 751) -A16 9 -B- 8X P 0.010 (0.25) M B M 1 8 D 16X 0.010 (0.25) M T A S BS J F R C -TG 14X K SEATING PLANE DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 X 45 M MC68HC805K3 — Rev. 1.0 116 Mechnical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC805K3 Section 14. Ordering Information 14.1 Contents Freescale Semiconductor, Inc... 14.2 14.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 14.2 Introduction This section contains instructions for ordering custom-masked ROM MCUs. 14.3 MC Order Numbers The following table shows the MC order numbers for the available package types. MC Order Number MC68HC805K3P (Standard) MC68HC805K3CP (Extended) MC68HC805K3DW (Standard) MC68HC805K3CDW (Extended) NOTES: P = Plastic Dual In-Line Package DW = Small Outline Integrated Circuit (SOIC) Package Operating Temperature Range –0 ° to 70 °C –40 ° to 85 °C –0 ° to 70 °C –40 ° to 85 °C MC68HC805K3 — Rev. 1.0 Ordering Information For More Information On This Product, Go to: www.freescale.com 117 Freescale Semiconductor, Inc. General Release Specification Freescale Semiconductor, Inc... MC68HC805K3 — Rev. 1.0 118 Ordering Information For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064, Japan 0120 191014 +81 2666 8080 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Freescale Semiconductor, Inc... Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. For More Information On This Product, Go to: www.freescale.com HC805K3GRS/D