68HC805P18

Freescale Semiconductor, Inc. HC805P18GRS/D REV 1.0 68HC805P18 SPECIFICATION (General Release) Freescale Semiconductor, Inc... © December 7, 1995 CSIC System Design Group Austin, Texas For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Title SECTION 1 INTRODUCTION 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Port A (PA0 through PA7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Port B (PB5/SDO, PB6/SDI, and PB7/SCK). . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.8 Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.9 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.10 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Page Freescale Semiconductor, Inc... SECTION 2 MEMORY 2.1 2.2 2.3 2.4 2.5 2.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 User Mode Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 User EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 SECTION 3 CENTRAL PROCESSING UNIT 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.2 Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Rev. 1.0 iii For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph 3.2.3 3.2.4 3.2.5 Title Page Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 SECTION 4 INTERRUPTS Freescale Semiconductor, Inc... 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.2 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.3 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 SECTION 5 RESETS 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.3 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 SECTION 6 OPERATING MODES 6.1 6.2 6.2.1 6.2.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 User Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 STOP Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 iv For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Rev. 1.0 Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Title SECTION 7 INPUT/OUTPUT PORTS 7.1 7.2 7.3 7.4 7.5 7.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 I/O Port Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Page Freescale Semiconductor, Inc... SECTION 8 EEPROM 8.1 8.2 8.3 8.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 EEPROM Programming Register (EEPROG). . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Programming/Erasing Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Mask Option Registers (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 SECTION 9 ANALOG-TO-DIGITAL CONVERTER 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.3 9.3.1 9.3.2 9.3.3 9.4 9.5 9.6 9.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Conversion Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Multi-Channel Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 A/D Conversion Data Register (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 A/D Subsystem During Wait/Halt Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 A/D Subsystem Operation During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Rev. 1.0 For More Information On This Product, Go to: www.freescale.com v Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Title SECTION 10 16-BIT TIMER 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 Timer Status Register (TSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Timer Operation During Wait/Halt Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 Timer Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 Page Freescale Semiconductor, Inc... SECTION 11 SERIAL INPUT/OUTPUT PORT 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.3 Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3.1 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.3.2 SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3.3 SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 SECTION 12 INSTRUCTION SET 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2.1 Inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.4 Extended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.2.8 Relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3 Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 MC68HC805P18 Rev. 1.0 vi For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Title Page 12.3.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.3.4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.3.5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.4 Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 SECTION 13 ELECTRICAL SPECIFICATIONS Freescale Semiconductor, Inc... 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 Active Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 A/D Converter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 OSC Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 SECTION 14 MECHANICAL SPECIFICATIONS 14.1 14.2 14.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 28-Pin Dual In-Line Package (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 28-Pin Small Outline Package (Case #751F) . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 SECTION 15 ORDERING INFORMATION 15.1 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 APPENDIX A EMULATION Rev. 1.0 For More Information On This Product, Go to: www.freescale.com vii Freescale Semiconductor, Inc. LIST OF FIGURES Figure 1-1 1-2 1-3 Title Page Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 MC68HC805P18 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 MC68HC805P18 I/O and Control Registers Memory Map . . . . . . . . . . . . . . 2-4 MC68HC805P18 I/O and Control Registers $0000–$000F . . . . . . . . . . . . . 2-5 MC68HC805P18 I/O and Control Registers $0010-$001F. . . . . . . . . . . . . . 2-6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Interrupt Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Unimplemented Vector and COP Watchdog Timer Register . . . . . . . . . . . . 5-2 Bootloader Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Port A I/O Circuitry Port B I/O Circuitry Port C I/O Circuitry Port D I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Freescale Semiconductor, Inc... 2-1 2-2 2-3 2-4 3-1 3-2 4-1 4-2 5-1 5-2 6-1 6-2 7-1 7-2 7-3 7-4 8-1 8-2 8-3 9-1 9-2 10-1 10-2 10-3 10-4 10-5 EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 A/D Conversion Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Timer Registers (TMRH/TMRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Alternate Counter Registers (ACRH/ACRL) . . . . . . . . . . . . . . . . . . . . . . . . 10-4 State Timing Diagram for Timer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 State Timing Diagram for Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Rev. 1.0 For More Information On This Product, Go to: www.freescale.com ix Freescale Semiconductor, Inc. LIST OF FIGURES Figure 10-6 10-7 10-8 10-9 10-10 10-11 11-1 11-2 11-3 11-4 11-5 13-1 13-2 13-3 A-1 A-2 A-3 A-4 Title Page Output Compare Registers (OCRH/OCRL) . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Output Compare Software Initialization Example . . . . . . . . . . . . . . . . . . . . 10-7 Input Compare Registers (ICRH/ICRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 State Timing Diagram for Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 OSC Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 Power-On Reset and External Reset Timing Diagram . . . . . . . . . . . . . . . . 13-8 MC68HC705P3 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5 MC68HC705P6 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5 MC68HC705P9 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-5 MC68HC805P18 Mask Option Registera . . . . . . . . . . . . . . . . . . . . . . . . . .A-5 Freescale Semiconductor, Inc... x For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Rev. 1.0 Freescale Semiconductor, Inc. LIST OF TABLES Table 4-1 6-1 6-2 6-3 7-1 7-2 7-3 7-4 8-1 8-2 9-1 12-1 12-2 12-3 12-4 12-5 12-6 12-7 15-1 A-1 A-2 A-3 A-4 Title Page Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Port A I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Port B I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Port C I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Port D I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 SIOP Clock Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 A/D Multiplexer Input Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Elements of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-2 Memory Breakdown by Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-3 P-Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4 Freescale Semiconductor, Inc... Rev. 1.0 For More Information On This Product, Go to: www.freescale.com xi Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 1 INTRODUCTION 1.1 Introduction The Motorola MC68HC805P18 microcontroller is a member of the M68HC05 microcontroller family with a 4-channel, 8-bit analog-to-digital (A/D) converter, a 16-bit timer with output compare and input capture, a serial communications port (SIOP), a computer operating properly (COP) watchdog timer, and 21 input/output (I/O) pins (20 bidirectional, one input-only). The memory map contains 192 bytes of RAM, 8064 bytes of program EEPROM (for user code), 512 bytes of boot ROM, and128 bytes of EEPROM (for data storage). This device is available in a 28-pin dual in-line package (DIP) or a small outline (SOIC) package. A functional block diagram of the MC68HC805P18 is shown in Figure 1-1. 1.2 Features • • • • • • • • • • • • • Low-cost HC05 core running at 2 MHz bus speed 28-pin DIP or SOIC package 4 MHz on-chip crystal/ceramic resonator oscillator 8064 bytes of user EEPROM including 48 bytes of page zero EEPROM and 16 bytes of user vectors 192 bytes of on-chip RAM 128 bytes of EEPROM Low-voltage reset 4-channel, 8-bit A/D converter SIOP serial communications port COP watchdog timer with active pulldown on RESET 16-bit timer with output compare and input capture 20 bidirectional I/O lines and one input-only line High current sink and source on two I/O pins (PC0 and PC1) 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... INTRODUCTION Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 COP PH2 ÷2 OSC OSC 1 OSC 2 CPU CONTROL RESET 68HC05 CPU IRQ ALU ÷4 16-BIT TIMER 1 INPUT CAPTURE 1 OUTPUT COMPARE PORT D LOGIC PD7/TCAP TCMP PD5/CKOUT ACCUMULATOR CPU REGISTERS DATA DIRECTION REGISTER INDEX REGISTER 0 0 0 0 0 0 0 0 1 1 STK PNTR PROGRAM COUNTER COND CODE REG 111H I NZC A/ D CONVERTER PC7/VREFH PC6/AD0 MUX PC5/AD1 PC4/AD2 PC3/AD3 PC2 PC1 PC0 SRAM — 192 BYTES PA7 DATA DIRECTION REGISTER USER EEPROM — 8064 BYTES PA6 PA5 PORT A PA4 PA3 PA2 PA1 PA0 PB5/SDO PB6/SDI PB7/SCK PORT B AND SIOP REGISTERS AND LOGIC VDD VSS Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A EEPROM — 128 BYTES Figure 1-1. Block Diagram 16 17 18 19 20 INTRODUCTION 1-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 PORT C Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.3 Mask Options EEPROM mask option register (MOR) selectable options include the following. For additional information, refer to 8.4 Mask Option Registers (MOR). • • • • • • IRQ is edge- and level-sensitive or edge-sensitive only. SIOP most significant bit (MSB) first or least significant bit (LSB) first SIOP clock rate set to oscillator divided by 2, 4, 8, or 16 COP watchdog timer enabled or disabled Stop instruction enabled or converted to halt mode Option to enable clock output pin to replace PD5 Option to individually enable pullups/interrupts on each of the eight port A pins LVR reset enabled or disabled 8 2 3 4 5 6 7 8 Freescale Semiconductor, Inc... • • NOTE A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. Any reference to voltage, current, or frequency specified in the following sections will refer to the nominal values. The exact values and their tolerance or limits are specified in SECTION 13 ELECTRICAL SPECIFICATIONS. 9 10 11 12 13 14 A 16 17 18 19 20 INTRODUCTION Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.4 Functional Pin Description 8 2 3 4 5 The following paragraphs describe the functionality of each pin on the MC68HC805P18 package. Pins connected to subsystems described in other sections provide a reference to the section instead of a detailed functional description.The pinout is shown in Figure 1-2. RESET IRQ PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 SDO/PB5 SDI/PB6 SCK/PB7 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD OSC1 OSC2 PD7/TCAP TCMP PD5/CKOUT PC0 PC1 PC2 PC3/AD3 PC4/AD2 PC5/AD1 PC6/AD0 PC7/VREFH Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A 1.4.1 VDD and VSS Power is supplied to the MCU through VDD and VSS. VDD is connected to a regulated positive supply and VSS is connected to ground. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, take special care to provide good power supply bypassing at the MCU. Use bypass capacitors with good high-frequency characteristics, and position them as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. Figure 1-2. User Mode Pinout 16 17 18 19 20 INTRODUCTION 1-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.4.2 OSC1 and OSC2 The OSC1 and OSC2 pins are the control connections for the on-chip oscillator. The OSC1 and OSC2 pins can accept the following: 1. A crystal as shown in Figure 1-3(a) 2. A ceramic resonator as shown in Figure 1-3(a) 3. An external clock signal as shown in Figure 1-3(b) The frequency, fosc, of the oscillator or external clock source is divided by two to produce the internal PH2 bus clock operating frequency, fop. The oscillator cannot be turned off by software if the stop-to-halt conversion is enabled via mask option register 1. Refer to 8.4 Mask Option Registers (MOR). 1.4.3 Crystal The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. Follow the crystal manufacturer’s recommendations, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. Mount the crystal and components as close as possible to the pins for startup stabilization and to minimize output distortion. Ceramic Resonator In cost-sensitive applications, use a ceramic resonator instead of a crystal. Use the circuit in Figure 1-3(a) for a ceramic resonator and follow the resonator manufacturer’s recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. Mount the resonator and components as close as possible to the pins for startup stabilization and to minimize output distortion. External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b). 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... INTRODUCTION Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 TO VDD (OR STOP) MCU TO VDD (OR STOP) MCU OSC1 OSC2 4.7 MΩ OSC1 OSC2 3 4 UNCONNECTED EXTERNAL CLOCK 5 37 pF 37 pF Freescale Semiconductor, Inc... 6 7 8 9 1.4.4 Reset (RESET) Driving this input low will reset the MCU to a known startup state. As an output, the RESET pin indicates that an internal MCU reset has occurred. The RESET pin contains an internal Schmitt trigger to improve its noise immunity. Refer to SECTION 5 RESETS. 1.4.5 Port A (PA0 through PA7) These eight I/O pins comprise port A. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. The pullups and interrupt options (active low) on the port A pins can be individually programmed in the mask option register 2 (MOR2). For further information, refer to SECTION 4 INTERRUPTS and SECTION 7 INPUT/OUTPUT PORTS. (a) Crystal or Ceramic Resonator Connections (b) External Clock Source Connections Figure 1-3. Oscillator Connections 10 11 12 13 14 A 16 17 18 19 20 INTRODUCTION 1-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.4.6 Port B (PB5/SDO, PB6/SDI, and PB7/SCK) These three I/O pins comprise port B and are shared with the SIOP communications subsystem. The state of any pin is software programmable and all port B lines are configured as inputs during power-on or reset. For further information, refer to SECTION 7 INPUT/OUTPUT PORTS and SECTION 11 SERIAL INPUT/OUTPUT PORT. 1.4.7 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH) These eight I/O pins comprise port C and are shared with the A/D converter subsystem. The state of any pin is software programmable and all port C lines are configured as inputs during power-on or reset. Port pins PC0 and PC1 are capable of sourcing and sinking high currents. For further information, refer to SECTION 7 INPUT/OUTPUT PORTS and SECTION 9 ANALOG-TO-DIGITAL CONVERTER. 1.4.8 Port D (PD5/CKOUT and PD7/TCAP) These two I/O pins comprise port D, and one of them is shared with the 16-bit timer subsystem. The state of PD5/CKOUT is software programmable and is configured as an input during power-on or reset (unless clock output has been selected). PD7 is always an input; it may be read at any time, regardless of the mode of operation the 16-bit timer may be in. For further information, refer to SECTION 7 INPUT/OUTPUT PORTS and SECTION 10 16-BIT TIMER. The PD5/CKOUT pin can be turned into a clock output pin by programming mask option register 1. Clock output is a buffered OSC2 signal with a CMOS output driver. 1.4.9 TCMP This pin is the output from the 16-bit timer’s output compare function. It is low after reset. For further information, refer to SECTION 10 16-BIT TIMER. 1.4.10 Maskable Interrupt Request (IRQ) This input pin drives the asynchronous interrupt function of the MCU. The MCU will complete the current instruction being executed before it responds to the IRQ interrupt request. When IRQ is driven low, the event is latched internally to signify an interrupt has been requested. When the MCU completes its current instruction, the interrupt latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit) in the condition code register is clear, the MCU will begin the interrupt sequence. 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... INTRODUCTION Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 Depending on the programming option selected in the mask option register 1 (MOR1), the IRQ pin will trigger this interrupt on either a negative-going edge at the IRQ pin and/or while the IRQ pin is held in the low state. In either case, the IRQ pin must be held low for at least one tILIH time period. If the edge- and level-sensitive edge is programmed in the MOR1,the IRQ input requires an external resistor connected to VDD for wired-OR operation. If the IRQ pin is not used, it must be tied to the VDD supply. The IRQ pin contains an internal Schmitt trigger as part of its input circuitry to improve noise immunity. For further information, refer to SECTION 4 INTERRUPTS. Freescale Semiconductor, Inc... NOTE If the voltage level applied to the IRQ pin exceeds VDD, it may affect the MCU’s mode of operation. See SECTION 6 OPERATING MODES. 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 INTRODUCTION 1-8 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 2 MEMORY 2.1 Introduction The MC68HC805P18 utilizes 14 address lines to access an internal memory space covering 16 Kbytes. This memory space is divided into I/O, RAM, EEPROM, and boot ROM areas. 2.2 User Mode Memory Map When the MC68HC805P18 is in the user mode, the 32 bytes of I/O, 192 bytes of RAM, 128 bytes of EEPROM, 8000 bytes of program EEPROM, 48 bytes of user page zero EEPROM, and 16 bytes of user vectors EEPROM are all active as shown in Figure 2-1. 2.3 I/O and Control Registers Figure 2-2 through Figure 2-4 briefly describe the I/O and control registers at locations $0000–$001F. Reading unimplemented bits will return unknown states, and writing unimplemented bits will be ignored. 2.4 RAM The user RAM consists of 192 bytes (including the stack) at locations $0050 through $010F. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM from $00FF to $00C0. 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... NOTE Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. MEMORY Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 2.5 EEPROM 8 2 3 4 5 The EEPROM is located at address $0140 and consists of 128 bytes. Programming the EEPROM can be done by the user on a single byte basis by manipulating the programming register, located at address $001C. Refer to SECTION 8 EEPROM for a discussion of the EEPROM. 2.6 User EEPROM There are 8064 bytes of user EEPROM available, consisting of 8000 bytes at locations $1FC0 through $3EFF, 48 bytes in page zero locations $0020 through $004F, and 16 additional bytes for user vectors at locations $3FF0 through $3FFF. This EEPROM can be programmed only in bootloader mode. Refer to 6.2.2 Bootloader Mode for more details. Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 MEMORY 2-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION $0000 $001F $0020 $004F $0050 $00BF $00C0 $00FF $010F $013F $0140 I/O 32 BYTES USER EEPROM 48 BYTES INTERNAL RAM 192 BYTES STACK 64 BYTES UNUSED 48 BYTES EEPROM 128 BYTES 0000 0031 0032 0079 0080 0191 0192 0255 0271 0272 0319 0320 0447 0448 $0000 8 I/O REGISTERS SEE FIGURE 2-2 2 $001F 3 4 COP CONTROL REGISTER UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED $3FF0 $3FF1 $3FF2 $3FF3 $3FF4 $3FF5 $3FF6 $3FF7 $3FF8 $3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... $01BF $01C0 UNUSED 7728 BYTES $1FBF $1FC0 USER EEPROM 8000 BYTES $3EFF $3F00 $3F01 $3F02 16127 MASK OPTION REGISTER UNUSED 238 BYTES $3FEF $3FF0 $3FFF USER VECTORS EEPROM 16 BYTES 16367 16368 16383 16128 16130 8127 8128 UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED TIMER VECTOR (HIGH BYTE) TIMER VECTOR (LOW BYTE) IRQ VECTOR (HIGH BYTE) IRQ VECTOR (LOW BYTE) SWI VECTOR (HIGH BYTE) SWI VECTOR (LOW BYTE) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE) Figure 2-1. MC68HC805P18 User Mode Memory Map MEMORY Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER PORT D DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER PORT D DATA DIRECTION REGISTER UNIMPLEMENTED UNIMPLEMENTED SIOP CONTROL REGISTER SIOP STATUS REGISTER SIOP DATA REGISTER UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED RESERVED TIMER CONTROL REGISTER TIMER STATUS REGISTER INPUT CAPTURE MOST SIGNIFICANT BIT INPUT CAPTURE LEAST SIGNIFICANT BIT OUTPUT COMPARE MOST SIGNIFICANT BIT OUTPUT COMPARE LEAST SIGNIFICANT BIT TIMER MOST SIGNIFICANT BIT TIMER LEAST SIGNIFICANT BIT ALTERNATE COUNTER MOST SIGNIFICANT BIT ALTERNATE COUNTER LEAST SIGNIFICANT BIT EEPROM PROGRAMMING REGISTER A/D CONVERTER DATA REGISTER A/D CONVERTER CONTROL AND STATUS REGISTER RESERVED $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A Figure 2-2. MC68HC805P18 I/O and Control Registers Memory Map 16 17 18 19 20 MEMORY 2-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION ADDR REGISTER READ WRITE R W R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 8 2 3 $0000 PORT A DATA PORTA PORT B DATA PORTB PORT C DATA PORTC PORT D DATA PORTD PORT A DATA DIRECTION DDRA PORT B DATA DIRECTION DDRB PORT C DATA DIRECTION DDRC PORT D DATA DIRECTION DDRD UNIMPLEMENTED PA7 PA6 PA5 PA4 0 PA3 0 PA2 0 PA1 0 PA0 0 $0001 PB7 PB6 PB5 $0002 PC7 PD7 PC6 0 PC5 PC4 1 PC3 0 PC2 0 PC1 0 PC0 0 4 5 $0003 PD5 Freescale Semiconductor, Inc... $0004 DDRA7 DDRA6 DDRA5 DDRA4 1 DDRA3 1 DDRA2 1 DDRA1 1 DDRA0 1 6 7 8 9 10 $0005 DDRB7 DDRB6 DDRB5 $0006 DDRC7 0 DDRC6 0 DDRC5 DDRC4 0 DDRC3 0 DDRC2 0 DDRC1 0 DDRC0 0 $0007 DDRD5 $0008 $0009 UNIMPLEMENTED R W $000A SIOP CONTROL REGISTER SCR SIOP STATUS REGISTER SSR SIOP DATA REGISTER SDR UNIMPLEMENTED R W R W R W R W 0 SPE SPIF DCOL 0 MSTR 0 0 0 0 0 0 11 12 0 0 0 0 $000B $000C SDR7 SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 13 14 A 16 $000D $000E UNIMPLEMENTED R W $000F UNIMPLEMENTED R W UNIMPLEMENTED RESERVED 17 Figure 2-3. MC68HC805P18 I/O and Control Registers $0000–$000F 18 19 20 MEMORY Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 ADDR REGISTER READ WRITE R W 7 6 5 4 3 2 1 0 $0010 UNIMPLEMENTED $0011 RESERVED R W $0012 TIMER CONTROL REGISTER TCR TIMER STATUS REGISTER TSR INPUT CAPTURE MSB ICRH INPUT CAPTURE LSB ICRL OUTPUT COMPARE MSB OCRH OUTPUT COMPARE LSB OCRL TIMER MSB TMRH TIMER LSB TMRL ALTERNATE COUNTER MSB ACRH ALTERNATE COUNTER LSB ACRL EEPROM Programming Register A/D CONVERSION DATA ADC A/D STATUS AND CONTROL ADSC RESERVED R W R W R W R W R W R W R W R W R W R W R W R W R W R W CC ADON AD7 AD6 AD5 0 CPEN 0 ACRL7 ACRL6 ACRL5 ACRH7 ACRH6 ACRH5 TMRL7 TMRL6 TMRL5 OCRL7 TMRH7 OCRL6 TMRH6 OCRL5 TMRH5 OCRH7 OCRH6 OCRH5 ICRL7 ICRL6 ICRL5 ICRH7 ICRH6 ICRH5 ICIE ICF OCIE OCF TOIE TOF 0 0 0 IEDG OLVL 0 0 0 0 0 $0013 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0 Freescale Semiconductor, Inc... $0014 6 $0015 ICRL4 ICRL3 ICRL2 ICRL1 ICRL0 7 8 9 $0016 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0 $0017 OCRL4 TMRH4 OCRL3 TMRH3 OCRL2 TMRH2 OCRL1 TMRH1 OCRL0 TMRH0 $0018 10 11 12 13 14 A TMRL4 TMRL3 TMRL2 TMRL1 TMRL0 $0019 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0 $001A ACRL4 ACRL3 ACRL2 ACRL1 ACRL0 $001B $001C ER1 AD4 ER0 AD3 LATCH AD2 EERC AD1 EEPGM AD0 $001D 0 0 CH2 CH1 CH0 $001E $001F 16 17 18 19 20 UNIMPLEMENTED RESERVED Figure 2-4. MC68HC805P18 I/O and Control Registers $0010-$001F MEMORY 2-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 3 CENTRAL PROCESSING UNIT 3.1 Introduction This section describes the CPU registers. 3 4 5 6 7 8 Freescale Semiconductor, Inc... 3.2 CPU Registers The five CPU registers are shown in Figure 3-1 and the interrupt stacking order are shown in Figure 3-2. 7 A 7 X 12 PC 12 0 0 0 0 0 7 1 1 SP CCR H I N Z C CONDITION CODE REGISTER 0 STACK POINTER 0 PROGRAM COUNTER 0 INDEX REGISTER 0 ACCUMULATOR 9 10 11 12 13 14 A 16 17 18 19 20 Figure 3-1. Programming Model CENTRAL PROCESSING UNIT Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 INCREASING MEMORY ADDRESSES R E T U R N 7 1 1 1 0 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL STACK I N T E R R U P T DECREASING MEMORY ADDRESSES UNSTACK NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. Figure 3-2. Stacking Order Freescale Semiconductor, Inc... 6 3.2.1 Accumulator (A) The accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 7 A 0 7 8 9 10 11 12 13 14 A 3.2.2 Index Register (X) The index register is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area. 7 X 0 16 17 18 19 20 CENTRAL PROCESSING UNIT 3-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.2.3 Condition Code Register (CCR) The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. CCR H I N Z C 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Half Carry (H) Freescale Semiconductor, Inc... This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/Borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates. CENTRAL PROCESSING UNIT Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.2.4 Stack Pointer (SP) 8 2 3 4 5 The stack pointer contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the seven most significant bits are permanently set to 0000011. These seven bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 12 0 0 0 0 0 7 1 1 SP 0 Freescale Semiconductor, Inc... 6 7 8 9 3.2.5 Program Counter (PC) The program counter is a 13-bit register that contains the address of the next byte to be fetched. 12 PC 0 10 11 12 NOTE The M68HC05 CPU core is capable of addressing a 64-Kbyte memory map. For this implementation, however, the addressing registers are limited to an 8-Kbyte memory map. 13 14 A 16 17 18 19 20 CENTRAL PROCESSING UNIT 3-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 4 INTERRUPTS 4.1 Introduction The MCU can be interrupted six different ways: 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... • • • • • • Non-maskable software interrupt instruction (SWI) External asynchronous interrupt (IRQ) Input capture interrupt (TIMER) Output compare interrupt (TIMER) Timer overflow interrupt (TIMER) Port A interrupt (if selected via MOR2, bits 0 through 7). Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is completed. When the current instruction is completed, the processor checks all pending hardware interrupts. If interrupts are not masked (I bit in the condition code register is clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing. Otherwise, the next instruction is fetched and executed. The SWI is executed the same as any other instruction, regardless of the I bit state. When an interrupt is to be processed, the CPU puts the register contents on the stack, sets the I bit in the CCR, and fetches the address of the corresponding interrupt service routine from the vector table at locations $3FF0 through $3FFF. If more than one interrupt is pending when the interrupt vector is fetched, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the CPU state to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occurs during interrupt processing. INTERRUPTS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 Table 4-1. Vector Addresses for Interrupts and Reset Register N/A N/A N/A TSR TSR TSR N/A N/A N/A N/A Flag Name N/A N/A N/A ICF OCF TOF N/A N/A N/A N/A Reset Software External Interrupt Timer Input Capture Timer Output Compare Timer Overflow Unimplemented Unimplemented Unimplemented Unimplemented Interrupts CPU Interrupt RESET SWI IRQ TIMER TIMER TIMER N/A N/A N/A N/A Vector Address $3FF3–$3FFF $3FFC–$3FFD $3FFA–$3FFB $3FF8–$3FF9 $3FF8–$3FF9 $3FF8–$3FF9 $3FF6–$3FF7 $3FF4–$3FF5 $3FF2–$3FF3 $3FF0–$3FF1 Freescale Semiconductor, Inc... 6 7 8 9 4.2 Interrupt Types The interrupts fall into three categories: reset, software, and hardware. 4.2.1 Reset Interrupt Sequence The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low level input on the RESET pin or internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations $3FFE and $3FFF. The I bit in the condition code register is also set. The MCU is configured to a known state during this type of reset as described in SECTION 5 RESETS. 4.2.2 Software Interrupt (SWI) The SWI is an executable instruction. It is also a non-maskable interrupt since it is executed regardless of the state of the I bit in the CCR. As with any instruction, interrupts pending during the previous instruction will be serviced before the SWI opcode is fetched. The interrupt service routine address for the SWI instruction is specified by the contents of memory locations $3FFC and $3FFD. 4.2.3 Hardware Interrupts All hardware interrupts are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. Four hardware interrupts are explained in the following paragraphs. INTERRUPTS 4-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION FROM RESET 8 2 Y CLEAR IRQ REQUEST LATCH Y IS I BIT SET? N IRQ INTERRUPT? N TIMER INTERRUPT? Y 3 4 5 STACK PC, X, A, CC Freescale Semiconductor, Inc... N 6 7 8 9 10 SET I BIT IN CCR LOAD PC FROM: SWI: $3FFC, $3FFD IRQ: $3FFA-$3FFB TIMER: $3FF8-$3FF9 FETCH NEXT INSTRUCTION 11 Y SWI INSTRUCTION? N RTI INSTRUCTION? N EXECUTE INSTRUCTION 12 RESTORE RESISTERS FROM STACK CC, A, X, PC Y 13 14 A 16 17 18 19 20 Figure 4-1. Interrupt Processing Flowchart External Interrupt (IRQ) The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector flip-flop is latched on the falling edge of IRQ. If either the output from the internal edge detector flip-flop or the level on the IRQ pin is low, a request is synchronized to the CPU to generate the IRQ interrupt. If the edge-sensitive only option is selected, the output of the internal edge detector flip-flop is sampled and the input level on the IRQ pin is ignored. If port A interrupts are INTERRUPTS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 programmed as an option, a port A interrupt will use the same vector. The interrupt service routine address is specified by the contents of memory locations $3FFA and $3FFB. NOTE The internal interrupt latch is cleared 9 PH2 clock cycles after the interrupt is recognized (after location $3FFA is read). Therefore, another external interrupt pulse could be latched during the IRQ service routine. Freescale Semiconductor, Inc... 6 7 8 9 The IRQ pin is one source of an IRQ interrupt and a mask option can also enable the port A pins (PA0 through PA7) to act as other IRQ interrupt sources. These sources are all combined into a single ORing function to be latched by the IRQ latch. IRQ PIN NOTE When the edge- and level-sensitive option is selected, the voltage applied to the IRQ pin must return to the high state before the RTI instruction in the interrupt service routine is executed. 10 11 12 13 14 A PA0 DDRA0 PA0 IRQ INHIBIT (MASK OPTION) : : : : PA7 DDRA7 PA7 IRQ INHIBIT (MASK OPTION) : : : : : TO BIH & BIL INSTRUCTION SENSING VDD IRQ LATCH R 16 17 18 19 20 4-4 TO IRQ PROCESSING IN CPU RST IRQ VECTOR FETCH MASK OPTION (IRQ LEVEL) Figure 4-2. IRQ Function Block Diagram INTERRUPTS For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the IRQ pin or a port A pin if port A interrupts have been enabled. If edge-only sensitivity is chosen by a mask option, only the IRQ latch output can activate a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases: 1. 2. Falling edge on the IRQ pin with all enabled port A interrupt pins at a high level. Falling edge on any enabled port A interrupt pin with all other enabled port A interrupt pins and the IRQ pin at a high level. 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A Freescale Semiconductor, Inc... If level sensitivity is chosen, the active high state of the IRQ input can also activate an IRQ request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases: 1. 2. 3. 4. Low level on the IRQ pin Falling edge on the IRQ pin with all enabled port A interrupt pins at a high level Low level on any enabled port A interrupt pin Falling edge on any enabled port A interrupt pin with all enabled port A interrupt pins and the IRQ pin at a high level This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $3FFA and $3FFB. The IRQ latch is automatically cleared by entering the interrupt service routine. Optional External Interrupts (PA0–PA7) The IRQ interrupt can be triggered by the inputs on the PA0 through PA7 port pins if enabled by individual mask options. With pullup enabled, each port A pin can activate the IRQ interrupt function and the interrupt operation will be the same as for inputs to the IRQ pin. Once enabled by mask option, each individual port A pin can be disabled as an interrupt source if its corresponding DDR bit is configured for output mode. NOTE The BIH and BIL instructions apply to the output of the logic OR function of the enabled PA0 through PA7 interrupt pins and the IRQ pin. The BIH and BIL instructions do not test only the state of the IRQ pin. 16 17 18 19 20 INTERRUPTS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 Input Capture Interrupt NOTE If enabled, the PA0 through PA7 pins will cause an IRQ interrupt only if these individual pins are configured as inputs. Freescale Semiconductor, Inc... 6 7 8 9 The input capture interrupt is generated by the 16-bit timer as described in SECTION 10 16-BIT TIMER. The input capture interrupt flag is located in register TSR and its corresponding enable bit can be found in register TCR. The I bit in the CCR must be clear in order for the input capture interrupt to be enabled. The interrupt service routine address is specified by the contents of memory locations $3FF8 and $3FF9. Output Compare Interrupt The output compare interrupt is generated by the 16-bit timer as described in SECTION 10 16-BIT TIMER. The output compare interrupt flag is located in register TSR and its corresponding enable bit can be found in register TCR. The I bit in the CCR must be clear in order for the output compare interrupt to be enabled. The interrupt service routine address is specified by the contents of memory locations $3FF8 and $3FF9. Timer Overflow Interrupt The timer overflow interrupt is generated by the 16-bit timer as described in SECTION 10 16-BIT TIMER. The timer overflow interrupt flag is located in register TSR and its corresponding enable bit can be found in register TCR. The I bit in the CCR must be clear in order for the timer overflow interrupt to be enabled. This internal interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $3FF8 and $3FF9. 10 11 12 13 14 A 16 17 18 19 20 INTERRUPTS 4-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 5 RESETS 5.1 Introduction The MCU can be reset from four sources: one external input and three internal reset conditions. The RESET pin is an input with a Schmitt trigger as shown in Figure 5-1. The CPU and all peripheral modules will be reset by the RST signal which is the logical OR of internal reset functions and is clocked by PH2. 5.2 External Reset (RESET) The RESET input is the only external reset and is connected to an internal Schmitt trigger. The external reset occurs whenever the RESET input is driven below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. The upper and lower thresholds are given in SECTION 13 ELECTRICAL SPECIFICATIONS. 3 4 5 6 7 8 9 10 11 12 13 R Freescale Semiconductor, Inc... IRQ D LATCH RESET TO IRQ LOGIC MODE SELECT (PULSE WIDTH =4 x E-CLK) PH2 CLOCKED ONE-SHOT 14 A CPU S D LATCH RST TO OTHER PERIPHERALS OSC DATA ADDRESS VDD VDD COP WATCHDOG (COPR) LOW-VOLTAGE RESET (LVR) POWER-ON RESET (POR) PH2 16 17 18 19 20 Figure 5-1. Reset Block Diagram RESETS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 5.3 Internal Resets 8 2 3 4 5 The three internally generated resets are the initial power-on reset (POR), the COP watchdog timer, and low-voltage reset (LVR) functions. 5.3.1 Power-On Reset (POR) The internal POR is generated at power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. There is a 4064 PH2 clock cycle oscillator stabilization delay after the oscillator becomes active. The POR will generate the RST signal and reset the MCU. The POR will also pull the RESET pin low at the same time, allowing external devices to be reset with the MCU. If any other reset function is active at the end of this 4064 PH2 clock cycle delay, the RST signal will remain active until the other reset condition(s) end. 5.3.2 Computer Operating Properly (COP) Reset When the COP watchdog timer is enabled (by MOR1, bit 0), the internal COP reset is generated automatically by a timeout of the COP watchdog timer. This timer is implemented with an 18-stage ripple counter that provides a time-out period of 65.5 ms when a 4-MHz oscillator is used. The COP watchdog counter is cleared by writing a logical zero to bit zero at location $3FF0. The COP register is shared with the most significant bit (MSB) of an unimplemented user interrupt vector as shown in Figure 5-2. Reading this location will return the MSB of the unimplemented user interrupt vector. Writing to this location will clear the COP watchdog timer. Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 Bit 7 Read: $3FF0 Write: Reset: R — 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 COPR A 16 17 18 19 20 — — — — R — = Reserved — — = Unimplemented Figure 5-2. Unimplemented Vector and COP Watchdog Timer Register RESETS 5-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 5.3.3 Low-Voltage Reset (LVR) If the LVR has been enabled via MOR1, the internal LVR reset is generated when the supply voltage to the VDD pin falls below a nominal 3.80 Vdc. The LVR threshold is not intended to be an accurate and stable trip point, but is intended to ensure that the CPU will be held in reset when the VDD supply voltage is below reasonable operating limits. If the LVR is tripped for a short time, the LVR reset signal will last at least two cycles of the CPU bus clock, PH2. The LVR will generate the RST signal which will reset the CPU and other peripherals. Also, the LVR will establish the mode of operation based on the state of the IRQ pin at the time the LVR signal ends. If any other reset function is active at the end of the LVR reset signal, the RST signal will remain in the reset condition until the other reset condition(s) end. 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... NOTE The voltage of the IRQ pin must be between 0–VDD volts to stay in the normal operation mode. RESETS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 6 OPERATING MODES 6.1 Introduction This section describes the user, bootloader, and low-power modes. In addition the computer operating properly (COP) timer considerations are discussed. 6.2 User Modes The MC68HC805P18 has two modes of operation available to the user: • • User mode Bootloader mode 3 4 5 6 7 8 9 10 11 Mode User Bootloader Freescale Semiconductor, Inc... The mode of operation is determined by the voltages on the IRQ and PD7/TCAP pins on the rising edge of the external RESET pin. Table 6-1 shows the condition required to go into each mode. Table 6-1. Operating Mode Conditions RESET IRQ 0–5 V 2 x VDD TCAP 0–5 V 5V 12 13 14 A 16 17 18 19 20 6.2.1 User Mode The user mode allows the MCU to function as a self-contained microcontroller with maximum use of the pins for on-chip peripheral functions. All address and data activity occurs within the MCU and is not available externally. User mode is entered on the rising edge of RESET, if the IRQ pin is within the normal operating voltage range. In the user mode, there is an 8-bit I/O port, a second 8-bit I/O port shared with the analog-to-digital (A/D) subsystem, one 3-bit I/O port shared with the serial input/output port (SIOP), and a 2-bit I/O port shared with the16-bit timer subsystem. OPERATING MODES Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 6.2.2 Bootloader Mode 8 2 3 4 5 Bootloader mode is entered upon the rising edge of RESET if the IRQ pin is twice the VDD voltage and the TCAP/PD7 pin is at logic one. In bootloader mode, the user EEPROM and mask option register (MOR) bytes can be erased and programmed. Figure 6-1 shows the bootloader circuit. PTC4 determines whether erasing or programming will occur as shown in Table 6-2. Table 6-2. Bootloader Functions PTC4 0 1 Function Bulk Erase/Blank Verify Bulk Erase/Program/Verify Freescale Semiconductor, Inc... 6 7 8 9 Bulk Erase/Blank Verify To use the bootloader circuit to bulk erase the user EEPROM, follow this sequence: 1. 2. 3. 4. 5. 6. 7. 8. Close RESET switch and PTC4 switch so these pins are held low. Apply 12 V power to IRQ. Release RESET. Programming LED will turn on while bulk erase is occurring. When bulk erase is finished, programming LED will turn off. When blank verify is finished, verify LED will turn on. Close RESET switch. Remove 12 V from IRQ, then remove power. 10 11 12 13 14 A 16 17 18 19 20 OPERATING MODES 6-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12 V 1 KΩ IRQ OSC1 4 MHz PA2 OSC2 PA3 10 MΩ 20 pF 20 pF PA6 PA4 PA5 DQ4 DQ5 DQ6 DQ7 DQ8 CE OE RESET 1 µF VDD 4.7 KΩ PC5 (SYNC) VDD 4.7 KΩ PROG 390 Ω PB7 TCAP PC1 PC2 VERF PB6 390 Ω PC4 VDD = 5.0 V PC3 4.7 KΩ VDD 10 KΩ PC6 PC7 A12 A13 A8 A7 A6 A5 A4 A3 A2 A1 A0 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 DQ3 A9 Q10 PA0 PA1 DQ1 DQ2 27C128 A11 A10 Q12 Q11 MC14040B 8 2 3 4 5 6 7 8 Freescale Semiconductor, Inc... PA7 VDD 10 KΩ RST CLK 9 10 11 12 13 14 A 16 17 Figure 6-1. Bootloader Circuit 18 19 20 OPERATING MODES Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Bulk Erase/Program Verify 8 2 3 4 To use the bootloader circuit to bulk erase, program, and verify the user EEPROM, follow this sequence: 1. 2. 3. 4. Close RESET switch so RESET is low upon power up. Open PTC4 switch so PTC4 remains high during reset sequence. Make sure code to be loaded into user EEPROM is in the external EPROM (shown as 27C128). Apply 12 V power to IRQ. Release RESET. Programming LED will be on during bulk erase and programming. (The code in the 27C128 will be loaded into the user EEPROM and MOR.) When programming is finished, the programming LED will turn off. When the verify is finished, verify LED will turn on. Close RESET switch. Remove 12 V from IRQ, then remove power. 5 5. 6. 7. 8. 9. 10. Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A NOTE Bootloader mode is the only mode in which the user can program the 8K user EEPROM and MOR. The 128-byte EEPROM can be programmed in user mode. 16 17 18 19 20 OPERATING MODES 6-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 6.3 Low-Power Modes The MC68HC805P18 is capable of running in a low-power mode in each of its configurations. The WAIT and STOP instructions provide modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT instructions are not normally used if the COP watchdog timer is enabled (MOR1, bit 0). The stop conversion to halt option (MOR1, bit 5) is used to modify the behavior of the STOP instruction from stop mode to halt mode. The flow of the stop, halt, and wait modes is shown in Figure 6-2. 6.4 STOP Instruction 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... The STOP instruction can result in one of two modes of operation depending on the option programmed in the mask option register 1. If the stop conversion to halt option (MOR1,bit 5) is not chosen, the STOP instruction will behave like a normal STOP instruction in the M68HC805 Family and place the MCU in the stop mode. If the stop conversion to halt option is chosen, the STOP instruction will behave like a WAIT instruction (with the exception of a brief delay at startup) and place the MCU in the halt mode. 6.4.1 Stop Mode Execution of the STOP instruction (without conversion to halt) places the MCU in its lowest-power consumption mode. In the stop mode, the internal oscillator is turned off stopping all internal processing including the COP watchdog timer. The RC oscillator that feeds the EEPROM and the A/D converter is also stopped. Execution of the STOP instruction automatically clears the I bit in the condition code register so that the IRQ external interrupt is enabled. All other registers and memory remain unaltered. All input/output lines remain unchanged. The MCU can be brought out of the stop mode only by an IRQ external interrupt (or port A, if selected as an option in the MOR2) or an externally generated reset. When exiting the stop mode, the internal oscillator will resume after a 4064 PH2 clock cycle oscillator stabilization delay. OPERATING MODES Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 STOP HALT WAIT STOP TO HALT OPTION? N Y EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE STOP RC OSCILLATOR STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR STOP EXTERNAL OSCILLATOR, STOP INTERNAL TIMER CLOCK, RESET START-UP DELAY EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE Freescale Semiconductor, Inc... 6 7 8 9 STOP RC OSCILLATOR STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR Y LVR OR EXTERNAL RESET? N STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR LVR OR EXTERNAL RESET? N IRQ EXTERNAL INTERRUPT? N Y Y IRQ EXTERNAL INTERRUPT? N Y LVR OR EXTERNAL RESET? N Y Y TIMER INTERNAL INTERRUPT? N Y IRQ EXTERNAL INTERRUPT? N 10 11 12 13 14 A RESTART EXTERNAL OSCILLATOR, START STABILIZATION DELAY Y COP INTERNAL RESET? N Y TIMER INTERNAL INTERRUPT? N END OF STABILIZATION DELAY? N Y Y RESTART INTERNAL PROCESSOR CLOCK COP INTERNAL RESET? N 1. 2. 16 17 18 19 20 FETCH RESET VECTOR OR SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE Figure 6-2. STOP/WAIT Flowcharts OPERATING MODES 6-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION NOTE Execution of the STOP instruction without conversion to halt (via MOR1) will cause the oscillator to stop, and therefore disable the COP watchdog timer. If the COP watchdog timer is to be used, the stop mode should be changed to the halt mode by programming the appropriate option in MOR1. 8 2 3 4 6.4.2 Halt Mode 5 6 7 8 9 10 11 12 13 14 NOTE Freescale Semiconductor, Inc... Execution of the STOP instruction with the conversion to halt places the MCU in this low-power mode. Halt mode consumes the same amount of power as wait mode (both halt and wait modes consume more power than stop mode). In halt mode the PH2 clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated from the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the condition code register enabling the IRQ external interrupt. All other registers, memory, and input/output lines remain in their previous states. If the 16-bit timer interrupt is enabled, it will cause the processor to exit the halt mode and resume normal operation. The halt mode also can be exited when an IRQ external interrupt (or port A, if selected as an option in the MOR2) or external RESET occurs. When exiting the halt mode, the PH2 clock will resume after a delay of one to 4064 PH2 clock cycles. This varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization delay timer (a feature of the stop mode), which has been free-running (a feature of the wait mode). The halt mode is not intended for normal use. This feature is provided to keep the COP watchdog timer active in the event a STOP instruction is executed inadvertently. A 16 17 18 19 20 OPERATING MODES Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 6.4.3 WAIT Instruction 8 2 3 4 5 The WAIT instruction places the MCU in a low-power mode which consumes more power than the stop mode. In wait mode the PH2 clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer and reset to be generated from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the condition code register enabling the IRQ external interrupt. All other registers, memory, and input/output lines remain in their previous state. If the 16-bit timer interrupt is enabled it will cause the processor to exit the wait mode and resume normal operation. The 16-bit timer may be used to generate a periodic exit from the wait mode. The wait mode may also be exited when an IRQ or RESET occurs. Note that if port A interrupts (if programmed as an option in the mask option register 1) will also exit wait mode. However, when exiting the wait mode, the internal oscillator will not need to wait for 4064 PH2 clock cycles to stabilize as in the stop and halt modes. 6.5 COP Watchdog Timer Considerations The COP watchdog timer is active in user mode of operation when programmed as an option in MOR1. Executing the STOP instruction without conversion to halt (via mask option register1) will cause the COP to be disabled. Therefore, it is recommended that the STOP instruction be modified to produce halt mode (via MOR1) if the COP watchdog timer will be enabled. Furthermore, it is recommended that the COP watchdog timer be disabled for applications that will use the halt or wait modes for time periods that will exceed the COP time-out period. COP watchdog timer interactions are summarized in Table 6-3. Table 6-3. COP Watchdog Timer Recommendations IF the following conditions exist: STOP Instruction Mode Halt Mode Selected via MOR1, Bit 5 Halt Mode Selected via MOR1, Bit 5 Stop Mode Selected via MOR1, Bit 5 Wait Period WAIT Period Less than COP Time Out WAIT Period More Than COP Time Out Any Length Wait Period THEN the COP Watchdog Timer should be: Enable or Disable COP via MOR1, Bit 0 Disable COP via MOR1, Bit 0 Disable COP via MOR1, Bit 0 Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 OPERATING MODES 6-8 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 7 INPUT/OUTPUT PORTS 7.1 Introduction In user mode, 20 bidirectional input/output (I/O) lines are arranged as two 8-bit I/O ports (ports A and C), one 3-bit I/O port (port B), and one 1-bit I/O port (port D). These ports are programmable as either inputs or outputs under software control of the data direction registers (DDRs). An input-only pin is associated with port D. 7.2 Port A Port A is an 8-bit bidirectional port which can share its pins with the IRQ interrupt system as shown in Figure 7-1. Each port A pin is controlled by the corresponding bits in a data direction register and a data register. The port A data register is located at address $0000. The port A data direction register (DDRA) is located at address $0004. Reset clears the DDRA, thereby initializing port A as an input port. The port A data register is unaffected by reset. MOR 2 (PULLUP INHIBIT) READ $0004 WRITE $0004 DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT I/O PIN VDD 3 4 5 6 7 8 9 10 11 12 13 14 A 100 µA PULLUP Freescale Semiconductor, Inc... WRITE $0000 READ $0000 16 17 INTERNAL HC05 DATA BUS RESET (RST) TO IRQ INTERRUPT SYSTEM 18 19 20 Figure 7-1. Port A I/O Circuitry INPUT/OUTPUT PORTS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.3 Port B 8 2 3 4 5 Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with the SIOP communications subsystem. The port B data register is located at address $0001 and its data direction register (DDR) is located at address $0005. Reset does not affect the data registers, but clears the DDRs, thereby setting all of the port pins to input mode. Writing a logic one to a DDR bit sets the corresponding port pin to output mode (see Figure 7-2). Port B may be used for general I/O applications when the SIOP subsystem is disabled. The SPE bit in register SPCR is used to enable/disable the SIOP subsystem. When the SIOP subsystem is enabled, port B registers are still accessible to software. Writing to either of the port B registers while a data transfer is under way could corrupt the data. See SECTION 11 SERIAL INPUT/OUTPUT PORT for a discussion of the SIOP subsystem. Freescale Semiconductor, Inc... 6 7 8 9 READ $0005 WRITE $0005 RESET (RST) DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT I/O PIN WRITE $0001 10 11 12 13 14 A READ $0001 INTERNAL HC05 DATA BUS Figure 7-2. Port B I/O Circuitry 16 17 18 19 20 INPUT/OUTPUT PORTS 7-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.4 Port C Port C is an 8-bit bidirectional port which can share pins PC3–PC7 with the A/D subsystem. The port C data register is located at address $0002 and its data direction register (DDR) is located at address $0006. Reset does not affect the data registers, but clears the DDRs, thereby setting all of the port pins to input mode. Writing a logic one to a DDR bit sets the corresponding port pin to output mode (see Figure 7-3). Two port C pins, PC0 and PC1, can source and sink a higher current than a typical I/O pin. See SECTION 13 ELECTRICAL SPECIFICATIONS regarding current specifications. Port C may be used for general I/O applications when the A/D subsystem is disabled. The ADON bit in register ADSC is used to enable/disable the A/D subsystem. Care must be exercised when using pins PC0–PC2 while the A/D subsystem is enabled. Accidental changes to bits that affect pins PC3–PC7 in the data or DDR registers will produce unpredictable results in the A/D subsystem. See SECTION 9 ANALOG-TO-DIGITAL CONVERTER. 8 2 3 4 5 6 7 8 Freescale Semiconductor, Inc... READ $0006 WRITE $0006 RESET (RST) DATA DIRECTION REGISTER BIT DATA REGISTER BIT HIGH CURRENT CAPABILITY, PC0 AND PC1 ONLY OUTPUT I/O PIN 9 10 11 12 WRITE $0002 READ $0002 INTERNAL HC05 DATA BUS Figure 7-3. Port C I/O Circuitry 13 14 A 16 17 18 19 20 INPUT/OUTPUT PORTS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.5 Port D 8 2 3 4 5 Port D is a 2-bit port with one bidirectional pin (PD5/CKOUT) and one input-only pin (PD7). Pin PD7 is shared with the 16-bit timer. PD5 can be replaced with a buffered OSC2 clock output via MOR1. The port D data register is located at address $0003 and its data direction register (DDR) is located at address $0007. Reset does not affect the data registers, but clears the DDRs, thereby setting PD5/CKOUT to input mode. Writing a one to DDR bit 5 sets PD5/CKOUT to output mode (see Figure 7-4). Port D may be used for general I/O applications regardless of the state of the 16-bit timer. Since PD7 is an input-only line, its state can be read from the port D data register at any time. Freescale Semiconductor, Inc... 6 7 8 9 READ $0007 WRITE $0007 RESET (RST) DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT I/O PIN WRITE $0003 READ $0003 INTERNAL HC05 DATA BUS 10 11 12 13 14 A Figure 7-4. Port D I/O Circuitry 16 17 18 19 20 INPUT/OUTPUT PORTS 7-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.6 I/O Port Programming Each pin on ports A through port D (except pin 7 of port D) may be programmed as an input or an output under software control as shown in Table 7-1, Table 7-2, Table 7-3, and Table 7-4. The direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (DDR). A pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logic zero. 8 2 3 4 Table 7-1. Port A I/O Functions 5 Access to Data Register @ $0000 Read I/O Pin PA0–PA7 Write * PA0–PA7 Freescale Semiconductor, Inc... DDRA I/O Pin Mode Access to DDRA @ $0004 Read/Write 6 7 8 9 0 1 Input, High Impedance Output DDRA0–DDRA7 DDRA0–DDRA7 *Does not affect input, but stored to data register Table 7-2. Port B I/O Functions DDRB I/O Pin Mode Access to DDRA @ $0005 Read/Write 0 1 Input, High Impedance Output DDRB5–DDRB7 DDRB5–DDRB7 Access to Data Register @ $0001 Read I/O Pin PB5–PB7 Write * PB5–PB7 10 11 12 13 14 A *Does not affect input, but stored to data register Table 7-3. Port C I/O Functions DDRA I/O Pin Mode Access to DDRA @ $0006 Read/Write 0 1 Input, High Impedance Output DDRC0–DDRC7 DDRC0–DDRC7 Accesses to Data Register @ $0002 Read I/O Pin PC0–PC7 Write * PC0–PC7 16 17 18 19 20 *Does not affect input, but stored to data register INPUT/OUTPUT PORTS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 DDRA Table 7-4. Port D I/O Functions I/O Pin Mode Access to DDRA @ $0007 Read/Write 0 1 Input, High Impedance Output DDRD5 DDRD5 Accesses to Data Register @ $0003 Read I/O Pin PD5/CKOUT Write * PD5/CKOUT *Does not affect input, but stored to data register **PD7 is input-only Freescale Semiconductor, Inc... 6 7 8 9 NOTE To avoid generating a glitch on an I/O port pin, data should be written to the I/O port data register before writing a logical one to the corresponding data direction register. 10 11 12 13 14 A 16 17 18 19 20 INPUT/OUTPUT PORTS 7-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 8 EEPROM 8.1 Introduction This section describes the EEPROM which is located at address $0140 and consists of 128 bytes. Programming the EEPROM can be done by the user on a single byte basis by manipulating the programming register located at address $001C. Also, the mask option register (MOR), which consists of two additional EEPROM bytes, is discussed. 8.2 EEPROM Programming Register (EEPROG) The contents and use of the programming register are discussed here. 3 4 5 6 7 8 9 10 4 3 ER0 0 2 LATCH 0 1 EERC 0 Bit 0 EEPGM Freescale Semiconductor, Inc... Bit 7 EEPROG $001C Read: Write: Reset: 0 0 6 CPEN 0 5 0 11 12 ER1 0 0 0 = Unimplemented 13 14 A 16 17 18 19 20 Figure 8-1. EEPROM Programming Register CPEN — Charge Pump Enable When set, CPEN enables the charge pump which produces the internal EEPROM programming voltage. This bit should be set concurrently with the LATCH bit. The programming voltage will not be available until EEPGM is set. The charge pump should be disabled when not in use. CPEN is readable and writable and is cleared by reset. ER1 and ER0 — Erase Select Bits ER1 and ER0 form a 2-bit field which is used to select one of three erase modes: byte, block, or bulk. Table 8-1 shows the modes selected for each bit configuration. These bits are readable and writable and are cleared by reset. EEPROM Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 In byte erase mode, only the selected byte is erased. In block mode, a 32-byte block of EEPROM is erased. The EEPROM memory space is divided into four 32-byte blocks ($140–$15F, $160–$17F, $180–$19F, $1A0–$1BF), and doing a block erase to any address within a block will erase the entire block. In bulk erase mode, the entire 128-byte EEPROM section is erased. Table 8-1. Erase Mode Select ER1 0 0 1 1 ER0 0 1 0 1 Mode Program (no Erase) Byte Erase Block Erase Bulk Erase Freescale Semiconductor, Inc... 6 7 8 9 LATCH — Latch Bit 10 11 12 13 14 A When set, LATCH configures the EEPROM address and data bus for programming. Writes to the EEPROM array cause the data bus and the address bus to be latched. This bit is readable and writable, but reads from the array are inhibited if the LATCH bit is set and a write to the EEPROM space has taken place. When clear, address and data buses are configured for normal operation. Reset clears this bit. EERC — EEPROM RC Oscillator Control When this bit is set, the EEPROM section uses the internal RC oscillator instead of the CPU clock. The RC oscillator is shared with the A/D converter, so this bit should be set by the user when the internal bus frequency is below 1.5 MHz to guarantee reliable operation of the EEPROM or A/D converter. After setting the EERC bit, delay a time, tRCON, to allow the RC oscillator to stabilize. This bit is readable and writable. The EERC bit is cleared by reset. The RC oscillator is disabled while the MCU is in stop mode. EEPGM — EEPROM Programming Power Enable EEPGM must be written to enable (or disable) the EEPGM function. When set, EEPGM turns on the charge pump and enables the programming (or erasing) power to the EEPROM array. When clear, this power is switched off. This will enable pulsing of the programming voltage to be controlled internally. This bit can be read at any time, but can only be written to if LATCH = 1. If LATCH is not set, then EEPGM cannot be set. LATCH and EEPGM cannot both be set with one write if LATCH is cleared. EEPGM is cleared automatically when LATCH is cleared. Reset clears this bit. 16 17 18 19 20 8-2 EEPROM For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8.3 Programming/Erasing Procedures To program a byte of EEPROM, set LATCH = CPEN = 1, set ER1 = ER0 = 0, write data to the desired address and then set EEPGM for a time, tEPGM. 8 2 3 4 5 6 7 8 NOTE Any bit should be erased before it is programmed. However, if write/erase cycling is a concern, the following procedure will minimize the cycling of each bit in each EEPROM byte. Freescale Semiconductor, Inc... If PB • EB = 0, then program the new data over the existing data without erasing it first. If PB • EB ≠ 0, then erase the byte before programming where PB = byte data to be programmed and EB = existing EEPROM byte data. To erase a byte of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 0 and ER0 = 1, write to the address to be erased and set EEPGM for a time, tEBYT. To erase a block of EEPROM, set LATCH = 1, CPEN = 1, ER1 = 1 and ER0 = 0, write to any address in the block, and set EEPGM for a time, tEBLOCK. For a bulk erase, set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 1, write to any address in the array, and set EEPGM for a time, tEBULK. To terminate the programming or erase sequence, clear EEPGM, delay for a time tFPV to allow the program voltage to fall, and then clear LATCH and CPEN to free up the buses. Following each erase or programming sequence, clear all programming control bits. 9 10 11 12 13 14 NOTE Erased/programmed state of the programming EEPROM (128 bytes) and the user EEPROM (8064 bytes) is opposite. An erased EEPROM memory location is a logic zero for user EEPROM, while it is a logic one for programming EEPROM. A 16 17 18 19 20 EEPROM Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8.4 Mask Option Registers (MOR) 8 2 3 4 5 The MOR consists of two EEPROM bytes located at $3F00 and $3F01. The MOR holds the 16 option bits for: • • • • • • The SIOP data format, interrupt sensitivity COP enable/disable SIOP clock rate LVR enable/disable Stop conversion to halt, pullup/interrupt enable on port A Clock output option to replace PD5 Freescale Semiconductor, Inc... 6 7 8 9 When in the erased state, the EEPROM cells will read as logic zeros. These registers are refreshed every 256 µs during power-on reset and every 16 ms after the part is out of reset (assuming fOSC = 4 MHz). Bit 7 MOR1 $3F00 Read: Write: Reset: = Unimplemented Unaffected by reset CLKOUT 6 LVRE 5 SWAIT 4 SPR1 3 SPR0 2 LSBF 1 LEVIRQ 0 COPEN 10 11 12 Figure 8-2. Mask Option Register 1 Bit 7 MOR2 $3F01 Read: Write: Reset: = Unimplemented Unaffected by reset PA7PU 6 PA6PU 5 PA5PU 4 PA4PU 3 PA3PU 2 PA2PU 1 PA1PU 0 PA0PU 13 14 A Figure 8-3. Mask Option Register 2 COPEN — COP enable/disable COPEN may be read at any time. In user mode, writing has no effect. It has to be programmed in bootloader mode. 0 = The COP is disabled (erased state). 1 = The COP is enabled. 16 17 18 19 20 EEPROM 8-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION LEVIRQ — Interrupt request option LEVIRQ may be read at any time. In user mode, writing has no effect. It has to be programmed in bootloader mode. 0 = The IRQ pin is edge-sensitive (erased state). 1 = The IRQ pin is edge- and level-sensitive. LSBF — SIOP MSB or LSB first LSBF may be read at any time. In user mode, writing has no effect. It has to be programmed in bootloader mode. 0 = The SIOP sends/receives MSB (bit 7) first (erased state). 1 = The SIOP sends/receives LSB (bit 0) first. 8 2 3 4 5 6 7 8 9 10 11 12 Freescale Semiconductor, Inc... SPR1 and SPR0 — SIOP Rate Select Bits These bits may be read at any time. In user mode, writing has no effect. It has to be programmed in bootloader mode. Table 8-2. SIOP Clock Rate Selection SPR1 0 0 1 1 SPR0 0 1 0 1 Frequency fOSC divided by 16 fOSC divided by 8 fOSC divided by 4 fOSC divided by 2 SWAIT — STOP conversion to WAIT SWAIT may be read at any time. In user mode, writing has no effect. It has to be programmed in bootloader mode. 0 = STOP instruction puts MCU in stop mode. 1 = STOP instruction puts MCU in halt mode. LVRE — LVR enable/disable LVRE may be read at any time. In user mode, writing has no effect. It has to be programmed in bootloader mode. 0 = The LVR is disabled (erased state). 1 = The LVR is enabled. CLKOUT — CLKOUT enable/disable CLKOUT may be read at any time. In user mode, writing has no effect. It has to be programmed in bootloader mode. 0 = The CLKOUT is disabled (erased state). 1 = The CLKOUT is enabled. EEPROM Rev. 1.0 For More Information On This Product, Go to: www.freescale.com 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION PA7PU through PA0PU — Port A pullups/interrupt enable/disable 8 2 3 4 5 These bits may be read at any time. In user mode, writing has no effect. It has to be programmed in bootloader mode. 0 = Port A (bits 0 through 7) pullups/interrupt is disabled (erased state). 1 = Port A (bits 0 through 7) pullups/interrupt is enabled. Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 EEPROM 8-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 9 ANALOG-TO-DIGITAL CONVERTER 9.1 Introduction The MC68HC805P18 includes a 4-channel, multiplexed input, 8-bit successive approximation analog-to-digital (A/D) converter. The A/D subsystem shares its inputs with port C pins PC3 through PC7. 9.2 Analog Section The following paragraphs describe the operation and performance of analog modules within the analog subsystem. 9.2.1 Ratiometric Conversion The A/D converter is ratiometric, with pin VREFH supplying the high reference voltage. Applying an input voltage equal to VREFH produces a conversion result of $FF (full scale). Applying an input voltage equal to VSS produces a conversion result of $00. An input voltage greater than VREFH will convert to $FF with no overflow indication. For ratiometric conversions, VREFH should be at the same potential as the supply voltage being used by the analog signal being measured and referenced to VSS. 9.2.2 VREFH The reference supply for the A/D converter shares pin PC7 with port C. The low reference is tied to the VSS pin internally. VREFH can be any voltage between VSS and VDD; however, the accuracy of conversions is tested and guaranteed only for VREFH = VDD. 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... ANALOG-TO-DIGITAL CONVERTER Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 9.2.3 Accuracy and Precision 8 2 3 4 5 The 8-bit conversion result is accurate to within ± 1 1/2 LSB, including quantization; however, the accuracy of conversions is tested and guaranteed only with external oscillator operation. 9.2.4 Conversion Process The A/D reference inputs are applied to a precision digital-to-analog converter. Control logic drives the D/A and the analog output is successively compared to the selected analog input which was sampled at the beginning of the conversion cycle. The conversion process is monotonic and has no missing codes. 9.3 Digital Section The following paragraphs describe the operation and performance of digital modules within the analog subsystem. 9.3.1 Conversion Times Each input conversion requires 32 PH2 clock cycles, which must be at a frequency equal to or greater than 1 MHz. 9.3.2 Internal versus External Oscillator If the MCU PH2 clock frequency is less than 1 MHz (2 MHz external oscillator), the internal RC oscillator (approximately 1.5 MHz) must be used for the A/D converter clock. The internal RC clock is selected by setting the EERC bit in the EEPROG register. Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 NOTE The RC oscillator is shared with the EEPROM module. The RC oscillator is disabled while the MCU is in stop mode. A 16 17 18 19 20 ANALOG-TO-DIGITAL CONVERTER 9-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION When the internal RC oscillator is being used, these limitations apply: 1. Since the internal RC oscillator is running asynchronously with respect to the PH2 clock, the conversion complete bit (CC) in the A/D status and control register must be used to determine when a conversion sequence has been completed. 2. Electrical noise will slightly degrade the accuracy of the A/D converter. The A/D converter is synchronized to read voltages during the quiet period of the clock driving it. Since the internal and external clocks are not synchronized the A/D converter occasionally will measure an input when the external clock is making a transition. 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... 3. If the PH2 clock is 1 MHz or greater (for instance, external oscillator 2 MHz or greater), the internal RC oscillator should be turned off and the external oscillator used as the conversion clock. 9.3.3 Multi-Channel Operation An input multiplexer allows the A/D converter to select from one of four external analog signals. Port C pins PC3 through PC6 are shared with the inputs to the multiplexer. ANALOG-TO-DIGITAL CONVERTER Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 9.4 A/D Status and Control Register (ADSC) 8 2 3 The ADSC register reports the completion of A/D conversion and provides control over oscillator selection, analog subsystem power, and input channel selection. See Figure 9-1. Bit 7 6 R 5 ADON 0 4 0 3 0 2 CH2 1 CH1 0 Bit 0 CH0 0 4 5 ADSC $001E Read: Write: Reset: CC 0 0 0 R 0 = Reserved 0 Freescale Semiconductor, Inc... 6 7 = Unimplemented Figure 9-1. A/D Status and Control Register CC — Conversion Complete This read-only status bit is set when a conversion sequence has completed and data is ready to be read from the ADC register. CC is cleared when a channel is selected for conversion, when data is read from the ADC register, or when the A/D subsystem is turned off. Once a conversion has been started, conversions of the selected channel will continue every 32 PH2 clock cycles until the ADSC register is written to again. During continuous conversion operation, the ADC register will be updated with new data and the CC bit set every 32 PH2 clock cycles. Also, data from the previous conversion will be overwritten regardless of the state of the CC bit. Reserved This bit is not used currently. It can be read or written, but does not control anything. ADON — A/D Subsystem On When the A/D subsystem is turned on (ADON = 1), it requires a time, tADON, to stabilize before accurate conversion results can be attained. CH2-CH0 — Channel Select Bits CH2, CH1, and CH0 form a 3-bit field which is used to select an input to the A/D converter. Channels 0 through 3 correspond to port C input pins PC6 through PC3. Channels 4 through 6 are used for reference measurements. In user mode channel 7 is reserved. If a conversion is attempted with channel 7 selected the result will be $00. Table 9-1 lists the inputs selected by bits CH0 through CH3. 8 9 10 11 12 13 14 A 16 17 18 19 20 ANALOG-TO-DIGITAL CONVERTER 9-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION If the ADON bit is set and an input from channels 0 through 4 is selected, the corresponding port C pin’s DDR bit will be cleared (making that port C pin an input). If the port C data register is read while the A/D is on and one of the shared input channels is selected using bit CH0 through CH2, the corresponding port C pin will read as a logic zero. The remaining port C pins will read normally. To digitally read a port C pin, the A/D subsystem must be disabled (ADON = 0) or input channel 5 through 7 must be selected. Table 9-1. A/D Multiplexer Input Channel Assignments Channel Signal AD0 — Port C, Bit 6 AD1 — Port C, Bit 5 AD2 — Port C, Bit 4 AD3 — Port C, Bit 3 VREFH — Port C, Bit 7 (VREFH + VSS)/2 VSS Reserved 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... 0 1 2 3 4 5 6 7 ANALOG-TO-DIGITAL CONVERTER Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 9.5 A/D Conversion Data Register (ADC) 8 2 This register contains the output of the A/D converter. See Figure 9-1. Bit 7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 AD0 3 4 5 ADC $001D Read: Write: Reset: AD7 X X X X X X X X = Unimplemented Freescale Semiconductor, Inc... Figure 9-2. A/D Conversion Data Register 9.6 A/D Subsystem During Wait/Halt Modes The A/D subsystem continues normal operation during wait and halt modes. To decrease power consumption during wait or halt, the ADON bit in the ADSC register and the EERC bit in the EEPROG register should be cleared if the A/D subsystem is not being used. 9.7 A/D Subsystem Operation During Stop Mode When the stop mode is enabled, execution of the STOP instruction will terminate all A/D subsystem functions. Any pending conversion is aborted. When the oscillator resumes operation upon leaving the stop mode, a finite amount of time passes before the A/D subsystem stabilizes sufficiently to provide conversions at its rated accuracy. The delays built into the MC68HC805P18 when coming out of stop mode are sufficient for this purpose. No explicit delays need to be added to the application software. 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 ANALOG-TO-DIGITAL CONVERTER 9-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 10 16-BIT TIMER 10.1 Introduction The MC68HC805P18 MCU contains a single 16-bit programmable timer with an input capture function and an output compare function. The 16-bit timer is driven by the output of a fixed divide-by-four prescaler operating from the PH2 clock. The 16-bit timer may be used for many applications including input waveform measurement, while simultaneously generating an output waveform. Pulse widths can vary from microseconds to seconds depending on the oscillator frequency selected. The 16-bit timer is also capable of generating periodic interrupts. See Figure 10-1. Because the timer has a 16-bit architecture, each function is represented by two registers. Each register pair contains the high and low byte of that function. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... NOTE The I bit in the condition code register (CCR) should be set while manipulating both the high and low byte registers of a specific timer function. This prevents interrupts from occurring between the time the high and low bytes are accessed. 16-BIT TIMER Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION INTERNAL HC05 BUS 8 2 3 4 5 OUTPUT COMPARE BUFFER PH2 CLOCK INPUT CAPTURE OCRH OCRL FREERUNNING COUNTER TMRH/ ACRH TMRL/ ACRL ÷4 ICRH ICRL Freescale Semiconductor, Inc... 6 7 8 9 R > R TIMER STATUS REGISTER OCF TOF ICF RESET R TCMP COMPARE DETECTOR OVERFLOW DETECTOR EDGE DETECTOR TCAP 10 11 12 13 14 A OCIE TOIE ICIE IEDG OLVL INTERRUPT GENERATOR TIMER INTERRUPT 16 17 18 19 20 TIMER CONTROL REGISTER Figure 10-1. 16-Bit Timer Block Diagram 16-BIT TIMER 10-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.2 Timer The key element of the programmable timer is a 16-bit free-running counter, or timer registers, preceded by a prescaler which divides the PH2 clock by four. The prescaler gives the timer a resolution of 2.0 microseconds when a 4-MHz crystal is used. The counter is incremented to increasing values during the low portion of the PH2 clock cycle. The double byte free-running counter can be read from either of two locations: the timer registers (TMRH and TMRL) or the alternate counter registers (ACRH and ACRL). Both locations will contain identical values. A read sequence containing only a read of the LSB of the counter (TMRL/ACRL) will return the count value at the time of the read. If a read of the counter accesses the MSB first (TMRH/ACRH), it causes the LSB (TMRL/ACRL) to be transferred to a buffer. This buffer value remains fixed after the first MSB byte read, even if the MSB is read several times. The buffer is accessed when reading the counter LSB (TMRL/ACRL), and thus completes a read sequence of the total counter value. When reading either the timer or alternate counter registers, if the MSB is read, the LSB must also be read to complete the read sequence. See Figure 10-2 and Figure 10-3. Bit 7 TMRH $0018 Read: Write: Reset: 1 1 1 1 1 1 1 1 TMRH7 6 TMRH6 5 TMRH5 4 TMRH4 3 TMRH3 2 TMRH2 1 TMRH1 Bit 0 TMRH0 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... Bit 7 TMRL $0019 Read: Write: Reset: 1 TMRL7 6 TMRL6 5 TMRL5 4 TMRL4 3 TMRL3 2 TMRL2 1 TMRL1 Bit 0 TMRL0 1 1 1 1 1 0 0 = Unimplemented Figure 10-2. Timer Registers (TMRH/TMRL) 16-BIT TIMER Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 ACRL $001B ACRH $001A Bit 7 Read: Write: Reset: 1 ACRH7 6 ACRH6 5 ACRH5 4 ACRH4 3 ACRH3 2 ACRH2 1 ACRH1 Bit 0 ACRH0 1 1 1 1 1 1 1 Bit 7 Read: Write: Reset: 1 ACRL7 6 ACRL6 5 ACRL5 4 ACRL4 3 ACRL3 2 ACRL2 1 ACRL1 Bit 0 ACRL0 Freescale Semiconductor, Inc... 1 1 1 1 1 0 0 6 7 8 9 = Unimplemented Figure 10-3. Alternate Counter Registers (ACRH/ACRL) The timer registers and alternate counter registers can be read at any time without affecting their value. However, the alternate counter registers differ from the timer registers in one respect: Aread of the timer register MSB can clear the timer overflow flag (TOF). Therefore, the alternate counter registers can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF. See Figure 10-4. 10 11 12 13 14 A PH2 CLOCK 16-BIT FREE-RUNNING COUNTER TIMER OVERFLOW FLAG (TOF) NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL). $FFFE $FFFF $0000 $0001 $0002 16 17 18 19 20 Figure 10-4. State Timing Diagram for Timer Overflow 16-BIT TIMER 10-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The free-running counter is initialized to $FFFC during reset and is a read-only register. During power-on-reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator startup delay. Because the counter is 16 bits preceded by a fixed divide-by-four prescaler, the value in the counter repeats every 262,144 PH2 clock cycles (524,288 oscillator cycles). When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) in register TSR is set. An interrupt can also be enabled when counter rollover occurs by setting the timer overflow interrupt enable bit (TOIE) in register TCR. See Figure 10-5. 8 2 3 4 5 Freescale Semiconductor, Inc... PH2 CLOCK INTERNAL RESET 16-BIT FREE-RUNNING COUNTER RESET (EXTERNAL OR OTHER) NOTE: The counter and control registers are the only 16-bit timer registers affected by reset. 6 7 $FFFC $FFFD $FFFE $FFFF 8 9 10 11 12 13 14 A 16 17 18 19 20 Figure 10-5. State Timing Diagram for Timer Reset 16-BIT TIMER Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.3 Output Compare 8 2 3 4 5 The output compare function may be used to generate an output waveform and/or as an elapsed time indicator. All of the bits in the output compare register pair OCRH/OCRL are readable and writable and are not altered by the 16-bit timer’s control logic. Reset does not affect the contents of these registers. If the output compare function is not utilized, its registers can be used for data storage. See Figure 10-3. Bit 7 OCRH $0016 Read: OCRH7 Write: Reset: X X X X X X X X OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... 6 7 Bit 7 OCRL $0017 Read: OCRL7 Write: Reset: X 6 OCRL6 X 5 OCRL5 X 4 OCRL4 X 3 OCRL3 X 2 OCRL2 X 1 OCRL1 X Bit 0 OCRL0 X 8 9 10 11 12 13 14 A Figure 10-6. Output Compare Registers (OCRH/OCRL) The contents of the output compare registers are compared with the contents of the free-running counter once every four PH2 clock cycles. If a match is found, the output compare flag bit (OCF) is set and the output level bit (OLVL) is clocked to the output latch. The values in the output compare registers and output level bit should be changed after each successful comparison to control an output waveform or to establish a new elapsed timeout. An interrupt can also accompany a successful output compare if the output compare interrupt enable bit (OCIE) is set. After a CPU write cycle to the MSB of the output compare register pair (OCRH), the output compare function is inhibited until the LSB (OCRL) is written. Both bytes must be written if the MSB is written. A write made only to the LSB will not inhibit the compare function. The free-running counter increments every four PH2 clock cycles. The minimum time required to update the output compare registers is a function of software rather than hardware. The output compare output level bit (OLVL) will be clocked to its output latch regardless of the state of the output compare flag bit (OCF). A valid output compare must occur before the OLVL bit is clocked to its output latch (TCMP). 16 17 18 19 20 16-BIT TIMER 10-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Since neither the output compare flag (OCF) nor the output compare registers are affected by reset, care must be exercised when initializing the output compare function. The following procedure is recommended: 1. Block interrupts by setting the I bit in the condition code register (CCR). 2. Write the MSB of the output compare register pair (OCRH) to inhibit further compares until the LSB is written. 3. Read the timer status register (TSR) to arm the output compare flag (OCF). 4. Write the LSB of the output compare register pair (OCRL) to enable the output compare function and to clear its flag (and interrupt). 5. Unblock interrupts by clearing the I bit in the CCR. 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... This procedure prevents the output compare flag bit (OCF) from being set between the time it is read and the time the output compare registers are updated. A software example is shown in Figure 10-7. 9B . . B6 BE B7 B6 BF . . . XX XX 16 13 17 . SEI . . LDA LDX STA LDA STX . . . DATAH DATAL OCRH TSR OCRL . BLOCK INTERRUPTS . . HI BYTE FOR COMPARE LO BYTE FOR COMPARE INHIBIT OUTPUT COMPARE ARM OCF BIT TO CLEAR READY FOR NEXT COMPARE . Figure 10-7. Output Compare Software Initialization Example 16-BIT TIMER Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.4 Input Capture 8 2 3 4 5 Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input capture. They are used to latch the value of the free-running counter after a defined transition is sensed by the input capture edge detector. NOTE The input capture edge detector contains a Schmitt trigger to improve noise immunity. Freescale Semiconductor, Inc... 6 7 8 Bit 7 ICRH $0014 Read: ICRH7 Write: Reset: X X X X X X X X ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0 6 5 4 3 2 1 Bit 0 The edge that triggers the counter transfer is defined by the input edge bit (IEDG) in register TCR. Reset does not affect the contents of the input capture registers. See Figure 10-3. 9 10 11 Bit 7 ICRL $0015 Read: ICRL7 Write: Reset: X 6 ICRL6 X 5 ICRL5 X 4 ICRL4 X 3 ICRL3 X 2 ICRL2 X 1 ICRL1 X Bit 0 ICRL0 X 12 13 14 A Figure 10-8. Input Compare Registers (ICRH/ICRL) The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the PH2 clock preceding the external transition (see Figure 10-9). This delay is required for internal synchronization. Resolution is affected by the prescaler, allowing the free-running counter to increment once every four PH2 clock cycles. The contents of the free-running counter are transferred to the input capture registers on each proper signal transition regardless of the state of the input capture flag bit (ICF) in register TSR. The input capture registers always contain the free-running counter value which corresponds to the most recent input capture. 16 17 18 19 20 16-BIT TIMER 10-8 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION After a read of the MSB of the input capture register pair (ICRH), counter transfers are inhibited until the LSB of the register pair (ICRL) is also read. This characteristic forces the minimum pulse period attainable to be determined by the time required to execute an input capture software routine in an application. Reading the LSB of the input capture register pair (ICRL) does not inhibit transfer of the free-running counter. Again, minimum pulse periods are ones which allow software to read the LSB of the register pair (ICRL) and perform needed operations. There is no conflict between reading the LSB (ICRL) and the free-running counter transfer, since they occur on opposite edges of the PH2 clock. 8 2 3 4 5 Freescale Semiconductor, Inc... PH2 CLOCK 6 7 $FFEB $FFEC $FFED $FFEE $FFEF 16-BIT FREE-RUNNING COUNTER TCAP PIN 8 9 INPUT CAPTURE LATCH INPUT CAPTURE REGISTER INPUT CAPTURE FLAG (SEE NOTE) 10 11 $???? $FFED 12 13 14 A 16 17 18 19 20 16-BIT TIMER NOTE: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture flag is set during the next T11 timer state. Figure 10-9. State Timing Diagram for Input Capture Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.5 Timer Control Register (TCR) 8 2 3 4 5 The timer control (TCR) shown in Figure 10-3 and free-running counter (TMRH, TMRL, ACRH, and ACRL) registers are the only registers of the 16-bit timer affected by reset. The output compare port (TCMP) is forced low after reset and remains low until OLVL is set and a valid output compare occurs. Bit 7 TCR $0012 Read: ICIE Write: Reset: 0 0 0 0 0 0 X 0 OCIE TOIE 6 5 4 0 3 0 2 0 IEDG OLVL 1 Bit 0 Freescale Semiconductor, Inc... 6 7 8 9 = Unimplemented Figure 10-10. Timer Control Register (TCR) ICIE — Input Capture Interrupt Enable Bit 7, when set, enables input capture interrupts to the CPU. The interrupt will occur at the same time bit 7 (ICF) in the TSR register is set. OCIE —Output Compare Interrupt Enable Bit 6, when set, enables output compare interrupts to the CPU. The interrupt will occur at the same time bit 6 (OCF) in the TSR register is set. TOIE — Timer Overflow Interrupt Enable Bit 5, when set, enables timer overflow (rollover) interrupts to the CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR register is set. IEDG — Input Capture Edge Select Bit 1 selects which edge of the input capture signal will trigger a transfer of the contents of the free-running counter registers to the input capture registers. Clearing this bit will select the falling edge; setting it selects the rising edge. OLVL — Output Compare Output Level Select Bit 0 selects the output level (high or low) that is clocked into the output compare output latch at the next successful output compare. 10 11 12 13 14 A 16 17 18 19 20 16-BIT TIMER 10-10 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.6 Timer Status Register (TSR) Reading the timer status register (TSR) satisfies the first condition required to clear status flags and interrupts. See Figure 10-3. The only remaining step is to read (or write) the register associated with the active status flag (and/or interrupt). This method does not present any problems for input capture or output compare functions. However, a problem can occur when using a timer interrupt function and reading the free-running counter at random times to, for example, measure an elapsed time. If the proper precautions are not designed into the application software, a timer interrupt flag (TOF) could unintentionally be cleared if: 8 2 3 4 5 6 7 8 9 Freescale Semiconductor, Inc... 1. The TSR is read when bit 5 (TOF) is set, and 2. The LSB of the free-running counter is read, but not for the purpose of servicing the flag or interrupt. The alternate counter registers (ACRH and ACRL) contain the same values as the timer registers (TMRH and TMRL). Registers ACRH and ACRL can be read at any time without affecting the timer overflow flag (TOF) or interrupt. Bit 7 TSR $0013 Read: Write: Reset: X X X 0 0 0 0 0 ICF 6 OCR 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0 10 11 12 13 = Unimplemented Figure 10-11. Timer Status Register (TSR) ICF — Input Capture Flag Bit 7 is set when the edge specified by IEDG in register TCR has been sensed by the input capture edge detector fed by pin TCAP. This flag and the input capture interrupt can be cleared by reading register TSR followed by reading the LSB of the input capture register pair (ICRL). OCF — Output Compare Flag Bit 6 is set when the contents of the output compare registers match the contents of the free-running counter. This flag and the output compare interrupt can be cleared by reading register TSR followed by writing the LSB of the output compare register pair (OCRL). 14 A 16 17 18 19 20 16-BIT TIMER Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION TOF — Timer Overflow Flag 8 2 3 4 5 Bit 5 is set by a rollover of the free-running counter from $FFFF to $0000. This flag and the timer overflow interrupt can be cleared by reading register TSR followed by reading the LSB of the timer register pair (TMRL). 10.7 Timer Operation During Wait/Halt Modes During wait and halt modes, the 16-bit timer continues to operate normally and may generate an interrupt to trigger the MCU out of the wait/halt mode. 10.8 Timer Operation During Stop Mode When the MCU enters the stop mode, the free-running counter stops counting (the PH2 clock is stopped). It remains at that particular count value until the stop mode is exited by applying a low signal to the IRQ pin, at which time the counter resumes from its stopped value as if nothing had happened. If stop mode is exited via an external RESET (logic low applied to the RESET pin), the counter is forced to $FFFC. If a valid input capture edge occurs at the TCAP pin during stop mode the input capture detect circuitry will be armed. This action does not set any flags or “wake up” the MCU, but when the MCU does “wake up” there will be an active input capture flag (and data) from the first valid edge. If the stop mode is exited by an external RESET, no input capture flag or data will be present even if a valid input capture edge was detected during stop mode. Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 16-BIT TIMER 10-12 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 11 SERIAL INPUT/OUTPUT PORT 11.1 Introduction The simple synchronous serial input/output port (SIOP) subsystem is designed to provide efficient serial communications between peripheral devices or other MCUs. The SIOP is implemented as a 3-wire master/slave system with serial clock (SCK), serial data Input (SDI), and serial data output (SDO). A block diagram of the SIOP is shown in Figure 11-1. The SIOP subsystem shares its input/output pins with port B. When the SIOP is enabled (SPE bit set in register SCR), port B data direction registers (DDR) and data registers are modified by the SIOP. Although port B DDR and data registers can be altered by application software, these actions could affect the transmitted or received data. 3 4 5 6 7 8 9 10 Freescale Semiconductor, Inc... HCO5 INTERNAL BUS 11 SPE 12 13 76543210 76543210 76543210 BAUD CONTROL REGISTER $0A GENERATOR STATUS RATE REGISTER $0B 14 SDO SDI I/O CONTROL LOGIC SDI/PB6 SDO/PB5 8-BIT SHIFT REGISTER $0C A 16 SCK PH2 CLOCK SCK/PB7 17 18 19 20 Figure 11-1. SIOP Block Diagram SERIAL INPUT/OUTPUT PORT Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 11.2 SIOP Signal Format 8 2 3 4 5 The SIOP subsystem is software configurable for master or slave operation. No external mode selection inputs are available (such as the slave select pin). 11.2.1 Serial Clock (SCK) The state of the SCK output normally remains a logic one during idle periods between data transfers. The first falling edge of SCK signals the beginning of a data transfer. At this time the first bit of received data is accepted at the SDI pin and the first bit of transmitted data is presented at the SDO pin (see Figure 11-2). Data is captured at the SDI pin on the rising edge of SCK, and the first bit of transmitted data is presented at the SDO pin. The transfer is terminated upon the eighth rising edge of SCK. BIT 0 SDO BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Freescale Semiconductor, Inc... 6 7 8 9 SCK 100 ns SDI BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 100 ns 10 11 12 13 14 A Figure 11-2. SIOP Timing Diagram The master and slave modes of operation differ only by the sourcing of SCK. In master mode, SCK is driven from an internal source within the MCU. In slave mode, SCK is driven from a source external to the MCU. The SCK frequency is programmable via the mask option register 1 (MOR1). Available rates are OSC divided by 2, 4, 8, or 16. 16 17 18 19 20 NOTE OSC divided by 2 is four times faster than the standard rate available on the 68HC05P6. Refer to 8.4 Mask Option Registers (MOR) for a description of available mask option registers. SERIAL INPUT/OUTPUT PORT 11-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 11.2.2 Serial Data Input (SDI) The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New data is presented to the SDI pin on the falling edge of SCK. Valid data must be present at least 100 nanoseconds before the rising edge of SCK and remain valid for 100 nanoseconds after the rising edge of SCK. See Figure 11-2. 11.2.3 Serial Data Output (SDO) The SDO pin becomes an output as soon as the SIOP subsystem is enabled. Prior to enabling the SIOP, PB5 can be initialized to determine the beginning state. While the SIOP is enabled, PB5 cannot be used as a standard output since that pin is connected to the last stage of the SIOP serial shift register. The data can be transmitted in either MSB first format or the LSB format by programming the MOR1. On the first falling edge of SCK, the first data bit will be shifted out to the SDO pin. The remaining data bits will be shifted out to the SDI pin on subsequent falling edges of SCK. The SDO pin will present valid data at least 100 nanoseconds before the rising edge of the SCK and remain valid for 100 nanoseconds after the rising edge of SCK. See Figure 11-2. 11.3 SIOP Registers The SIOP is programmed and controlled by the SIOP control register (SCR) located at address $000A, the SIOP status register (SSR) located at address $000B, and the SIOP data register (SDR) located at address $000C. 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... SERIAL INPUT/OUTPUT PORT Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 11.3.1 SIOP Control Register (SCR) 8 2 3 4 5 This register is located at address $000A and contains two bits. Figure 11-3 shows the position of each bit in the register and indicates the value of each bit after reset. Bit 7 SCR $000A Read: Write: Reset: 0 0 6 SPE 0 5 0 4 MSTR 3 0 2 0 1 0 Bit 0 0 0 0 0 0 0 0 = Unimplemented Freescale Semiconductor, Inc... 6 7 8 9 Figure 11-3. SIOP Control Register SPE — Serial Peripheral Enable When set, the SPE bit enables the SIOP subsystem such that SDO/PB5 is the serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a serial clock input in the slave mode or a serial clock output in the master mode. Port B DDR and data registers can be manipulated as usual (except for PB5); however, these actions could affect the transmitted or received data. The SPE bit is readable and writable at any time. Clearing the SPE bit while a transmission is in progress will 1) abort the transmission, 2) reset the serial bit counter, and 3) convert the port B/SIOP port to a general-purpose I/O port. Reset clears the SPE bit. MSTR — Master Mode Select When set, the MSTR bit configures the serial I/O port for master mode. A transfer is initiated by writing to the SDR. Also, the SCK pin becomes an output providing a synchronous data clock dependent upon the oscillator frequency. When the device is in slave mode, the SDO and SDI pins do not change function. These pins behave exactly the same in both the master and slave modes. The MSTR bit is readable and writable at any time regardless of the state of the SPE bit. Clearing the MSTR bit will abort any transfers that may have been in progress. Reset clears the MSTR bit, placing the SIOP subsystem in slave mode. 10 11 12 13 14 A 16 17 18 19 20 SERIAL INPUT/OUTPUT PORT 11-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 11.3.2 SIOP Status Register (SSR) This register is located at address $000B and contains two bits. Figure 11-3 shows the position of each bit in the register and indicates the value of each bit after reset. 8 2 3 4 Bit 7 SSR $000B Read: Write: Reset: 0 SPIF 6 DCOL 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0 0 0 0 0 0 0 = Unimplemented 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... Figure 11-4. SIOP Status Register SPIF — Serial Port Interface Flag SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data transfer has been completed. It has no effect on any future data transfers and can be ignored. The SPIF bit is cleared by reading the SSR followed by a read or write of the SDR. If the SPIF is cleared before the last rising edge of SCK, it will be set again on the last rising edge of SCK. Reset clears the SPIF bit. DCOL — Data Collision DCOL is a read-only status bit which indicates that an illegal access of the SDR has occurred. The DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF is set. Reading or writing the SDR during this time will result in invalid data being transmitted or received. The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or write of the SDR. If the last part of the clearing sequence is done after another transfer has started, the DCOL bit will be set again. Reset clears the DCOL bit. SERIAL INPUT/OUTPUT PORT Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 11.3.3 SIOP Data Register (SDR) 8 2 3 4 5 This register is located at address $000C and serves as both the transmit and receive data register. Writing to this register will initiate a message transmission if the SIOP is in master mode. The SIOP subsystem is not double buffered and any write to this register will destroy the previous contents. The SDR can be read at any time; however, if a transfer is in progress, the results may be ambiguous and the DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted and/or received. Figure 11-3 shows the position of each bit in the register. This register is not affected by reset. Freescale Semiconductor, Inc... Bit 7 SDR $000C Read: SD7 Write: Reset: 6 SD6 5 SD5 4 SD4 3 SD3 2 SD2 1 SD1 Bit 0 SD0 6 7 8 9 Unaffected by reset Figure 11-5. SIOP Data Register 10 11 12 13 14 A 16 17 18 19 20 SERIAL INPUT/OUTPUT PORT 11-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SECTION 12 INSTRUCTION SET 12.1 Introduction This section describes the addressing modes and instruction types. Freescale Semiconductor, Inc... 12.2 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are: • • • • • • • • Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative 12.2.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long. 12.2.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. INSTRUCTION SET Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.2.3 Direct Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are 3-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 12.2.4 Extended Extended instructions use only three bytes to access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. 12.2.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the conditional address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. 12.2.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. Freescale Semiconductor, Inc... INSTRUCTION SET 12-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.2.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. Freescale Semiconductor, Inc... As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. 12.2.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch. INSTRUCTION SET Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.3 Instruction Types The MCU instructions fall into five categories: • • • • • Register/Memory instructions Read-Modify-Write instructions Jump/Branch instructions Bit Manipulation instructions Control instructions 12.3.1 Register/Memory Instructions Freescale Semiconductor, Inc... Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 12-1 lists the register/memory instructions. Table 12-1. Register/Memory Instructions Instruction Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB INSTRUCTION SET 12-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.3.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST) is an exception to the read-modify-write sequence because it does not write a replacement value. Table 12-2 lists the read-modify-write instructions. Table 12-2. Read-Modify-Write Instructions Instruction Arithmetic Shift Left Mnemonic ASL ASR BCLR BSET CLR COM DEC INC LSL LSR NEG ROL ROR TST Freescale Semiconductor, Inc... Arithmetic Shift Right Clear Bit in Memory Set Bit in Memory Clear Complement (One’s Complement) Decrement Increment Logical Shift Left Logical Shift Right Negate (Two’s Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero 12.3.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump to subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions use relative addressing. Bit test and branch instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition INSTRUCTION SET Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 12-3 lists the jump and branch instructions. Table 12-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR Freescale Semiconductor, Inc... Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine INSTRUCTION SET 12-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.3.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Bit manipulation instructions use direct addressing. Table 12-4 lists these instructions. Table 12-4. Bit Manipulation Instructions Instruction Clear Bit Mnemonic BCLR BRCLR BRSET BSET Freescale Semiconductor, Inc... Branch if Bit Clear Branch if Bit Set Set Bit 12.3.5 Control Instructions These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 12-5, use inherent addressing. Table 12-5. Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT INSTRUCTION SET Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.4 Instruction Set Summary Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 12-6. Instruction Set Summary Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel Operation Description HINZC Freescale Semiconductor, Inc... Add with Carry A ← (A) + (M) + (C) ¤—¤ ¤ ¤ IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL A9 ii B9 dd C9 hh ll D9 ee ff E9 ff F9 AB ii BB dd CB hh ll DB ee ff EB ff FB A4 ii B4 dd C4 hh ll D4 ee ff E4 ff F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 dd Add without Carry A ← (A) + (M) ¤—¤ ¤ ¤ Logical AND A ← (A) ∧ (M) —— ¤ ¤ — Arithmetic Shift Left (Same as LSL) C b7 b0 0 —— ¤ ¤ ¤ ff dd Arithmetic Shift Right b7 b0 C —— ¤ ¤ ¤ ff Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? C = 0 ————— rr dd dd dd dd dd dd dd dd rr rr BCLR n opr Clear Bit n Mn ← 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ————— DIR (b4) DIR (b5) DIR (b6) DIR (b7) ————— ————— REL REL BCS rel BEQ rel Branch if Carry Bit Set (Same as BLO) Branch if Equal PC ← (PC) + 2 + rel ? C = 1 PC ← (PC) + 2 + rel ? Z = 1 INSTRUCTION SET 12-8 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Cycles 2 3 4 5 4 3 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form BHCC rel BHCS rel BHI rel BHS rel Operation Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Description PC ← (PC) + 2 + rel ? H = 0 PC ← (PC) + 2 + rel ? H = 1 HINZC ————— ————— REL REL REL REL REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL 28 29 22 24 2F 2E rr rr rr rr rr rr PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — — PC ← (PC) + 2 + rel ? C = 0 PC ← (PC) + 2 + rel ? IRQ = 1 PC ← (PC) + 2 + rel ? IRQ = 0 ————— ————— ————— Freescale Semiconductor, Inc... BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Bit Test Accumulator with Memory Byte (A) ∧ (M) —— ¤ ¤ — A5 ii B5 dd C5 hh ll D5 ee ff E5 ff F5 p 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 00 02 04 06 08 0A 0C 0E 21 rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC ← (PC) + 2 + rel ? C = 1 ————— PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — PC ← (PC) + 2 + rel ? I = 0 PC ← (PC) + 2 + rel ? N = 1 PC ← (PC) + 2 + rel ? I = 1 PC ← (PC) + 2 + rel ? Z = 0 PC ← (PC) + 2 + rel ? N = 0 PC ← (PC) + 2 + rel ? 1 = 1 ————— ————— ————— ————— ————— ————— BRCLR n opr rel Branch if bit n clear PC ← (PC) + 2 + rel ? Mn = 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ———— ¤ DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ———— ¤ DIR (b4) DIR (b5) DIR (b6) DIR (b7) ————— REL BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 INSTRUCTION SET Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Cycles 3 3 3 3 3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form Operation Description Cycles 5 5 5 5 5 5 5 5 6 2 2 dd 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 Effect on CCR HINZC BSET n opr Set Bit n Mn ← 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ————— DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd Freescale Semiconductor, Inc... BSR rel Branch to Subroutine Clear Carry Bit Clear Interrupt Mask PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel C←0 I←0 M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 ————— REL AD CLC CLI CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X ———— 0 — 0 ——— INH INH DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX 98 9A 3F 4F 5F 6F 7F Clear Byte —— 0 1 — Compare Accumulator with Memory Byte (A) – (M) —— ¤ ¤ ¤ A1 ii B1 dd C1 hh ll D1 ee ff E1 ff F1 33 43 53 63 73 dd Complement Byte (One’s Complement) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) —— ¤ ¤ 1 Compare Index Register with Memory Byte (X) – (M) —— ¤ ¤ 1 A3 ii B3 dd C3 hh ll D3 ee ff E3 ff F3 3A 4A 5A 6A 7A dd Decrement Byte M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 —— ¤ ¤ — EXCLUSIVE OR Accumulator with Memory Byte A ← (A) ⊕ (M) —— ¤ ¤ — A8 ii B8 dd C8 hh ll D8 ee ff E8 ff F8 INSTRUCTION SET 12-10 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Operand rr ff ff ff Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL Operation Description M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 HINZC Increment Byte —— ¤ ¤ — DIR INH INH IX1 IX DIR EXT IX2 IX1 IX 3C 4C 5C 6C 7C dd ff Freescale Semiconductor, Inc... Unconditional Jump PC ← Jump Address ————— BC C dd C hh ll D ee ff ff C EC FC BD C dd D hh ll D ee ff ff D ED FD A6 ii B6 dd C6 hh ll D6 ee ff E6 ff F6 AE ii BE dd CE hh ll DE ee ff EE ff FE 38 48 58 68 78 34 44 54 64 74 42 dd Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Conditional Address ————— DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH Load Accumulator with Memory Byte A ← (M) —— ¤ ¤ — Load Index Register with Memory Byte X ← (M) —— ¤ ¤ — Logical Shift Left (Same as ASL) C b7 b0 0 —— ¤ ¤ ⋅ ff dd Logical Shift Right 0 b7 b0 C —— 0 ¤ ¤ ff Unsigned Multiply X : A ← (X) × (A) 0 ——— 0 11 INSTRUCTION SET Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Cycles 5 3 3 6 5 2 3 4 3 2 5 6 7 6 5 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP Operation Description M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) HINZC Negate Byte (Two’s Complement) —— ¤ ¤ ¤ DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH 30 40 50 60 70 9D ii ff No Operation ————— Freescale Semiconductor, Inc... Logical OR Accumulator with Memory A ← (A) ∨ (M) —— ¤ ¤ — AA ii BA dd CA hh ll DA ee ff EA ff FA 39 49 59 69 79 36 46 56 66 76 9C dd Rotate Byte Left through Carry Bit C b7 b0 —— ¤ ¤ ¤ ff dd Rotate Byte Right through Carry Bit C b7 b0 —— ¤ ¤ ¤ ff Reset Stack Pointer SP ← $00FF SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) ————— RTI Return from Interrupt ¤¤¤¤¤ INH 80 RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP Return from Subroutine INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH A2 ii B2 dd C2 hh ll D2 ee ff E2 ff F2 99 9B B7 dd C7 hh ll D7 ee ff E7 ff F7 8E 2 3 4 5 4 3 2 2 4 5 6 5 4 2 Subtract Memory Byte and Carry Bit from Accumulator A ← (A) – (M) – (C) —— ¤ ¤ ¤ Set Carry Bit Set Interrupt Mask C←1 I←1 ———— 1 — 1 ——— Store Accumulator in Memory M ← (A) —— ¤ ¤ — Stop Oscillator and Enable IRQ Pin — 0 ——— INSTRUCTION SET 12-12 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Cycles 5 3 3 6 5 2 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 2 6 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Opcode Source Form STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Operation Description HINZC Store Index Register In Memory M ← (X) —— ¤ ¤ — DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX BF dd CF hh ll DF ee ff EF ff FF A0 ii B0 dd C0 hh ll D0 ee ff E0 ff F0 Freescale Semiconductor, Inc... Subtract Memory Byte from Accumulator A ← (A) – (M) —— ¤ ¤ ¤ SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) — 1 ——— SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte X ← (A) ————— INH 83 10 TAX TST opr TSTA TSTX TST opr,X TST ,X TXA Transfer Accumulator to Index Register INH DIR INH INH IX1 IX INH 97 3D 4D 5D 6D 7D 9F dd Test Memory Byte for Negative or Zero (M) – $00 ————— ff Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts A ← (X) ————— WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n — ¤ ——— opr PC PCH PCL REL rel rr SP X Z # ∧ ∨ ⊕ () –( ) ← ? : ¤ — INH 8F Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Loaded with If Concatenated with Set or cleared Not affected INSTRUCTION SET Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Cycles 4 5 6 5 4 2 3 4 5 4 3 2 4 3 3 5 4 2 2 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc... Table 12-7. Opcode Map Read-Modify-Write Control Register/Memory IMM DIR EXT IX2 IX1 IX F 4 3 12-14 DIR INH INH IX1 IX INH 8 9 9 2 3 4 5 5 Branc Bit h Manipulation DIR DIR REL INH A B C D E SUB IX1 1 4 IX2 2 5 MSB LSB 0 2 3 4 5 6 7 6 3 3 5 3 1 BRA REL 2 3 INH 6 DIR 1 INH 1 INH 2 IX1 1 IX 1 2 IMM 2 2 DIR 3 3 EXT 3 4 MSB LSB SUB IX 3 5 5 0 NEG RTS 1 INH 11 2 IMM 2 2 DIR 3 3 EXT 3 4 BRSET0 BRN REL 3 BSET0 CMP SBC 2 3 6 5 10 IMM 2 2 DIR 3 3 EXT 3 4 NEGA CMP SBC CPX DIR 3 3 NEGX CMP SBC CPX EXT 3 4 NEG CMP IX2 2 5 NEG RTI SUB SUB SUB SUB 3 DIR 2 5 DIR 2 5 0 CMP IX1 1 4 IX 3 1 BHI REL 3 5 INH 3 1 BRCLR0 MUL COM DIR 1 5 INH INH 1 3 INH 2 3 IX1 1 6 IX 1 5 2 IMM 2 2 BCLR0 SBC CMP SBC 3 DIR 2 5 DIR 2 5 1 SBC IX1 1 4 IX 3 2 BLS REL 2 3 BRSET1 COMA LSRA INH 1 IX INH 2 IX1 1 2 IMM 2 2 DIR 3 3 BSET1 COMX LSRX BIT 2 5 3 3 6 5 IMM 2 2 3 DIR 2 5 DIR 2 5 IX2 2 5 2 CPX IX2 2 5 3 COM LSR BIT DIR 3 3 BRCLR1 BCC REL 2 3 REL 3 DIR 1 BCLR1 LSR LSR AND AND AND COM SWI CPX CPX IX1 1 4 CPX IX 3 3 DIR 2 5 DIR 2 5 3 AND AND AND IX2 2 5 IX1 1 4 IX 3 4 BCS/BLO BNE REL 2 3 IX 5 2 DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 2 BRSET2 BSET2 3 DIR 2 5 DIR 2 5 EXT 3 4 4 BIT EXT 3 4 5 ROR ASR DIR 1 5 IX 5 INH 2 INH 1 3 INH 2 3 IX1 1 6 1 BRCLR2 RORA ASRA ASL/LSL IX 5 1 BCLR2 RORX ASRX CLC INH 2 2 BIT IX2 2 5 BIT IX1 1 4 BIT IX 3 3 DIR 2 5 DIR 2 5 5 LDA DIR 3 4 EXT 3 5 6 ROR ASR ASR TAX ROR LDA BEQ REL 2 3 BRSET3 BSET3 LDA STA 2 2 DIR 3 3 LDA IX2 2 6 LDA IX1 1 5 LDA IX 4 3 DIR 2 5 DIR 2 5 IMM 2 6 STA EXT 3 4 7 BHCC REL 2 3 DIR 1 5 INH 1 3 INH 2 3 IX1 1 6 BRCLR3 ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ROL DIR 1 5 IX 5 INH 1 3 INH 2 3 IX1 1 6 1 BCLR3 STA IX2 2 5 STA IX1 1 4 STA IX 3 3 DIR 2 5 DIR 2 5 7 EOR IMM 2 2 DIR 3 3 INSTRUCTION SET EOR ADC INH 2 2 IMM 2 2 8 BHCS REL 2 3 BRSET4 ROLA DECA INH 1 IX INH 2 IX1 1 BSET4 ROLX DECX DEC DEC 1 EOR EXT 3 4 EOR IX2 2 5 EOR IX1 1 4 EOR IX 3 3 DIR 2 5 DIR 2 5 8 ADC DIR 3 3 9 ROL ROL BPL REL 2 3 DIR 1 BRCLR4 DEC BCLR4 SEC CLI INH 2 2 ADC EXT 3 4 ADC IX2 2 5 ADC IX1 1 4 ADC IX 3 3 DIR 2 5 DIR 2 5 9 ORA IMM 2 2 A BMI REL 3 5 3 3 6 5 BRSET5 BSET5 ORA DIR 3 3 ORA EXT 3 4 ORA IX2 2 5 ORA IX1 1 4 ORA IX 3 3 DIR 2 5 DIR 2 5 A SEI 1 INH 2 2 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ADD IMM 2 B BMC REL 2 3 DIR 1 4 INH 1 3 INH 2 3 IX1 1 5 BRCLR5 INC TST DIR 1 INH 1 INH 2 BCLR5 INCA TSTA TSTX TST IX1 1 ADD DIR 3 2 ADD EXT 3 3 ADD IX2 2 4 ADD IX1 1 3 ADD IX 2 3 DIR 2 5 DIR 2 5 B RSP JMP JMP JMP JMP JMP 1 2 C INCX INC INC BMS REL 2 3 BRSET6 BSET6 3 DIR 2 5 DIR 2 5 IX 4 C INH 2 6 DIR 3 5 EXT 3 6 IX2 2 7 IX1 1 6 IX 5 D BIL REL 3 5 3 3 BRCLR6 BCLR6 TST IX 2 1 NOP INH 2 BSR REL 2 2 JSR DIR 3 3 JSR EXT 3 4 JSR IX2 2 5 JSR IX1 1 4 JSR IX 3 3 DIR 2 5 DIR 2 5 D STOP 1 2 E BIH REL 2 DIR 1 INH 1 BRSET7 CLR CLRA CLRX INH 2 BSET7 LDX IMM 2 6 5 INH 2 2 LDX DIR 3 4 LDX EXT 3 5 LDX IX2 2 6 LDX IX1 1 5 LDX IX 4 3 DIR 2 5 DIR 2 5 E CLR IX1 1 F BRCLR7 BCLR7 CLR IX 1 WAIT INH 1 TXA INH 2 STX DIR 3 STX EXT 3 STX IX2 2 STX IX1 1 STX IX 3 DIR 2 DIR 2 F MSB LSB LSB of Opcode in Hexadecimal 0 3 0 MSB of Opcode in Hexadecimal 5 Number of Cycles BRSET0 Opcode Mnemonic DIR Number of Bytes/Addressing Mode MC68HC805P18 REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset INH = Inherent IMM = Immediate DIR = Direct EXT = Extended Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 13 ELECTRICAL SPECIFICATIONS 13.1 Introduction This section contains electrical and timing specifications for the MC68HC805P18. 3 4 5 6 Freescale Semiconductor, Inc... 13.2 Maximum Ratings Rating Supply Voltage Input Voltage Factory Mode (IRQ Pin Only) Current Drain Per Pin Excluding VDD and VSS Storage Temperature Range NOTE: Voltages referenced to VSS Symbol VDD VIN VIN I TSTG Value –0.3 to +7.0 VSS –0.3 to VDD + 0.3 VSS –0.3 to 2 x VDD 25 –65 to +150 Unit V V V mA °C 7 8 9 10 11 12 13.3 Operating Temperature Range Rating Operating Temperature Range MC68HC805P18 (Standard) MC68HC805P18 (Extended) MC68HC805P18 (Automotive) Symbol Value TL to TH 0 to +70 –40 to +85 –40 to +125 Unit 13 14 A TA °C NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for instance, either VSS or VDD). 16 17 18 19 20 ELECTRICAL SPECIFICATIONS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.4 Thermal Characteristics 8 2 3 4 5 Thermal Resistance Plastic SOIC Characteristic Symbol θJA Value 60 60 Unit °C/W 13.5 Power Considerations The average chip-junction temperature, TJ, in °C, can be obtained from: TJ = TA + (PD × θJA) where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction to ambient, °C/W. PD = PINT + PI/O PINT = IDD × VDD watts (chip internal power) PI/O = Power dissipation on input and output pins (user-determined) For most applications, PI/O « PINT and can be neglected. The following is an approximate relationship between PD and TJ (neglecting PI/O): PD = K ÷ (TJ + 273 °C) Solving equations (1) and (2) for K gives: K = PD × (TA + 273 °C) + θJA × (PD)2 (3) (2) (1) Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. 16 17 18 19 20 ELECTRICAL SPECIFICATIONS 13-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.6 DC Electrical Characteristics (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C) Characteristic Output Voltage ILoad = 10.0 µA Output High Voltage (ILoad = –0.8 mA) PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT Output Low Voltage (ILoad = 1.6 mA) PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT Input High Voltage PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT, TCAP/PD7, IRQ, RESET, OSC1 Input Low Voltage PA0–PA7, PB5–PB7, PC0–PC7, PD5, TCAP/PD7, IRQ, RESET, OSC1 Supply Current Run Wait (see Note 3) Stop (see Note 8) 25 °C 0 °C to +70 °C (Standard) –40 °C to +85 °C (Extended) –40 °C to +125 °C (Automotive I/O Ports Hi-Z Leakage Current PA0–PA7, PB5–PB7, PC0–PC7, PD5/CKOUT, TCAP/PD7 I/O Ports Switch Resistance (Pullup Enabled PA0–PA7) A/D Ports Hi-Z Leakage Current PC3–PC7 Input Current RESET, IRQ, OSC1 Capacitance Ports (as Input or Output) RESET, IRQ EEPROM Program/Erase Time (128 Byte Array) Byte Block (Erase Only) Bulk (Erase Only) Low Voltage Reset Voltage Symbol VOL VOH VOH Min — VDD –0.1 VDD –0.8 Typ — — — Max 0.1 — — Unit V 8 2 3 4 5 6 V VOL — — 0.4 V VIH 0.7 x VDD — VDD V Freescale Semiconductor, Inc... VIL VSS — 0.2 x VDD V 7 — — IDD — — — — — 4.75 2.75 TBD TBD TBD TBD — 7.50 5.00 350 400 500 500 ±10 mA mA µA µA µA µA µA 8 9 10 11 12 13 14 A IIL RPTA IIL IIN COUT CIN 62 — — — — — 102 ±1 ±1 k µA µA — — — — — 3.6 — — 2 5 10 3.8 12 8 10 15 50 — pF ms 16 17 18 19 20 V NOTES: 1. All values shown reflect average measurements. 2. Typical vlaues at midpoint of voltage range, 25 °C only. 3. Wait IDD with active systems: Timer, SIOP, and A/D. 4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2 5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V 6. Stop IDD measured with OSC1 = VSS 7. Wait IDD is affected linearly by the OSC2 capacitance. 8. Stop IDD maximum values given with LVR option enabled. ELECTRICAL SPECIFICATIONS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.7 Active Reset Characteristics 8 2 3 4 5 Rise Time 0.5 µs 1.0 µs 2.5 µs Fall Time 13 ns 20 ns 20 ns Pulse Width 2.4 µs 2.7 µs 2.7 µs CLoad 50 pF 100 pF 250 pF Pullup 10 K 10 K 10 K NOTE: VDD = 4.5 Vdc, VSS = 0 Vdc, TA = 125 °C 13.8 A/D Converter Characteristics (VDD = 4.5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise noted) Characteristic Resolution Absolute Accuracy (VDD ≥ VREFH > 4.5) Conversion Range VREFH Input Leakage AD0, AD1, AD2, AD3 VREFH Conversion Time (Includes Sampling Time) Monotonicity Zero Input Reading Full-Scale Reading Sample Time Input Capacitance Analog Input Voltage 00 FE 12 — VSS 01 FF 12 12 VREFH Min 8 — VSS VSS — — 32 Max 8 ± 1 1/2 VREFH VDD ±1 ±1 32 Unit Bits LSB V Including quantization A/D accuracy may decrease proportionately as VREFH is reduced below 4.5 Comments Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 A µA µA tAD* Inherent (Within Total Error) Hex Hex tAD* pF V Vin = 0 V Vin = VREFH *tAD = tcyc if clock source equals MCU 16 17 18 19 20 ELECTRICAL SPECIFICATIONS 13-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.9 SIOP Timing (VDD = 4.5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise note) Number Characteristic Operating Frequency Master Slave 1 2 3 Cycle Time Master Slave SCK Low Time SDO Data Valid Time SDO Hold Time SDI Setup Time SDI Hold Time Symbol fSIOP(M) fSIOP(S) tSCK(M) tSCK(S) tCYC tv tHO tS tH Min 1 dc 1 — 238 — 0 100 100 Max 1 1 1 1 — 200 — — — Unit fOP 8 2 3 tCYC ns ns ns ns ns 4 5 6 7 8 9 Freescale Semiconductor, Inc... 4 5 6 NOTES: 1. fOP = fOSC ÷ 2 = 2.1 MHz max; tCYC = 1 ÷ fOP 2. In master mode, the SCK rate is determined by the programmable option in MOR1. t1 SCK t2 10 t5 t6 11 12 SDI t3 SDI t4 SDI SDI 13 14 SDI BIT 7 SDI SDI A Figure 13-1. SIOP Timing Diagram 16 17 18 19 20 ELECTRICAL SPECIFICATIONS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.10 OSC Out Timing 8 2 3 4 5 Cycle Time Rise Time Fall Time Pulse Width *Refer to Figure 13-2 Characteristic Symbol 1* 4* 5* 2 and 3* Min 476 3.5 7.5 200 Max — 12 27.5 — Unit ns ns ns ns (1) (2) (3) Freescale Semiconductor, Inc... 6 7 8 9 OSC OUT (4) (5) Figure 13-2. OSC Out Timing 10 11 12 13 14 A NOTE All timing is shown with respect to 20% and 70% VDD. Maximum rise and fall times assume 44% duty cycle. Minimum rise and fall times assume 55% duty cycle 16 17 18 19 20 ELECTRICAL SPECIFICATIONS 13-6 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.11 Control Timing (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise note) Characteristic Frequency of Operation Crystal Option External Clock Option Internal Operating Frequency Crystal (fosc ÷ 2) External Clock (fosc ÷ 2) Cycle Time Crystal Oscillator Startup Time Symbol fOSC Min — dc — dc 476 — — 1.5 125 * 200 — — Max 4.2 4.2 2.1 2.1 — 100 100 — — — — 100 5.0 Unit MHz 8 2 3 MHz ns ms ms tCYC ns tCYC ns µs µs fOP tCYC tOXOV tILCH tRL tILIH tILIL tOH, tOL tADON tRCON 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... Stop Recovery Startup Time (Crystal Oscillator) RESET Pulse Width Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width A/D On Current Stabilization Time RC Oscillator Stabilization Time (A/D) * The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 tCYC. ELECTRICAL SPECIFICATIONS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... 9 8 7 6 5 4 3 2 8 A 14 13 12 11 10 20 GENERAL RELEASE SPECIFICATION t CYC 3FFE 3FFF NEW PC NEW PC 3FFE 3FFE 3FFE 3FFE 3FFF NEW PC NEW PC NEW PCH NEW PCL tRL NOTE 3 OP CODE PCH PCL OP CODE 19 18 17 16 13-8 t VDDR V DD V DD THRESHOLD (1–2 V TYPICAL) OSC12 4064 tCYC INTERNAL PROCESSOR CLOCK1 INTERNAL ADDRESS BUS1 ELECTRICAL SPECIFICATIONS INTERNAL DATA BUS1 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com RESET NOTES: 1. Internal timing signal and bus information not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the PH2 clock following the rising edge of RESET initiates the reset sequence. MC68HC805P18 Figure 13-3. Power-On Reset and External Reset Timing Diagram Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 14 MECHANICAL SPECIFICATIONS 14.1 Introduction This section provides package dimension drawings for the 28-pin dual in-line (DIP) or 28-pin small outline (SOIC) packages. To make sure that you have the latest case outline specifications, contact one of the following: • • Local Motorola Sales Office Motorola Mfax – Phone 602-244-6609 – EMAIL rmfax0@email.sps.mot.com Worldwide Web (wwweb) at http://design-net.com 3 4 5 6 7 8 9 10 11 12 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0° 15° 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0° 15° 0.020 0.040 Freescale Semiconductor, Inc... • Follow Mfax or wwweb on-line instructions to retrieve the current mechanical specifications. 14.2 28-Pin Dual In-Line Package (Case #710) 13 14 A 16 17 18 19 20 28 15 B 1 14 A N C L H G F D K SEATING PLANE M J MECHANICAL SPECIFICATIONS Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 14.3 28-Pin Small Outline Package (Case #751F) 8 2 3 1 -A28 15 14X -B14 P 0.010 (0.25) M B M 4 5 -T- 28X D 0.010 (0.25) M T A S B S M R X 45° C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8° 0° 10.05 10.55 0.75 0.25 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 8° 0° 0.395 0.415 0.010 0.029 Freescale Semiconductor, Inc... 6 7 8 9 26X G K -TSEATING PLANE F J 10 11 12 13 14 A 16 17 18 19 20 MECHANICAL SPECIFICATIONS 14-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 SECTION 15 ORDERING INFORMATION 15.1 Introduction This section contains instructions for ordering the MC68HC805P18. 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... 15.2 MC Order Numbers Table 15-1 shows the MC order numbers for the available package types. Table 15-1. MC Order Numbers MC Order Number MC68HC805P18P (Standard) MC68HC805P18DW (Standard) MC68HC805P18CP (Extended) MC68HC805P18CDW (Extended) MC68HC805P18MP (Automotive) MC68HC805P18MDW (Automotive) P = Plastic Dual In-Line Package DW = Small Outline (Wide Body) Package Operating Temperature Range 0 °C to 70 °C 0 °C to 70 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +125 °C –40 °C to +125 °C ORDERING INFORMATION Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 APPENDIX A EMULATION This appendix discusses the functional differences between the P-series devices. The MC68HC805P18 can be used to emulate the following devices: MC68HC05P1A MC68HC05P7 MC68HC05P2 MC68HC05P7A MC68HC05P3 MC68HC05P8 MC68HC05P4 MC68HC05P9 MC68HC05P4A MC68HC705P9 MC68HC05P6 MC68HC05P10 MC68HC705P6 MC68HC05P18 These functional differences will be summarized in: Table A-1. Elements of Memory Table A-2. Memory Breakdown by Types Table A-3. P-Series Features Table A-4. Mask Options 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... EMULATION Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 P3 Table A-1. Elements of Memory Device RAM 128 b 0080-00FF 96 b 00A0-00FF 128 b 0080-00FF 128 b 0080-00FF 176 b 0050-00FF 176 b 0050-00FF 176 b 0050-00FF 128 b 0080-00FF 112 b 0090-00FF 128 b 0080-00FF 128 b 0080-00FF 128 b 0080-00FF 192 b 0050-010F 192 b 0050-010F User ROM R 2320 b 0020-004F 0100-08FF* R 3088 b 0020-004F 1300-1EFF R 3072 b 0020-004F 0300-0EFF N R 4160 b 0020-004F 0100-10FF R 4672 b 0020-004F 0100-10FF* N R 2112 b 0020-004F 0100-08FF* R 2064 b 1680-1E7F R 2112 b 0020-004F 0100-08FF N R 4160 b 0020-004F 0100-10FF R 8064 b 0020-004F 1FC0-3EFF N EPROM EEPROM User EEPROM N ROM Security N P1A N N P2 N N N N N 3072 b 0020-004F 0300-0EFF N Freescale Semiconductor, Inc... 6 7 8 9 705P3 128 b 0100-017F 128 b 0100-017F N N N N P4/P4A N N N/Y P6 N 4672 b 0020-004F 0100-12FF* N N N N 10 11 12 13 14 A 705P9 P10 705P6 N N N P7/P7A N 32 b 0030-004F N N N/Y P8 N N N P9/P9A N 2112 b 0020-004F 0100-08FF* N N N/Y N N N 16 17 18 19 20 N N N P18 N 128 b 0140-01BF 128 b 0140-01BF N 8064 b 0020-004F 1FC0-3EFF N 805P18 N Y EMULATION A-2 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table A-2. Memory Breakdown by Types Range 0020–004F 0030–004F 0050–007F 0080–008F 0090–009F 00A0–00FF RAM RAM RAM ROM ROM ROM ROM ROM ROM ROM ROME ROME ROM RAM RAM RAM RAM EE EE EE RAM RAM RAM RAM ROM ROM ROM ROM ROM ROM ROM RON ROM ROM RAM RAM RAM RAM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM UEE UEE UEE ROM RAM RAM RAM RAM E E E E E E E E E E E RAM RAM RAM ROM ROM ROM ROM ROM ROM ROM RAM RAM RAM RAM RAM ROME ROME ROME ROME ROME ROME ROME RAM RAM RAM ROM ROM ROM ROM ROM ROM ROM ROM ROM ROM EE EE EE EE ROM P1a ROM P2 ROM P3/ 705P3 ROM/E P4/ P4a ROM P6 ROM 705 P6 ROM P7/ P7a ROM EE RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM P8 P9/ 705P9 ROM/E P10 ROM P18 ROM 805 P18 UEE 8 2 3 4 5 6 7 8 9 10 11 12 13 14 A 16 17 18 19 20 Freescale Semiconductor, Inc... 0100–010F 0110–013F 0140–017F 0180–01BF 01C0–02D1 02D2–02FF 0300–08FF 0900–0EFF 0F00–0FEF 0FF0–10FF 1100–12FF 1300–167F 1680–1EFF 1F00 1F01–1FBF 1FC0–1FEF 1FF0–3EFF 3F00–3F01 3F02–3FEF NOTE: I/O registers are common to all parts so they are not included in the table. There are an additional 16 bytes of user vectors in the memory map for each device. E = EPROM EE = EEPROM PEE = User EEPROM EMULATION Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8 2 3 4 5 Devices P1A P2 P3/705P3 P4/P4A P6/705P6 P7/P7A P8 P9/705P9/P9A P10 P18/805P18 Table A-3. P-Series Features Mask Option Y Y Y/N Y Y/N Y Y Y/N/Y Y Y/N MOR N N N/Y N N/Y N N N/Y/N N N/Y A/D N N N N Y N Y Y N Y LVR N N N N N N N N N Y High Current Y N N N/Y N N/Y N N/N/Y N Y Freescale Semiconductor, Inc... 6 7 8 9 Table A-4. Mask Options Devices P1A P2 P3 P4/P4A P6 P7/P7A P8 P9/P9A P10 P18 10 11 12 13 14 A XTAL/RC Y Y N Y Y Y N N Y N SIOP Clock Rate N N N N Y N N N N Y* SIOP MSB/LSB N N N Y Y Y N Y Y Y Port A PU/INT Y N N N/Y N N/Y N N/Y Y Y STOP to HALT Y N N N/Y Y N/Y N N/Y N Y 16 17 18 19 20 * The MC68HC05P18 and MC68HC805P18 have selectable clock rates that are four times as fast as the MC68HC05P6 selectable rates. EMULATION A-4 For More Information On This Product, Go to: www.freescale.com MC68HC805P18 Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Bit 7 $0F Read: Write: Reset: 0 6 1 5 0 4 0 3 1 2 0 1 OPTCOP Bit 0 OPTIRQ 8 2 Unaffected by reset 3 4 1 IRQ Bit 0 COP Figure A-1. MC68HC705P3 Mask Option Register Bit 7 6 RC 5 SWAIT 4 SPR1 3 SPR0 2 LSBF 5 6 7 8 9 Freescale Semiconductor, Inc... $900 Read: Write: Reset: — Unaffected by reset Figure A-2. MC68HC705P6 Mask Option Register Bit 7 $900 Read: Write: Reset: — 6 — 5 — 4 — 3 — 2 SIOP 1 IRQ Bit 0 COP 10 11 Unaffected by reset 12 Figure A-3. MC68HC705P9 Mask Option Register 13 1 LEVIRQ Bit 0 COPEN Bit 7 Read: MOR1 Write: Reset: CLKOUT 6 LVRE 5 SWAIT 4 SPR1 3 SPR0 2 LSBF 14 A 16 Unaffected by reset Bit 7 Read: MOR2 Write: Reset: PA7PU 6 PA6PU 5 PA5PU 4 PA4PU 3 PA3PU 2 PA2PU 1 PA1PU Bit 0 PA0PU 17 18 Unaffected by reset 19 20 Figure A-4. MC68HC805P18 Mask Option Register EMULATION Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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For More Information On This Product, Go to: www.freescale.com 68HC805P18GRS/D REV 1.0