908E425

Freescale Semiconductor Advance Information Document Number: MM908E425 Rev. 1.0, 8/2006 Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication The 908E425 is an integrated single-package solution including a high-performance HC08 microcontroller with a SMARTMOS TM analog control IC. The HC08 includes Flash Memory, a timer, Enhanced Serial Communications Interface (ESCI), an Analog-toDigital Converter (ADC), Serial Peripheral Interface (SPI) (only internal), and an Internal Clock Generator (ICG) module. The analog control die provides fully protected H-Bridge/high-side outputs, voltage regulator, autonomous watchdog with cyclic wake-up, and Local Interconnect Network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive mirror, door lock, and light-levelling applications. Features • • • • • • • • • • • • • High-Performance M68HC908EY16 Core 16 K Bytes of On-Chip Flash Memory 512 Bytes of RAM Internal Clock Generation Module Two 16-bit, 2-Channel Timers 10-Bit Analog-to-Digital Converter LIN Physical Layer Autonomous Watchdog with Cyclic Wakeup Three Two-Pin Hall-Effect Sensor Input Ports One Analog Input with Switchable Current Source Four Low RDS (ON) Half-Bridge Outputs One Low RDS (ON) High-Side Output 13 Micro Controller I/Os 3 LIN VREFH VDDA EVDD VDD VREFL VSSA EVSS VSS RST RST_A IRQ IRQ_A SS PTB1/AD1 RXD PTE1/RXD PTD1/TACH1 FGEN BEMF PTD0/TACH0/BEMF VSUP 908E425 H-BRIDGE POWER SUPPLY WITH EMBEDDED MCU AND LIN DWB SUFFIX 98ASA10712D 54-PIN SOICWB-EP ORDERING INFORMATION Device MM908E425AIDWB Temperature Range (TA) 0°C to 85°C Package 54 SOICW EP 908E425 HB1 M HB2 HB3 HB4 HS High-Side Output HVDD H1 H2 H3 PA1 PORT A I/OS PORT B I/OS PORT C I/OS Switchable Internal VDD Output Three 2-Terminal Hall-Effect Sensor Inputs Analog Input with Current Source Microcontroller Ports M M 4 Half-Bridges Controlling 3 Loads GND 2 EP Figure 1. 908E425 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. CPU Registers ALU 5-Bit Keyboard Interrupt Module Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes 2-channel Timer Interface Module B FGEN Internal Bus DDRC DDRA PORT A PTC3/OSC2 PTD1/TACH1 PTD0/TACH0 PORT C DDRD PORT D PORT B DDRB DDRE PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTE1/RxD PTE0/TxD PORT E 2 PTD0/TACH0 PTB1/AD1 BEMF VSUP1-3 GND1-2 RST_A IRQ_A FGEN SS VREFL PTD1/TACH1 PTE1/RXD VDDA M68HC08 CPU Voltage Regulator 908E425 EVDD EVSS VSSA RXD RST LIN IRQ Single Breakpoint Break Module BLOCK DIAGRAM VREFH PTE0/TXD TXD LIN Physical Layer Switched VDD Driver & Diagnostic 2-Channel Timer Interface Module A Reset Control Module VSS VDD HVDD VSUP PTA0/KBD0 User Flash Vector Space, 36 Bytes OSC2 OSC1 Flash Programming (burn in) ROM, 1024 Bytes Enhanced Serial Communication Interface Module Computer Operating Properly Module Interrupt Control Module PTA1/KBD1 Internal Clock Generator Module High Side Driver & Diagnostic HS VSUP FGEN PTA2/KBD2 SS RST PTA3/KBD3 Serial Pheripheral Interface Module 24 Internal System Integration Module PTC0/MISO MISO MOSI SPSCK PTC1/MOSI PTA5/SPSCK BEMF Half Bridge Driver & Diagnostic HB1 PTA4/KBD4 IRQ Single External IRQ Module Configuration Register Module VSUP FGEN SPI & CONTROL PTB3/AD3 VREFH VDDA VREFL VSSA PTB4/AD4 VDD VSS 10 Bit Analog-toDigital Converter Module Periodic Wake-Up Timebase Module BEMF Half Bridge Driver & Diagnostic VSUP BLOCK DIAGRAM HB2 PTB5/AD5 Power-On Reset Module Prescaler Module POWER Arbiter Module FGEN PTB6/AD6/TBCH0 BEMF Half Bridge Driver & Diagnostic Autonomous Watchdog VSUP FGEN HB3 PTB7/AD7/TBCH1 Security Module BEMF Module Figure 2. 908E425 Simplified Internal Block Diagram Chip Temp BEMF PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTC2/MCLK Half Bridge Driver & Diagnostic VSUP Prescaler HB4 PTC4/OSC1 PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 H1 PTB0/AD0 ADOUT Hall-Effect Sensor Inputs Analog Multiplexer H2 H3 Analog Input with Current Source FLSVPP PA1 MCU Die Analog Die Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF RST_A IRQ_A SS Exposed Pad 41 40 39 38 37 36 35 34 33 32 31 30 29 28 LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS PA1 VDD H1 H2 H3 HVDD NC HB4 VSUP3 GND2 HB3 HS Figure 3. 908E425 Pin Connections (Transparent Package Top View) Table 1. 908E425 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. Pin Function MCU Pin 1 2 6 7 8 11 3 4 5 9 10 12 13 14, 21, 22, 33 42 43 48 Pin Name PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK IRQ RST PTD0/TACH0/BEMF PTD1/TACH1 NC PTE1/ RXD VREFL VREFH Formal Name Port B I/Os Definition These pins are special-function, bidirectional I/O port pins that are shared with other functional modules in the MCU. MCU Port C I/Os These pins are special-function, bidirectional I/O port pins that are shared with other functional modules in the MCU. This pin is an asynchronous external interrupt input pin. This pin is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. These pins are special-function, bidirectional I /O port pins that are shared with other functional modules in the MCU. Not connected. This pin is a special-function, bidirectional I/O port pin that can is shared with other functional modules in the MCU. These pins are the reference voltage pins for the analog-todigital converter (ADC). 908E425 MCU MCU MCU – MCU MCU External Interrupt Input External Reset Port D I /Os No Connect Port E I /O ADC References Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 908E425 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. Pin Function MCU MCU MCU Pin 44 47 45 46 49 50 52 53 54 51 15 16 17 18 19 20 23 26 29 32 24 27 31 25 30 28 34 Pin Name VSSA VDDA EVSS EVDD PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 FLSVPP FGEN BEMF RST_A IRQ_A SS LIN HB1 HB2 HB3 HB4 VSUP1 VSUP2 VSUP3 GND1 GND2 HS HVDD Formal Name ADC Supply Pins MCU Power Supply Pins Port A I /Os Definition These pins are the power supply pins for the analog-to-digital converter. These pins are the ground and power supply pins, respectively. The MCU operates from a single power supply. These pins are special-function, bidirectional I/O port pins that are shared with other functional modules in the MCU. MCU Analog Analog Analog Analog Analog Analog Analog Test Pin Current Limitation Frequency Input For test purposes only. Do not connect in the application. This is the input pin for the half-bridge current limitation and the high-side inrush current limiter PWM frequency. Back Electromagnetic This pin gives the user information about back electromagnetic force (BEMF). Force Output Internal Reset Internal Interrupt Output Slave Select LIN Bus Half-Bridge Outputs This pin is the bidirectional reset pin of the analog die. This pin is the interrupt output pin of the analog die indicating errors or wake-up events. This pin is the SPI slave select pin for the analog chip. This pin represents the single-wire bus transmitter and receiver. This device includes power MOSFETs configured as four halfbridge driver outputs. These outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. These pins are device power supply pins. Analog Power Supply Pins Analog Analog Analog Power Ground Pins High-Side Output Switchable VDD Output Hall-Effect Sensor Inputs Voltage Regulator Output Analog Input Voltage Regulator Ground LIN Transceiver Output Exposed Pad These pins are device power ground connections. This output pin is a low RDS(ON) high-side switch. This pin is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-pin Hall-effect sensors. These pins provide inputs for Hall-effect sensors and switches. Analog 35 36 37 38 39 40 41 EP H3 H2 H1 VDD PA1 VSS RXD Exposed Pad Analog Analog Analog Analog – The + 5.0 V voltage regulator output pin is intended to supply the embedded microcontroller. This pin is an analog input port with selectable source values. Ground pin for the connection of all non-power ground connections (microcontroller and sensors). This pin is the output of LIN transceiver. The exposed pad pin on the bottom side of the package conducts heat from the chip to the PCB board. 908E425 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Supply Voltage Analog Chip Supply Voltage under Normal Operation, Steady State Analog Chip Supply Voltage under Transient Conditions (1) Microcontroller Chip Supply Voltage Input Pin Voltage Analog Chip Microcontroller Chip Maximum Microcontroller Current per Pin All Pins Except VDD, VSS, PTA0 : PTA6, PTC0 : PTC1 Pins PTA0 : PTA6, PTC0 : PTC1 Maximum Microcontroller VSS Output Current Maximum Microcontroller VDD Input Current LIN Supply Voltage Normal Operation (Steady-State) Transient Conditions (1) ESD Voltage (2) Symbol Value Unit V VSUP(SS) VSUP(PK) VDD - 0.3 to 28 - 0.3 to 40 - 0.3 to 6.0 V VIN (ANALOG) VIN (MCU) IPIN(1) IPIN(2) IMVSS IMVDD VBUS(SS) VBUS(DYNAMIC) VESD ± 3000 ± 150 ± 500 - 0.3 to 5.5 VSS - 0.3 to VDD + 0.3 mA ±15 ± 25 100 100 mA mA V -18 to 28 40 V Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) THERMAL RATINGS Storage Temperature Ambient Operating Temperature Operating Case Temperature (3) Operating Junction Temperature (4) Peak Package Reflow Temperature During Solder Mounting (5) TSTG TA TC TJ TSOLDER – 0 to 85 0 to 85 0 to 125 245 °C °C °C °C °C Notes 1. Transient capability for pulses with a time of t < 0.5 sec. 2. ESD voltage testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD voltage testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω, ESD voltage testing is performed in accordance with Charge Device Model, robotic (CZAP = 4.0 pF). 3. 4. 5. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation on the analog die. The analog die temperature must not exceed 150°C under these conditions. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, 0°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic SUPPLY VOLTAGE Nominal Operating Voltage SUPPLY CURRENT NORMAL Mode VSUP = 12 V, Power Die ON (PSON = 1), MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled STOP Mode (6) VSUP = 12 V, Cyclic Wake-Up Disabled DIGITAL INTERFACE RATINGS (ANALOG DIE) Output Pins RST_A, IRQ_A Low-State Output Voltage (IOUT = - 1.5 mA) High-State Output Voltage (IOUT = 1.0 µA) Output Pins BEMF, RXD Low-State Output Voltage (IOUT = - 1.5 mA) High-State Output Voltage (IOUT = 1.5 mA) Output Pin RXD – Capacitance (7) Input Pins RST_A, FGEN, SS Input Logic Low Voltage Input Logic High Voltage Input Pins RST_A, FGEN, SS – Capacitance Pins RST_A, IRQ_A – Pullup Resistor Pin SS – Pullup Resistor Pins FGEN, MOSI, SPSCK – Pulldown Resistor Pin TXD – Pullup Current Source Notes 6. STOP mode current will increase if VSUP exceeds 15 V. 7. This parameter is guaranteed by process monitoring but is not production tested. (7) Symbol Min Typ Max Unit VSUP 8.0 – 18 V IRUN – 20 – mA ISTOP – – 60 µA V VOL VOH – 3.85 – – 0.4 – V VOL VOH CIN – 3.85 – – – 4.0 0.4 – – pF V VIL VIH CIN RPULLUP1 RPULLUP2 RPULLDOWN IPULLUP – 3.5 – – – – – – – 4.0 10 60 60 35 1.5 – – – – – – pF kΩ kΩ kΩ µA 908E425 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, 0°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic SYSTEM RESETS AND INTERRUPTS High-Voltage Reset Threshold Hysteresis Low-Voltage Reset Threshold Hysteresis High-Voltage Interrupt Threshold Hysteresis Low-Voltage Interrupt Threshold Hysteresis High-Temperature Reset Threshold Hysteresis High-Temperature Interrupt Threshold Hysteresis VOLTAGE REGULATOR Normal Mode Output Voltage IOUT = 60 mA, 6.0 V < VSUP < 18 V Load Regulation IOUT = 80 mA, VSUP = 9.0 V, TJ = 125°C STOP Mode Output Voltage (Maximum Output Current 100 µA) LIN PHYSICAL LAYER Output Low Level TXD LOW, 500 Ω Pullup to VSUP Output High Level TXD HIGH, IOUT = 1.0 µA Pullup Resistor to VSUP Leakage Current to GND Recessive State (- 0.5 V < VLIN < VSUP) Leakage Current to GND (VSUP Disconnected) Including Internal Pullup Resistor, VLIN @ -18 V Including Internal Pullup Resistor, VLIN @ +18 V IBUS_NO_GND IBUS – – - 600 25 – – RSLAVE IBUS_PAS_rec 0.0 – 20 µA VLIN-HIGH VSUP - 1.0 20 – 30 – 60 kΩ µA VLIN-LOW – – 1.4 V V VLR – VDDSTOP 4.5 – 4.7 100 4.9 V VDDRUN 4.75 5.0 5.25 mV V (9) (8) Symbol Min Typ Max Unit V VHVRON VHVRH VLVRON VLVRH VHVION VHVIH VLVION VLVIH TRON TRH TION TIH 27 – 30 1.5 33 – 3.6 – 4.0 100 4.5 – V mV V 17.5 – 21 1.0 23 – V 6.5 – – 0.4 8.0 – °C – 5.0 170 – – – °C – 5.0 160 – – – Notes 8. This parameter is guaranteed by process monitoring but is not production tested. 9. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10°C). 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, 0°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic LIN PHYSICAL LAYER (continued) LIN Receiver Recessive Dominant Threshold Input Hysteresis LIN Wake-Up Threshold HIGH-SIDE OUTPUT (HS) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A High-Side Overcurrent Shutdown HALF-BRIDGE OUTPUTS (HB1:HB4) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A High Side Low Side High-Side Overcurrent Shutdown Low-Side Overcurrent Shutdown Low-Side Current Limitation @ TJ = 25°C Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1) Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0) Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1) Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0) Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1) Half-Bridge Output HIGH Threshold for BEMF Detection Half-Bridge Output LOW Threshold for BEMF Detection Hysteresis for BEMF Detection Low-Side Current-to-Voltage Ratio (VADOUT [V] / IHB [A]) CSA = 1 CSA = 0 SWITCHABLE VDD OUTPUT (HVDD) Overcurrent Shutdown Threshold VSUP DOWN-SCALER Voltage Ratio (RATIOVSUP = VSUP / VADOUT) INTERNAL DIE TEMPERATURE SENSOR Voltage / Temperature Slope Output Voltage @ 25°C STtoV VT25 – 1.7 19 2.1 – 2.5 mV/ °C V RATIOVSUP 4.8 5.1 5.35 – IHVDDOCT 24 30 40 mA RATIOH RATIOL 7.0 1.0 12 2.0 14 3.0 ICL1 ICL2 ICL3 ICL4 ICL5 VBEMFH VBEMFL VBEMFHY – 210 300 450 600 – – – 55 260 370 550 740 - 30 - 60 30 – 315 440 650 880 0 - 5.0 – V mV mV V/A RDS(ON)HB_HS RDS(ON)HB_LS IHBHSOC IHBLSOC – – 4.0 2.8 425 400 – – 500 500 7.5 7.5 mΩ RDS(ON)HS IHSOC – 3.9 600 – 700 7.0 mΩ A VIH VIL VITH VIHY VWTH 0.6 VLIN 0.0 – 0.01 VSUP – – – VSUP / 2 – VSUP / 2 VSUP 0.4 VLIN – 0.1 VSUP – V V Symbol Min Typ Max Unit A A mA 908E425 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, 0°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic HALL-EFFECT SENSOR INPUTS (H1: H3) Output Voltage VSUP < 16.2 V VSUP > 16.2 V Sense Current Threshold Hysteresis Output Current Limitation Overcurrent Warning HP_OCF Flag Threshold] Dropout Voltage @ ILOAD = 15 mA ANALOG INPUT (PA1) Current Source PA1 CSSEL1 = 1, CSSEL0 = 1 Selectable Scaling Factor Current Source PA1 (I(N) = ICSPA1* N) CSSEL1 = 0, CSSEL0 = 0 CSSEL1 = 0, CSSEL0 = 1 CSSEL1 = 1, CSSEL0 = 0 NCSPA1-0 NCSPA1-1 NCSPA1-2 8.5 28.5 58.5 10 30 60 11.5 31.5 61.5 ICSPA1 570 670 770 % µA IHSCT IHSCH 6.9 – – – – 8.8 0.88 90 3.0 0.5 11 – – – – mA V V VHALL1 VHALL2 – – VSUP - 1.2 – – 15 mA V Symbol Min Typ Max Unit IHL VHPOCT VHPDO 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics All characteristics are for the analog chip only. Please refer to the specification for 68HC908EY16 for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, 0°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic LIN PHYSICAL LAYER Propagation Delay (10), (11) TXD LOW to LIN LOW TXD HIGH to LIN HIGH LIN LOW to RXD LOW LIN HIGH to RXD HIGH TXD Symmetry RXD Symmetry Output Falling Edge Slew Rate 80% to 20% Output Rising Edge Slew Rate (10), (12) 20% to 80%, RBUS > 1.0 kΩ, CBUS < 10 nF LIN Rise / Fall Slew Rate Symmetry (10), (12) (10) (12) Symbol Min Typ Max Unit µs t TXD-LIN-low t TXD-LIN-high t LIN-RXD-low t LIN-RXD-high t TXD-SYM t RXD-SYM , SRF -1.0 SRR 1.0 SRS - 2.0 2.0 – 3.0 2.0 µs - 2.0 - 3.0 V/µs – – – – - 2.0 - 2.0 – – 4.0 4.0 – – 6.0 6.0 8.0 8.0 2.0 2.0 V/µs HALL-EFFECT SENSOR INPUTS (H1:H3) Propagation Delay AUTONOMOUS WATCHDOG (AWD) AWD Oscillator Period AWD Period Low = 512 t OSC AWD Period High = 256 t OSC AWD Cyclic Wake-Up On Time t OSC t AWDPH t AWDPL t AWDHPON – 16 8.0 – 40 22 11 90 – 28 14 – µs ms ms µs t HPPD – 1.0 – µs Notes 10. All LIN characteristics are for initial LIN slew rate selection (20 kBaud) (SRS0 : SRS1= 00). 11. See Figure 2. 12. See Figure 3. 908E425 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MICROCONTROLLER MICROCONTROLLER Table 5. Microcontroller Description For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet. Module Core Timer Flash RAM ADC SPI ESCI Description High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Two 16-Bit Timers with Two Channels (TIM A and TIM B) 16 K Bytes 512 Bytes 10-Bit Analog-to-Digital Converter SPI Module Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%) Special Counter for SMARTMOS™ BEMF Output ICG BEMF Counter 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS tTx-LIN-low t TXD-LIN-LOW TXD Tx TXD tTx-LIN-high t TXD-LIN-HIGH LIN LIN Recessive State 0.9 VSUP 0.9 VSUP Recessive State 0.6 VSUP VSUP 0.4 VSUP VSUP 0.1 VSUP 0.1 VSUP Dominant State Rx RXD t LIN-RXD-LOW t LIN-Rx-low t LIN-RXD-HIGH t LIN-Rx-high Figure 4. LIN Timing Description ∆t Fall-time ∆t Rise-time 0.8 VSUP 0.8 VSUP 0.8 VSUP VSUP ∆V Fall ∆V Rise 0.2 VSUP 0.2 VSUP Dominant State 0.2 VSUP 0.2 VSUP SRF = ∆V Fall ∆t Fall-time SRR = ∆V Rise ∆t Rise-time Figure 5. LIN Slew Rate Description 908E425 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES ELECTRICAL PERFORMANCE CURVES 1.6 1.4 Forward Voltage (V) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 ILOAD (A) 3.0 3.5 4.0 4.5 5.0 H-Bridge Low Side TJ = 25°C Figure 6. Free Wheel Diode Forward Voltage vs ILOAD 250 Drop Out Voltage (mV) 200 150 TA = 125°C TA = 25°C 100 TA = 0°C 50 0 0 5 10 ILoad (mA) 15 20 25 Figure 7. Dropout Voltage on HVDD vs ILOAD 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E425 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E425 is well suited to perform complete mirror, door lock, and light-levelling control all via a three-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS™ IC chip. The SMARTMOS™ IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS™ IC configured as half-bridge outputs with one high-side switch. Other ports are also provided; they include Hall-effect sensor input ports, analog input ports, and a selectable HVDD pin. An internal voltage regulator is provided on the SMARTMOS™ IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. FUNCTIONAL PIN DESCRIPTION See Figure 1 for a graphic representation of the various pins referred to in the following paragraphs. Also, see the pin diagram on Figure 3 for a depiction of the pin locations on the package. PORT D I /O PINS (PTD0:1) PTD1/ TACH1 and PTD0/ TACH0/BEMF are specialfunction, bidirectional I /O port pins that can also be programmed to be timer pins. In step motor applications the PTD0 pin should be connected to the BEMF output of the analog die in order to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 pin is recommended for use as an output pin for generating the FGEN signal (PWM signal) if required by the application. PORT A I /O PINS (PTA0:4) These pins are special-function, bidirectional I/O port pins that are shared with other functional modules in the MCU. PTA0 : PTA4 are shared with the keyboard interrupt pins, KBD0 : KBD4. The PTA5/SPSCK pin is not accessible in this device and is internally connected to the SPI clock pin of the analog die. The PTA6/SS pin is likewise not accessible. For details refer to the 68HC908EY16 datasheet. PORT E I /O PIN (PTE1) PTE1/ RXD and PTE0/ TXD are special-function, bidirectional I/O port pins that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD pin of the analog die. The connection for the receiver must be done externally. PORT B I/O PINS (PTB1, PTB3:7) These pins are special-function, bidirectional I/O port pins that are shared with other functional modules in the MCU. All pins are shared with the ADC module. The PTB6 : PTB7 pins are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT pin of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2 pin is not accessible in this device. For details refer to the 68HC908EY16 datasheet. EXTERNAL INTERRUPT PIN (IRQ) The IRQ pin is an asynchronous external interrupt pin. This pin contains an internal pull-up resistor that is always activated, even when the IRQ pin is pulled LOW. For details refer to the 68HC908EY16 datasheet. PORT C I/O PINS (PTC2:4) These pins are special-function, bidirectional I/O port pins that are shared with other functional modules in the MCU. For example, PTC2 : PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI pins of the analog die. For details refer to the 68HC908EY16 datasheet. EXTERNAL RESET PIN (RST) A Logic [0] on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This pin contains an internal pull-up resistor that is always activated, even when the reset pin is pulled LOW. For details refer to the 68HC908EY16 datasheet. 908E425 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CURRENT LIMITATION FREQUENCY INPUT PIN (FGEN) Input pin for the half-bridge current limitation and the highside inrush current limiter PWM frequency. This input is not a real PWM input pin; it should just supply the period of the PWM. The duty cycle will be generate automatically. Important The recommended FGEN frequency should be in the range of 0.1 kHz to 20 kHz. systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple VSUP pins are provided. All VSUP pins must be connected to get full chip functionality. POWER GROUND PINS (GND1 AND GND2) GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple pins are provided. GND1 and GND2 pins must be connected to get full chip functionality. BACK ELECTROMAGNETIC FORCE OUTPUT PIN (BEMF) This pin gives the user information about back electromagnetic force (BEMF). This feature is mainly used in step motor applications for detecting a stalled motor. In order to evaluate this signal the pin must be directly connected to pin PTD0 / TACH0 / BEMF. HIGH-SIDE OUTPUT PIN (HS) The HS output pin is a low RDS(ON) high-side switch. The switch is protected against overtemperature and overcurrent. The output is capable of limiting the inrush current with an automatic PWM generation using the FGEN module. RESET PIN (RST_A) RST_A is the bidirectional reset pin of the analog die. It is an open drain with pull-up resistor and must be connected to the RST pin of the MCU. SWITCHABLE VDD OUTPUT PIN (HVDD) The HVDD pin is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-pin Hall-effect sensors. The output is short-circuit protected. INTERRUPT PIN (IRQ_A) IRQ_A is the interrupt output pin of the analog die indicating errors or wake-up events. It is an open drain with pull-up resistor and must be connected to the IRQ pin of the MCU. HALL-EFFECT SENSOR INPUT PINS (H1: H3) The Hall-effect sensor input pins H1: H3 provide inputs for Hall-effect sensors and switches. SLAVE SELECT PIN (SS) This pin is the SPI Slave Select pin for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I /O of the microcontroller. + 5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD) The VDD pin is needed to place an external capacitor to stabilize the regulated output voltage. The VDD pin is intended to supply the embedded microcontroller. Important The VDD pin should not be used to supply other loads; use the HVDD pin for this purpose. The VDD, EVDD, VDDA, and VREFH pins must be connected together. LIN BUS PIN (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. ANALOG INPUT PIN (PA1) This pin is an analog input port with selectable current source values. HALF-BRIDGE OUTPUT PINS (HB1: HB4) The 908E425 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1: HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. The HB1: HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low-side MOSFETs. VOLTAGE REGULATOR GROUND PIN (VSS) The VSS pin is the ground pin for the connection of all nonpower ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VREFL pins must be connected together. LIN TRANSCEIVER OUTPUT PIN (RXD) This pin is the output of LIN transceiver. The pin must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD pin). POWER SUPPLY PINS (VSUP1: VSUP3) VSUP1: VSUP3 are device power supply pins. The nominal input voltage is designed for operation from 12 V 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION ADC REFERENCE PINS (VREFL AND VREFH) VREFL and VREFH are the reference voltage pins for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these pins. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet. MCU POWER SUPPLY PINS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. TEST PIN (FLSVPP) This pin is for test purposes only. This pin should be either left open (not connected) or connected to GND. ADC SUPPLY PINS (VDDA AND VSSA) VDDA and VSSA are the power supply pins for the analogto-digital converter (ADC). It is recommended that a highquality ceramic decoupling capacitor be placed between these pins. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground pin for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. EXPOSED PAD PIN The exposed pad pin on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential. 908E425 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTERRUPTS The 908E425 has seven different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled. AUTONOMOUS WATCHDOG INTERRUPT (AWD ) Refer to Autonomous Watchdog Autonomous Watchdog (AWD) on page 37. LIN INTERRUPT If the LINIE bit is set, a falling edge on the LIN pin will generate an interrupt. During STOP mode this interrupt will initiate a system wake-up. LOW-VOLTAGE INTERRUPT The Low-Voltage Interrupt (LVI) is related to the external supply voltage, VSUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the low-voltage interrupt is enabled, an interrupt will be initiated. With LVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the LVI circuitry is disabled. HALL-EFFECT SENSOR INPUT PIN INTERRUPT If the PHIE bit is set, the enabled Hall-Effect Sensor input pins H1: H3 can generate an interrupt if a current above the threshold is detected. During STOP mode this interrupt, combined with the cyclic wake-up feature of the AWD, can wake up the system. Refer to pin HALL-EFFECT SENSOR INPUT PINS (H1: H3). HIGH-VOLTAGE INTERRUPT The High-Voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High-Voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the HVI circuitry is disabled. OVERCURRENT INTERRUPT If an overcurrent condition on a half-bridge occurs, the high-side or the HVDD output is detected and the OCIE bit is set and an interrupt generated. SYSTEM WAKE-UP System wake-up can be initiated by any of four events: • A falling edge on the LIN pin • A wake-up signal from the AWD • A Logic [1] at Hall-effect sensor input pin during cyclic check via AWD • An LVR condition If one of these wake-up events occurs and the interrupt mask bit for this event is set, the interrupt will wake-up the microcontroller as well as the main voltage regulator (MREG) (Figure 8). HIGH-TEMPERATURE INTERRUPT The High-Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is above the HTI threshold, the HTI flag will be set. If the HighTemperature Interrupt is enabled, an interrupt will be initiated. During STOP mode the HTI circuitry is disabled. 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES MCU Die From Reset Analog Die Initialize Operate SPI: GS =1 (MREG off) STOP MREG STOP Wait for Action LIN AWD Hallport IRQ Interrupt? Assert IRQ_A SPI: Reason for Interrupt Start MREG Operate MREG = Main Voltage Regulator Figure 8. STOP Mode / Wake-Up Procedure 908E425 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS SERIAL SPI INTERFACE The SPI creates the communication link between the microcontroller and the 908E425. The interface consists of four pins. See Figure 9: • SS — Slave Select • MOSI — Master-Out Slave-In SS • MISO — Master-In Slave-Out • SPSCK — Serial Clock A complete data transfer via the SPI consists of 2 bytes. The master sends address and data, slave system status, and data of the selected address. Read/Write, Address, Parity Data (Register write) P X D7 D6 D5 D4 D3 D2 D1 D0 MOSI R/W A4 A3 A2 A1 A0 System Status Register Data (Register read) S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 MISO S7 S6 S5 S4 S3 S2 SPSCK Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Slave latch register address Slave latch data Figure 9. SPI Protocol During the inactive phase of SS, the new data transfer is prepared. The falling edge on the SS line indicates the start of a new data transfer and puts MISO in the low-impedance mode. The first valid data are moved to MISO with the rising edge of SPSCK. The MISO output changes data on a rising edge of SPSCK. The MOSI input is sampled on a falling edge of SPSCK. The data transfer is only valid if exactly 16 sample clock edges are present in the active phase of SS. After a write operation, the transmitted data is latched into the register by the rising edge of SS. Register read data is internally latched into the SPI at the time when the parity bit is transferred. SS HIGH forces MISO to high impedance. selected register prior to write operation, write data is latched in the SMARTMOS™ register on rising edge of SS. PARITY P The parity bit is equal to 0 if the number of 1 bits is an even number contained within R/ W, A4 : A0. If the number of 1 bits is odd, P equals 1. For example, if R/ W = 1, A4 : A0 = 00001, then P equals 0. The parity bit is only evaluated during a write operation. BIT X Not used. A4 : A0 Contains the address of the desired register. MASTER DATA BYTE Contains data to be written or no valid data during a read operation. R/W Contains information about a read or a write operation. • If R/ W = 1, the second byte of master contains no valid information, slave just transmits back register data. • If R/ W = 0, the master sends data to be written in the second byte, slave sends concurrently contents of SLAVE STATUS BYTE Contains the contents of the System Status Register ($0c) independent of whether it is a write or read operation or which register was selected. 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS SLAVE DATA BYTE Contains the contents of selected register. During a write operation it includes the register content prior to a write operation. Table 6. List of Registers Addr $01 Register Name H-Bridge Output (HBOUT) H-Bridge Control (HBCTL) System Control (SYSCTL) Interrupt Mask (IMR) Interrupt Flag (IFR) Reset Mask (RMR) Analog Multiplexer Configuration (ADMUX) Hall-Effect Sensor Input Pin Control (HACTL) Hall-Effect Sensor Input Pin Status (HASTAT) AWD Control (AWDCTL) Power Output (POUT) System Status (SYSSTAT) R/W R W $02 R W $03 R W $04 R W $05 R W $06 R W $07 R W $08 R W R W R W $0b R W $0c R W HP_OCF LINCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TTEST 0 0 0 HPF 0 HPIE PSON SRS1 OFC_EN CSA 0 SPI REGISTER OVERVIEW Table 6 summarizes the SPI register addresses and the bit names of each register. Bit 7 HB4_H 6 HB4_L 5 HB3_H 4 HB3_L 3 HB2_H 2 HB2_L 1 HB1_H 0 HB1_L 0 0 CLS2 CLS1 CLS0 SRS0 0 0 0 0 0 GS LINIE HTIE LVIE HVIE OCIE 0 LINF HTF LVF HVF OCF 0 0 0 0 HVRE HTRE 0 SS3 SS2 SS1 SS0 0 0 H3EN H2EN H1EN $09 0 0 H3F H2F H1F $0a AWDRE AWDIE AWDCC AWDF AWDR AWDRST CSSEL1 CSSEL0 CSEN1 CSEN0 HVDDON HS_ON HVDD_OCF HS_OCF LVF HVF HB_OCF HTF 908E425 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS INTERRUPT FLAG REGISTER (IFR) Register Name and Address: IFR - $05 Bits Read Write Reset 0 0 0 0 0 0 0 0 7 0 6 HPF 5 LINF 4 HTF 3 LVF 2 HVF 1 OCF 0 0 condition is still present while writing a Logic [1] to HTF, the writing has no effect. Therefore, a high-temperature interrupt cannot be lost due to inadvertent clearing of HTF. Reset clears the HTF bit. Writing a Logic [0] to HTF has no effect. • 1 = High-temperature condition has occurred • 0 = High-temperature condition has not occurred LOW-VOLTAGE FLAG BIT (LVF ) This read / write flag is set on a low-voltage condition. Clear LVF by writing a Logic [1] to LVF. If a low-voltage condition is still present while writing a Logic [1] to LVF, the writing has no effect. Therefore, a low-voltage interrupt cannot be lost due to inadvertent clearing of LVF. Reset clears the LVF bit. Writing a Logic [0] to LVF has no effect. • 1 = Low-voltage condition has occurred • 0 = Low-voltage condition has not occurred HIGH-VOLTAGE FLAG BIT (HVF ) This read / write flag is set on a high-voltage condition. Clear HVF by writing a Logic [1] to HVF. If high-voltage condition is still present while writing a Logic [1] to HVF, the writing has no effect. Therefore, a high-voltage interrupt cannot be lost due to inadvertent clearing of HVF. Reset clears the HVF bit. Writing a Logic [0] to HVF has no effect. • 1 = High-voltage condition has occurred • 0 = High-voltage condition has not occurred OVERCURRENT FLAG BIT (OCF ) This read-only flag is set on an overcurrent condition. Reset clears the OCF bit. To clear this flag, write a Logic [1] to the appropriate overcurrent flag in the SYSSTAT Register. See Figure 10,illustrating the three signals triggering the OCF. • 1 = High-current condition has occurred • 0 = High-current condition has not occurred HALL-EFFECT SENSOR INPUT PIN FLAG BIT (HPF ) This read / write flag is set depending on RUN / STOP mode. RUN MODE An interrupt will be generated when a state change on any enabled Hall-effect sensor input pin is detected. Clear HPF by writing a Logic [1] to HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF has no effect. • 1 = State change on the hallflags detected • 0 = No state change on the hallflags detected STOP MODE An interrupt will be generated when AWDCC is set and a current above the threshold is detected on any enabled Halleffect sensor input pin. Clear HPF by writing a Logic [1] to HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF has no effect. • 1 = One or more of the selected Hall-effect sensor input pins had been pulled HIGH • 0 = None of the selected Hall-effect sensor input pins has been pulled HIGH LIN FLAG BIT (LINF ) This read / write flag is set on the falling edge at the LIN data line. Clear LINF by writing a Logic [1] to LINF. Reset clears the LINF bit. Writing a Logic [0] to LINF has no effect. • 1 = Falling edge on LIN data line has occurred • 0 = Falling edge on LIN data line has not occurred since last clear HIGH-TEMPERATURE FLAG BIT (HTF ) This read / write flag is set on a high-temperature condition. Clear HTF by writing a Logic [1] to HTF. If a high-temperature HVDD_OCF HS_OCF HB_OCF OCF Figure 10. Principal Implementation for OCF 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS INTERRUPT MASK REGISTER (IMR) Register Name and Address: IMR - $04 Bits Read Write Reset 0 0 0 0 0 0 0 0 7 0 6 5 4 3 LVIE 2 1 0 0 HIGH-TEMPERATURE INTERRUPT ENABLE BIT (HTIE ) This read / write bit enables CPU interrupts by the hightemperature flag, HTF. Reset clears the HTIE bit. • 1 = Interrupt requests from HTF flag enabled • 0 = Interrupt requests from HTF flag disabled LOW-VOLTAGE INTERRUPT ENABLE BIT (LVIE ) This read / write bit enables CPU interrupts by the lowvoltage flag, LVF. Reset clears the LVIE bit. • 1 = Interrupt requests from LVF flag enabled • 0 = Interrupt requests from LVF flag disabled HIGH-VOLTAGE INTERRUPT ENABLE BIT (HVIE ) This read / write bit enables CPU interrupts by the highvoltage flag, HVF. Reset clears the HVIE bit. • 1 = Interrupt requests from HVF flag enabled • 0 = Interrupt requests from HVF flag disabled OVERCURRENT INTERRUPT ENABLE BIT (OCIE ) This read / write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit. • 1 = Interrupt requests from OCF flag enabled • 0 = Interrupt requests from OCF flag disabled HPIE LINIE HTIE HVIE OCIE HALL-EFFECT SENSOR INPUT PIN INTERRUPT ENABLE BIT (HPIE ) This read / write bit enables CPU interrupts by the Halleffect sensor input pin flag, HPF. Reset clears the HPIE bit. • 1 = Interrupt requests from HPF flag enabled • 0 = Interrupt requests from HPF flag disabled LIN LINE INTERRUPT ENABLE BIT (LINIE ) This read / write bit enables CPU interrupts by the LIN flag, LINF. Reset clears the LINIE bit. • 1 = Interrupt requests from LINF flag enabled • 0 = Interrupt requests from LINF flag disabled 908E425 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS RESET The 908E425 chip has four internal reset sources and one external reset source, as explained in the paragraphs below. Figure 11 depicts the internal reset sources. HIGH-TEMPERATURE RESET To prevent damage to the device, a reset will be initiated if the temperature rises above a certain value. The reset is maskable with bit HTRE in the Reset Mask Register. After a reset the high-temperature reset is disabled. LOW-VOLTAGE RESET The LVR is related to the internal VDD. In case the voltage falls below a certain threshold, it will pull down the RST_A pin. RESET INTERNAL SOURCES AUTONOMOUS WATCHDOG AWD modules generates a reset because of a timeout (watchdog function). SPI REGISTERS AWDRE Flag AWD Reset Sensor HVRE Flag High-Voltage Reset Sensor HTRE Flag High-Temperature Reset Sensor VDD RST_A MONO FLOP Low-Voltage Reset Figure 11. Internal Reset Routing HIGH-VOLTAGE RESET The HVR is related to the external VSUP voltage. In case the voltage is above a certain threshold, it will pull down the RST_A pin. The reset is maskable with bit HVRE in the Reset Mask Register. After a reset the high-voltage reset is disabled. RESET MASK REGISTER (RMR) Register Name and Address: RMR - $06 Bits Read Write Reset 0 0 0 0 0 0 0 0 7 TTEST 6 0 5 0 4 0 3 0 2 0 1 0 HVRE HTRE RESET EXTERNAL SOURCE EXTERNAL RESET PIN The microcontroller has the capability of resetting the SMARTMOS™ device by pulling down the RST pin. HIGH-TEMPERATURE RESET TEST (TTEST ) This read / write bit is for test purposes only. It decreases the overtemperature shutdown limit for final test. Reset clears the TTEST bit. • 1 = Low-temperature threshold enabled • 0 = Low-temperature threshold disabled 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS HIGH-VOLTAGE RESET ENABLE BIT (HVRE) This read / write bit enables resets on high-voltage conditions. Reset clears the HVRE bit. • 1 = High-voltage reset enabled • 0 = High-voltage reset disabled HIGH-TEMPERATURE RESET ENABLE BIT (HTRE ) This read / write bit enables resets on high-temperature conditions. Reset clears the HTRE bit. • 1 = High-temperature reset enabled • 0 = High-temperature reset disabled STOP MODE / WAKE-UP FEATURE During STOP mode operation the transmitter of the physical layer is disabled. The receiver pin is still active and able to detect wake-up events on the LIN bus line. If LIN interrupt is enabled (LINIE bit in the Interrupt Mask Register is set), a falling edge on the LIN line causes an interrupt. This interrupt switches on the main voltage regulator and generates a system wake-up. ANALOG MULTIPLEXER /ADOUT PIN The ADOUT pin is the analog output interface to the ADC of the MCU. See Figure 12. An analog multiplexer is used to read seven internal diagnostic analog voltages. CURRENT RECOPY The analog multiplexer is connected to the four low-side current sense circuits of the half-bridges. These sense circuits offer a voltage proportional to the current through the low-side MOSFET. High or low resolution is selectable: 5.0 V / 2.5 A or 5.0 V / 500 mA, respectively. Refer to HalfBridge Current Recopy on page 32.) ANALOG INPUT PA1 The analog input PA1 is directly connected to the analog multiplexer, permitting analog values from the periphery to be read. ANALOG DIE I / OS LIN PHYSICAL LAYER The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The LIN pin offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set. Due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately. TEMPERATURE SENSOR The 908E425 includes an on-chip temperature sensor. This sensor offers a voltage that is proportional to the actual chip junction temperature. VSUP PRESCALER The VSUP prescaler permits the reading or measurement of the external supply voltage. The output of this voltage is VSUP / RATIOVSUP. The different internal diagnostic analog voltages can be selected with the ADMUX Register. TXD PIN The TXD pin is the MCU interface to control the state of the LIN transmitter (see Figure 1). When TXD is LOW, LIN output is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off. The TXD pin has an internal pull-up current source in order to set the LIN bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. ANALOG MULTIPLEXER CONFIGURATION REGISTER (ADMUX) Register Name and Address: ADMUX - $07 Bit s 7 0 6 0 5 0 4 0 3 SS3 2 SS2 1 SS1 0 SS0 RXD PIN The RXD transceiver pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. Read Write Reset 0 0 0 0 0 0 0 0 SS3, SS2, SS1, AND SS0 — A / D INPUT SELECT BITS These read / write bits select the input to the ADC in the microcontroller according to Table 7. Reset clears SS3, SS2, SS1, and SS0 bits. 908E425 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 7. Analog Multiplexer Configuration Register SS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 0 1 0 1 0 Channel Current Recopy HB1 Current Recopy HB2 Current Recopy HB3 Current Recopy HB4 VSUP Prescaler Temperature Sensor Not Used PA1 Pin Not Used ANALOG INPUT PA1 The Analog input PA1 pin provides an input for reading analog signals and is internally connected to the analog multiplexer. It can be used for reading switches, potentiometers or resistor values, etc. ANALOG INPUT PA1 CURRENT SOURCE The analog input PA1 has an additional selectable current source. It enables the reading of switches, NTC, etc., without the need of an additional supply line for the sensor illustrated in Figure 12. With this feature it is also possible to read multiple switches on one input. Current source is enabled if the PSON bit in the System Control Register (SYSCTL) and the CSEN bit in the Power Output Register (POUT) is set. Four different current source values can be selected with the CSSELx bits shown in Table 8. This function ceases during STOP mode operation. Table 8. PA1 Current Source Level Selection Bits CSSEL1 CSSEL0 Current Source Enable (typ.) 10% 30% 60% 100% 1 0 1 0 0 1 1 0 1 0 1 Source Selection Bits SSx 3 Selectable Current Source VDD CSSEL PSON ADOUT Analog Multiplexer CSEN PA1 Analog Input PA1 NTC Figure 12. Analog Input PA1 and Multiplexer 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS POWER OUTPUT REGISTER (POUT) Register Name and Address: POUT - $0b Bit s Read Write Reset 0 0 0 0 0 0 0 0 HALL-EFFECT SENSOR INPUT PINS (H1: H3) FUNCTION 1 0 7 0 6 0 5 4 3 CSEN 2 0(13) CSSEL1 CSSEL0 HVDDON HS_ON Notes 13. This bit must always be set to 0. CURRENT SOURCE SELECT BITS (CSSEL0 : CSSEL1 ) These read / write bits select the current source values. Reset clears the CSSEL0 : CSSEL1 bits. CURRENT SOURCE ENABLE BIT (CSEN ) This read / write bit enables the current source for PA1. Reset clears the CSEN bit (Table 9). Table 9. PA1 Current Source Enable Bit CSEN 0 1 Current Source Enable Current Source Off Current Source On HVDD ON BIT (HVDDON ) This read/write bit enables HVDD output. Reset clears the HVDDON bit. • 1 = HVDD enabled • 0 = HVDD disabled LAMP DRIVER ON BIT (HS_ON ) This read / write bit enables the Lamp driver. Reset clears the HS_ON bit. • 1 = Lamp driver enabled • 0 = Lamp driver disabled The Hall-effect sensor input pins provide three inputs for two-pin Hall-effect sensors for detecting stall and position or reading Hall-effect sensor contact switches. The Hall-effect sensor input pins are not influenced by the PSON bit in the System Control Register. Each pin of the Hall-effect sensor can be enabled by setting the HxEN bit in the Hall-Effect Sensor Input Pin Control Register (HACTL). If the pins are enabled, the Halleffect sensors are supplied with VSUP voltage and the sense circuitry is working. An internal clamp circuity limits the supply voltage to the sensor to 15 V. This sense circuitry monitors the current to VSS. The result of this sense operation is given by the HxF flags in the Hall-Effect Sensor Input Pin Status Register (HASTAT). The flag is set if the sensed current is higher than IHSCT. To prevent noise on this flag, a hysteresis is implemented on these pins. After switching on the Hall-effect sensor input pins (HxEN = 1), the Hall-effect sensors need some time to stabilize the output. In RUN mode the software must wait at least 40 µs between enabling the Hall-effect sensor and reading the hall flag. The Hall-effect sensor input pin works in an dynamic output voltage range from VSUP down to 2.0 V. Below 2.0 V the hallflags are not functional anymore. If the output voltage is below a certain threshold, the Hall-Effect Sensor Input Pin Overcurrent Flag (HP_OCF) in the System Status Register is set. Figures 13 through 15 illustrate the connections to the Hall-effect input sensors. 908E425 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS HxEN Sense Circuitry Hx Two-Terminal Hall-Effect Sensor HxF V GND Figure 13. Hall-Effect Sensor Input Pin Connected to Two-Pin Hall-Effect Sensor HxEN Sense Circuitry Hx Rv HxF V GND Figure 14. Hall-Effect Sensor Input Pin Connected to Local Switch 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Three-Terminal Hall-Effect Sensor Vs HxEN Sense Circuitry Hx Out HxF V GND GND Figure 15. Hall-Effect Sensor Input Pin Connected to Three-Pin Hall-Effect Sensor INTERRUPTS The Hall-effect sensor input pins are interrupt capable. How and when an interrupt occurs is dependent on the operating mode, RUN or Stop. RUN MODE In RUN mode the Hall-effect sensor input pin interrupt flag (HPF) will be set if a state change on the hallflags (HxF) is detected. The interrupt is maskable with the HPIE bit in the Interrupt Mask Register. Before enabling the interrupt, the flag should be cleared in order to prevent a wrong interrupt. STOP MODE In STOP mode the Hall-effect sensor input pins are disabled independent of the state of the HxEN flags. CYCLIC WAKE-UP The Hall-effect sensor inputs can be used to wake up the system. This wake-up function is provided by the cyclic check wake-up feature of the AWD (Autonomous Watchdog). If the cyclic check wake-up feature is enabled (AWDCC bit is set), the AWD switches on the enabled Hall-effect sensor pins periodically. To ensure that the Hall-effect sensor current is stabilized after switching on, the inputs are sensed after ~40 µs. If a 1 is detected (IHall sensor > IHSCT) and the interrupt mask bit HPIE is set, an interrupt is performed. This wakes up the MCU and starts the main voltage regulator. The wake-up function via this input is available when all three conditions exist: • The two-pin Hall-effect sensor input is enabled (HxEN = 1) • The cyclic wake-up of the AWD is enabled (AWDCC = 1); see Figure 16 • The Hall-effect sensor input pin interrupt is enabled (HPIE = 1) 908E425 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS SPI: AWDCC = 1 GS = 1 SPI Command STOP MREG STOP No AWD Timer Overflow? Yes No IRQ? IRQ_A = 0 Start MREG Switch on Selected Hallport Yes SPI: Reason for Wakeup Wait 40 µs Yes Operate Assert IRQ_A Hallport = 1 No Switch off Selected Hallport MREG = Main Voltage Regulator Figure 16. Hall-Effect Sensor Input Pin Cyclic Check Wake-Up Feature HALL-EFFECT SENSOR INPUT PIN CONTROL REGISTER (HACTL) Register Name and Address: HACTL - $08 Bits Read Write Reset 0 0 0 0 0 0 0 0 7 0 6 0 5 0 4 0 3 0 2 H3EN 1 H2EN 0 H1EN • 0 = Hall-effect sensor input pin Hx disabled HALL-EFFECT SENSOR INPUT PIN STATUS REGISTER (HASTAT) Register Name and Address: HASTAT - $09 Bits Read Write Reset 0 0 0 0 0 0 0 0 7 0 6 0 5 0 4 0 3 0 2 H3F 1 H2F 0 H1F HALL-EFFECT SENSOR INPUT PIN ENABLE BITS (H3EN : H1EN ) These read / write bits enable the Hall-effect sensor input pins. Reset clears the H3EN : H1EN bits. • 1 = Hall-effect sensor input pin Hx switched on and sensed HALL-EFFECT SENSOR INPUT PIN FLAG BITS (H3F : H1F ) These read-only flag bits reflect the input Hx while the Halleffect sensor input pin Hx is enabled (HxEN = 1). Reset clears the H3F : H1F bits. 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS • 1 = Hall-effect sensor input pin current above threshold • 0 = Hall-effect sensor input pin current below threshold HALF-BRIDGES Outputs HB1 : HB4 provide four low-resistive half-bridge output stages. The half-bridges can be used in H-Bridge, high-side, or low-side configurations. Reset clears all bits in the H-Bridge Output Register (HBOUT) owing to the fact that all half-bridge outputs are switched off. HB1: HB4 output features: • Short circuit (overcurrent) protection on high-side and low-side MOSFETs • Current recopy feature (low side MOSFET) • Overtemperature protection • Overvoltage and undervoltage protection • Current limitation feature (low side MOSFET) VSUP On/Off Status High-Side Driver Charge Pump, Overtemperature Protection, Overcurrent Protection Control BEMF HBx On/Off Low-Side Driver Status Current Limit Current Recopy, Current Limitation, Overcurrent Protection GND Figure 17. Half-Bridge Push-Pull Output Driver HALF-BRIDGE CONTROL Each output MOSFET can be controlled individually. The general enable of the circuitry is done by setting PSON in the System Control Register (SYSCTL). HBx_L and HBx_H form one half-bridge. It is not possible to switch on both MOSFETs in one half-bridge at the same time. If both bits are set, the high-side MOSFET has a higher priority. To avoid both MOSFETs (high side and low side) of one half-bridge being on at the same time, a break-before-make circuit exists. Switching the high-side MOSFET on is inhibited as long as the potential between gate and VSS is not below a certain threshold. Switching the low-side MOSFET on is blocked as long as the potential between gate and source of the high-side MOSFET did not fall below a certain threshold. HALF-BRIDGE OUTPUT REGISTER (HBOUT) Register Name and Address: HBOUT - $01 Bits Read Write Reset 0 0 0 0 0 0 0 0 7 HB4_H 6 HB4_L 5 HB3_H 4 HB3_L 3 HB2_H 2 HB2_L 1 HB1_H 0 HB1_L LOW-SIDE ON / OFF BITS (HBX_L ) These read / write bits turn on the low-side MOSFETs. Reset clears the HBx_L bits. • 1 = Low-side MOSFET turned on for half-bridge output x 908E425 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS • 0 = Low-side MOSFET turned off for half-bridge output x HIGH-SIDE ON/OFF BITS (HBX_H ) These read / write bits turn on the high-side MOSFETs. Reset clears the HBx_H bits. • 1 = High-side MOSFET turned on for half-bridge output x • 0 = High-side MOSFET turned on for half-bridge output x modulation on the outputs is controlled by the FGEN input and the load characteristics. The FGEN input provides the PWM frequency, whereas the duty cycle is controlled by the load characteristics. The recommended frequency range for the FGEN and the PWM is 0.1 kHz to 20 kHz. FUNCTIONALITY Each low-side MOSFET switches off if a current above the selected current limit was detected. The 908E425 offers five different current limits. Refer to Table 10 for current limit values. The low-side MOSFET switches on again if a rising edge on the FGEN input was detected (Figure 18). HALF-BRIDGE CURRENT LIMITATION Each low-side MOSFET offers a current limit or constant current feature. This features is realized by a pulse width modulation on the low-side MOSFET. The pulse width Coil Current H-Bridge low-side MOSFET will be switched off if select current limit is reached. H-Bridge low-side MOSFET will be turned on with each rising edge of the FGEN input. t Half-Bridge Low-Side Output t FGEN Input (MCU PWM Signal) t Minimum 50 µs Figure 18. Half-Bridge Current Limitation 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS OFFSET CHOPPING If bit OFC_EN in the H-Bridge Control Register (HBCTL) is set, HB1 and HB2 will continue to switch on the low-side MOSFETs with the rising edge of the FGEN signal and HB3 and HB4 will switch on the low-side MOSFETs with the falling Coil1 Current edge on the FGEN input. In step motor applications this feature allows the reduction of EMI due to a reduction of the di/dt (Figure 19). Coil2 Current FGEN Input (MCU PWM Signal) HB1 HB2 HB3 HB4 Coil2….. Coil1….. Current in VSUP Line Figure 19. Offset Chopping for Step Motor Control HALF-BRIDGE CURRENT RECOPY Each low-side MOSFET has an additional sense output to allow a current recopy feature. This sense source is internally connected to a shunt resistor. The drop voltage is amplified and switched to the analog multiplexer. The factor for the current sense amplification can be selected via bit CSA in the System Control Register. • CSA = 1: Low resolution selected (500 mA measurement range) • CSA = 0: High resolution selected (2.5 A measurement range) HALF-BRIDGE BEMF GENERATION The BEMF output is set to 1 if a recirculation current is detected in any half-bridge. This recirculation current flows via the two freewheeling diodes of the power MOSFETs. The BEMF circuitry detects that and generates a HIGH on the BEMF output as long as a recirculation current is detected. This signal provides a flexible and reliable detection of stall in step motor applications. For this the BEMF circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. In addition the signal can be used for open load detection (absence of this signal), see Figure 20. 908E425 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Coil Current Voltage on 1 1 BEMF Signal Figure 20. BEMF Signal Generation HALF-BRIDGE OVERTEMPERATURE PROTECTION The half-bridge outputs provide an overtemperature prewarning with the HTF in the Interrupt Flag Register (IFR). In order to protect the outputs against overtemperature, the High-Temperature Reset must be enabled. If this value is reached, the part generates a reset and disables all power outputs. done by the low- and high-voltage interrupt circuitry. If one of these flags (LVF, HVF) is set, the outputs are automatically disabled. The overvoltage / undervoltage status flags are cleared (and the outputs re-enabled) by writing a Logic [1] to the LVF / HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high- or low-voltage condition is present. HALF-BRIDGE OVERCURRENT PROTECTION The half-bridges are protected against short to GND, short to VSUP, and load shorts. In the event an overcurrent on the high side is detected, the high-side MOSFETs on all HB high-side MOSFETs are switched off automatically. In the event an overcurrent on the low side is detected, all HB low-side MOSFETs are switched off automatically. In both cases the overcurrent status flag HB_OCF in the System Status Register (SYSSTAT) is set. The overcurrent status flag is cleared (and the outputs reenabled) by writing a Logic [1] to the HB_OCF flag in the System Status Register or by reset. HALF-BRIDGE CONTROL REGISTER (HBCTL) Register Name and Address: HBCTL - $02 Bits 7 6 5 0 4 0 3 0 2 1 0 Read OFC_EN CSA Write Reset 0 0 CLS2 CLS1 CLS0 0 0 0 0 0 0 H-BRIDGE OFFSET CHOPPING ENABLE BIT (OFC_EN) This read / write bit enables offset chopping. Reset clears the OFC_EN bit. • 1 = Offset chopping enabled • 0 = Offset chopping disabled HALF-BRIDGE OVERVOLTAGE / UNDERVOLTAGE The half-bridge outputs are protected against undervoltage and overvoltage conditions. This protection is 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS H-BRIDGES CURRENT SENSE AMPLIFICATION SELECT BIT (CSA ) This read / write bit selects the current sense amplification of the H-Bridges. Reset clears the CSA bit. • 1 = Current sense amplification set for measuring 0.5 A. • 0 = Current sense amplification set for measuring 2.5 A. H-BRIDGE CURRENT LIMITATION SELECTION BITS (CLS2 : CLS0) These read / write bits select the current limitation value according to Table 10. Reset clears the CLS2 : CLS0 bits. Table 10. H-Bridge Current Limitation Value Selection Bits CLS2 0 0 0 0 1 1 1 1 CLS1 0 0 1 1 0 0 1 1 CLS0 0 1 0 1 0 1 0 1 55 mA (typ) 260 mA (typ) 370 mA (typ) 550 mA (typ) 740 mA (typ) Current Limit No Limit HIGH-SIDE DRIVER The high-side output is a low-resistive high-side switch targeted for driving lamps. The high side is protected against overtemperature. To limit the high inrush current of bulbs, overcurrent protection circuitry is used to limit the current. The output is enabled with bit PSON in the System Control Register and can be switched on / off with bit HS_ON in the Power Output Register. Figure 21 depicts the high-side switch circuitry and connection to external lamp. HIGH-SIDE OVERVOLTAGE / UNDERVOLTAGE PROTECTION The high-side output pin, HS, is protected against undervoltage / overvoltage conditions. This protection is done by the low- and high-voltage interrupt circuitry. If one of these flags (LVF, HVF) is set, the output is disabled. The overvoltage / undervoltage status flags are cleared and the output re-enabled by writing a Logic [1] to the LVF / HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high- or low-voltage condition is present. VSUP On/Off High-Side Driver Control Status Current Limit Charge Pump, Overcurrent Protection, Inrush Current Limiter HS Figure 21. High-Side Circuitry 908E425 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS HIGH-SIDE OVERTEMPERATURE PROTECTION The high-side output provides an overtemperature prewarning with the HTF in the Interrupt Flag Register. In order to protect the output against overtemperature, the HighTemperature Reset must be enabled. If this value is reached, the part generates a reset and disables all power outputs. HIGH-SIDE OVERCURRENT PROTECTION The high-side output is protected against overcurrent. In the event overcurrent limit is or was reached, the output automatically switches off and the overcurrent flag is set. Due to the high inrush current of bulbs, a special feature of the 908E425 prevents an overcurrent shutdown during this HS Current HS Overcurrent Shutdown Threshold inrush. If an PWM frequency is supplied to the FGEN output during the switching on of a bulb, the inrush current is limited to the overcurrent shutdown limit. This means if the current reaches the overcurrent shutdown, the high side will be switched off, but each rising edge on the FGEN input will enable the driver again. To distinguish between a shutdown due to an inrush current or a real shutdown, the software must check if the overcurrent status flag (HS_OCF) in the System Status Register is set beyond a certain period of time. The overcurrent status flag is cleared by writing a Logic [1] to the HS_OCF in the System Status Register, see Figure 22. t FGEN Input (MCU PWM Signal) t Figure 22. Inrush Current Limiter on High-Side Output SWITCHABLE VDD OUTPUT (HVDD) The HVDD pin is a switchable VDD output pin. It can be used for driving external circuitry that requires a VDD voltage. The output is enabled with bit PSON in the System Control Register and can be switched on / off with bit HVDDON in the Power Output Register. Low- or high-voltage conditions (LVI / HVI) have no influence on this circuitry. HVDD OVERTEMPERATURE PROTECTION Overtemperature protection is enabled if the hightemperature reset is enabled. HVDD OVERCURRENT PROTECTION The HVDD output is protected against overcurrent. In the event the overcurrent limit is or was reached, the output automatically switches off and the HVDD overcurrent flag in the System Status Register is set. 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS SYSTEM CONTROL REGISTER (SYSCTL) Register Name and Address: SYSCTL - $03 Bit s 7 6 5 SRS0 4 0 3 0 2 0 1 0 0 0 GS 0 0 0 0 0 0 0 0 HALL-EFFECT SENSOR INPUT PIN OVERCURRENT FLAG BIT (HP_OCF ) This read / write flag is set on an overcurrent condition at one of the Hall-effect sensor input pins. Clear HP_OCF and enable the output by writing a Logic [1] to the HP_OCF flag. Reset clears the HP_OCF bit. Writing a Logic [0] to HP_OCF has no effect. • 1 = Overcurrent condition on Hall-effect sensor input pin has occurred • 0 = No overcurrent condition on Hall-effect sensor input pin has occurred LIN CURRENT LIMITATION BIT (LINCL) This read-only bit is set if the LIN transmitter operates in current limitation region. Due to excessive power dissipation in the transmitter, software is advised to turn the transmitter off immediately. •1 = Transmitter operating in current limitation region •0 = Transmitter not operating in current limitation region HVDD OUTPUT OVERCURRENT FLAG BIT (HVDD_OCF ) This read / write flag is set on an overcurrent condition at the HVDD pin. Clear HVDD_OCF and enable the output by writing a Logic [1] to the HVDD_OCF Flag. Reset clears the HVDD_OCF bit. Writing a Logic [0] to HVDD_OCF has no effect. •1 = Overcurrent condition on HVDD has occurred •0 = No overcurrent condition on HVDD has occurred HIGH-SIDE OVERCURRENT FLAG BIT (HS_OCF ) This read / write flag is set on an overcurrent condition at the high-side driver. Clear HS_OCF and enable the high-side driver by writing a Logic [1] to HS_OCF. Reset clears the HS_OCF bit. Writing a Logic [0] to HS_OCF has no effect. • 1 = Overcurrent condition on high-side drivers has occurred • 0 = No overcurrent condition on high-side drivers has occurred LOW-VOLTAGE BIT (LVF ) This read only bit is a copy of the LVF bit in the Interrupt Flag Register. • 1 = Low-voltage condition has occurred • 0 = No low-voltage condition has occurred 1 0 Read PSON SRS1 Write Reset POWER STAGES ON BIT (PSON ) This read / write bit enables the power stages (half-bridges, high side, LIN transmitter, Analog Input PA1 current sources, and HVDD output). Reset clears the PSON bit. • 1 = Power stages enabled. • 0 = Power stages disabled. LIN SLEW RATE SELECTION BITS (SRS0 : SRS1 ) These read / write bits enable the user to select the appropriate LIN slew rate for different baud rate configurations as shown in Table 11. The high speed slew rates are used, for example, for programming via the LIN and are not intended for use in the application. Table 11. LIN Slew Rate Selection Bits SRS1 0 0 1 1 SRS0 0 1 0 1 LIN Slew Rate Initial Slew Rate (20 kBaud) Slow Slew Rate (10 kBaud) High Speed II (8 x) High Speed I (4 x) GO TO STOP MODE BIT (GS ) This write-only bit instructs the 908E425 to power down and go into STOP mode. Reset or CPU interrupt requests clear the GS bit. • 1 = Power down and go into STOP mode • 0 = Not in STOP mode SYSTEM STATUS REGISTER (SYSSTAT) Register Name and Address: SYSSTAT - $0c Bit s 7 6 5 4 3 2 HIGH-VOLTAGE SENSOR BIT (HVF ) This read-only bit is a copy of the HVF bit in the Interrupt Flag Register. • 1 = High-voltage condition has occurred • 0 = No high-voltage condition has occurred H-BRIDGE OVERCURRENT FLAG BIT (HB_OCF ) This read / write flag is set on an overcurrent condition at the H-Bridges. Clear HB_OCF and enable the H-Bridge Read HP_OCF LINCL HVDD_OCF HS_OCF LVF HVF HB_OCF HTF Write Reset 0 0 0 0 0 0 0 0 908E425 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS driver by writing a Logic [1] to HB_OCF. Reset clears the HB_OCF bit. Writing a Logic [0] to HB_OCF has no effect. • 1 = Overcurrent condition on H-Bridges has occurred • 0 = No overcurrent condition on H-Bridges has occurred OVERTEMPERATURE STATUS BIT (HTF ) This read-only bit is a copy of the HTF bit in the Interrupt Flag Register. • 1 = Overtemperature condition has occurred • 0 = No overtemperature condition has occurred AUTONOMOUS WATCHDOG CONTROL REGISTER (AWDCTL) Register Name and Address: AWDCTL - $0a Bit s Read Write Reset 0 0 7 0 6 0 5 0 AWDRST 0 4 3 2 1 0 AWDRE AWDIE AWDCC AWDF AWDR 0 0 0 0 0 AUTONOMOUS WATCHDOG (AWD) The Autonomous Watchdog module consists of three functions: • Watchdog function for the CPU in RUN mode • Periodic interrupt function in STOP mode • Cyclic wake-up function in STOP mode The AWD is enabled if AWDIE, AWDRE, or AWDCC in the AWDCTL Register is set. If these bits are cleared, the AWD oscillator is disabled and the watchdog switched off. AUTONOMOUS WATCHDOG RESET BIT (AWDRST) This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit. • 1 = Reset AWD and restart timeout period • 0 = No effect AUTONOMOUS WATCHDOG RESET ENABLE BIT (AWDRE ) This read / write bit enables resets on AWD time-outs. A reset on the RST_A is only asserted when the device is in RUN mode. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit. • 1 = Autonomous watchdog enabled • 0 = Autonomous watchdog disabled AUTONOMOUS WATCHDOG INTERRUPT ENABLE BIT (AWDIE) This read / write bit enables CPU interrupts by the Autonomous Watchdog timeout flag, AWFD. IRQ_A is only asserted when the device is in STOP mode. Reset clears the AWDIE bit. • 1 = CPU interrupt requests from AWDF enabled • 0 = CPU interrupt requests from AWDF disabled AUTONOMOUS WATCHDOG CYCLIC CHECK (AWDCC ) This read / write bit enables the cyclic check of the two-pin Hall-effect sensor and the analog inputs. Reset clears the AWDCC bit. • 1 = Cyclic check of the Hall-effect sensor and analog port • 0 = No cyclic check of the Hall-effect sensor and analog port AUTONOMOUS WATCHDOG TIMEOUT FLAG BIT (AWDF) This read / write flag is set when the Autonomous Watchdog has timed out. Clear AWDF by writing a Logic [1] to AWDF. Clearing AWDF also resets the AWD counter and starts a new timeout period. Reset clears the AWDF bit. Writing a Logic [0] to AWDF has no effect. • 1 = AWD has timed out • 0 = AWD has not yet timed out WATCHDOG The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software. If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. PERIODIC INTERRUPT Periodic interrupt is only available in STOP mode. It is enabled by setting the AWDIE bit in the AWDCTL Register. If AWDIE is set, the AWD wakes up the system after a fixed period of time. This time period can be selected with bit AWDR in the AWDCTL Register. CYCLIC WAKE-UP The cyclic wake-up feature is only available in STOP mode. If this feature is enabled, the selected Hall-effect sensor input pins are switched on and sensed. If a “1” is detected on one of these inputs and the interrupt for the Halleffect sensors is enabled, a system wake-up is performed. (Switch on main voltage regulator and assert IRQ_A to the microcontroller). 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION FACTORY TRIMMING AND CALIBRATION AUTONOMOUS WATCHDOG RATE BIT (AWDR ) This read / write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit. • 1 = Fast rate selected (10 ms) • 0 = Slow rate selected (20 ms) device. The output of the regulator is also connected to the VDD pin to provide the 5.0 V to the microcontroller. RUN MODE During RUN mode the main voltage regulator is on. It provides a regulated supply to all digital sections. STOP MODE During STOP mode the STOP mode regulator supplies a regulated output voltage. The STOP mode regulator has a very limited output current capability. The output voltage will be lower than the output voltage of the main voltage regulator. VOLTAGE REGULATOR The 908E425 chip contains a low-power, low-drop voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E425, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the empty (0xFF) state: •0xFD80: 0xFDDF Trim and Calibration Values •0xFFFE : 0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. TRIM VALUES Below the usage of the trim values located in the flash memory is explained INTERNAL CLOCK GENERATOR (ICG) TRIM VALUE The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate for these dependencies a ICG trim values is located at address $FDC2. After trimming the ICG is a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100 nF) and stabilized (4.7 µF) VDD = 5.0 V, TAmbient~25°C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG this values has to be copied to the ICG Trim Register ICGTR at dress $38 of the MCU. Important The value has to copied after every reset. 908E425 38 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E425 has the MC68HC908EY16 MCU embedded typically all the development tools available for the MCU also apply for this device, however due to the fact of the additional analog die circuitry and the nominal +12 V supply voltage some additional items have to be considered: • nominal 12 V rather than 5.0 V or 3.0 V supply • high voltage VTST might be applied not only to IRQ pin, but IRQ_A pin For a detailed information on the MCU related development support see the MC68HC908EY16 datasheet section development support. The programming is principally possible at two stages in the manufacturing process - first on chip level, before the IC is soldered onto a pcb board and second after the IC is soldered onto the pcb board. CHIP LEVEL PROGRAMMING On Chip level the easiest way is to only power the MCU with +5.0 V (see Figure 23) and not to provide the analog chip with VSUP, in this setup all the analog pinpin should be left open (e.g. VSUP[1:3]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 datasheet - section development support. Of course its also possible to supply the whole system with Vsup (12 V) instead as described in Figure 24, page 40. VSUP[1:3] GND[1:2] VDD VSS +5V VREFH VDDA RST EVDD RST_A +5V 1 1µF + 3 4 1µF + 5 C1C2+ GND V+ V15 2 6 1µF + 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 R2OUT 9 2 1 5 3 6 4 5 10k 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 9.8304MHz CLOCK +5V CLK PTC4/OSC1 PTB4/AD4 10k +5V 16 + 1µF 1µF VTST IRQ IRQ_A VREFL 100nF 4.7µF C1+ VCC MM908E425 MM908E625 VSSA EVSS MAX232 C2- RS232 DB-9 2 Figure 23. Normal Monitor Mode Circuit (MCU only) 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 39 TYPICAL APPLICATIONS PCB LEVEL PROGRAMMING If the IC is soldered onto the pcb board its typically not possible to separately power the MCU with +5V, the whole system has to be powered up providing VSUP (see Figure 24). VDD VSUP + 47µF 100nF VSUP[1:3] GND[1:2] VDD VSS VREFH VDDA RST EVDD RST_A VDD 1 1µF + 3 4 1µF + 5 C1C2+ GND V+ V15 2 6 1µF + 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 R2OUT 9 2 1 5 3 6 4 5 10k 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 9.8304MHz CLOCK VDD CLK PTC4/OSC1 PTB4/AD4 10k VDD 16 + 1µF 1µF VTST IRQ IRQ_A VREFL 100nF 4.7µF C1+ VCC MM908E425 MM908E625 VSSA EVSS MAX232 C2- RS232 DB-9 2 Figure 24. Normal Monitor Mode Circuit Table 12 summarizes the possible configurations and the necessary setups. Table 12. Monitor Mode Signal Requirements and Options Serial Communication PTA0 Mode IRQ RST Reset Vector Mode Selection ICG COP PTB3 0 PTA1 0 PTB4 1 OFF disabled Communication Speed Normal Request Baud Bus Timeout External Clock Frequency Rate disabled 9.8304 MHz 9.8304 MHz — 2.4576 MHz 2.4576 MHz Nominal 1.6MHz Nominal 1.6MHz 9600 Normal Monitor VTST VDD VDD X 1 OFF VDD $FFFF (blank) 1 0 X X ON not $FFFF (not blank) disabled disabled 9600 Nominal 6300 Nominal 6300 Forced Monitor GND disabled disabled User VDD VDD X X X X ON enabled enabled — Notes 1. PTA0 must have a pullup resistor to VDD in monitor mode 2. 3. 4. 5. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1 Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256 X = don’t care VTST is a high voltage VDD + 3.5 V ≤ VTST ≤ VDD + 4.5 V 908E425 40 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS EMC/EMI RECOMMENDATIONS This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be e.g. found on the Freescale web site www.freescale.com. MCU DIGITAL SUPPLY PINS (EVDD AND EVSS) Fast signal transitions on MCU pins place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high-quality ceramic decoupling capacitor be placed between these pins. VSUP PINS (VSUP1:VSUP3) Its recommended to place a high-quality ceramic decoupling capacitor close to the VSUP pins to improve EMC/EMI behavior. MCU ANALOG SUPPLY PINS (VREFH, VDDA AND VREFL, VSSA) To avoid noise on the analog supply pins its important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via separate traces and connected to the voltage regulator output. Figure 25 and Figure 26 show the recommendations on schematics and layout level and Table 13 indicates recommended external components and layout considerations. LIN PIN For DPI (Direct Power Injection) and ESD (Electro Static Discharge) its recommended to place a high-quality ceramic decoupling capacitor near the LIN pin. An additional varistor will further increase the immunity against ESD. A ferrite in the LIN line will suppress some of the noise induced. VOLTAGE REGULATOR OUTPUT PINS (VDD AND AGND) Use a high-quality ceramic decoupling capacitor to stabilize the regulated voltage. D1 VSUP + C1 C2 VSUP1 VSUP2 VSUP3 VREFH L1 LIN V1 C5 C3 C4 LIN EVDD VDDA VDD VSS MM908E425 MM908E625 GND1 GND2 EVSS VSSA VREFL Figure 25. EMC/EMI recommendations 908E425 Analog Integrated Circuit Device Data Freescale Semiconductor 41 TYPICAL APPLICATIONS 1 2 3 4 5 6 54 53 52 51 50 49 VREFH VDDA EVDD EVSS VSSA VREFL 48 47 46 45 44 43 42 NC 10 11 12 13 14 15 16 17 18 19 908E425 VSS VDD 41 40 39 38 37 36 C3 C4 Pins 21, 22 (NC) used for signal routing 7 8 9 C5 LIN L1 V1 20 21 22 23 24 LIN NC NC NC 35 34 33 32 VSUP1 GND1 VSUP3 GND2 31 30 29 GND C1 25 26 27 VSUP2 28 C2 VBAT D1 Figure 26. PCB Layout Recommendations . Table 13. Component Value Recommendation Component D1 C1 C2 C3 Bulk Capacitor 100 nF, SMD Ceramic 100 nF, SMD Ceramic Close (