908E625

Freescale Semiconductor Technical Data MM908E625 Rev 4.0, 09/2005 Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication The 908E625 is an integrated single-package solution including a high-performance HC08 microcontroller with a SMARTMOS TM analog control IC. The HC08 includes Flash Memory, a timer, Enhanced Serial Communications Interface (ESCI), an Analog-toDigital Converter (ADC), Serial Peripheral Interface (SPI) (only internal), and an Internal Clock Generator (ICG) module. The analog control die provides fully protected H-Bridge/high-side outputs, voltage regulator, autonomous watchdog with cyclic wake-up, and Local Interconnect Network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive mirror, door lock, and light-levelling applications. Features • • • • • • • • • • • • • High-Performance M68HC908EY16 Core 16 K Bytes of On-Chip Flash Memory 512 Bytes of RAM Internal Clock Generation Module Two 16-bit, 2-Channel Timers 10-Bit Analog-to-Digital Converter LIN Physical Layer Autonomous Watchdog with Cyclic Wakeup Three Two-Terminal Hall-Effect Sensor Input Ports One Analog Input with Switchable Current Source Four Low RDS(ON) Half-Bridge Outputs One Low RDS(ON) High-Side Output 13 Micro Controller I/Os 3 LIN VREFH VDDA EVDD VDD VREFL VSSA EVSS VSS RST RST_A IRQ IRQ_A SS PTB1/AD1 RXD PTE1/RXD PTD1/TACH1 FGEN BEMF PTD0/TACH0/BEMF VSUP 908E625 H-BRIDGE POWER SUPPLY WITH EMBEDDED MCU AND LIN DWB SUFFIX 98ARL105910 54-TERMINAL SOICWB-EP ORDERING INFORMATION Device MM908E625ACDWB Temperature Range (TA) -40°C to 85°C Package 54 SOICW EP 908E625 HB1 M HB2 HB3 HB4 HS High-Side Output HVDD H1 H2 H3 PA1 Port A I/Os Port B I/Os Port C I/Os Switchable Internal VDD Output Three 2-Terminal Hall-Effect Sensor Inputs Analog Input with Current Source Microcontroller Ports M M 4 Half-Bridges Controlling 3 Loads GND 2 EP Figure 1. 908E625 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005. All rights reserved. CPU Registers ALU 5-Bit Keyboard Interrupt Module Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes 2-channel Timer Interface Module B FGEN Internal Bus DDRC DDRA PORT A PTC3/OSC2 PTD1/TACH1 PTD0/TACH0 PORT C DDRD PORT D DDRB PORT B DDRE PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTE1/RxD PTE0/TxD PORT E 2 PTD0/TACH0 PTB1/AD1 BEMF VSUP1-3 GND1-2 RST_A IRQ_A FGEN PTD1/TACH1 PTE1/RXD VREFH SS VREFL VDDA M68HC08 CPU Voltage Regulator 908E625 EVDD EVSS RXD RST LIN IRQ Single Breakpoint Break Module INTERNAL BLOCK DIAGRAM VSSA PTE0/TXD TXD LIN Physical Layer Switched VDD Driver & Diagnostic 2-Channel Timer Interface Module A Reset Control Module VSS VDD HVDD VSUP PTA0/KBD0 User Flash Vector Space, 36 Bytes OSC2 OSC1 Flash Programming (burn in) ROM, 1024 Bytes Enhanced Serial Communication Interface Module Computer Operating Properly Module Interrupt Control Module PTA1/KBD1 Internal Clock Generator Module High Side Driver & Diagnostic HS VSUP FGEN PTA2/KBD2 SS PTC0/MISO MISO MOSI SPSCK PTC1/MOSI PTA5/SPSCK RST PTA3/KBD3 Serial Pheripheral Interface Module IRQ 24 Internal System Integration Module Single External IRQ Module Configuration Register Module BEMF Half Bridge Driver & Diagnostic HB1 PTA4/KBD4 VREFH VDDA VREFL VSSA VSUP FGEN SPI & CONTROL PTB3/AD3 10 Bit Analog-toDigital Converter Module Periodic Wake-Up Timebase Module POWER Arbiter Module PTB4/AD4 VDD VSS BEMF Half Bridge Driver & Diagnostic VSUP FGEN HB2 PTB5/AD5 Power-On Reset Module Prescaler Module INTERNAL BLOCK DIAGRAM HB3 Autonomous Watchdog BEMF VSUP FGEN PTB6/AD6/TBCH0 Security Module BEMF Module Half Bridge Driver & Diagnostic PTB7/AD7/TBCH1 Figure 2. 908E625 Simplified Internal Block Diagram Chip Temp BEMF PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTC2/MCLK Half Bridge Driver & Diagnostic VSUP Prescaler HB4 PTC4/OSC1 H1 PTB0/AD0 ADOUT Hall-Effect Sensor Inputs Analog Multiplexer H2 H3 Analog Input with Current Source FLSVPP PA1 MCU Die Analog Die Analog Integrated Circuit Device Data Freescale Semiconductor TERMINAL CONNECTIONS TERMINAL CONNECTIONS PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF RST_A IRQ_A SS Exposed Pad 41 40 39 38 37 36 35 34 33 32 31 30 29 28 LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS PA1 VDD H1 H2 H3 HVDD NC HB4 VSUP3 GND2 HB3 HS Figure 3. 908E625 Terminal Connections (Transparent Package Top View) Table 1. 908E625 Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 15. Terminal Function MCU Terminal 1 2 6 7 8 11 3 4 5 9 10 Terminal Name PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK IRQ Formal Name Port B I/Os Definition These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU Port C I/Os These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU MCU External Interrupt Input This terminal is an asynchronous external interrupt input terminal. External Reset This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. Not connected. RST MCU 12 13 14, 21, 22, 33 PTD0/TACH0/BEMF PTD1/TACH1 NC Port D I/Os – No Connect 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 3 TERMINAL CONNECTIONS Table 1. 908E625 Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 15. Terminal Function MCU MCU MCU MCU MCU Terminal 42 43 48 44 47 45 46 49 50 52 53 54 51 15 16 17 18 19 20 23 26 29 32 24 27 31 25 30 28 34 Terminal Name PTE1/RXD VREFL VREFH VSSA VDDA EVSS EVDD PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 FLSVPP FGEN BEMF RST_A IRQ_A Formal Name Port E I/O ADC References Definition This terminal is a special-function, bidirectional I/O port terminal that can is shared with other functional modules in the MCU. These terminals are the reference voltage terminals for the analog-to-digital converter (ADC). ADC Supply Terminals These terminals are the power supply terminals for the analogto-digital converter. MCU Power Supply Terminals Port A I/Os These terminals are the ground and power supply terminals, respectively. The MCU operates from a single power supply. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU Analog Analog Analog Analog Analog Analog Analog Test Terminal Current Limitation Frequency Input For test purposes only. Do not connect in the application. This is the input terminal for the half-bridge current limitation and the high-side inrush current limiter PWM frequency. Back Electromagnetic This terminal gives the user information about back Force Output electromagnetic force (BEMF). Internal Reset Internal Interrupt Output Slave Select LIN Bus Half-Bridge Outputs This terminal is the bidirectional reset terminal of the analog die. This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal is the SPI slave select terminal for the analog chip. This terminal represents the single-wire bus transmitter and receiver. This device includes power MOSFETs configured as four halfbridge driver outputs. These outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. These terminals are device power supply terminals. SS LIN HB1 HB2 HB3 HB4 VSUP1 VSUP2 VSUP3 GND1 GND2 HS HVDD Analog Power Supply Terminals Power Ground Terminals High-Side Output Analog Analog Analog These terminals are device power ground connections. This output terminal is a low RDS(ON) high-side switch. Switchable VDD Output This terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Halleffect sensors. Hall-Effect Sensor Inputs Voltage Regulator Output Analog Input Voltage Regulator Ground These terminals provide inputs for Hall-effect sensors and switches. The +5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller. This terminal is an analog input port with selectable source values. Ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Analog 35 36 37 38 39 40 H3 H2 H1 VDD PA1 VSS Analog Analog Analog 908E625 4 Analog Integrated Circuit Device Data Freescale Semiconductor TERMINAL CONNECTIONS Table 1. 908E625 Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 15. Terminal Function Analog – Terminal 41 EP Terminal Name RXD Exposed Pad Formal Name Definition LIN Transceiver Output This terminal is the output of LIN transceiver. Exposed Pad The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 5 MAXIMUM RATINGS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Supply Voltage Analog Chip Supply Voltage under Normal Operation, Steady State Analog Chip Supply Voltage under Transient Conditions (1) Microcontroller Chip Supply Voltage Input Terminal Voltage Analog Chip Microcontroller Chip Maximum Microcontroller Current per Terminal All Terminals Except VDD, VSS, PTA0:PTA6, PTC0:PTC1 Terminals PTA0:PTA6, PTC0:PTC1 Maximum Microcontroller VSS Output Current Maximum Microcontroller VDD Input Current LIN Supply Voltage Normal Operation (Steady-State) Transient Conditions (1) ESD Voltage Human Body Model (HBM)(2) VESD ±3000 ±150 ±500 Machine Model (MM)(3) Charge Device Model (CDM)(4) THERMAL RATINGS Storage Temperature Ambient Operating Temperature Operating Case Temperature (5) Symbol Value Unit V VSUP(SS) VSUP(PK) VDD -0.3 to 28 -0.3 to 40 -0.3 to 6.0 V VIN (ANALOG) VIN (MCU) IPIN(1) IPIN(2) IMVSS IMVDD VBUS(SS) VBUS(DYNAMIC) -0.3 to 5.5 VSS -0.3 to VDD +0.3 mA ±15 ±25 100 100 mA mA V -18 to 28 40 V TSTG TA TC TJ TSOLDER -40 to 150 -40 to 85 -40 to 85 -40 to 125 245 °C °C °C °C °C Operating Junction Temperature(6) Peak Package Reflow Temperature During Solder Mounting (7) Notes 1. Transient capability for pulses with a time of t < 0.5 sec. 2. ESD voltage testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω) 3. 4. 5. 6. 7. ESD voltage testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP = 0 Ω) ESD voltage testing is performed in accordance with Charge Device Model, robotic (CZAP =4.0 pF). The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation on the analog die. The analog die temperature must not exceed 150°C under these conditions. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 908E625 6 Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic SUPPLY VOLTAGE Nominal Operating Voltage SUPPLY CURRENT NORMAL Mode VSUP = 12 V, Power Die ON (PSON=1), MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled STOP Mode (8) VSUP = 12 V, Cyclic Wake-Up Disabled DIGITAL INTERFACE RATINGS (ANALOG DIE) Output Terminals RST_A, IRQ_A Low-State Output Voltage (IOUT = - 1.5 mA) High-State Output Voltage (IOUT = 1.0 µA) Output Terminals BEMF, RXD Low-State Output Voltage (IOUT = - 1.5 mA) High-State Output Voltage (IOUT = 1.5 mA) Output Terminal RXD–Capacitance (9) Input Terminals RST_A, FGEN, SS Input Logic Low Voltage Input Logic High Voltage Input Terminals RST_A, FGEN, SS –Capacitance (9) Terminals RST_A, IRQ_A –Pullup Resistor Terminal SS –Pullup Resistor Terminals FGEN, MOSI, SPSCK–Pulldown Resistor Terminal TXD–Pullup Current Source Notes 8. STOP mode current will increase if VSUP exceeds 15 V. 9. This parameter is guaranteed by process monitoring but is not production tested. VIL VIH CIN RPULLUP1 RPULLUP2 RPULLDOWN IPULLUP – 3.5 – – – – – – – 4.0 10 60 60 35 1.5 – – – – – – pF kΩ kΩ kΩ µA V VOL VOH CIN – 3.85 – – – 4.0 0.4 – – pF V VOL VOH – 3.85 – – 0.4 – V IRUN – 20 – mA VSUP 8.0 – 18 V Symbol Min Typ Max Unit ISTOP – – 60 µA 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 7 STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic SYSTEM RESETS AND INTERRUPTS High-Voltage Reset Threshold Hysteresis Low-Voltage Reset Threshold Hysteresis High-Voltage Interrupt Threshold Hysteresis Low-Voltage Interrupt Threshold Hysteresis High-Temperature Reset (10) Threshold Hysteresis High-Temperature Interrupt (11) Threshold Hysteresis VOLTAGE REGULATOR Normal Mode Output Voltage IOUT = 60 mA, 6.0 V < VSUP < 18 V Load Regulation IOUT = 80 mA, VSUP = 9.0 V, TJ = 125°C STOP Mode Output Voltage (Maximum Output Current 100 µA) LIN PHYSICAL LAYER Output Low Level TXD LOW, 500 Ω Pullup to VSUP Output High Level TXD HIGH, IOUT = 1.0 µA Pullup Resistor to VSUP Leakage Current to GND Recessive State (-0.5 V < VLIN < VSUP) Leakage Current to GND (VSUP Disconnected) Including Internal Pullup Resistor, VLIN @ -18 V Including Internal Pullup Resistor, VLIN @ +18 V IBUS_NO_GND IBUS – – -600 25 – – RSLAVE IBUS_PAS_rec 0.0 – 20 µA VLIN-HIGH VSUP -1.0 20 – 30 – 60 kΩ µA VLIN-LOW – – 1.4 V V VDDSTOP VLR – 4.5 – 4.7 100 4.9 V VDDRUN 4.75 5.0 5.25 mV V TION TIH – 5.0 160 – – – TRON TRH – 5.0 170 – – – VLVION VLVIH 6.5 – – 0.4 8.0 – VHVION VHVIH 17.5 – 21 1.0 23 – V VLVRON VLVRH 3.6 – 4.0 100 4.5 – V mV V VHVRON VHVRH 27 – 30 1.5 33 – V Symbol Min Typ Max Unit °C °C Notes 10. This parameter is guaranteed by process monitoring but is not production tested. 11. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10°C). 908E625 8 Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic LIN Receiver Recessive Dominant Threshold Input Hysteresis LIN Wake-Up Threshold HIGH-SIDE OUTPUT (HS) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A High-Side Overcurrent Shutdown HALF-BRIDGE OUTPUTS (HB1:HB4) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A High Side Low Side High-Side Overcurrent Shutdown Low-Side Overcurrent Shutdown Low-Side Current Limitation @ TJ = 25°C Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1) Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0) Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1) Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0) Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1) Half-Bridge Output HIGH Threshold for BEMF Detection Half-Bridge Output LOW Threshold for BEMF Detection Hysteresis for BEMF Detection Low-Side Current-to-Voltage Ratio (VADOUT [V]/IHB [A]) CSA = 1 CSA = 0 SWITCHABLE VDD OUTPUT (PH.D.) Overcurrent Shutdown Threshold VSUP DOWN-SCALER Voltage Ratio (RATIOVSUP = VSUP / VADOUT) INTERNAL DIE TEMPERATURE SENSOR Voltage/Temperature Slope Output Voltage @ 25°C HALL-EFFECT SENSOR INPUTS (H1:H3) Output Voltage VSUP < 16.2 V VSUP > 16.2 V VHALL1 VHALL2 – – VSUP - 1.2 – – 15 V STtoV VT25 – 1.7 19 2.1 – 2.5 mV/°C V RATIOVSUP 4.8 5.1 5.35 – IHVDDOCT 24 30 40 mA RATIOH RATIOL 7.0 1.0 12.0 2.0 14.0 3.0 RDS(ON)HB_HS RDS(ON)HB_LS – – 4.0 2.8 – 210 300 450 600 – – – 425 400 – – 55 260 370 550 740 -30 -60 30 500 500 7.5 7.5 – 315 440 650 880 0 -5.0 – V mV mV V/A mΩ RDS(ON)HS IHSOC – 3.9 600 – 700 7.0 mΩ A VIH VIL VITH VIHY VWTH 0.6 VLIN 0.0 – 0.01 VSUP – – – VSUP /2 – VSUP /2 VSUP 0.4 VLIN – 0.1 VSUP – V Symbol Min Typ Max Unit V IHBHSOC IHBLSOC ICL1 ICL2 ICL3 ICL4 ICL5 VBEMFH VBEMFL VBEMFHY A A mA 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 9 STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Sense Current Threshold Hysteresis Output Current Limitation Overcurrent Warning HP_OCF Flag Threshold] Dropout Voltage @ ILOAD = 15 mA ANALOG INPUT (PA1) Current Source PA1 CSSEL1 = 1, CSSEL0 = 1 Selectable Scaling Factor Current Source PA1 (I(N) = ICSPA1* N) CSSEL1 = 0, CSSEL0 = 0 CSSEL1 = 0, CSSEL0 = 1 CSSEL1 = 1, CSSEL0 = 0 ICSPA1 NCSPA1-0 NCSPA1-1 NCSPA1-2 570 670 770 % 8.5 28.5 58.5 10 30 60 11.5 31.5 61.5 µA IHSCT IHSCH 6.9 – – – – 8.8 0.88 90 3.0 0.5 11 – – – – mA V V Symbol Min Typ Max Unit mA IHL VHPOCT VHPDO 908E625 10 Analog Integrated Circuit Device Data Freescale Semiconductor DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics All characteristics are for the analog chip only. Please refer to the specification for 68HC908EY16 for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic LIN PHYSICAL LAYER Propagation Delay (12), (13) TXD LOW to LIN LOW TXD HIGH to LIN HIGH LIN LOW to RXD LOW LIN HIGH to RXD HIGH TXD Symmetry RXD Symmetry Output Falling Edge Slew Rate (12), (14) 80% to 20% Output Rising Edge Slew Rate (12), (14) 20% to 80%, RBUS > 1.0 kΩ, CBUS < 10 nF LIN Rise/Fall Slew Rate Symmetry (12), (14) HALL-EFFECT SENSOR INPUTS (H1:H3) Propagation Delay AUTONOMOUS WATCHDOG (AWD) AWD Oscillator Period AWD Period Low = 512 t OSC AWD Period High = 256 t OSC AWD Cyclic Wake-Up On Time t OSC t AWDPH t AWDPL t AWDHPON – 16 8.0 – 40 22 11 90 – 28 14 – µs ms ms µs t HPPD – 1.0 – µs SRS SRR 1.0 -2.0 2.0 – 3.0 2.0 µs µs t TXD-LIN-low t TXD-LIN-high t LIN-RXD-low t LIN-RXDhigh Symbol Min Typ Max Unit t TXD-SYM t RXD-SYM SRF – – – – -2.0 -2.0 – – 4.0 4.0 – – 6.0 6.0 8.0 8.0 2.0 2.0 V/µs -1.0 -2.0 -3.0 V/µs Notes 12. All LIN characteristics are for initial LIN slew rate selection (20 kBaud) (SRS0:SRS1= 00). 13. See Figure 2. 14. See Figure 3. 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 11 MICROCONTROLLER PARAMETRICS MICROCONTROLLER PARAMETRICS Table 5. Microcontroller Description For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet. Module Core Timer Flash RAM ADC SPI ESCI Description High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Two 16-Bit Timers with Two Channels (TIM A and TIM B) 16 K Bytes 512 Bytes 10-Bit Analog-to-Digital Converter SPI Module Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%) Special Counter for SMARTMOS™ BEMF Output ICG BEMF Counter 908E625 12 Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAMS TIMING DIAGRAMS t TXD-LIN-low t Tx-LIN-low t TXD-LIN-high tTx-LIN-high TXD Tx TXD LIN LIN Recessive State 0.9 VSUP 0.9 VSUP Recessive State 0.6 VSUP VSUP 0.4 VSUP VSUP 0.1 VSUP 0.1 VSUP Dominant State Rx RXD t LIN-RXD-low t LIN-Rx-low t LIN-RXD-high t LIN-Rx-high Figure 4. LIN Timing Description ∆t Fall-time ∆t Rise-time 0.8 VSUP 0.8 VSUP 0.8 VSUP VSUP ∆V Fall ∆V Rise 0.2 VSUP 0.2 VSUP Dominant State 0.2 VSUP 0.2 VSUP SRF = ∆V Fall ∆t Fall-time SRR = ∆V Rise ∆t Rise-time Figure 5. LIN Slew Rate Description 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL PERFORMANCE CURVES ELECTRICAL PERFORMANCE CURVES 1.6 1.4 Forward Voltage (V) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 ILOAD (A) 3.0 3.5 4.0 4.5 5.0 H-Bridge Low Side TJ = 25°C Figure 6. Free Wheel Diode Forward Voltage vs ILOAD 250 200 TA = 125°C 150 100 TA = 25°C 50 0 0 5 10 ILoad (mA) 15 TA = -40°C 20 25 Drop Out Voltage (mV) Figure 7. Dropout Voltage on HVDD vs ILOAD 908E625 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E625 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E625 is well suited to perform complete mirror, door lock, and light-levelling control all via a three-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS™ IC chip. The SMARTMOS™ IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS™ IC configured as half-bridge outputs with one high-side switch. Other ports are also provided; they include Hall-effect sensor input ports, analog input ports, and a selectable HVDD terminal. An internal voltage regulator is provided on the SMARTMOS™ IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 1 for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on Figure 3 for a depiction of the terminal locations on the package. PORT D I/O TERMINALS (PTD0:1) PTD1/TACH1 and PTD0/TACH0/BEMF are specialfunction, bidirectional I/O port terminals that can also be programmed to be timer terminals. In step motor applications the PTD0 terminal should be connected to the BEMF output of the analog die in order to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 terminal is recommended for use as an output terminal for generating the FGEN signal (PWM signal) if required by the application. PORT A I/O TERMINALS (PTA0:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt terminals, KBD0:KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/SS terminal is likewise not accessible. For details refer to the 68HC908EY16 datasheet. PORT E I/O TERMINAL (PTE1) PTE1/RXD and PTE0/TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. PORT B I/O TERMINALS (PTB1, PTB3:7) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6:PTB7 terminals are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT terminal of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2 terminal is not accessible in this device. For details refer to the 68HC908EY16 datasheet. EXTERNAL INTERRUPT TERMINAL (IRQ) The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pull-up resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. PORT C I/O TERMINALS (PTC2:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet. EXTERNAL RESET TERMINAL (RST) A Logic [0] on the RST terminal forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pull-up resistor that is always activated, even when the reset terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION CURRENT LIMITATION FREQUENCY INPUT TERMINAL (FGEN) Input terminal for the half-bridge current limitation and the high-side inrush current limiter PWM frequency. This input is not a real PWM input terminal; it should just supply the period of the PWM. The duty cycle will be generate automatically. Important The recommended FGEN frequency should be in the range of 0.1 kHz to 20 kHz. requirements of the half-bridge driver outputs and high-side output driver, multiple VSUP terminals are provided. All VSUP terminals must be connected to get full chip functionality. POWER GROUND TERMINALS (GND1 AND GND2) GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple terminals are provided. GND1 and GND2 terminals must be connected to get full chip functionality. BACK ELECTROMAGNETIC FORCE OUTPUT TERMINAL (BEMF) This terminal gives the user information about back electromagnetic force (BEMF). This feature is mainly used in step motor applications for detecting a stalled motor. In order to evaluate this signal the terminal must be directly connected to terminal PTD0/TACH0/BEMF. HIGH-SIDE OUTPUT TERMINAL (HS) The HS output terminal is a low RDS(ON) high-side switch. The switch is protected against overtemperature and overcurrent. The output is capable of limiting the inrush current with an automatic PWM generation using the FGEN module. RESET TERMINAL (RST_A) RST_A is the bidirectional reset terminal of the analog die. It is an open drain with pull-up resistor and must be connected to the RST terminal of the MCU. SWITCHABLE VDD OUTPUT TERMINAL (HVDD) The HVDD terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors. The output is short-circuit protected. INTERRUPT TERMINAL (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. It is an open drain with pull-up resistor and must be connected to the IRQ terminal of the MCU. HALL-EFFECT SENSOR INPUT TERMINALS (H1:H3) The Hall-effect sensor input terminals H1:H3 provide inputs for Hall-effect sensors and switches. SLAVE SELECT TERMINAL (SS) This terminal is the SPI Slave Select terminal for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I/O of the microcontroller. + 5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD) The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is intended to supply the embedded microcontroller. Important The VDD terminal should not be used to supply other loads; use the HVDD terminal for this purpose. The VDD, EVDD, VDDA, and VREFH terminals must be connected together. LIN BUS TERMINAL (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. HALF-BRIDGE OUTPUT TERMINALS (HB1:HB4) The 908E625 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1:HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. The HB1:HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low-side MOSFETs. ANALOG INPUT TERMINAL (PA1) This terminal is an analog input port with selectable current source values. VOLTAGE REGULATOR GROUND TERMINAL (VSS) The VSS terminal is the ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VREFL terminals must be connected together. POWER SUPPLY TERMINALS (VSUP1:VSUP3) VSUP1:VSUP3 are device power supply terminals. The nominal input voltage is designed for operation from 12 V systems. Owing to the low ON-resistance and current 908E625 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION LIN TRANSCEIVER OUTPUT TERMINAL (RXD) This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD terminal). VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. ADC REFERENCE TERMINALS (VREFL AND VREFH) VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet. MCU POWER SUPPLY TERMINALS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground terminals. The MCU operates from a single power supply. Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. TEST TERMINAL (FLSVPP) This terminal is for test purposes only. This terminal should be either left open (not connected) or connected to GND. ADC SUPPLY TERMINALS (VDDA AND VSSA) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. EXPOSED PAD TERMINAL The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential. 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTERRUPTS The 908E625 has seven different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled. AUTONOMOUS WATCHDOG INTERRUPT (AWD) Refer to Autonomous Watchdog Autonomous Watchdog (AWD). LIN INTERRUPT If the LINIE bit is set, a falling edge on the LIN terminal will generate an interrupt. During STOP mode this interrupt will initiate a system wake-up. LOW-VOLTAGE INTERRUPT The Low-Voltage Interrupt (LVI) is related to the external supply voltage, VSUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the low-voltage interrupt is enabled, an interrupt will be initiated. With LVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the LVI circuitry is disabled. HALL-EFFECT SENSOR INPUT TERMINAL INTERRUPT If the PHIE bit is set, the enabled Hall-Effect Sensor input terminals H1:H3 can generate an interrupt if a current above the threshold is detected. During STOP mode this interrupt, combined with the cyclic wake-up feature of the AWD, can wake up the system. Refer to terminal Hall-Effect Sensor HIGH-VOLTAGE INTERRUPT The High-Voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High-Voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the HVI circuitry is disabled. Input Terminals (H1:H3). OVERCURRENT INTERRUPT If an overcurrent condition on a half-bridge occurs, the high-side or the HVDD output is detected and the OCIE bit is set and an interrupt generated. SYSTEM WAKE-UP System wake-up can be initiated by any of four events: • A falling edge on the LIN terminal • A wake-up signal from the AWD • A Logic [1] at Hall-effect sensor input terminal during cyclic check via AWD • An LVR condition If one of these wake-up events occurs and the interrupt mask bit for this event is set, the interrupt will wake-up the microcontroller as well as the main voltage regulator (MREG) (Figure 8). HIGH-TEMPERATURE INTERRUPT The High-Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is above the HTI threshold, the HTI flag will be set. If the HighTemperature Interrupt is enabled, an interrupt will be initiated. During STOP mode the HTI circuitry is disabled. 908E625 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES MCU Die From Reset Analog Die Initialize Operate SPI: GS =1 (MREG off) STOP MREG STOP Wait for Action LIN AWD Hallport IRQ Interrupt? Assert IRQ_A SPI: Reason for Interrupt Start MREG Operate MREG = Main Voltage Regulator Figure 8. STOP Mode/Wake-Up Procedure 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES SERIAL SPI INTERFACE The SPI creates the communication link between the microcontroller and the 908E625. The interface consists of four terminals. See Figure 9: • SS —Slave Select • MOSI—Master-Out Slave-In • MISO—Master-In Slave-Out • SPSCK—Serial Clock A complete data transfer via the SPI consists of 2 bytes. The master sends address and data, slave system status, and data of the selected address. SS Read/Write, Address, Parity Data (Register write) P X D7 D6 D5 D4 D3 D2 D1 D0 MOSI R/W A4 A3 A2 A1 A0 System Status Register Data (Register read) S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 MISO S7 S6 S5 S4 S3 S2 SPSCK Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Slave latch register address Slave latch data Figure 9. SPI Protocol selected register prior to write operation, write data is latched in the SMARTMOS™ register on rising edge of During the inactive phase of SS, the new data transfer is SS. prepared. The falling edge on the SS line indicates the start of a new data transfer and puts MISO in the low-impedance mode. The first valid data are moved to MISO with the rising edge of SPSCK. The MISO output changes data on a rising edge of SPSCK. The MOSI input is sampled on a falling edge of SPSCK. The data transfer is only valid if exactly 16 sample clock edges are present in the active phase of SS. After a write operation, the transmitted data is latched into the register by the rising edge of SS. Register read data is internally latched into the SPI at the time when the parity bit is transferred. SS HIGH forces MISO to high impedance. PARITY P The parity bit is equal to 0 if the number of 1 bits is an even number contained within R/ W, A4:A0. If the number of 1 bits is odd, P equals 1. For example, if R/ W = 1, A4:A0 = 00001, then P equals 0. The parity bit is only evaluated during a write operation. BIT X Not used. A4:A0 Contains the address of the desired register. MASTER DATA BYTE Contains data to be written or no valid data during a read operation. R/ W Contains information about a read or a write operation. • If R/ W = 1, the second byte of master contains no valid information, slave just transmits back register data. • If R/ W = 0, the master sends data to be written in the second byte, slave sends concurrently contents of SLAVE STATUS BYTE Contains the contents of the System Status Register ($0c) independent of whether it is a write or read operation or which register was selected. 908E625 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES SLAVE DATA BYTE Contains the contents of selected register. During a write operation it includes the register content prior to a write operation. Table 6. List of Registers Addr Register Name H-Bridge Output (HBOUT) H-Bridge Control (HBCTL) System Control (SYSCTL) Interrupt Mask (IMR) Interrupt Flag (IFR) Reset Mask (RMR) Analog Multiplexer Configuration (ADMUX) Hall-Effect Sensor Input Terminal Control (HACTL) Hall-Effect Sensor Input Terminal Status (HASTAT) AWD Control (AWDCTL) Power Output (POUT) System Status (SYSSTAT) R/W R W R W R W R W R W R W R W R W R W R W R W R W HP_OCF LINCL 0 0 0 0 0 0 0 0 SPI REGISTER OVERVIEW Table 6 summarizes the SPI register addresses and the bit names of each register. Bit 7 HB4_H 6 HB4_L 5 HB3_H 0 4 HB3_L 0 3 HB2_H 0 2 HB2_L 1 HB1_H 0 HB1_L $01 $02 OFC_EN CSA CLS2 0 CLS1 0 CLS0 0 GS $03 PSON SRS1 SRS0 0 0 $04 0 HPIE LINIE HTIE LVIE HVIE OCIE OCF 0 $05 0 HPF 0 LINF 0 HTF 0 LVF 0 HVF 0 0 $06 TTEST 0 HVRE HTRE $07 0 0 0 SS3 0 SS2 SS1 SS0 0 0 $08 H3EN 0 0 0 H3F H2EN H2F H1EN H1F $09 $0a 0 AWDRST CSSEL1 AWDRE AWDIE AWDCC AWDF AWDR $0b CSSEL0 CSEN1 LVF CSEN0 HVF HVDDON HS_ON HTF $0c HVDD_OC HS_OCF F HB_OCF 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS INTERRUPT FLAG REGISTER (IFR) Register Name and Address: IFR - $05 Bits Read Write Reset 7 0 0 6 HPF 0 5 LINF 0 4 HTF 0 3 LVF 0 2 HVF 0 1 OCF 0 0 condition is still present while writing a Logic [1] to HTF, the writing has no effect. Therefore, a high-temperature interrupt cannot be lost due to inadvertent clearing of HTF. Reset clears the HTF bit. Writing a Logic [0] to HTF has no effect. • 1 = High-temperature condition has occurred • 0 = High-temperature condition has not occurred Low-Voltage Flag Bit (LVF) 0 0 Hall-Effect Sensor Input Terminal Flag Bit (HPF) This read/write flag is set depending on RUN/STOP mode. RUN Mode An interrupt will be generated when a state change on any enabled Hall-effect sensor input terminal is detected. Clear HPF by writing a Logic [1] to HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF has no effect. • 1 = State change on the hallflags detected • 0 = No state change on the hallflags detected STOP Mode An interrupt will be generated when AWDCC is set and a current above the threshold is detected on any enabled Halleffect sensor input terminal. Clear HPF by writing a Logic [1] to HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF has no effect. • 1 = One or more of the selected Hall-effect sensor input terminals had been pulled HIGH • 0 = None of the selected Hall-effect sensor input terminals has been pulled HIGH LIN Flag Bit (LINF) This read/write flag is set on the falling edge at the LIN data line. Clear LINF by writing a Logic [1] to LINF. Reset clears the LINF bit. Writing a Logic [0] to LINF has no effect. • 1 = Falling edge on LIN data line has occurred • 0 = Falling edge on LIN data line has not occurred since last clear High-Temperature Flag Bit (HTF) This read/write flag is set on a high-temperature condition. Clear HTF by writing a Logic [1] to HTF. If a high-temperature This read/write flag is set on a low-voltage condition. Clear LVF by writing a Logic [1] to LVF. If a low-voltage condition is still present while writing a Logic [1] to LVF, the writing has no effect. Therefore, a low-voltage interrupt cannot be lost due to inadvertent clearing of LVF. Reset clears the LVF bit. Writing a Logic [0] to LVF has no effect. • 1 = Low-voltage condition has occurred • 0 = Low-voltage condition has not occurred High-Voltage Flag Bit (HVF) This read/write flag is set on a high-voltage condition. Clear HVF by writing a Logic [1] to HVF. If high-voltage condition is still present while writing a Logic [1] to HVF, the writing has no effect. Therefore, a high-voltage interrupt cannot be lost due to inadvertent clearing of HVF. Reset clears the HVF bit. Writing a Logic [0] to HVF has no effect. • 1 = High-voltage condition has occurred • 0 = High-voltage condition has not occurred Overcurrent Flag Bit (OCF) This read-only flag is set on an overcurrent condition. Reset clears the OCF bit. To clear this flag, write a Logic [1] to the appropriate overcurrent flag in the SYSSTAT Register. See Figure 10,illustrating the three signals triggering the OCF. • 1 = High-current condition has occurred • 0 = High-current condition has not occurred HVDD_OCF HS_OCF HB_OCF OCF Figure 10. Principal Implementation for OCF 908E625 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS INTERRUPT MASK REGISTER (IMR) Register Name and Address: IMR - $04 Bits Read Write Reset 7 0 0 6 5 4 3 LVIE 0 2 1 0 0 High-Temperature Interrupt Enable Bit (HTIE) This read/ write bit enables CPU interrupts by the hightemperature flag, HTF. Reset clears the HTIE bit. • 1 = Interrupt requests from HTF flag enabled • 0 = Interrupt requests from HTF flag disabled Low-Voltage Interrupt Enable Bit (LVIE) 0 HPIE LINIE HTIE 0 0 0 HVIE OCIE 0 0 Hall-Effect Sensor Input Terminal Interrupt Enable Bit (HPIE ) This read/write bit enables CPU interrupts by the Halleffect sensor input terminal flag, HPF. Reset clears the HPIE bit. • 1 = Interrupt requests from HPF flag enabled • 0 = Interrupt requests from HPF flag disabled LIN Line Interrupt Enable Bit (LINIE) This read/write bit enables CPU interrupts by the LIN flag, LINF. Reset clears the LINIE bit. • 1 = Interrupt requests from LINF flag enabled • 0 = Interrupt requests from LINF flag disabled This read/write bit enables CPU interrupts by the lowvoltage flag, LVF. Reset clears the LVIE bit. • 1 = Interrupt requests from LVF flag enabled • 0 = Interrupt requests from LVF flag disabled High-Voltage Interrupt Enable Bit (HVIE) This read/write bit enables CPU interrupts by the highvoltage flag, HVF. Reset clears the HVIE bit. • 1 = Interrupt requests from HVF flag enabled • 0 = Interrupt requests from HVF flag disabled Overcurrent Interrupt Enable Bit (OCIE) This read/write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit. • 1 = Interrupt requests from OCF flag enabled • 0 = Interrupt requests from OCF flag disabled 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS RESET The 908E625 chip has four internal reset sources and one external reset source, as explained in the paragraphs below. Figure 11 depicts the internal reset sources. High-Temperature Reset To prevent damage to the device, a reset will be initiated if the temperature rises above a certain value. The reset is maskable with bit HTRE in the Reset Mask Register. After a reset the high-temperature reset is disabled. Low-Voltage Reset The LVR is related to the internal VDD. In case the voltage falls below a certain threshold, it will pull down the RST_A terminal. RESET INTERNAL SOURCES Autonomous Watchdog AWD modules generates a reset because of a timeout (watchdog function). SPI REGISTERS AWDRE Flag AWD Reset Sensor HVRE Flag High-Voltage Reset Sensor VDD HTRE Flag RST_A High-Temperature Reset Sensor MONO FLOP Low-Voltage Reset Figure 11. Internal Reset Routing High-Voltage Reset The HVR is related to the external VSUP voltage. In case the voltage is above a certain threshold, it will pull down the RST_A terminal. The reset is maskable with bit HVRE in the Reset Mask Register. After a reset the high-voltage reset is disabled. 908E625 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS RESET EXTERNAL SOURCE External Reset Terminal The microcontroller has the capability of resetting the SMARTMOS™ device by pulling down the RST terminal. • 1 = Low-temperature threshold enabled • 0 = Low-temperature threshold disabled High-Voltage Reset Enable Bit (HVRE) This read/write bit enables resets on high-voltage conditions. Reset clears the HVRE bit. • 1 = High-voltage reset enabled • 0 = High-voltage reset disabled 0 RESET MASK REGISTER (RMR) Register Name and Address: RMR - $06 Bits Read Write Reset 7 TTEST 0 6 0 5 0 4 0 3 0 2 0 1 High-Temperature Reset Enable Bit (HTRE) This read/write bit enables resets on high-temperature conditions. Reset clears the HTRE bit. • 1 = High-temperature reset enabled • 0 = High-temperature reset disabled HVRE HTRE 0 0 0 0 0 0 0 High-Temperature Reset Test (TTEST ) This read/write bit is for test purposes only. It decreases the overtemperature shutdown limit for final test. Reset clears the HTRE bit. 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS ANALOG DIE I/OS LIN Physical Layer The LIN bus terminal provides a physical layer for singlewire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The LIN terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set. Due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately. Analog Multiplexer/ADOUT Terminal The ADOUT terminal is the analog output interface to the ADC of the MCU. See Figure 12. An analog multiplexer is used to read seven internal diagnostic analog voltages. Current Recopy The analog multiplexer is connected to the four low-side current sense circuits of the half-bridges. These sense circuits offer a voltage proportional to the current through the low-side MOSFET. High or low resolution is selectable: 5.0 V/2.5 A or 5.0 V/500 mA, respectively. Refer to HalfBridge Current Recopy.) Analog Input PA1 The analog input PA1 is directly connected to the analog multiplexer, permitting analog values from the periphery to be read. TEMPERATURE SENSOR The 908E625 includes an on-chip temperature sensor. This sensor offers a voltage that is proportional to the actual chip junction temperature. VSUP PRESCALER The VSUP prescaler permits the reading or measurement of the external supply voltage. The output of this voltage is VSUP /RATIOVSUP. The different internal diagnostic analog voltages can be selected with the ADMUX Register. TXD TERMINAL The TXD terminal is the MCU interface to control the state of the LIN transmitter (see Figure 1). When TXD is LOW, LIN output is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off. The TXD terminal has an internal pull-up current source in order to set the LIN bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. ANALOG MULTIPLEXER CONFIGURATION REGISTER (ADMUX) Register Name and Address: ADMUX - $07 Bits Read Write Reset 0 0 0 0 7 0 6 0 5 0 4 0 3 SS3 0 2 SS2 0 1 SS1 0 0 SS0 0 RXD TERMINAL The RXD transceiver terminal is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. STOP MODE/WAKE-UP FEATURE During STOP mode operation the transmitter of the physical layer is disabled. The receiver terminal is still active and able to detect wake-up events on the LIN bus line. If LIN interrupt is enabled (LINIE bit in the Interrupt Mask Register is set), a falling edge on the LIN line causes an interrupt. This interrupt switches on the main voltage regulator and generates a system wake-up. SS3, SS2, SS1, and SS0—A/D Input Select Bits These read/write bits select the input to the ADC in the microcontroller according to Table 7. Reset clears SS3, SS2, SS1, and SS0 bits. 908E625 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS ANALOG INPUT PA1 Table 7. Analog Multiplexer Configuration Register SS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Not Used Channel Current Recopy HB1 Current Recopy HB2 Current Recopy HB3 Current Recopy HB4 VSUP Prescaler Temperature Sensor Not Used PA1 Terminal The Analog input PA1 terminal provides an input for reading analog signals and is internally connected to the analog multiplexer. It can be used for reading switches, potentiometers or resistor values, etc. ANALOG INPUT PA1 CURRENT SOURCE The analog input PA1 has an additional selectable current source. It enables the reading of switches, NTC, etc., without the need of an additional supply line for the sensor illustrated in Figure 12. With this feature it is also possible to read multiple switches on one input. Current source is enabled if the PSON bit in the System Control Register (SYSCTL) and the CSEN bit in the Power Output Register (POUT) is set. Four different current source values can be selected with the CSSELx bits shown in Table 8. This function ceases during STOP mode operation. Table 8. PA1 Current Source Level Selection Bits CSSEL1 CSSEL0 0 0 1 1 0 1 0 1 Current Source Enable (typ.) 10% 30% 60% 100% Source Selection Bits SSx 3 Selectable Current Source VDD CSSEL PSON ADOUT Analog Multiplexer CSEN PA1 Analog Input PA1 NTC Figure 12. Analog Input PA1 and Multiplexer 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS POWER OUTPUT REGISTER (POUT) Register Name and Address: POUT - $0b Bits Read Write Reset 0 0 0 0 0 0 0 0 7 0 6 0 CSSEL1 CSSEL0 CSEN Lamp Driver On Bit (HS_ON) This read/write bit enables the Lamp driver. Reset clears the HS_ON bit. • 1 = Lamp driver enabled • 0 = Lamp driver disabled 5 4 3 2 0(15) 1 0 HVDDON HS_ON Hall-Effect Sensor Input Terminals (H1:H3) Function The Hall-effect sensor input terminals provide three inputs for two-terminal Hall-effect sensors for detecting stall and position or reading Hall-effect sensor contact switches. The Hall-effect sensor input terminals are not influenced by the PSON bit in the System Control Register. Each terminal of the Hall-effect sensor can be enabled by setting the HxEN bit in the Hall-Effect Sensor Input Terminal Control Register (HACTL). If the terminals are enabled, the Hall-effect sensors are supplied with VSUP voltage and the sense circuitry is working. An internal clamp circuity limits the supply voltage to the sensor to 15 V. This sense circuitry monitors the current to VSS. The result of this sense operation is given by the HxF flags in the Hall-Effect Sensor Input Terminal Status Register (HASTAT). The flag is set if the sensed current is higher than IHSCT. To prevent noise on this flag, a hysteresis is implemented on these terminals. After switching on the Hall-effect sensor input terminals (HxEN = 1), the Hall-effect sensors need some time to stabilize the output. In RUN mode the software must wait at least 40 µs between enabling the Hall-effect sensor and reading the hall flag. The Hall-effect sensor input terminal works in an dynamic output voltage range from VSUP down to 2.0 V. Below 2.0 V the hallflags are not functional anymore. If the output voltage is below a certain threshold, the Hall-Effect Sensor Input Terminal Overcurrent Flag (HP_OCF) in the System Status Register is set. Figures 13 through 15 illustrate the connections to the Hall-effect input sensors. Notes 15. This bit must always be set to 0. Current Source Select Bits (CSSEL0:CSSEL1) These read/write bits select the current source values. Reset clears the CSSEL0:CSSEL1 bits. Current Source Enable Bit (CSEN) This read/write bit enables the current source for PA1. Reset clears the CSEN bit (Table 9). Table 9. PA1 Current Source Enable Bit CSEN 0 1 Current Source Enable Current Source Off Current Source On HVDD On Bit (HVDDON) This read/write bit enables HVDD output. Reset clears the HVDDON bit. • 1 = HVDD enabled • 0 = HVDD disabled 908E625 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS HxEN Sense Circuitry Hx Two-Terminal Hall-Effect Sensor HxF V GND Figure 13. Hall-Effect Sensor Input Terminal Connected to Two-Terminal Hall-Effect Sensor HxEN Sense Circuitry Hx Rv HxF V GND Figure 14. Hall-Effect Sensor Input Terminal Connected to Local Switch 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Three-Terminal Hall-Effect Sensor Vs HxEN Sense Circuitry Hx Out HxF V GND GND Figure 15. Hall-Effect Sensor Input Terminal Connected to Three-Terminal Hall-Effect Sensor CYCLIC WAKE-UP Interrupts The Hall-effect sensor input terminals are interrupt capable. How and when an interrupt occurs is dependent on the operating mode, RUN or Stop. RUN Mode In RUN mode the Hall-effect sensor input terminal interrupt flag (HPF) will be set if a state change on the hallflags (HxF) is detected. The interrupt is maskable with the HPIE bit in the Interrupt Mask Register. Before enabling the interrupt, the flag should be cleared in order to prevent a wrong interrupt. STOP Mode In STOP mode the Hall-effect sensor input terminals are disabled independent of the state of the HxEN flags. The Hall-effect sensor inputs can be used to wake up the system. This wake-up function is provided by the cyclic check wake-up feature of the AWD (Autonomous Watchdog). If the cyclic check wake-up feature is enabled (AWDCC bit is set), the AWD switches on the enabled Hall-effect sensor terminals periodically. To ensure that the Hall-effect sensor current is stabilized after switching on, the inputs are sensed after ~40 µs. If a 1 is detected (IHall sensor > IHSCT) and the interrupt mask bit HPIE is set, an interrupt is performed. This wakes up the MCU and starts the main voltage regulator. The wake-up function via this input is available when all three conditions exist: • The two-terminal Hall-effect sensor input is enabled (HxEN = 1) • The cyclic wake-up of the AWD is enabled (AWDCC = 1); see Figure 16 • The Hall-effect sensor input terminal interrupt is enabled (HPIE = 1) 908E625 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS SPI: AWDCC = 1 GS = 1 SPI Command STOP MREG STOP No AWD Timer Overflow? Yes No IRQ? IRQ_A = 0 Start MREG Switch on Selected Hallport Yes SPI: Reason for Wakeup Wait 40 µs Operate Assert IRQ_A Yes Hallport = 1 No Switch off Selected Hallport MREG = Main Voltage Regulator Figure 16. Hall-Effect Sensor Input Terminal Cyclic Check Wake-Up Feature HALL-EFFECT SENSOR INPUT TERMINAL CONTROL REGISTER (HACTL) Register Name and Address: HACTL - $08 Bits Read Write Reset 0 0 0 0 0 7 0 6 0 5 0 4 0 3 0 2 H3EN 0 1 H2EN 0 0 H1EN 0 • 0 = Hall-effect sensor input terminal Hx disabled HALL-EFFECT SENSOR INPUT TERMINAL STATUS REGISTER (HASTAT) Register Name and Address: HASTAT - $09 Bits Read Write Reset 0 0 0 0 0 0 0 0 7 0 6 0 5 0 4 0 3 0 2 H3F 1 H2F 0 H1F Hall-Effect Sensor Input Terminal Enable Bits (H3EN:H1EN) These read/write bits enable the Hall-effect sensor input terminals. Reset clears the H3EN:H1EN bits. • 1 = Hall-effect sensor input terminal Hx switched on and sensed Hall-Effect Sensor Input Terminal Flag Bits (H3F:H1F) These read-only flag bits reflect the input Hx while the Halleffect sensor input terminal Hx is enabled (HxEN = 1). Reset clears the H3F:H1F bits. 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS • 1 = Hall-effect sensor input terminal current above threshold • 0 = Hall-effect sensor input terminal current below threshold HALF-BRIDGES Outputs HB1:HB4 provide four low-resistive half-bridge output stages. The half-bridges can be used in H-Bridge, high-side, or low-side configurations. Reset clears all bits in the H-Bridge Output Register (HBOUT) owing to the fact that all half-bridge outputs are switched off. HB1:HB4 output features: • Short circuit (overcurrent) protection on high-side and low-side MOSFETs • Current recopy feature (low side MOSFET) • Overtemperature protection • Overvoltage and undervoltage protection • Current limitation feature (low side MOSFET) VSUP On/Off Status High-Side Driver Charge Pump, Overtemperature Protection, Overcurrent Protection Control BEMF HBx On/Off Status Current Limit Low-Side Driver Current Recopy, Current Limitation, Overcurrent Protection GND Figure 17. Half-Bridge Push-Pull Output Driver HALF-BRIDGE CONTROL Each output MOSFET can be controlled individually. The general enable of the circuitry is done by setting PSON in the System Control Register (SYSCTL). HBx_L and HBx_H form one half-bridge. It is not possible to switch on both MOSFETs in one half-bridge at the same time. If both bits are set, the high-side MOSFET has a higher priority. To avoid both MOSFETs (high side and low side) of one half-bridge being on at the same time, a break-before-make circuit exists. Switching the high-side MOSFET on is inhibited as long as the potential between gate and VSS is not below a certain threshold. Switching the low-side MOSFET on is blocked as long as the potential between gate and source of the high-side MOSFET did not fall below a certain threshold. HALF-BRIDGE OUTPUT REGISTER (HBOUT) Register Name and Address: HBOUT - $01 Bits Read Write Reset 7 6 5 4 3 2 1 0 HB4_ HB4_ HB3_ HB3_ HB2_ HB2_ HB1_ HB1_ H L H L H L H L 0 0 0 0 0 0 0 0 Low-Side On/Off Bits (HBx_L) These read/write bits turn on the low-side MOSFETs. Reset clears the HBx_L bits. 908E625 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS • 1 = Low-side MOSFET turned on for half-bridge output x • 0 = Low-side MOSFET turned off for half-bridge output x High-Side On/Off Bits (HBx_H) These read/write bits turn on the high-side MOSFETs. Reset clears the HBx_H bits. • 1 = High-side MOSFET turned on for half-bridge output x • 0 = High-side MOSFET turned on for half-bridge output x modulation on the low-side MOSFET. The pulse width modulation on the outputs is controlled by the FGEN input and the load characteristics. The FGEN input provides the PWM frequency, whereas the duty cycle is controlled by the load characteristics. The recommended frequency range for the FGEN and the PWM is 0.1 kHz to 20 kHz. Functionality Each low-side MOSFET switches off if a current above the selected current limit was detected. The 908E625 offers five different current limits. Refer to Table 10 for current limit values. The low-side MOSFET switches on again if a rising edge on the FGEN input was detected (Figure 18). HALF-BRIDGE CURRENT LIMITATION Each low-side MOSFET offers a current limit or constant current feature. This features is realized by a pulse width Coil Current H-Bridge low-side MOSFET will be switched off if select current limit is reached. H-Bridge low-side MOSFET will be turned on with each rising edge of the FGEN input. t Half-Bridge Low-Side Output t FGEN Input (MCU PWM Signal) t Minimum 50 µs Figure 18. Half-Bridge Current Limitation 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS OFFSET CHOPPING If bit OFC_EN in the H-Bridge Control Register (HBCTL) is set, HB1 and HB2 will continue to switch on the low-side MOSFETs with the rising edge of the FGEN signal and HB3 and HB4 will switch on the low-side MOSFETs with the falling Coil1 Current edge on the FGEN input. In step motor applications this feature allows the reduction of EMI due to a reduction of the di/dt (Figure 19). Coil2 Current FGEN Input (MCU PWM Signal) HB1 HB2 HB3 HB4 Coil1….. Coil2….. Current in VSUP Line Figure 19. Offset Chopping for Step Motor Control HALF-BRIDGE CURRENT RECOPY Each low-side MOSFET has an additional sense output to allow a current recopy feature. This sense source is internally connected to a shunt resistor. The drop voltage is amplified and switched to the analog multiplexer. The factor for the current sense amplification can be selected via bit CSA in the System Control Register. • CSA = 1: Low resolution selected (500 mA measurement range) • CSA = 0: High resolution selected (2.5 A measurement range) HALF-BRIDGE BEMF GENERATION The BEMF output is set to 1 if a recirculation current is detected in any half-bridge. This recirculation current flows via the two freewheeling diodes of the power MOSFETs. The BEMF circuitry detects that and generates a HIGH on the BEMF output as long as a recirculation current is detected. This signal provides a flexible and reliable detection of stall in step motor applications. For this the BEMF circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. In addition the signal can be used for open load detection (absence of this signal), see Figure 20. 908E625 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Coil Current Voltage on 1 1 BEMF Signal Figure 20. BEMF Signal Generation HALF-BRIDGE OVERTEMPERATURE PROTECTION The half-bridge outputs provide an overtemperature prewarning with the HTF in the Interrupt Flag Register (IFR). In order to protect the outputs against overtemperature, the High-Temperature Reset must be enabled. If this value is reached, the part generates a reset and disables all power outputs. done by the low- and high-voltage interrupt circuitry. If one of these flags (LVF, HVF) is set, the outputs are automatically disabled. The overvoltage/undervoltage status flags are cleared (and the outputs re-enabled) by writing a Logic [1] to the LVF/ HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high- or low-voltage condition is present. HALF-BRIDGE OVERCURRENT PROTECTION The half-bridges are protected against short to GND, short to VSUP, and load shorts. In the event an overcurrent on the high side is detected, the high-side MOSFETs on all HB high-side MOSFETs are switched off automatically. In the event an overcurrent on the low side is detected, all HB low-side MOSFETs are switched off automatically. In both cases the overcurrent status flag HB_OCF in the System Status Register (SYSSTAT) is set. The overcurrent status flag is cleared (and the outputs reenabled) by writing a Logic [1] to the HB_OCF flag in the System Status Register or by reset. HALF-BRIDGE CONTROL REGISTER (HBCTL) Register Name and Address: HBCTL - $02 Bits Read Write Reset 7 OFC_EN 0 6 CSA 0 5 0 4 0 3 0 2 CLS2 1 CLS1 0 0 CLS0 0 0 0 0 0 H-Bridge Offset Chopping Enable Bit (OFC_EN) This read/write bit enables offset chopping. Reset clears the OFC_EN bit. • 1 = Offset chopping enabled • 0 = Offset chopping disabled HALF-BRIDGE OVERVOLTAGE/UNDERVOLTAGE The half-bridge outputs are protected against undervoltage and overvoltage conditions. This protection is 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS H-Bridges Current Sense Amplification Select Bit (CSA) This read/write bit selects the current sense amplification of the H-Bridges. Reset clears the CSA bit. • 1 = Current sense amplification set for measuring 0.5 A. • 0 = Current sense amplification set for measuring 2.5 A. H-Bridge Current Limitation Selection Bits (CLS2:CLS0) These read/write bits select the current limitation value according to Table 10. Reset clears the CLS2:CLS0 bits. Table 10. H-Bridge Current Limitation Value Selection Bits CLS2 0 0 0 0 1 1 1 1 CLS1 0 0 1 1 0 0 1 1 CLS0 0 1 0 1 0 1 0 1 55 mA (typ) 260 mA (typ) 370 mA (typ) 550 mA (typ) 740 mA (typ) No Limit Current Limit HIGH-SIDE DRIVER The high-side output is a low-resistive high-side switch targeted for driving lamps. The high side is protected against overtemperature. To limit the high inrush current of bulbs, overcurrent protection circuitry is used to limit the current. The output is enabled with bit PSON in the System Control Register and can be switched on/off with bit HS_ON in the Power Output Register. Figure 21 depicts the high-side switch circuitry and connection to external lamp. HIGH-SIDE OVERVOLTAGE/UNDERVOLTAGE PROTECTION The high-side output terminal, HS, is protected against undervoltage/overvoltage conditions. This protection is done by the low- and high-voltage interrupt circuitry. If one of these flags (LVF, HVF) is set, the output is disabled. The overvoltage/undervoltage status flags are cleared and the output re-enabled by writing a Logic [1] to the LVF/ HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high- or low-voltage condition is present. VSUP On/Off Status Current Limit High-Side Driver Charge Pump, Overcurrent Protection, Inrush Current Limiter HS Control Figure 21. High-Side Circuitry 908E625 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS HIGH-SIDE OVERTEMPERATURE PROTECTION The high-side output provides an overtemperature prewarning with the HTF in the Interrupt Flag Register. In order to protect the output against overtemperature, the HighTemperature Reset must be enabled. If this value is reached, the part generates a reset and disables all power outputs. HIGH-SIDE OVERCURRENT PROTECTION The high-side output is protected against overcurrent. In the event overcurrent limit is or was reached, the output automatically switches off and the overcurrent flag is set. Due to the high inrush current of bulbs, a special feature of the 908E625 prevents an overcurrent shutdown during this HS Current HS Overcurrent Shutdown Threshold inrush. If an PWM frequency is supplied to the FGEN output during the switching on of a bulb, the inrush current is limited to the overcurrent shutdown limit. This means if the current reaches the overcurrent shutdown, the high side will be switched off, but each rising edge on the FGEN input will enable the driver again. To distinguish between a shutdown due to an inrush current or a real shutdown, the software must check if the overcurrent status flag (HS_OCF) in the System Status Register is set beyond a certain period of time. The overcurrent status flag is cleared by writing a Logic [1] to the HS_OCF in the System Status Register, see Figure 22. t FGEN Input (MCU PWM Signal) t Figure 22. Inrush Current Limiter on High-Side Output SWITCHABLE VDD OUTPUT (HVDD) The HVDD terminal is a switchable VDD output terminal. It can be used for driving external circuitry that requires a VDD voltage. The output is enabled with bit PSON in the System Control Register and can be switched on/off with bit HVDDON in the Power Output Register. Low- or high-voltage conditions (LVI/HVI) have no influence on this circuitry. HVDD OVERTEMPERATURE PROTECTION Overtemperature protection is enabled if the hightemperature reset is enabled. HVDD OVERCURRENT PROTECTION The HVDD output is protected against overcurrent. In the event the overcurrent limit is or was reached, the output automatically switches off and the HVDD overcurrent flag in the System Status Register is set. 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS SYSTEM CONTROL REGISTER (SYSCTL) Register Name and Address: SYSCTL - $03 Bits Read Write Reset 7 PSON 0 6 SRS1 0 5 SRS0 0 4 0 3 0 2 0 1 0 0 0 GS flag. Reset clears the HP_OCF bit. Writing a Logic [0] to HP_OCF has no effect. • 1 = Overcurrent condition on Hall-effect sensor input terminal has occurred • 0 = No overcurrent condition on Hall-effect sensor input terminal has occurred LIN Current Limitation Bit (LINCL) This read-only bit is set if the LIN transmitter operates in current limitation region. Due to excessive power dissipation in the transmitter, software is advised to turn the transmitter off immediately. • 1 = Transmitter operating in current limitation region • 0 = Transmitter not operating in current limitation region HVDD Output Overcurrent Flag Bit (HVDD_OCF) This read/write flag is set on an overcurrent condition at the HVDD terminal. Clear HVDD_OCF and enable the output by writing a Logic [1] to the HVDD_OCF Flag. Reset clears the HVDD_OCF bit. Writing a Logic [0] to HVDD_OCF has no effect. • 1 = Overcurrent condition on HVDD has occurred • 0 = No overcurrent condition on HVDD has occurred High-Side Overcurrent Flag Bit (HS_OCF) This read/write flag is set on an overcurrent condition at the high-side driver. Clear HS_OCF and enable the high-side driver by writing a Logic [1] to HS_OCF. Reset clears the HS_OCF bit. Writing a Logic [0] to HS_OCF has no effect. • 1 = Overcurrent condition on high-side drivers has occurred • 0 = No overcurrent condition on high-side drivers has occurred Low-Voltage Bit (LVF) This read only bit is a copy of the LVF bit in the Interrupt Flag Register. • 1 = Low-voltage condition has occurred • 0 = No low-voltage condition has occurred High-Voltage Sensor Bit (HVF) This read-only bit is a copy of the HVF bit in the Interrupt Flag Register. • 1 = High-voltage condition has occurred • 0 = No high-voltage condition has occurred H-Bridge Overcurrent Flag Bit (HB_OCF) 0 0 0 0 0 Power Stages On Bit (PSON) This read/write bit enables the power stages (half-bridges, high side, LIN transmitter, Analog Input PA1 current sources, and HVDD output). Reset clears the PSON bit. • 1 = Power stages enabled. • 0 = Power stages disabled. LIN Slew Rate Selection Bits (SRS0:SRS1) These read/write bits enable the user to select the appropriate LIN slew rate for different baud rate configurations as shown in Table 11. The high speed slew rates are used, for example, for programming via the LIN and are not intended for use in the application. Table 11. LIN Slew Rate Selection Bits SRS1 0 0 1 1 SRS0 0 1 0 1 LIN Slew Rate Initial Slew Rate (20 kBaud) Slow Slew Rate (10 kBaud) High Speed II (8x) High Speed I (4x) Go to STOP Mode Bit (GS) This write-only bit instructs the 908E625 to power down and go into STOP mode. Reset or CPU interrupt requests clear the GS bit. • 1 = Power down and go into STOP mode • 0 = Not in STOP mode SYSTEM STATUS REGISTER (SYSSTAT) Register Name and Address: SYSSTAT - $0c Bits Read Write Reset 7 HP_ OCF 0 6 LINCL 5 HVDD _OCF 0 4 HS_ OCF 0 3 LVF 2 HVF 1 HB_ OCF 0 0 HTF 0 0 0 0 Hall-Effect Sensor Input Terminal Overcurrent Flag Bit (HP_OCF) This read/write flag is set on an overcurrent condition at one of the Hall-effect sensor input terminals. Clear HP_OCF and enable the output by writing a Logic [1] to the HP_OCF 908E625 This read / write flag is set on an overcurrent condition at the H-Bridges. Clear HB_OCF and enable the H-Bridge driver by writing a Logic [1] to HB_OCF. Reset clears the HB_OCF bit. Writing a Logic [0] to HB_OCF has no effect. • 1 = Overcurrent condition on H-Bridges has occurred • 0 = No overcurrent condition on H-Bridges has occurred 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Overtemperature Status Bit (HTF) This read-only bit is a copy of the HTF bit in the Interrupt Flag Register. • 1 = Overtemperature condition has occurred • 0 = No overtemperature condition has occurred AUTONOMOUS WATCHDOG CONTROL REGISTER (AWDCTL) Register Name and Address: AWDCTL - $0a Bits Read Write Reset 0 0 7 0 6 0 5 0 AWDRS T 4 AWDR E 3 AWDI E 2 AWDC C 1 AWDF 0 AWD R AUTONOMOUS WATCHDOG (AWD) The Autonomous Watchdog module consists of three functions: • Watchdog function for the CPU in RUN mode • Periodic interrupt function in STOP mode • Cyclic wake-up function in STOP mode The AWD is enabled if AWDIE, AWDRE, or AWDCC in the AWDCTL Register is set. If these bits are cleared, the AWD oscillator is disabled and the watchdog switched off. 0 0 0 0 0 0 Autonomous Watchdog Reset Bit (AWDRST) This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit. • 1 = Reset AWD and restart timeout period • 0 = No effect Autonomous Watchdog Reset Enable Bit (AWDRE) This read/write bit enables resets on AWD time-outs. A reset on the RST_A is only asserted when the device is in RUN mode. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit. • 1 = Autonomous watchdog enabled • 0 = Autonomous watchdog disabled Autonomous Watchdog Interrupt Enable Bit (AWDIE) This read/write bit enables CPU interrupts by the Autonomous Watchdog timeout flag, AWFD. IRQ_A is only asserted when the device is in STOP mode. Reset clears the AWDIE bit. • 1 = CPU interrupt requests from AWDF enabled • 0 = CPU interrupt requests from AWDF disabled Autonomous Watchdog Cyclic Check (AWDCC) This read/write bit enables the cyclic check of the twoterminal Hall-effect sensor and the analog inputs. Reset clears the AWDCC bit. • 1 = Cyclic check of the Hall-effect sensor and analog port • 0 = No cyclic check of the Hall-effect sensor and analog port Autonomous Watchdog Timeout Flag Bit (AWDF) This read/write flag is set when the Autonomous Watchdog has timed out. Clear AWDF by writing a Logic [1] to AWDF. Clearing AWDF also resets the AWD counter and starts a new timeout period. Reset clears the AWDF bit. Writing a Logic [0] to AWDF has no effect. • 1 = AWD has timed out • 0 = AWD has not yet timed out WATCHDOG The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software. If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. PERIODIC INTERRUPT Periodic interrupt is only available in STOP mode. It is enabled by setting the AWDIE bit in the AWDCTL Register. If AWDIE is set, the AWD wakes up the system after a fixed period of time. This time period can be selected with bit AWDR in the AWDCTL Register. CYCLIC WAKE-UP The cyclic wake-up feature is only available in STOP mode. If this feature is enabled, the selected Hall-effect sensor input terminals are switched on and sensed. If a “1” is detected on one of these inputs and the interrupt for the Halleffect sensors is enabled, a system wake-up is performed. (Switch on main voltage regulator and assert IRQ_A to the microcontroller). 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION FACTORY TRIMMING AND CALIBRATION Autonomous Watchdog Rate Bit (AWDR) This read/write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit. • 1 = Fast rate selected (10 ms) • 0 = Slow rate selected (20 ms) device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. RUN Mode During RUN mode the main voltage regulator is on. It provides a regulated supply to all digital sections. STOP Mode During STOP mode the STOP mode regulator supplies a regulated output voltage. The STOP mode regulator has a very limited output current capability. The output voltage will be lower than the output voltage of the main voltage regulator. VOLTAGE REGULATOR The 908E625 chip contains a low-power, low-drop voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E625, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the empty (0xFF) state: • 0xFD80:0xFDDF Trim and Calibration Values • 0xFFFE:0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values Below the usage of the trim values located in the flash memory is explained Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate this dependancies a ICG trim values is located at adress $FDC2. After trimming the ICG is a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) VDD = 5V, TAmbient~25°C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG this values has to be copied to the ICG Trim Register ICGTR at adress $38 of the MCU. Important The value has to copied after every reset. 908E625 40 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E625 has the MC68HC908EY16 MCU embedded typically all the development tools available for the MCU also apply for this device, however due to the fact of the additional analog die circuitry and the nominal +12V supply voltage some additional items have to be considered: • nominal 12V rather than 5V or 3V supply • high voltage VTST might be applied not only to IRQ terminal, but IRQ_A terminal For a detailed information on the MCU related development support see the MC68HC908EY16 datasheet section development support. The programming is principially possible at two stages in the manufacturing process - first on chip level, before the IC is soldered onto a pcb board and second after the IC is soldered onto the pcb board. Chip level programming On Chip level the easiest way is to only power the MCU with +5V (see Figure 23) and not to provide the analog chip with VSUP, in this setup all the analog terminal should be left open (e.g. VSUP[1:3]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well descripted in the MC68HC908EY16 datasheet - section development support. VSUP[1:3] GND[1:2] VDD VSS +5V VREFH VDDA RST EVDD RST_A +5V 1 1µF + 3 4 1µF + 5 C2C1C2+ GND V+ 15 2 6 1µF 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 5 R2OUT 9 2 1 3 6 4 5 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 9.8304MHz CLOCK +5V + CLK PTC4/OSC1 PTB4/AD4 10k 10k +5V C1+ VCC 16 + 1µF 1µF VTST IRQ IRQ_A VREFL 100nF 4.7µF MM908E625 VSSA EVSS MAX232 V- RS232 DB-9 2 Figure 23. Normal Monitor Mode Circuit (MCU only) Of course its also possible to supply the whole system with Vsup (12V) instead as descibted in Figure 24, page 42. PCB level programming If the IC is soldered onto the pcb board its typically not possible to seperately power the MCU with +5V, the whole 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 41 TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION system has to be powered up providing VSUP (see Figure 24). VDD VSUP 47µF + 100nF VSUP[1:3] GND[1:2] VDD VSS VREFH VDDA RST EVDD RST_A VDD 1 1µF + 3 4 1µF + 5 C2C1C2+ GND V+ 15 2 6 1µF 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 5 R2OUT 9 2 1 3 6 4 5 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 9.8304MHz CLOCK VDD + CLK PTC4/OSC1 PTB4/AD4 10k 10k VDD C1+ VCC 16 + 1µF 1µF VTST IRQ IRQ_A VREFL 100nF 4.7µF MM908E625 VSSA EVSS MAX232 V- RS232 DB-9 2 Figure 24. Normal Monitor Mode Circuit Table 12 summarizes the possible configurations and the necessary setups. Table 12. Monitor Mode Signal Requirements and Options Reset Vector Serial Communication PTA0 Mode IRQ RST Mode Selection PTB3 0 ICG COP PTA1 0 PTB4 1 OFF OFF disabled disabled disabled Communication Speed Normal Request Baud Bus Timeout External Clock Frequency Rate disabled disabled disabled 9.8304 MHz 9.8304 MHz — 2.4576 MHz 2.4576 MHz Nominal 1.6MHz Nominal 1.6MHz 9600 9600 Nominal 6300 Nominal 6300 Normal Monitor VTST VDD VDD X 1 Forced Monitor VDD GND $FFFF (blank) 1 0 X X ON User VDD VDD not $FFFF (not blank) X X X X ON enabled enabled — Notes 1. PTA0 must have a pullup resistor to VDD in monitor mode 2. 3. 4. 5. External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1 Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256 X = don’t care VTST is a high voltage VDD + 3.5V ≤ VTST ≤ VDD + 4.5V 908E625 42 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION EMC/EMI RECOMMENDATIONS This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be e.g. found on the Freescale website www.freescale.com. VSUP terminals (VSUP1:VSUP3) Its recommended to place a high-quality ceramic decoupling capacitor close to the VSUP terminals to improve EMC/EMI behaviour. LIN terminal For DPI (Direct Power Injection) and ESD (Electro Static Discharge) its recommended to place a high-quality ceramic decoupling capacitor near the LIN terminal. An additional varistor will further increase the immunity against ESD. A ferrit in the LIN line will suppress some of the noise induced. Voltage regulator output terminals (VDD and AGND) Use a high-quality ceramic decoupling capacitor to stabilize the regulated voltage. D1 VSUP C1 + C2 VSUP1 VSUP2 VSUP3 VREFH L1 LIN V1 C5 C3 C4 EVSS VSSA VREFL GND2 LIN EVDD VDDA VDD VSS MCU digital supply terminals (EVDD and EVSS) Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. MCU analog supply terminals (VREFH, VDDA and VREFL, VSSA) To avoid noise on the analog supply terminals its important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via seperate traces and connected to the voltage regulator output. Figure 25 and Figure 26 show the recommendations on schematics and layout level and Table 13 incidates recommended external components and layout considerations. MM908E625 GND1 Figure 25. EMC/EMI recommendations 908E625 Analog Integrated Circuit Device Data Freescale Semiconductor 43 TYPICAL APPLICATIONS FACTORY TRIMMING AND CALIBRATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VDD NC VREFH VDDA EVDD EVSS VSSA VREFL 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS 40 39 38 37 36 LIN NC NC VSUP1 GND1 VSUP2 NC VSUP3 GND2 35 34 33 32 31 30 29 28 908E625 C3 C4 C5 LIN L1 V1 20 21 22 23 24 25 26 27 GND C1 C2 VBAT D1 Figure 26. PCB Layout Recommendations . Table 13. Component Value Recommendation Component D1 C1 C2 C3 Bulk Capacitor 100nF, SMD Ceramic, Low ESR 100nF, SMD Ceramic, Low ESR Close (