K20P144M100SF2

Freescale Semiconductor Data Sheet: Technical Data Document Number: K20P144M100SF2 Rev. 6, 9/2011 Supports the following: MK20DX128ZVLQ10, MK20DX128ZVMD10, MK20DX256ZVLQ10, MK20DX256ZVMD10, MK20DN512ZVLQ10, MK20DN512ZVMD10 K20 Sub-Family Data Sheet K20P144M100SF2 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz • Memories and memory interfaces – Up to 512 KB program flash memory on nonFlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort) – FlexBus external bus interface • Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator • System peripherals – 10 low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 16-channel DMA controller, supporting up to 64 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit • Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip • Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output • Analog modules – Two 16-bit SAR ADCs – Programmable gain amplifier (PGA) (up to x64) integrated into each ADC – Two 12-bit DACs – Three analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference • Timers – Programmable delay block – Eight-channel motor control/general purpose/PWM timer – Two 2-channel quadrature decoder/general purpose timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2010–2011 Freescale Semiconductor, Inc. • Communication interfaces – USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – I2S module K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 2 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts...........................................................................5 1.1 Determining valid orderable parts......................................5 2 Part identification......................................................................5 2.1 Description.........................................................................5 2.2 Format...............................................................................5 2.3 Fields.................................................................................5 2.4 Example............................................................................6 3 Terminology and guidelines......................................................6 3.1 Definition: Operating requirement......................................6 3.2 Definition: Operating behavior...........................................7 3.3 Definition: Attribute............................................................7 3.4 Definition: Rating...............................................................8 3.5 Result of exceeding a rating..............................................8 3.6 Relationship between ratings and operating requirements......................................................................8 3.7 Guidelines for ratings and operating requirements............9 3.8 Definition: Typical value.....................................................9 3.9 Typical value conditions....................................................10 4 Ratings......................................................................................10 4.1 Thermal handling ratings...................................................11 4.2 Moisture handling ratings..................................................11 4.3 ESD handling ratings.........................................................11 4.4 Voltage and current operating ratings...............................11 5 General.....................................................................................12 5.1 AC electrical characteristics..............................................12 5.2 Nonswitching electrical specifications...............................12 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 Voltage and current operating requirements......13 LVD and POR operating requirements...............14 Voltage and current operating behaviors............14 Power mode transition operating behaviors.......15 Power consumption operating behaviors............16 EMC radiated emissions operating behaviors....19 Designing with radiated emissions in mind.........20 Capacitance attributes........................................20 6.8.7 6.8.8 6.8.9 6.8.10 6.8.6 5.4.2 Thermal attributes...............................................22 6 Peripheral operating requirements and behaviors....................23 6.1 Core modules....................................................................23 6.1.1 6.1.2 Debug trace timing specifications.......................23 JTAG electricals..................................................24 6.2 System modules................................................................27 6.3 Clock modules...................................................................27 6.3.1 6.3.2 6.3.3 MCG specifications.............................................27 Oscillator electrical specifications.......................29 32kHz Oscillator Electrical Characteristics.........31 6.4 Memories and memory interfaces.....................................32 6.4.1 6.4.2 6.4.3 Flash (FTFL) electrical specifications.................32 EzPort Switching Specifications.........................34 Flexbus Switching Specifications........................35 6.5 Security and integrity modules..........................................38 6.6 Analog...............................................................................38 6.6.1 6.6.2 6.6.3 6.6.4 ADC electrical specifications..............................38 CMP and 6-bit DAC electrical specifications......46 12-bit DAC electrical characteristics...................49 Voltage reference electrical specifications..........52 6.7 Timers................................................................................53 6.8 Communication interfaces.................................................53 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 USB electrical specifications...............................53 USB DCD electrical specifications......................54 USB VREG electrical specifications...................54 CAN switching specifications..............................55 DSPI switching specifications (limited voltage range).................................................................55 DSPI switching specifications (full voltage range).................................................................56 I2C switching specifications................................58 UART switching specifications............................58 SDHC specifications...........................................58 I2S switching specifications................................59 5.3 Switching specifications.....................................................20 5.3.1 5.3.2 Device clock specifications.................................20 General switching specifications.........................20 6.9 Human-machine interfaces (HMI)......................................61 6.9.1 TSI electrical specifications................................61 7 Dimensions...............................................................................62 7.1 Obtaining package dimensions.........................................62 8 Pinout........................................................................................63 5.4 Thermal specifications.......................................................21 5.4.1 Thermal operating requirements.........................21 K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 3 8.1 K20 Signal Multiplexing and Pin Assignments..................63 8.2 K20 Pinouts.......................................................................69 9 Revision History........................................................................71 K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 4 Freescale Semiconductor, Inc. Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK20 and MK20. 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Q K## A M Qualification status Kinetis family Key attribute Flash memory type Description Values • M = Fully qualified, general market flow • P = Prequalification • K20 • D = Cortex-M4 w/ DSP • F = Cortex-M4 w/ DSP and FPU • N = Program flash only • X = Program flash and FlexMemory Table continues on the next page... K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 5 Terminology and guidelines Field FFF Description Program flash memory size • • • • • • 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB Values R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main • V = –40 to 105 • C = –40 to 85 • • • • • • • • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) EX = 64 LQFN (9 mm x 9 mm) LH = 64 LQFP (10 mm x 10 mm) LK = 80 LQFP (12 mm x 12 mm) MB = 81 MAPBGA (8 mm x 8 mm) LL = 100 LQFP (14 mm x 14 mm) MC = 121 MAPBGA (8 mm x 8 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) MF = 196 MAPBGA (15 mm x 15 mm) MJ = 256 MAPBGA (17 mm x 17 mm) 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz T PP Temperature range (°C) Package identifier CC Maximum CPU frequency (MHz) N Packaging type • R = Tape and reel • (Blank) = Trays 2.4 Example This is an example part number: MK20DN512ZVMD10 3 Terminology and guidelines K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 6 Freescale Semiconductor, Inc. Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply voltage 0.9 Min. 1.1 Max. V Unit 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol IWP Description Digital I/O weak pullup/ 10 pulldown current Min. 130 Max. µA Unit 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 7 Terminology and guidelines 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins — Min. 7 Max. pF Unit 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage –0.3 Min. 1.2 Max. V Unit 3.5 Result of exceeding a rating 40 Failures in time (ppm) 30 20 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 10 0 Operating rating Measured characteristic K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 8 Freescale Semiconductor, Inc. Terminology and guidelines 3.6 Relationship between ratings and operating requirements go a rh nd lin g in rat g( mi n.) ir qu em en t( n. mi ) ir qu em en t( x ma .) r go ha nd lin g in rat g( x.) ma e gr e gr Op era tin Op era tin Op era tin Op era tin Fatal range - Probable permanent failure Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Normal operating range - No permanent failure - Correct operation Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range - Probable permanent failure Handling range - No permanent failure –ȡ ȡ 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 9 Ratings Symbol IWP Description Digital I/O weak pullup/pulldown current 10 Min. 70 Typ. 130 Max. µA Unit 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 3500 IDD_STOP (μA) 3000 2500 2000 1500 1000 500 0 0.90 0.95 1.00 VDD (V) 1.05 1.10 TJ 150 °C 105 °C 25 °C –40 °C 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol TA VDD Description Ambient temperature 3.3 V supply voltage 25 3.3 Value °C V Unit 4 Ratings K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 10 Freescale Semiconductor, Inc. Ratings 4.1 Thermal handling ratings Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Solder temperature, leaded Min. –55 — — Max. 150 260 245 Unit °C °C Notes 1 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. — Max. 3 Unit — Notes 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol VHBM VCDM ILAT Description Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 105°C Min. -2000 -500 -100 Max. +2000 +500 +100 Unit V V mA Notes 1 2 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol VDD IDD VDIO Description Digital supply voltage Digital supply current Digital input voltage (except RESET, EXTAL, and XTAL) Table continues on the next page... Min. –0.3 — –0.3 Max. 3.8 185 5.5 Unit V mA V K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 11 General Symbol VAIO ID VDDA VUSB_DP VUSB_DM VREGIN VBAT Description Analog1, RESET, EXTAL, and XTAL input voltage Min. –0.3 –25 VDD – 0.3 –0.3 –0.3 –0.3 –0.3 Max. VDD + 0.3 25 VDD + 0.3 3.63 3.63 6.0 3.8 Unit V mA V V V V V Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage USB_DP input voltage USB_DM input voltage USB regulator input RTC battery supply voltage 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins • have CL=30pF loads, • are configured for fast slew rate (PORTx_PCRn[SRE]=0), and • are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins • have their passive filter disabled (PORTx_PCRn[PFE]=0) 5.2 Nonswitching electrical specifications K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 12 Freescale Semiconductor, Inc. General 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol VDD VDDA Description Supply voltage Analog supply voltage Min. 1.71 1.71 –0.1 –0.1 1.71 Max. 3.6 3.6 0.1 0.1 3.6 Unit V V V V V Notes VDD – VDDA VDD-to-VDDA differential voltage VSS – VSSA VSS-to-VSSA differential voltage VBAT VIH RTC battery supply voltage Input high voltage • 2.7 V ≤ VDD ≤ 3.6 V • 1.7 V ≤ VDD ≤ 2.7 V VIL Input low voltage • 2.7 V ≤ VDD ≤ 3.6 V • 1.7 V ≤ VDD ≤ 2.7 V VHYS IICDIO Input hysteresis Digital pin negative DC injection current — single pin • VIN < VSS-0.3V IICAIO Analog2, EXTAL, and XTAL pin DC injection current — single pin • VIN < VSS-0.3V (Negative current injection) • VIN > VDD+0.3V (Positive current injection) IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Negative current injection • Positive current injection VRAM VRFVBAT VDD voltage required to retain RAM VBAT voltage required to retain the VBAT register file 0.7 × VDD 0.75 × VDD — — V V — — 0.06 × VDD -5 0.35 × VDD 0.3 × VDD — — V V V 1 mA 3 mA -5 — — +5 -25 — 1.2 VPOR_VBAT — +25 — — mA V V 1. All 5 volt tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances. K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 13 General 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol VPOR VLVDH Description Falling VDD POR detect voltage Falling low-voltage detect threshold — high range (LVDV=01) Low-voltage warning thresholds — high range VLVW1H VLVW2H VLVW3H VLVW4H VHYSH VLVDL • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) • Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis — high range Falling low-voltage detect threshold — low range (LVDV=00) Low-voltage warning thresholds — low range VLVW1L VLVW2L VLVW3L VLVW4L VHYSL VBG tLPO • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) • Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis — low range Bandgap voltage reference Internal low power oscillator period — factory trimmed 1.74 1.84 1.94 2.04 — 0.97 900 1.80 1.90 2.00 2.10 ±60 1.00 1000 1.86 1.96 2.06 2.16 — 1.03 1100 V V V V mV V μs 2.62 2.72 2.82 2.92 — 1.54 2.70 2.80 2.90 3.00 ±80 1.60 2.78 2.88 2.98 3.08 — 1.66 V V V V mV V 1 Min. 0.8 2.48 Typ. 1.1 2.56 Max. 1.5 2.64 Unit V V 1 Notes 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description Min. 0.8 Typ. 1.1 Max. 1.5 Unit V Notes VPOR_VBAT Falling VBAT supply POR detect voltage K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 14 Freescale Semiconductor, Inc. General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Output high voltage — high drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA Output high voltage — low drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA IOHT VOL Output high current total for all ports Output low voltage — high drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA Output low voltage — low drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA IOLT IIN IIN IOZ RPU RPD Output low current total for all ports Input leakage current (per pin) for full temperature range Input leakage current (per pin) at 25°C Hi-Z (off-state) leakage current (per pin) Internal pullup resistors Internal pulldown resistors — — — — — — 20 20 0.5 0.5 100 1 0.025 1 50 50 V V mA μA μA μA kΩ kΩ 2 3 1 1 — — 0.5 0.5 V V VDD – 0.5 VDD – 0.5 — — — 100 V V mA VDD – 0.5 VDD – 0.5 — — V V Min. Max. Unit Notes 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD 5.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSx→RUN recovery times in the following table assume this clock configuration: • • • • CPU and system clocks = 100 MHz Bus clock = 50 MHz FlexBus clock = 50 MHz Flash clock = 25 MHz K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 15 General Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VLLS1 → RUN • VLLS2 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN 1. Normal boot (FTFL_OPT[LPBOOT]=1) Min. — Max. 300 Unit μs Notes 1 — — — — — — 112 74 73 5.9 5.8 4.2 μs μs μs μs μs μs 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Run mode current — all peripheral clocks disabled, code executing from flash • @ 1.8V • @ 3.0V IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash • @ 1.8V • @ 3.0V • @ 25°C • @ 125°C IDD_WAIT IDD_WAIT IDD_VLPR Wait mode high frequency current at 3.0 V — all peripheral clocks disabled Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — — — — — 63 72 35 15 N/A 71 87 — — — mA mA mA mA mA 2 5 6 — 61 85 mA — — 45 47 70 72 mA mA 3, 4 Min. — Typ. — Max. See note Unit mA Notes 1 2 Table continues on the next page... K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 16 Freescale Semiconductor, Inc. General Table 6. Power consumption operating behaviors (continued) Symbol IDD_VLPR IDD_VLPW IDD_STOP Description Very-low-power run mode current at 3.0 V — all peripheral clocks enabled Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled Stop mode current at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C IDD_VLPS Very-low-power stop mode current at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C IDD_LLS Low leakage stop mode current at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C — — — 0.33 0.60 1.97 0.39 0.78 2.9 μA μA μA — — — 2.1 6.2 30 7.6 13.5 46 μA μA μA — — — 2.2 7.1 41 5.4 12.5 125 μA μA μA — — — 3.1 17 82 8.9 35 148 μA μA μA — — — 4.8 28 126 20 68 270 μA μA μA 9 — — — 93 520 1350 435 2000 4000 μA μA μA 9 — — — 0.59 2.26 5.94 1.4 7.9 19.2 mA mA mA Min. — — Typ. N/A N/A Max. — — Unit mA mA Notes 7 8 Table continues on the next page... K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 17 General Table 6. Power consumption operating behaviors (continued) Symbol IDD_VBAT Description Average current when CPU is not accessing RTC registers • @ 1.8V • @ –40 to 25°C • @ 70°C • @ 105°C • @ 3.0V • @ –40 to 25°C • @ 70°C • @ 105°C — — — 0.84 1.17 3.16 0.94 1.5 4.6 μA μA μA — — — 0.71 1.01 2.82 0.81 1.3 4.3 μA μA μA Min. Typ. Max. Unit Notes 10 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode. 6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. For devices with 32 KB of RAM, power consumption is reduced by 3 μA. 10. Includes 32kHz oscillator current and RTC operation. 5.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies • USB regulator disabled • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 18 Freescale Semiconductor, Inc. General Figure 2. Run mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 144LQFP Symbol VRE1 VRE2 VRE3 VRE4 VRE_IEC Description Radiated emissions voltage, band 1 Radiated emissions voltage, band 2 Radiated emissions voltage, band 3 Radiated emissions voltage, band 4 IEC level Frequency band (MHz) 0.15–50 50–150 150–500 500–1000 0.15–1000 Typ. 23 27 28 14 K Unit dBμV dBμV dBμV dBμV — 2, 3 Notes 1, 2 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 19 General 2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to http://www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol CIN_A CIN_D Description Input capacitance: analog pins Input capacitance: digital pins Min. — — Max. 7 7 Unit pF pF 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Normal run mode fSYS fSYS_USB fBUS FB_CLK fFLASH fLPTMR System and core clock System and core clock when Full Speed USB in operation Bus clock FlexBus clock Flash clock LPTMR clock — 20 — — — — 100 — 50 50 25 25 MHz MHz MHz MHz MHz MHz Min. Max. Unit Notes K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 20 Freescale Semiconductor, Inc. General 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CAN, CMT, and I2C signals. Table 10. General switching specifications Symbol Description GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) — Asynchronous path GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) — Asynchronous path External reset pulse width (digital glitch filter disabled) Mode select (EZP_CS) hold time after reset deassertion Port rise and fall time (high drive strength) • Slew disabled • 1.71 ≤ VDD ≤ 2.7V • 2.7 ≤ VDD ≤ 3.6V • Slew enabled • 1.71 ≤ VDD ≤ 2.7V • 2.7 ≤ VDD ≤ 3.6V Port rise and fall time (low drive strength) • Slew disabled • 1.71 ≤ VDD ≤ 2.7V • 2.7 ≤ VDD ≤ 3.6V • Slew enabled • 1.71 ≤ VDD ≤ 2.7V • 2.7 ≤ VDD ≤ 3.6V 1. 2. 3. 4. The greater synchronous and asynchronous timing must be met. This is the shortest pulse that is guaranteed to be recognized. 75pF load 15pF load — — 36 24 ns ns — — 12 6 ns ns — — 36 24 ns ns 4 — — 12 6 ns ns Min. 1.5 100 16 100 2 Max. — — — — — Unit Bus clock cycles ns ns ns Bus clock cycles 3 Notes 1 2 2 2 5.4 Thermal specifications K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 21 General 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol TJ TA Description Die junction temperature Ambient temperature Min. –40 –40 Max. 125 105 Unit °C °C 5.4.2 Thermal attributes Board type Single-layer (1s) Symbol RθJA Description 144 LQFP 48 144 MAPBGA Unit °C/W Notes 1 Thermal 45 resistance, junction to ambient (natural convection) Thermal 36 resistance, junction to ambient (natural convection) Thermal 36 resistance, junction to ambient (200 ft./ min. air speed) Thermal 30 resistance, junction to ambient (200 ft./ min. air speed) Thermal resistance, junction to board Thermal resistance, junction to case 24 Four-layer (2s2p) RθJA 29 °C/W 1 Single-layer (1s) RθJMA 38 °C/W 1 Four-layer (2s2p) RθJMA 25 °C/W 1 — RθJB 16 °C/W 2 — RθJC 9 9 °C/W 3 — ΨJT Thermal 2 characterization parameter, junction to package top outside center (natural convection) 2 °C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 22 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 2. 3. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 4. 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Debug trace timing specifications Table 12. Debug trace operating behaviors Symbol Tcyc Twl Twh Tr Tf Ts Th Description Clock period Low pulse width High pulse width Clock and data rise time Clock and data fall time Data setup Data hold Min. Max. Unit MHz ns ns ns ns ns ns Frequency dependent 2 2 — — 3 2 — — 3 3 — — Figure 3. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 4. Trace data specifications K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 23 Peripheral operating requirements and behaviors 6.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol Description Operating voltage J1 TCLK frequency of operation • Boundary Scan • JTAG and CJTAG • Serial Wire Debug J2 J3 TCLK cycle period TCLK clock pulse width • Boundary Scan • JTAG and CJTAG • Serial Wire Debug J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 TCLK rise and fall times Boundary scan input data setup time to TCLK rise Boundary scan input data hold time after TCLK rise TCLK low to boundary scan output data valid TCLK low to boundary scan output high-Z TMS, TDI input data setup time to TCLK rise TMS, TDI input data hold time after TCLK rise TCLK low to TDO data valid TCLK low to TDO high-Z TRST assert time TRST setup time (negation) to TCLK high 50 20 10 — 20 0 — — 8 1 — — 100 8 — — — 3 — — 25 25 — — 17 17 — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 0 0 1/J1 10 25 50 — ns Min. 2.7 Max. 3.6 Unit V MHz Table 14. JTAG full voltage range electricals Symbol Description Operating voltage J1 TCLK frequency of operation • Boundary Scan • JTAG and CJTAG • Serial Wire Debug J2 TCLK cycle period Table continues on the next page... 0 0 0 1/J1 10 20 40 — ns Min. 1.71 Max. 3.6 Unit V MHz K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 24 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol J3 Description TCLK clock pulse width • Boundary Scan • JTAG and CJTAG • Serial Wire Debug J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 TCLK rise and fall times Boundary scan input data setup time to TCLK rise Boundary scan input data hold time after TCLK rise TCLK low to boundary scan output data valid TCLK low to boundary scan output high-Z TMS, TDI input data setup time to TCLK rise TMS, TDI input data hold time after TCLK rise TCLK low to TDO data valid TCLK low to TDO high-Z TRST assert time TRST setup time (negation) to TCLK high 50 25 12.5 — 20 0 — — 8 1.4 — — 100 8 — — — 3 — — 25 25 — — 22.1 22.1 — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. Unit J2 J3 J3 TCLK (input) J4 J4 Figure 5. Test clock input timing K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 25 Peripheral operating requirements and behaviors TCLK J5 J6 Data inputs J7 Input data valid Data outputs J8 Output data valid Data outputs J7 Data outputs Output data valid Figure 6. Boundary scan (JTAG) timing TCLK J9 J10 TDI/TMS J11 Input data valid TDO J12 Output data valid TDO J11 TDO Output data valid Figure 7. Test Access Port timing K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 26 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 8. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG specifications Table 15. MCG specifications Symbol fints_ft fints_t Iints Δfdco_res_t Description Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C Internal reference frequency (slow clock) — user trimmed Internal reference (slow clock) current Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25°C Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C Internal reference (fast clock) current Loss of external clock minimum frequency — RANGE = 00 Loss of external clock minimum frequency — RANGE = 01, 10, or 11 Min. — 31.25 — — Typ. 32.768 — 20 ± 0.3 Max. — 38.2 — ± 0.6 Unit kHz kHz µA %fdco 1 Notes Δfdco_t — ± 1.5 ± 4.5 %fdco 1 fintf_ft fintf_t Iintf floc_low floc_high — 3 — (3/5) x fints_t (16/5) x fints_t 4 — 25 — — — 5 — — — MHz MHz µA kHz kHz Table continues on the next page... K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 27 Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Description FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 640 × ffll_ref Mid range (DRS=01) 1280 × ffll_ref Mid-high range (DRS=10) 1920 × ffll_ref High range (DRS=11) 2560 × ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS=00) 732 × ffll_ref Mid range (DRS=01) 1464 × ffll_ref Mid-high range (DRS=10) 2197 × ffll_ref High range (DRS=11) 2929 × ffll_ref Jcyc_fll FLL period jitter • fVCO = 48 MHz • fVCO = 98 MHz tfll_acquire FLL target frequency acquisition time PLL fvco Ipll VCO operating frequency PLL operating current • PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) PLL operating current • PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) PLL reference frequency range PLL period jitter (RMS) • fvco = 48 MHz • fvco = 100 MHz — — 120 50 — — ps ps 48.0 — — 1060 100 — MHz µA 7 — — — 180 150 — — — 1 ms 6 ps — 95.98 — MHz — 71.99 — MHz — 47.97 — MHz — 23.99 — MHz 4, 5 80 83.89 100 MHz 60 62.91 75 MHz 40 41.94 50 MHz 31.25 20 — 20.97 39.0625 25 kHz MHz 2, 3 Min. Typ. Max. Unit Notes Ipll — 600 — µA 7 fpll_ref Jcyc_pll 2.0 — 4.0 MHz 8 Table continues on the next page... K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 28 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Jacc_pll Description PLL accumulated jitter over 1µs (RMS) • fvco = 48 MHz • fvco = 100 MHz Dlock Dunl tpll_lock Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time — — ± 1.49 ± 4.47 — 1350 600 — — — — — ± 2.98 ± 5.97 150 × 10-6 + 1075(1/ fpll_ref) ps ps % % s 9 Min. Typ. Max. Unit Notes 8 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. 6.3.2.1 Symbol VDD IDDOSC Oscillator DC electrical specifications Description Supply voltage Supply current — low-power mode (HGO=0) • 32 kHz • 4 MHz • 8 MHz (RANGE=01) • 16 MHz • 24 MHz • 32 MHz — — — — — — Min. 1.71 Table 16. Oscillator DC electrical specifications Typ. — Max. 3.6 Unit V 1 500 200 300 950 1.2 1.5 — — — — — — nA μA μA μA mA mA Notes Table continues on the next page... K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 29 Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol IDDOSC Description Supply current — high gain mode (HGO=1) • 32 kHz • 4 MHz • 8 MHz (RANGE=01) • 16 MHz • 24 MHz • 32 MHz Cx Cy RF EXTAL load capacitance XTAL load capacitance Feedback resistor — low-frequency, low-power mode (HGO=0) Feedback resistor — low-frequency, high-gain mode (HGO=1) Feedback resistor — high-frequency, low-power mode (HGO=0) Feedback resistor — high-frequency, high-gain mode (HGO=1) RS Series resistor — low-frequency, low-power mode (HGO=0) Series resistor — low-frequency, high-gain mode (HGO=1) Series resistor — high-frequency, low-power mode (HGO=0) Series resistor — high-frequency, high-gain mode (HGO=1) — Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) 1. 2. 3. 4. — 0 0.6 — — kΩ V — — — — — — — — — — — — — — — 25 400 500 2.5 3 4 — — — 10 — 1 — 200 — — — — — — — — — — — — — — — — MΩ MΩ MΩ MΩ kΩ kΩ kΩ μA μA μA mA mA mA 2, 3 2, 3 2, 4 Min. Typ. Max. Unit Notes 1 — VDD — V — 0.6 — V — VDD — V VDD=3.3 V, Temperature =25 °C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 30 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Symbol fosc_lo fosc_hi_1 Oscillator frequency specifications Description Oscillator crystal or resonator frequency — low frequency mode (MCG_C2[RANGE]=00) Oscillator crystal or resonator frequency — high frequency mode (low range) (MCG_C2[RANGE]=01) Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) Input clock frequency (external clock mode) Input clock duty cycle (external clock mode) Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) Min. 32 3 Table 17. Oscillator frequency specifications Typ. — — Max. 40 8 Unit kHz MHz Notes fosc_hi_2 8 — 32 MHz fec_extal tdc_extal tcst — 40 — — — — 50 750 250 0.6 50 60 — — — MHz % ms ms ms 1, 2 3, 4 — 1 — ms 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 6.3.3 32kHz Oscillator Electrical Characteristics This section describes the module electrical characteristics. 6.3.3.1 Symbol VBAT RF 32kHz oscillator DC electrical specifications Description Supply voltage Internal feedback resistor Min. 1.71 — Table continues on the next page... Table 18. 32kHz oscillator DC electrical specifications Typ. — 100 Max. 3.6 — Unit V MΩ K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 31 Peripheral operating requirements and behaviors Table 18. 32kHz oscillator DC electrical specifications (continued) Symbol Cpara Cload Vpp1 Description Parasitical capacitance of EXTAL32 and XTAL32 Internal load capacitance (programmable) Peak-to-peak amplitude of oscillation Min. — — — Typ. 5 15 0.6 Max. 7 — — Unit pF pF V 1. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 Symbol fosc_lo tstart 32kHz oscillator frequency specifications Description Oscillator crystal Crystal start-up time Min. — — Table 19. 32kHz oscillator frequency specifications Typ. 32.768 1000 Max. — — Unit kHz ms 1 Notes 1. Proper PC board layout procedures must be followed to achieve specifications. 6.4 Memories and memory interfaces 6.4.1 Flash (FTFL) electrical specifications This section describes the electrical characteristics of the FTFL module. 6.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 20. NVM program/erase timing specifications Symbol thvpgm4 thversscr Description Longword Program high-voltage time Sector Erase high-voltage time Min. — — — Typ. 7.5 13 416 Max. 18 113 3616 Unit μs ms ms 1 1 Notes thversblk256k Erase Block high-voltage time for 256 KB 1. Maximum time based on expectations at cycling end-of-life. K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 32 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.4.1.2 Symbol Flash timing specifications — commands Description Read 1s Block execution time Min. Table 21. Flash command timing specifications Typ. Max. Unit Notes trd1blk256k trd1sec2k tpgmchk trdrsrc tpgm4 • 256 KB program/data flash Read 1s Section execution time (flash sector) Program Check execution time Read Resource execution time Program Longword execution time Erase Flash Block execution time — — — — — — — — — 65 1.7 60 45 30 145 ms μs μs μs μs 2 1 1 1 tersblk256k tersscr • 256 KB program/data flash Erase Flash Sector execution time Program Section execution time — — 435 14 3700 114 ms ms 2 tpgmsec512 tpgmsec1k tpgmsec2k trd1all trdonce tpgmonce tersall tvfykey • 512 B flash • 1 KB flash • 2 KB flash Read 1s All Blocks execution time Read Once execution time Program Once execution time Erase All Blocks execution time Verify Backdoor Access Key execution time Swap Control execution time — — — — — — — — 2.4 4.7 9.3 — — 65 870 — — — — 1.8 25 — 7400 30 ms ms ms ms μs μs ms μs 2 1 1 tswapx01 tswapx02 tswapx04 tswapx08 • control code 0x01 • control code 0x02 • control code 0x04 • control code 0x08 — — — — 200 70 70 — — 150 150 30 μs μs μs μs 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 6.4.1.3 Flash (FTFL) current and power specfications Description Worst case programming current in program flash Table 22. Flash (FTFL) current and power specfications Typ. 10 Unit mA Symbol IDD_PGM K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 33 Peripheral operating requirements and behaviors 6.4.1.4 Symbol Reliability specifications Description Table 23. NVM reliability specifications Min. Program Flash Typ.1 Max. Unit Notes tnvmretp10k tnvmretp1k tnvmretp100 nnvmcycp Data retention after up to 10 K cycles Data retention after up to 1 K cycles Data retention after up to 100 cycles Cycling endurance 5 10 15 10 K 50 100 100 35 K — — — — years years years cycles 2 2 2 3 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. 2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application). 3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 6.4.2 EzPort Switching Specifications Table 24. EzPort switching specifications Num Description Operating voltage EP1 EP1a EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 EZP_CK frequency of operation (all commands except READ) EZP_CK frequency of operation (READ command) EZP_CS negation to next EZP_CS assertion EZP_CS input valid to EZP_CK high (setup) EZP_CK high to EZP_CS input invalid (hold) EZP_D input valid to EZP_CK high (setup) EZP_CK high to EZP_D input invalid (hold) EZP_CK low to EZP_Q output valid EZP_CK low to EZP_Q output invalid (hold) EZP_CS negation to EZP_Q tri-state Min. 1.71 — — 2 x tEZP_CK 5 5 2 5 — 0 — Max. 3.6 fSYS/2 fSYS/8 — — — — — 16 — 12 Unit V MHz MHz ns ns ns ns ns ns ns ns K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 34 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors EZP_CK EP3 EP4 EP2 EZP_CS EP8 EP9 EP7 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 9. EzPort Timing Diagram 6.4.3 Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 25. Flexbus limited voltage range switching specifications Num Description Operating voltage Frequency of operation FB1 FB2 FB3 FB4 FB5 Clock period Address, data, and control output valid Address, data, and control output hold Data and FB_TA input setup Data and FB_TA input hold Min. 2.7 — 20 — 0.5 8.5 0.5 Max. 3.6 FB_CLK — 11.5 — — — Unit V MHz ns ns ns ns ns 1 1 2 2 Notes 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 35 Peripheral operating requirements and behaviors 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 26. Flexbus full voltage range switching specifications Num Description Operating voltage Frequency of operation FB1 FB2 FB3 FB4 FB5 Clock period Address, data, and control output valid Address, data, and control output hold Data and FB_TA input setup Data and FB_TA input hold Min. 1.71 — 1/FB_CLK — 0 13.7 0.5 Max. 3.6 FB_CLK — 13.5 — — — Unit V MHz ns ns ns ns ns 1 1 2 2 Notes 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 36 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB5 FB_A[Y] FB2 Address FB4 Data FB_D[X] FB_RW FB_TS FB_ALE Address AA=1 FB_CSn FB_OEn FB4 AA=0 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 10. FlexBus read timing diagram K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 37 Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 Address FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE Address Data AA=1 FB_CSn FB_OEn FB4 AA=0 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 11. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. 38 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DM3. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 29 and Table 30. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 Symbol VDDA ΔVDDA ΔVSSA VREFH VREFL VADIN CADIN 16-bit ADC operating conditions Description Supply voltage Supply voltage Ground voltage ADC reference voltage high Reference voltage low Input voltage Input capacitance • 16 bit modes • 8/10/12 bit modes Conditions Absolute Delta to VDD (VDDVDDA) Delta to VSS (VSSVSSA) Min. 1.71 -100 -100 1.13 VSSA VREFL — — Table 27. 16-bit ADC operating conditions Typ.1 — 0 0 VDDA VSSA — 8 4 Max. 3.6 +100 +100 VDDA VSSA VREFH 10 5 Unit V mV mV V V V pF 2 2 Notes RADIN RAS Input resistance Analog source resistance 13/12 bit modes fADCK < 4MHz ≤ 13 bit modes — 2 5 kΩ 3 — — 5 kΩ fADCK fADCK ADC conversion clock frequency ADC conversion clock frequency 4 1.0 — 18.0 MHz 4 2.0 — 12.0 MHz 16 bit modes Table continues on the next page... K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011. Freescale Semiconductor, Inc. 39 Peripheral operating requirements and behaviors Table 27. 16-bit ADC operating conditions (continued) Symbol Crate Description ADC conversion rate Conditions ≤ 13 bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16 bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the best results. The results in this datasheet were derived from a system which has