KMPC870

Freescale Semiconductor MPC885EC Rev. 3, 07/2004 MPC885/MPC880 Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC885/MPC880 (refer to Table 1 for the list of devices). The MPC885 is the superset device of the MPC885/MPC880 family. The CPU on the MPC885/MPC880 is a 32-bit PowerPC™ core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set. 1 Overview The MPC885/880 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC885/MPC880 provides enhanced ATM functionality, an additional fast Ethernet controller, a USB, and an encryption block. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 15. 16. 17. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 9 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal Calculation and Measurement . . . . . . . . . . 12 Power Supply and Power Sequencing . . . . . . . . . . . 14 Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44 CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46 UTOPIA AC Electrical Specifications . . . . . . . . . . . 69 FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 71 Mechanical Data and Ordering Information . . . . . . . 75 Document Revision History . . . . . . . . . . . . . . . . . . . 89 © Freescale Semiconductor, Inc., 2004. All rights reserved. Features Table 1 shows the functionality supported by the members of the MPC885 family. Table 1. MPC885 Family Cache Part I Cache MPC885 MPC880 8 Kbyte 8 Kbyte D Cache 10BaseT 8 Kbyte 8 Kbyte Up to 3 Up to 2 10/100 2 2 3 2 2 2 1 1 Serial ATM and UTOPIA interface Serial ATM and UTOPIA interface Ethernet SCC SMC USB ATM Support Security Engine Yes No 2 Features The MPC885/880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC885/880 features: • • Embedded MPC8xx core up to 133 MHz Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) — The 133-MHz core frequency supports 2:1 mode only. — The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes. Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) — The core performs branch prediction with conditional prefetch and without conditional execution. — 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) – Instruction cache is two-way, set-associative with 256 sets in 2 blocks – Data cache is two-way, set-associative with 256 sets – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. – Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. — MMUs with 32-entry TLB, fully associative instruction and data TLBs — MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups — Advanced on-chip emulation debug mode Provides enhanced ATM functionality found on the MPC862 and MPC866 families and includes the following: — Improved operation, administration and maintenance (OAM) support — OAM performance monitoring (PM) support — Multiple APC priority levels available to support a range of traffic pace requirements — Port-to-port switching capability without the need for RAM-based microcode — Simultaneous MII (100BaseT) and UTOPIA (half- or full -duplex) capability — Optional statistical cell counters per PHY • • MPC885/MPC880 Hardware Specifications, Rev. 3 2 Freescale Semiconductor Features • • • • • • • — UTOPIA L2-compliant interface with added FIFO buffering to reduce the total cell transmission time and multi-PHY support. (The earlier UTOPIA L1 specification is also supported.) — Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode — Supports full-duplex UTOPIA master (ATM side) and slave (PHY side) operations using a split bus — AAL2/VBR functionality is ROM-resident. Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chip select or RAS to support a DRAM bank. — Up to 30 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices — DRAM controller programmable to support most size and speed memory interfaces — Four CAS lines, four WE lines, and one OE line — Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbyte–256 Mbyte) — Selectable write protection — On-chip bus arbitration logic General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting. — Interrupt can be masked on reference match and event capture Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that interface through MII and/or RMII interfaces System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Clock synthesizer — Decrementer and time base — Reset controller — IEEE 1149.1 test access port (JTAG) Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP, 802.11i, and iSCSI processing. Available on the MPC885, the security engine contains a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are: — Data encryption standard execution unit (DEU) – DES, 3DES – Two key (K1, K2, K1) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 3 Features • • • • • — Advanced encryption standard unit (AESU) – Implements the Rinjdael symmetric key cipher – ECB, CBC, and counter modes – 128-, 192-, and 256- bit key lengths — Message digest execution unit (MDEU) – SHA with 160- or 256-bit message digest – MD5 with 128-bit message digest – HMAC with either algorithm — Crypto-channel supporting multi-command descriptor chains — Integrated controller managing internal resources and bus mastering — Buffer size of 256 bytes for the DEU, AESU, and MDEU, with flow control for large data sizes Interrupts — Six external interrupt request (IRQ) lines — 12 port pins with interrupt capability — 23 internal interrupt sources — Programmable priority between SCCs — Programmable highest priority request Communications processor module (CPM) — RISC controller — Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT) — Supports continuous mode transmission and reception on all serial channels — 8-Kbytes of dual-port RAM — Several serial DMA (SDMA) channels to support the CPM — Three parallel I/O registers with open-drain capability On-chip 16 × 16 multiply accumulate controller (MAC) — One operation per clock (two-clock latency, one-clock blockage) — MAC operates concurrently with other instructions — FIR loop—Four clocks per four multiplies Four baud rate generators — Independent (can be connected to any SCC or SMC) — Allow changes during operation — Autobaud support option Up to three serial communication controllers (SCCs) supporting the following protocols: — Serial ATM capability on SCCs — Optional UTOPIA port on SCC4 — Ethernet/IEEE 802.3 optional on the SCC(s) supporting full 10-Mbps operation — HDLC/SDLC — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support point-to-point protocol (PPP) MPC885/MPC880 Hardware Specifications, Rev. 3 4 Freescale Semiconductor Features • • • • • — AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Binary synchronous communication (BISYNC) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC)) Up to two serial management channels (SMCs) supporting the following protocols: — UART (low-speed operation) — Transparent — General circuit interface (GCI) controller — Provide management for BRI devices as GCI controller in time-division multiplexed (TDM) channels Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host controller, or both for testing purposes (loop-back diagnostics) — USB 2.0 full-/low-speed compatible — The USB function mode has the following features: – Four independent endpoints support control, bulk, interrupt, and isochronous data transfers. – CRC16 generation and checking – CRC5 checking – NRZI encoding/decoding with bit stuffing – 12- or 1.5-Mbps data rate – Flexible data buffers with multiple buffers per frame – Automatic retransmission upon transmit error — The USB host controller has the following features: – Supports control, bulk, interrupt, and isochronous data transfers – CRC16 generation and checking – NRZI encoding/decoding with bit stuffing – Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub. – Flexible data buffers with multiple buffers per frame – Supports local loop back mode for diagnostics (12 Mbps only) Serial peripheral interface (SPI) — Supports master and slave modes — Supports multiple-master operation on the same bus Inter-integrated circuit (I2C) port — Supports master and slave modes — Supports a multiple-master environment Time-slot assigner (TSA) — Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 5 Features • • • • • • — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame synchronization, and clocking — Allows dynamic changes — Can be internally connected to four serial channels (two SCCs and two SMCs) Parallel interface port (PIP) — Centronics interface support — Supports fast connection between compatible ports on MPC885/880 and other MPC8xx devices PCMCIA interface — Master (socket) interface, release 2.1-compliant — Supports two independent PCMCIA sockets — 8 memory or I/O windows supported Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — Supports conditions: = ≠ < > — Each watchpoint can generate a break point internally. Normal high and normal low power modes to conserve power 1.8-V core and 3.3-V I/O operation The MPC885/880 comes in a 357-pin ball grid array (PBGA) package. MPC885/MPC880 Hardware Specifications, Rev. 3 6 Freescale Semiconductor Features The MPC885 block diagram is shown in Figure 1. Instruction Bus Embedded MPC8xx Processor Core Load/Store Bus 8-Kbyte Instruction Cache Instruction MMU 32-Entry ITLB 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF Unified Bus System Interface Unit (SIU) Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface Fast Ethernet Controller DMAs DMAs FIFOs 10/100 BaseT Media Access Control MIII/RMII Parallel I/O 4 Baud Rate Generators Parallel Interface Port Timers 4 Timers Security Engine Controller Channel AESU DEU MDEU Interrupt 8-Kbyte Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Virtual IDMA and Serial DMAs USB SCC2 SCC3 SCC4/ UTOPIA SMC1 SMC2 SPI I2C Time Slot Assigner Serial Serial Interface Figure 1. MPC885 Block Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 7 Features The MPC880 block diagram is shown in Figure 2. Instruction Bus Embedded MPC8xx Processor Core Load/Store Bus 8-Kbyte Instruction Cache Instruction MMU 32-Entry ITLB 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF Unified Bus System Interface Unit (SIU) Memory Controller External Internal Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface Fast Ethernet Controller DMAs DMAs FIFOs 10/100 BaseT Media Access Control MIII/RMII Parallel I/O 4 Baud Rate Generators Parallel Interface Port Timers 4 Timers Interrupt 8-Kbyte Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Virtual IDMA and Serial DMAs USB SCC3 SCC4/ UTOPIA SMC1 SMC2 SPI I2C Time Slot Assigner Serial Interface Figure 2. MPC880 Block Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 8 Freescale Semiconductor Maximum Tolerated Ratings 3 Maximum Tolerated Ratings Table 2. Maximum Tolerated Ratings Rating Symbol VDDH VDDL VDDSYN Difference between VDDL and VDDSYN Value –0.3 to 4.0 –0.3 to 2.0 –0.3 to 2.0 100 KHz) timings. Table 29. I2C Timing (SCL > 100 KHZ) All Frequencies Num Characteristic Expression Min 200 200 202 203 204 205 206 207 208 209 210 211 1 SCL Unit Max BRGCLK/48 BRGCLK/48 — — — — — — — 1/(10 × fSCL) 1/(33 × fSCL) — Hz Hz s s s s s s s s s s SCL clock frequency (slave) SCL clock frequency (master) 1 Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time SDL/SCL fall time Stop condition setup time fSCL fSCL — — — — — — — — — — 0 BRGCLK/16512 1/(2.2 × fSCL) 1/(2.2 × fSCL) 1/(2.2 × fSCL) 1/(2.2 × fSCL) 1/(2.2 × fSCL) 0 1/(40 × fSCL) — — 1/2(2.2 × fSCL) frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) × pre_scaler × 2). The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1. MPC885/MPC880 Hardware Specifications, Rev. 3 68 Freescale Semiconductor UTOPIA AC Electrical Specifications Figure 69 shows the I2C bus timing. SDA 202 205 SCL 206 209 210 211 203 207 204 208 Figure 69. I2C Bus Timing Diagram 13 UTOPIA AC Electrical Specifications Table 30, Table 31, and Table 32, show the AC electrical specifications for the UTOPIA interface. Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications Num U1 Signal Characteristic UtpClk rise/fall time (internal clock option) Duty cycle Frequency U2 U3 U4 UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (and PHREQ and PHSEL active delay in multi-PHY mode) UTPB, SOC, Rxclav and Txclav setup time UTPB, SOC, Rxclav and Txclav hold time Output Input Input 2 ns 4 ns 1 ns Direction Output 50 Min Max 4 ns 50 33 16 ns Unit ns % MHz ns ns ns Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications Num U1 Signal Characteristic UtpClk rise/fall time (Internal clock option) Duty cycle Frequency U2 U3 U4 UTPB, SOC, RxEnb, TxEnb, RxAddr and TxAddr active delay (PHREQ and PHSEL active delay in multi-PHY mode) UTPB_Aux, SOC_Aux, Rxclav and Txclav setup time UTPB_Aux, SOC_Aux, Rxclav and Txclav hold time Output Input Input 2 ns 4 ns 1 ns Direction Output 50 Min Max 4 ns 50 33 16 ns Unit ns % MHz ns ns ns MPC885/MPC880 Hardware Specifications, Rev. 3 69 Freescale Semiconductor UTOPIA AC Electrical Specifications Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications Num U1 Signal Characteristic UtpClk rise/fall time (external clock option) Duty cycle Frequency U2 U3 U4 UTPB, SOC, Rxclav and Txclav active delay UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup time UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold time Output Input Input 2 ns 4 ns 1 ns Direction Input 40 Min Max 4 ns 60 33 16 ns Unit ns % MHz ns ns ns Figure 70 shows signal timings during UTOPIA receive operations. U1 UtpClk U2 PHREQn U3 3 RxClav High-Z at MPHY U2 2 U1 U4 4 High-Z at MPHY RxEnb UTPB SOC U3 3 U4 4 Figure 70. UTOPIA Receive Timing MPC885/MPC880 Hardware Specifications, Rev. 3 70 Freescale Semiconductor USB Electrical Characteristics Figure 71 shows signal timings during UTOPIA transmit operations. U1 1 UtpClk U2 5 PHSELn U3 3 TxClav High-Z at MPHY TxEnb UTPB SOC U2 2 High-Z at Multi-PHYP U4 4 U1 U2 5 Figure 71. UTOPIA Transmit Timing 14 USB Electrical Characteristics This section provides the AC timings for the USB interface. 14.1 USB Interface AC Timing Specifications The USB Port uses the transmit clock on SCC1. Table 33 lists the USB interface timings. Table 33. USB Interface AC Timing Specifications All Frequencies Name US1 Characteristic Min USBCLK frequency of operation 1 Low speed Full speed USBCLK duty cycle (measured at 1.5 V) 45 6 48 55 Max MHz MHz % Unit US4 1 USBCLK accuracy should be ±500 ppm or better. USBCLK may be stopped to conserve power. 15 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. MPC885/MPC880 Hardware Specifications, Rev. 3 71 Freescale Semiconductor FEC Electrical Characteristics 15.1 MII and Reduced MII Receive Signal Timing The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. The reduced MII (RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%. Table 34 provides information on the MII and RMII receive signal timing. Table 34. MII Receive Signal Timing Num M1 M2 M3 M4 Characteristic MII_RXD[3:0], MII_RX_DV, MII_RX_ERR to MII_RX_CLK setup MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold MII_RX_CLK pulse width high MII_RX_CLK pulse width low Min 5 5 35% 35% 4 2 Max — — 65% 65% — — Unit ns ns MII_RX_CLK period MII_RX_CLK period ns ns M1_RMII RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK setup M2_RMII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR hold Figure 72 shows MII receive signal timing. M3 MII_RX_CLK (input) M4 MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER M1 M2 Figure 72. MII Receive Signal Timing Diagram 15.2 MII and Reduced MII Transmit Signal Timing The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. The RMII transmitter functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – 1%. MPC885/MPC880 Hardware Specifications, Rev. 3 72 Freescale Semiconductor FEC Electrical Characteristics Table 35 provides information on the MII and RMII transmit signal timing. Table 35. MII Transmit Signal Timing Num M5 M6 Characteristic MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid Min 5 — 4 2 35% Max — 25 — — 65% Unit ns ns ns ns MII_TX_CLK or RMII_REFCLK period MII_TX_CLK or RMII_REFCLK period M20_R RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup MII M21_R RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising MII edge M7 MII_TX_CLK and RMII_REFCLK pulse width high M8 MII_TX_CLK and RMII_REFCLK pulse width low 35% 65% Figure 73 shows the MII transmit signal timing diagram. M7 MII_TX_CLK (input) RMII_REFCLK M5 M8 MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER M6 Figure 73. MII Transmit Signal Timing Diagram 15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 36 provides information on the MII async inputs signal timing. Table 36. MII Async Inputs Signal Timing Num M9 Characteristic MII_CRS, MII_COL minimum pulse width Min 1.5 Max — Unit MII_TX_CLK period MPC885/MPC880 Hardware Specifications, Rev. 3 73 Freescale Semiconductor FEC Electrical Characteristics Figure 74 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL M9 Figure 74. MII Async Inputs Timing Diagram 15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 37 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table 37. MII Serial Management Channel Timing Num M10 M11 M12 M13 M14 M15 Characteristic MII_MDC falling edge to MII_MDIO output invalid (minimum propagation delay) MII_MDC falling edge to MII_MDIO output valid (max prop delay) MII_MDIO (input) to MII_MDC rising edge setup MII_MDIO (input) to MII_MDC rising edge hold MII_MDC pulse width high MII_MDC pulse width low Min 0 — 10 0 40% 40% Max — 25 — — 60% 60% Unit ns ns ns ns MII_MDC period MII_MDC period Figure 75 shows the MII serial management channel timing diagram. M14 MM15 MII_MDC (output) M10 MII_MDIO (output) M11 MII_MDIO (input) M12 M13 Figure 75. MII Serial Management Channel Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 74 Freescale Semiconductor Mechanical Data and Ordering Information 16 Mechanical Data and Ordering Information Table 38 identifies the available packages and operating frequencies for the MPC885/880 derivative devices. Table 38. Available MPC885/880 Packages/Frequencies Package Type Plastic ball grid array ZP suffix — Leaded VR suffix — Lead-Free are available as needed Temperature (Tj) Frequency (MHz) 0°C to 95°C 66 Order Number KMPC885ZP66 KMPC880ZP66 MPC885ZP66 MPC880ZP66 KMPC885ZP80 KMPC880ZP80 MPC885ZP80 MPC880ZP80 KMPC885ZP133 KMPC880ZP133 MPC885ZP133 MPC880ZP133 KMPC885CZP66 KMPC880CZP66 MPC885CZP66 MPC880CZP66 KMPC885CZP133 KMPC880CZP133 MPC885CZP133 MPC880CZP133 80 133 Plastic ball grid array CZP suffix — Leaded CVR suffix — Lead-Free are available as needed -40°C to 100°C 66 133 MPC885/MPC880 Hardware Specifications, Rev. 3 75 Freescale Semiconductor Mechanical Data and Ordering Information 16.1 Pin Assignments Figure 76 shows the top-view pinout of the PBGA package. For additional information, see the MPC885 PowerQUICC Family User’s Manual. NOTE: This is the top view of the device. W TRST PA10 PB23 PA8 PC8 PA5 PB17 PA13 PC4 PA11 PE17 PE30 PE15 PD6 PD4 PD7 PA3 V PB28 TMS PB25 PC11 PB22 PA7 PB19 PC7 PB16 PC13 PE21 PE24 PE14 PD5 PE28 PE27 PB31 PE23 PE22 U PB27 PB14 TCK PB24 PC10 PB21 PA6 MII1_COL PC6 PB15 PE31 PD15 PD14 PD13 PD12 PA4 PA0 PD9 PA1 T PB29 PC12 TDO TDI PA9 PC9 PB20 PB18 MII1_CRS PC5 PD3 PE29 PE16 PE19 MII1_TXEN PA2 PE25 PD10 PE26 R PC15 PC14 PB26 GND VDDL VDDL VDDL VDDL VDDH PE20 PD8 PD11 PE18 P MII_MDIO PB30 PA14 PA12 VDDH GND VDDH VDDH GND IRQ7 IRQ1 D0 D8 N A2 A1 N/C PA15 GND VDDL IRQ0 D12 D13 D4 M A3 A5 A4 A0 VDDL VDDH D17 D23 D27 D1 L A7 A9 A8 A6 VDDH GND GND VDDL D9 D10 D11 D2 K A10 A11 A12 A13 VDDL GND VDDH D5 D14 D3 D15 J A14 A16 A15 A17 VDDL D22 D19 D16 D18 H A27 A19 A20 A24 VDDH GND D28 D6 D20 D21 G A21 A29 A23 TSIZ0 VDDL VDDH GND GND VDDH CLKOUT D26 D24 D25 F A25 A30 A22 BSA3 VDDH IPA2 D31 D7 D29 A18 A28 TSIZ1 WE1 VDDL VDDL VDDL VDDL VSSSYN IPA3 IPA6 D30 E D A26 A31 BSA0 GPL_AB2 CS6 CS3 WR BI BR IRQ6 IPB1 ALEB AS MODCK1 EXTAL RSTCONF IPA7 IPA4 IPA5 C BSA2 BSA1 WE2 CS4 CE2_A CS1 GPL_A5 TA BG BURST IPB3 IPB2 IRQ4 OP1 BADDR28 TEXP WAIT_B VSSSYN1 IPA1 B WE3 WE0 GPL_A0 CS7 CE1_A CS0 GPL_A4 TEA BB IRQ2 IPB4 IPB7 ALEA OP0 BADDR29 HRESET PORESET VDDLSYN IPA0 A OE GPL_AB3 CS5 CS2 GPL_B4 BDIP TS IRQ3 IPB5 IPB0 IPB6 BADDR30 MODCK2 EXTCLK XTAL SRESET WAIT_A 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 76. Pinout of the PBGA Package MPC885/MPC880 Hardware Specifications, Rev. 3 76 Freescale Semiconductor Mechanical Data and Ordering Information Table 39 contains a list of the MPC885 input and output signals and shows multiplexing and pin assignments. Table 39. Pin Assignments Name A[0:31] Pin Number Type M16, N18, N19, M19, M17, M18, L16, L19, L17, L18, K19, K18, K17, Bidirectional K16, J19, J17, J18, J16, E19, H18, H17, G19, F17, G17, H16, F19, D19, Three-state H19, E18, G18, F18, D18 P2, M1, L1, K2, N1, K4, H3, F2, P1, L4, L3, L2, N3, N2, K3, K1, J2, M4, Bidirectional J1, J3, H2, H1, J4, M3, G2, G1, G3, M2, H4, F1, E1, F3 Three-state G16 E17 D13 C10 A13 A12 C12 B12 D12 B10 C7 Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Output Bidirectional Active pull-up Bidirectional Active pull-up Open-drain Bidirectional Active pull-up Bidirectional Three-state Bidirectional Three-state D[0:31] TSIZ0 REG TSIZ1 RD/WR BURST BDIP GPL_B5 TS TA TEA BI IRQ2 RSV IRQ4 KR RETRY SPKROUT CR IRQ3 BR BG BB FRZ IRQ6 IRQ0 IRQ1 IRQ7 A11 D11 C11 B11 D10 N4 P3 P4 Input Bidirectional Bidirectional Bidirectional Active pull-up Bidirectional Input Input Input MPC885/MPC880 Hardware Specifications, Rev. 3 77 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name CS[0:5] CS6 CE1_B CS7 CE2_B WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] CS[2:3] UPWAITA GPL_A4 UPWAITB GPL_B4 GPL_A5 PORESET RSTCONF HRESET SRESET XTAL EXTAL CLKOUT EXTCLK Pin Number B14, C14, A15, D14, C16, A16 D15 B16 B18 Output Output Output Output Type E16 Output C17 Output B19 Output D17, C18, C19, F16 B17 A18 Output Output Output D16, A17 Output B13 A14 C13 B3 D4 B4 A3 A4 D5 G4 A5 Bidirectional Bidirectional Output Input Input Open-drain Open-drain Analog output Analog input (3.3 V only) Output Input (3.3 V only) MPC885/MPC880 Hardware Specifications, Rev. 3 78 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name TEXP ALE_A CE1_A CE2_A WAIT_A SOC_Split1 WAIT_B IP_A0 UTPB_Split01 IP_A1 UTPB_Split11 IP_A2 IOIS16_A UTPB_Split21 IP_A3 UTPB_Split31 IP_A4 UTPB_Split41 IP_A5 UTPB_Split51 IP_A6 UTPB_Split61 IP_A7 UTPB_Split71 ALE_B DSCK/AT1 IP_B[0:1] IWP[0:1] VFLS[0:1] IP_B2 IOIS16_B AT2 IP_B3 IWP2 VF2 IP_B4 LWP0 VF0 IP_B5 LWP1 VF1 C4 B7 B15 C15 A2 C3 B1 C1 F4 Pin Number Output Output Output Output Input Input Input Input Input Type E3 D2 D1 E2 D3 D8 A9, D9 Input Input Input Input Input Bidirectional Three-state Bidirectional C8 Bidirectional Three-state Bidirectional C9 B9 Bidirectional A10 Bidirectional MPC885/MPC880 Hardware Specifications, Rev. 3 79 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name IP_B6 DSDI AT0 IP_B7 PTR AT3 OP0 UtpClk_Split1 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR30 REG BADDR[28:29] AS PA15 USBRXD PA14 USBOE PA13 RXD2 PA12 TXD2 PA11 RXD4 MII1-TXD0 RMII1-TXD0 PA10 MII1-TXER TIN4 CLK7 PA9 L1TXDA RXD3 PA8 L1RXDA TXD3 A8 Pin Number Type Bidirectional Three-state Bidirectional Three-state Bidirectional Output Bidirectional B8 B6 C6 D6 A6 Bidirectional A7 C5, B5 D7 N16 P17 W11 P16 W9 Output Output Input Bidirectional Bidirectional (Optional: open-drain) Bidirectional Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) W17 Bidirectional (Optional: open-drain) T15 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) W15 MPC885/MPC880 Hardware Specifications, Rev. 3 80 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PA7 CLK1 L1RCLKA BRGO1 TIN1 PA6 CLK2 TOUT1 PA5 CLK3 L1TCLKA BRGO2 TIN2 PA4 CTS4 MII1-TXD1 RMII1-TXD1 PA3 MII1-RXER RMII1-RXER BRGO3 V14 Pin Number Type Bidirectional U13 Bidirectional W13 Bidirectional U4 Bidirectional W2 Bidirectional PA2 T4 MII1-RXDV RMII1-CRS_DV TXD4 PA1 MII1-RXD0 RMII1-RXD0 BRGO4 PA0 MII1-RXD1 RMII1-RXD1 TOUT4 PB31 SPISEL MII1 - TXCLK RMII1-REFCLK PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 U1 Bidirectional Bidirectional U3 Bidirectional V3 Bidirectional (Optional: open-drain) P18 T19 V19 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) MPC885/MPC880 Hardware Specifications, Rev. 3 81 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PB27 I2CSDA BRGO1 PB26 I2CSCL BRGO2 PB25 RXADDR31 TXADDR3 SMTXD1 PB24 TXADDR31 RXADDR3 SMRXD1 PB23 TXADDR21 RXADDR2 SDACK1 SMSYN1 PB22 TXADDR41 RXADDR4 SDACK2 SMSYN2 PB21 SMTXD2 TXADDR1 1 BRG01 RXADDR1 PHSEL[1] PB20 SMRXD2 L1CLKOA TXADDR01 RXADDR0 PHSEL[0] PB19 MII1-RXD3 RTS4 PB18 RXADDR41 TXADDR4 RTS2 L1ST2 U19 Pin Number Type Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) R17 V17 U16 Bidirectional (Optional: open-drain) W16 Bidirectional (Optional: open-drain) V15 Bidirectional (Optional: open-drain) U14 Bidirectional (Optional: open-drain) T13 Bidirectional (Optional: open-drain) V13 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) T12 MPC885/MPC880 Hardware Specifications, Rev. 3 82 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PB17 L1ST3 BRGO2 RXADDR11 TXADDR1 PHREQ[1] PB16 L1RQa L1ST4 RTS4 RXADDR01 TXADDR0 PHREQ[0] PB15 TXCLAV BRG03 RXCLAV PB14 RXADDR21 TXADDR2 PC15 DREQ0 RTS3 L1ST1 TXCLAV RXCLAV PC14 DREQ1 RTS2 L1ST2 PC13 MII1-TXD3 SDACK1 PC12 MII1-TXD2 TOUT1 PC11 USBRXP PC10 USBRXN TGATE1 PC9 CTS2 PC8 CD2 TGATE2 W12 Pin Number Type Bidirectional (Optional: open-drain) V11 Bidirectional (Optional: open-drain) U10 Bidirectional U18 Bidirectional R19 Bidirectional R18 Bidirectional V10 Bidirectional T18 Bidirectional V16 U15 Bidirectional Bidirectional T14 W14 Bidirectional Bidirectional MPC885/MPC880 Hardware Specifications, Rev. 3 83 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PC7 CTS4 L1TSYNCB USBTXP PC6 CD4 L1RSYNCB USBTXN PC5 CTS3 L1TSYNCA SDACK2 PC4 CD3 L1RSYNCA PD15 L1TSYNCA UTPB0 PD14 L1RSYNCA UTPB1 PD13 L1TSYNCB UTPB2 PD12 L1RSYNCB UTPB3 PD11 RXD3 RXENB PD10 TXD3 TXENB PD9 TXD4 UTPCLK PD8 RXD4 MII-MDC RMII-MDC PD7 RTS3 UTPB4 V12 Pin Number Type Bidirectional U11 Bidirectional T10 Bidirectional W10 Bidirectional U8 Bidirectional U7 Bidirectional U6 Bidirectional U5 Bidirectional R2 Bidirectional T2 Bidirectional U2 Bidirectional R3 Bidirectional W3 Bidirectional MPC885/MPC880 Hardware Specifications, Rev. 3 84 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PD6 RTS4 UTPB5 PD5 CLK8 L1TCLKB UTPB6 PD4 CLK4 UTPB7 PD3 CLK7 TIN4 SOC PE31 CLK8 L1TCLKB MII1-RXCLK PE30 L1RXDB MII1-RXD2 PE29 MII2-CRS PE28 TOUT3 MII2-COL PE27 RTS3 L1RQB MII2-RXER RMII2-RXER W5 Pin Number Type Bidirectional V6 Bidirectional W4 Bidirectional T9 Bidirectional U9 Bidirectional (Optional: open-drain) W7 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) T8 V5 V4 PE26 T1 L1CLKOB MII2-RXDV RMII2-CRS_DV PE25 RXD4 MII2-RXD3 L1ST2 PE24 SMRXD1 BRGO1 MII2-RXD2 T3 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) V8 Bidirectional (Optional: open-drain) MPC885/MPC880 Hardware Specifications, Rev. 3 85 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PE23 SMSYN2 TXD4 MII2-RXCLK L1ST1 PE22 TOUT2 MII2-RXD1 RMII2-RXD1 SDACK1 PE21 SMRXD2 TOUT1 MII2-RXD0 RMII2-RXD0 RTS3 PE20 L1RSYNCA SMTXD2 CTS3 MII2-TXER PE19 L1TXDB MII2-TXEN RMII2-TXEN PE18 L1TSYNCA SMTXD1 MII2-TXD3 PE17 TIN3 CLK5 BRGO3 SMSYN1 MII2-TXD2 PE16 L1RCLKB CLK6 TXD3 MII2-TXCLK RMII2-REFCLK PE15 TGATE1 MII2-TXD1 RMII2-TXD1 V2 Pin Number Type Bidirectional (Optional: open-drain) V1 Bidirectional (Optional: open-drain) V9 Bidirectional (Optional: open-drain) R4 Bidirectional (Optional: open-drain) T6 Bidirectional (Optional: open-drain) R1 Bidirectional (Optional: open-drain) W8 Bidirectional (Optional: open-drain) T7 Bidirectional (Optional: open-drain) W6 Bidirectional MPC885/MPC880 Hardware Specifications, Rev. 3 86 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PE14 RXD3 MII2-TXD0 RMII2-TXD0 TMS TDI DSDI TCK DSCK TRST TDO DSDO MII1_CRS MII_MDIO MII1_TXEN RMII1_TXEN MII1_COL VSSSYN1 VSSSYN VDDLSYN GND V7 Pin Number Type Bidirectional V18 T16 U17 W18 T17 T11 P19 T5 U12 C2 E4 B2 Input Input Input Input Output Input Bidirectional Output Input PLL analog VDD and GND Power Power G6, G7, G8, G9, G10, G11, G12, G13, H7, H8, H9, H10, H11, H12, H13, Power H14, J7, J8, J9, J10, J11, J12, J13, K7, K8, K9, K10, K11, K12, K13, L7, L8, L9, L10, L11, L12, L13, M7, M8, M9, M10, M11, M12, M13, N7, N8, N9, N10, N11, N12, N13, N14, P7, P13, R16 E5, E6, E9, E11, E14, G15, H5, J5, J15, K15, L5, M15, N5, R6, R9, R10, Power R12, R15 E7, E8, E10, E12, E13, E15, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, G5, G14, H6, H15, J6, J14, K5, K6, K14, L6, L14, L15, M5, M6, M14, N6, N15, P5, P6, P8, P9, P10, P11, P12, P14, P15, R5, R7, R8, R11, R13, R14 N17 mode only. Power VDDL VDDH N/C 1 ESAR No-connect MPC885/MPC880 Hardware Specifications, Rev. 3 87 Freescale Semiconductor Mechanical Data and Ordering Information 16.2 Mechanical Dimensions of the PBGA Package Figure 77 shows the mechanical dimensions of the PBGA package. NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 77. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC885/MPC880 Hardware Specifications, Rev. 3 88 Freescale Semiconductor Document Revision History 17 Document Revision History Table 40 lists significant changes between revisions of this hardware specification. Table 40. Document Revision History Revision Number 0 0.1 Date 02/2003 04/2003 Initial revision. Added pinout and pinout assignments table. Added the USB timing to Section 14. Added the Reduced MII to Section 15. Removed the Data Parity. Made some changes to the Features list. Made the changes to the RMII Timing, Made sure all the VDDL, VDDH, and GND show up on the pinout diagram. Changed the SPI Master Timing Specs. 162 and 164. Corrected the signals that had overlines on them. Changed the pin descriptions for PD8 and PD9. Changed some more typos, put in the phsel and phreq pins. Corrected the USB timing. Changed the pin descriptions per the June 22 spec. Added the RxClav and TxClav signals to PC15. Added the Reference to USB 2.0 to the Features list and removed 1.1 from USB on the block diagrams. Changed the USB description to full-/low-speed compatible. Added the DSP information in the Features list Fixed table formatting. Nontechnical edits. Released to the external web. Changed the maximum operating frequency to 133 MHz. Put in the orderable part numbers that are orderable. Put the timing in the 80 MHz column. Rounded the timings to hundredths in the 80 MHz column. Put the pin numbers in footnotes by the maximum currents in Table 6. Changed 22 and 41 in the Timing. Put in the Thermal numbers. • Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values • Added a footnote to Spec 41 specifying that EDM = 1 • Added RMII1_EN under M1II_EN in Table 36 Pin Assignments • Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the I2C Standard • Put the new part numbers in the Ordering Information Section Changes 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 05/2003 05/2003 5/2003 5/2003 6/2003 7/2003 8/2003 8/2003 9/2003 2.0 12/2003 3.0 7/22/2004 MPC885/MPC880 Hardware Specifications, Rev. 3 89 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC885/MPC880 Hardware Specifications, Rev. 3 90 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 91 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. 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Learn More: For more information about Freescale Semiconductor products, please visit www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004. MPC885EC Rev. 3 07/2004