MC8610TVT1067G

Freescale Semiconductor Data Sheet Document Number: MPC8610EC Rev. 0, 10/2008 MPC8610 Integrated Host Processor Hardware Specifications Features • High-performance, 32-bit e600 core, that implements the Power Architecture™ technology – Eleven execution units and three register files – Two separate 32-Kbyte instruction and data level 1 (L1) caches – Integrated 256-Kbyte, eight-way set-associative unified instruction and data level 2 (L2) cache with ECC – 36-bit real addressing – Multiprocessing support features – Power and thermal management • MPX coherency module (MCM) • Address translation and mapping units (ATMUs) • DDR/DDR2 memory controller – 64- or 32-bit data path (72-bit with ECC) – Up to 533-MHz DDR2 data rate and up to 400 MHz DDR data rate – Up to 16 Gbytes memory • Enhanced local bus controller (eLBC) – Operating at up to 133 MHz – Eight chip selects • Display interface unit – Maximum display resolution: 1280 × 1024 – Maximum display refresh rate: 60 Hz – Display color depth: up to 24 bpp – Display interface: parallel TTL • OpenPIC-compliant programmable interrupt controller (PIC) – Supports 16 programmable interrupt and processor task priority levels – Supports 12 discrete external interrupts and 48 internal interrupts – Eight global high resolution timers/counters that can generate interrupts – Support for PCI Express message-shared interrupts (MSIs) • Dual I2C controllers – Master or slave I2C mode support – Boot sequencer – Optionally loads configuration data from serial ROM at reset via I2C interface – Can be used to initialize configuration registers and/or memory – Supports extended I2C addressing mode DUART Fast InfraRed interface Serial peripheral interface – Master or slave support Dual integrated four-channel DMA controllers – All channels accessible by both local and remote masters – Supports transfers to or from any local memory or I/O port – Ability to start and flow control each DMA channel from external 3-pin interface Watchdog timer Dual global timer modules 32-bit PCI interface, 33 or 66 MHz bus frequency Dual PCI Express® controllers – PCI Express 1.0a compatible – PCI Express controller 1 supports x1, x2, and x4 link widths; PCI Express controller 2 supports x1, x2, x4, and x8 link widths – 2.5 Gbaud, 2.0 Gbps lane Device performance monitor – Supports eight 32-bit counters that count the occurrence of selected events – Ability to count up to 512 counter-specific events – Supports 64 reference events that can be counted on any of the 8 counters – Supports duration and quantity threshold counting – Burstiness feature that permits counting of burst events with a programmable time between bursts – Triggering and chaining capability – Ability to generate an interrupt on overflow IEEE Std 1149.1™ compliant, JTAG boundary scan Available as 783-pin, flip-chip, plastic ball grid array (FC-PBGA) • • • • • • • • • • • © Freescale Semiconductor, Inc., 2008. All rights reserved. Table of Contents 1 2 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4 1.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .16 2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.6 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . .26 2.7 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.8 Display Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.9 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 2.11 Fast/Serial Infrared Interfaces (FIRI/SIRI). . . . . . . . . . .44 2.12 Synchronous Serial Interface (SSI). . . . . . . . . . . . . . . .44 2.13 Global Timer Module. . . . . . . . . . . . . . . . . . . . . . . . . . .48 2.14 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.15 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . .50 2.16 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.17 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . .54 2.18 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3 2.19 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . 3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Power Supply Design and Sequencing . . . . . . . . . . . . 3.3 Decoupling Recommendations . . . . . . . . . . . . . . . . . . 3.4 SerDes Block Power Supply Decoupling Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Connection Recommendations . . . . . . . . . . . . . . . . . . 3.6 Pull-Up and Pull-Down Resistor Requirements . . . . . . 3.7 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . . 3.8 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . . 3.9 JTAG Configuration Signals. . . . . . . . . . . . . . . . . . . . . 3.10 Guidelines for High-Speed Interface Termination . . . . 3.11 Guidelines for PCI Interface Termination . . . . . . . . . . . 3.12 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 72 72 76 77 77 77 78 78 79 79 82 83 84 90 92 93 94 4 5 6 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 2 Freescale Semiconductor Figure 1 shows the major functional units within the MPC8610. MPC8610 e600 Core Block e600 Core w/ AltiVec 32-Kbyte L1 Instruction Cache 32-Kbyte L1 Data Cache MPX Bus MPX Coherency Module (MCM) DDR/DDR2 SDRAM Controller Local Bus Controller (eLBC) PCI Express x1,x2,x4 PCI Express Interface 1 (×4) OCeaN Switch Fabric 1 Display Interface Unit Programmable Interrupt Controller (PIC) 2 x I2C Controller External Control Four-Channel DMA Controller 1 2 x Dual Universal Asynchronous Receiver/Transmitter (DUART) 2 x Fast/Serial Infra-Red Interface (FIRI/SIRI) PCI Express x1,x2,x4,x8 PCI Express Interface 2 (×8) OCeaN Switch Fabric 2 Serial Peripheral Interface 2 x Global Timer Module 2 x Synchronous Serial Interface (SSI) DDR/DDR2 SDRAM ROM, NAND Flash, NOR Flash, GPIO LCD 256-Kbyte L2 Cache IRQs I2C 32-Bit PCI 32-Bit PCI Interface Serial IrDA SPI Peripherals Timer Control I2S/AC97 Audio External Control Four-Channel DMA Controller 2 Figure 1. MPC8610 Block Diagram MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 3 Pin Assignments and Reset States 1 1.1 Pin Assignments and Reset States Pin Assignments Table 1. Signal Reference by Functional Block Name1 Package Pin Number Clocking Signals4 Pin Type Power Supply Notes Table 1 provides the pin assignments for the signals. SYSCLK RTC D28 A25 DDR Memory Interface Signals2 I I OV DD OV DD 17 MA[15:0] AH28, AH25, AH6, AH24, AH22, AG13, AG22, AG19, AH21, AH19, AH18, AG16, AH16, AG15, AH15, AH14 AG25, AH13, AH12 AH10, AG7, AH9, AG4 W26, Y26, AB24, AC28, W27, Y28, AB27, AB26 AD27, AE27, AD25, AF25, AC26, AD28, AC25, AD24, AG24, AF23, AE21, AG21, AE24, AE23, AF22, AD21, AH20, AC19, AG18, AF17, AE20, AF20, AE18, AC17, AC13, AD12, AG9, AE9, AD13, AE12, AD10, AC10, AF8, AE8, AD6, AH5, AD9, AH8, AG6, AE6, AF4, AD4, AC3, AC1, AF5, AE5, AD2, AC4, AB1, AB2, Y1, Y6, AB6, AA6, Y3, Y4 AD16, AF16, AC15, AF15, AH17, AE17, AA15, AB15 Y25, AE26, AH23, AD19, AF11, AF7, AE3, AB4, AC16 AA25, AF26, AD22, AD18, AF10, AC7, AD3, AA5, Y15 AA27, AF28, AC22, AF19, AE11, AD7, AE2, AB5, AB16 AG10 AH11 AG12 AF14, AG28, AH3, AD15, AH27, AG2 AF13, AG27, AH2, AD14, AH26, AG1 AB28, AA28, AE28, W28 AD1, AE1 O GVDD MBA[2:0] M CS[0:3] MDQ[0:63] O O I/O GVDD GVDD GVDD MECC[0:7] MDM[0:8] MDQS[0:8] MDQS[0:8] M CAS M WE M RAS MCK[0:5] MCK [0:5] MCKE[0:3] MDIC[0:1] I/O O I/O I/O O O O O O O I/O GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD 18 19 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 4 Freescale Semiconductor Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 MODT[0:3] Package Pin Number AH7, AH4, AG3, AF1 Enhanced Local Bus Signals4 LAD[0:31] AA21, AA22, AA23, Y21, Y22, Y23, Y24, W23, W24, W25, V28, V27, V25, V23, V21, W22, U28, U26, U24, U22, U23, U20, U21, W20, V20, T24, T25, T27, T26, T21, T22, T23 N28, M28, L28, P25 P19 M27 U18 P28 R18 R19 R20 M18 N18 N27 P20 P21 M19, M21, M22, M23, N23, N24, M26, N20, N21, N22 R24, R22, P23, P24, P27 R23 N26 R26 T19 T20 W19 T18 T28 R28 L19 L20 L21 I/O BVDD 20 Pin Type O Power Supply GVDD Notes LDP[0:3]/LA[6:9] LA10/SSI1_TXD LA11/SSI1_TFS LA12/SSI1_TCK LA13/SSI1_RCK LA14/SSI1_RFS LA15/SSI1_RXD LA16/SSI2_TXD LA17/SSI2_TFS LA18/SSI2_TCK LA19/SSI2_RCK LA20/SSI2_RFS LA21/SSI2_RXD LA[22:31] LCS[0:4] LCS5/DMA2_DREQ0 LCS6/DMA2_DACK0 LCS7/DMA2_DDONE0 LWE0/LFWE/LBS0 LWE1/LBS1 LWE2/LBS2 LWE3/LBS3 LBCTL LALE LGPL0/LFCLE LGPL1/LFALE LGPL2/LOE/LFRE I/O O O O O O O O O O O O O O O O O O O O O O O O O O O BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD 20, 23 23 23 23 23 23 23 23 23 23 23 23 20 21 21, 22, 23 21, 23 21, 23 20 20 20 20 20 20 20 20 20 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 5 Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 LGPL3/LFWP LGTA/LFRB/LGPL4/ LUPWAIT/LPBSE LGPL5 LCLK[0:2] L22 L23 L24 R25, M25, L26 DIU/LCD Signals DIU_LD[23:16]/ GPIO1[15:8] DIU_LD[15:0]/ GPIO1[31:16] DIU_VSYNC DIU_HSYNC DIU_DE DIU_CLK_OUT R3, R10, T10, N7, N4, P6, P5, P4 T3, R9, T9, R8, R7, R6, R4, T7, U5, T6, T5, W4, W5, W6, V4, V6 V7 U7 U4 N6 Programmable Interrupt Controller (PIC) IRQ[0:5] IRQ6/DMA1_DREQ0 IRQ7/DMA1_DACK0 IRQ8/DMA1_DDONE0 IRQ9/DMA1_DREQ3 IRQ10/DMA1_DACK3 IRQ11/DMA1_DDONE3 IRQ_OUT MCP SMI L25, J23, K26, E23, K28, K22 G27 J25 J27 H26 J26 K27 K23 A24 B24 I2C Signals IIC1_SDA/GPIO2[10] IIC1_SCL/GPIO2[9] IIC2_SDA/SPISEL/ GPIO2[12] IIC2_SCL/SPICLK/ GPIO2[11] D24 E24 E27 E28 DUART Signals4 UART_SIN0/SPIMOSI/ GPIO2[5] K24 I OV DD 23 I/O I/O I/O I/O OV DD OV DD OV DD OV DD 21, 23, 25 21, 23, 25 21, 23, 25 21, 23, 25 4 Package Pin Number Pin Type O I/O O O Power Supply BVDD BVDD BVDD BVDD Notes 20 24 O O O O O O Signals4 I I I I I I I O I I OV DD OV DD OV DD OV DD OV DD OV DD 5, 23 5, 14, 20, 23 20 20 20 OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD 22, 23 23 23 22, 23 23 23 21, 25 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 6 Freescale Semiconductor Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 UART_SOUT0/SPIMISO UART_CTS0/GPIO2[6] UART_RTS0 UART_SIN1/IR2_RXD/ GPIO2[7] UART_SOUT1/IR2_TXD UART_CTS1/GPIO2[8] UART_RTS1 H25 G24 G26 F25 H24 C23 D23 IrDA Signals4 IR1_TXD/GPIO2[13] IR1_RXD/GPIO2[14] IR_CLKIN IR2_TXD/UART_SOUT1 IR2_RXD/UART_SIN1/ GPIO2[7] F27 E26 F28 H24 F25 SPI Signals SPIMOSI/UART_SIN0/ GPIO2[5] SPIMISO/UART_SOUT0 SPISEL/IIC2_SDA/ GPIO2[12] SPICLK/IIC2_SCL/ GPIO2[11] K24 H25 E27 E28 SSI Signals3, 6 SSI1_RXD/LA15 SSI1_TXD/LA10 SSI1_RFS/LA14 SSI1_TFS/LA11 SSI1_RCK/LA13 SSI1_TCK/LA12 SSI2_RXD/LA21 SSI2_TXD/LA16 SSI2_RFS/LA20 SSI2_TFS/LA17 SSI2_RCK/LA19 R19 P19 R18 M27 P28 U18 P21 R20 P20 M18 N27 I O I/O I/O I/O I/O I O I/O I/O I/O BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD 23 23 23 23 23 23 23 23 23 23 23 I/O I/O I I OV DD OV DD OV DD OV DD 23 23 23 23 O I I O I OV DD OV DD OV DD OV DD OV DD 23 23 23 23 Package Pin Number Pin Type O I O I O I O Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD Notes 23 23 20 23 23 23 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 7 Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 SSI2_TCK/LA18 N18 DMA Signals4 DMA1_DREQ0/IRQ6/ GPIO2[24] DMA1_DREQ3/IRQ9/ GPIO2[26] DMA1_DACK0/IRQ7/ GPIO2[25] DMA1_DACK3/IRQ10/ GPIO2[27] DMA1_DDONE0/IRQ8 DMA1_DDONE3/IRQ11/ GPIO2[28] DMA2_DREQ0/LCS5 G27 H26 J25 J26 J27 K27 R23 I I O O O O I I O O O O General-Purpose Timer Signals4 GTM1_TIN1/GPIO2[15] GTM1_TIN3/GPIO2[21] GTM1_TGATE 1/ GPIO2[16] GTM1_TGATE 3/ GPIO2[22] GTM1_TOUT1/GPIO2[17] GTM1_TOUT3/GPIO2[23] GTM2_TIN1/GPIO2[18] GTM2_TGATE 1/ GPIO2[19] GTM2_TOUT1/GPIO2[20] U3 W2 V2 U1 W3 U2 V1 W1 V3 PCI PCI_AD[31:0] Signals4 I/O OV DD I I I I O O I I O OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD 23 23 23 23 23 23 23 23 23 OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD 22, 23 23 23 23 23 23 23 23 23 23 23 23 Package Pin Number Pin Type I/O Power Supply BVDD Notes 23 DMA2_DREQ3/ GPIO2[29] H27 DMA2_DACK0/LCS6 N26 DMA2_DACK3/ GPIO2[30] H28 DMA2_DDONE0/LCS7 DMA2_DDONE3/ GPIO2[31] R26 J28 M1, M2, M3, M4, M5,M7, L1, L6, J1, K2, K3, K4, K5, K6, K7, H1, H7, G1, G2, G3, G4, G5, G6, F1, F4, F6, F7, F8, D2, D3, E1, E2 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 8 Freescale Semiconductor Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 PCI_C/BE[3:0] PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_PERR PCI_SERR PCI_REQ0 PCI_REQ1/GPIO1[0] PCI_REQ2/GPIO1[2] PCI_REQ3/GPIO1[4] PCI_REQ4/GPIO1[6] PCI_GNT0 PCI_GNT1/GPIO1[1] PCI_GNT2/GPIO1[3] PCI_GNT3/GPIO1[5] PCI_GNT4/GPIO1[7] PCI_CLK Package Pin Number L2, J2, H6, F2 H5 J3 J6 J5 E4 J7 L5 H2 H3 N3 N1 P3 P1 P2 N2 T1 T2 R1 R2 C1 SerDes 1 Signals SD1_TX[3:0] SD1_TX[3:0] SD1_RX[3:0] SD1_RX[3:0] SD1_REF_CLK SD1_REF_CLK SD1_PLL_TPD SD1_PLL_TPA SD1_IMP_CAL_TX SD1_IMP_CAL_RX J13, G12, F10, H9 H13, F12, G10, J9 B9, D8, D5, B4 A9, C8, C5, A4 A7 B7 C7 B6 E11 B3 SerDes 2 Signals O O I I I I O Analog Analog Analog X1VDD X1VDD S1VDD S1VDD S1VDD S1VDD X1VDD S1VDD X1VDD S1VDD 9, 10 9, 11 7 8 Pin Type I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD 23 23 23 23 23 23 23 23 Notes MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 9 Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 SD2_TX[7:0] SD2_TX[7:0] SD2_RX[7:0] SD2_RX[7:0] SD2_REF_CLK SD2_REF_CLK SD2_PLL_TPD SD2_PLL_TPA SD2_IMP_CAL_TX SD2_IMP_CAL_RX Package Pin Number F22, J21, F20, H19, J17, G16, H15, G14 G22, H21, G20, J19, H17, F16, J15, F14 B22, D21, B20, D19, C15, B14, C13, A12 A22, C21, A20, C19, D15, A14, D13, B12 A18 B18 D17 C17 E21 B11 System Control Signals4 HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT B23 J22 A26 C27 F24 Power Management Signals4 ASLEEP B26 Debug Signals4 TRIG_IN TRIG_OUT/READY/ QUIESCE MSRCID[0:4] MDVAL CLK_OUT K20 C28 Y20, AB23, AB20, AB21, AC23 AC20 G28 Test LSSD_MODE TEST_MODE[0:1] G23 K12, K10 JTAG Signals4 TCK TDI TDO TMS D26 B25 D27 C25 I I O I OV DD OV DD OV DD OV DD 27 18 27 Signals4 I I OV DD OV DD 26 26 I O O O O OV DD OV DD BVDD BVDD OV DD 14 14, 20 20 18 O OV DD 20 I O I I O OV DD OV DD OV DD OV DD OV DD 21, 25 Pin Type O O I I I I O Analog Analog Analog Power Supply X2VDD X2VDD S2VDD S2VDD S2VDD S2VDD X2VDD S2VDD X2VDD S2VDD 9, 10 9, 11 7 8 Notes MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 10 Freescale Semiconductor Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 TRST A28 Additional Analog Signals TEMP_ANODE TEMP_CATHODE C11 C10 Thermal Thermal Special Connection Requirement Pins No Connects B1, B10, C2, C3, E22, F18, G11, G18, H8, H11, H14, J11, AA1, AA2, AA3, AA4 Power and Ground Signals MV REF OVDD AE14 C24, C26, D1, E25, F3, G7, G25, H4, J24, K1, L4, L7, N5, P10, P7, T4, T8, V5, V8 DDR2 reference voltage LCD, general purpose timer, PCI, MPIC, I2C, DUART, IrDA, SPI, DMA, system control, clocking, debug, test, JTAG, & power management I/O supply DDR SDRAM I/O supply GVDD/2 OV DD — — 16 — — Package Pin Number Pin Type I Power Supply OV DD Notes 27 GV DD Y2, Y16, AA7, AA24, AA26, AB14, AB17, AC2, AC5, AC6, AC9, AC12, AC18, AC21, AC24, AC27, AE4, AE7, AE10, AE13, AE16, AE19, AE22, AE25, AF2, AG5, AG8, AG11, AG14, AG17, AG20, AG23, AG26, AH1 L27, M20, M24, P18, P22, P26, U19, U27, V24, W21, AA20 A3, A10, B5, B8, D4, D7 GVDD BVDD S1VDD eLBC & SSI I/O voltage Receiver and SerDes core power supply for port 1 Receiver and SerDes core power supply for port 2 Transmitter power supply for SerDes port 1 Transmitter power supply for SerDes port 2 BVDD S1VDD S2VDD A11, A15, A19, A23, B13, B17, B21, C14, C18, D12, D16, D20 S2VDD X1VDD F11, G9, H12, J10, K13 X1VDD X2VDD F13, F17, F21, G15, G19, H18, H22, J16, J20 X2VDD MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 11 Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 L1VDD K14 Package Pin Number Pin Type Digital logic power supply for SerDes port 1 Digital logic power supply for SerDes port 2 Core voltage supply Power Supply L1VDD Notes L2VDD K16, K18 L2VDD VDD_Core L8, L10, M9, M11, M13, M15, N8, N10, N12, N14, N16, P9, P11, P13, P15, R12, R14, R16, T11, T13, T15, U10, U12, U14, U16, V9, V11, V13, V15, W8, W10, W12, W14, W16, Y9, Y11, Y13, Y7, AA8, AA10, AA12, AB9, AB11, AC8 L12, L14, L16, L18, M17, P17, T17, V17, V19, W18, Y17, Y19, AA18 A27 B28 A2 A6 A16 AC11 AB12 B2, B27, D25, E3, F26, F5, G8, H23, J4, K25, L11, L13, L15, L17, L3, L9, M10, M12, M14, M16, M6, M8, N11, N13, N15, N17, N19, N25, N9, P12, P14, P16, P8, R11, R13, R15, R17, R21, R27, R5, T12, T14, T16, U11, U13, U15, U17, U25, U6, U8, U9, V10, V12, V14, V16, V18, V22, V26, W11, W13, W15, W17, W7, W9, Y10, Y12, Y14, Y18, Y27, Y5, Y8, AA11AA13, AA14, AA16, AA17, AA19, AA9, AB10, AB13, AB18, AB19, AB22, AB25, AB3, AB7, AB8, AC14, AD11, AD17, AD20, AD23, AD26, AD5, AD8, AE15, AF12, AF18, AF21, AF24, AF27, AF3, AF6, AF9 C6 VDD_Core VDD_PLAT AVDD_Core AVDD_PLAT AVDD_PCI SD1AV DD SD2AV DD SENSEVDD SENSEVSS GND Platform supply voltage Core PLL supply Platform PLL supply VDD_PLAT AVDD_Core AVDD_PLAT AVDD_PCI SD1AVDD SD2AVDD VDD_Core sensing pin Core GND sensing pin GND 28 28 SD1AGND SerDes port 1 ground pin for SD1AVDD SerDes port 2 ground pin for SD2AVDD SD2AGND B16 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 12 Freescale Semiconductor Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 SGND Package Pin Number A5, A8, A13, A17, A21, B15, B19, C4, C9, C12, C16, C20, C22, D6, D9, D10, D11, D14, D18, D22, E5, E6, E7, E8, E9, E10, E13, E14, E15, E16, E17, E18, E19, E20 E12, F9, F15, F19, F23, G13, G17, G21, H10, H16, H20, J8, J12, J14, J18, K8, K9, K11, K15, K17, K19, K21 Pin Type Ground pins for SVDD Power Supply Notes XGND Ground pins for XVDD Reset Configuration Signals15 LAD[0:31] cfg_gpinout[0:31] AA21, AA22, AA23, Y21, Y22, Y23, Y24, W23, W24, W25, V28, V27, V25, V23, V21, W22, U28, U26, U24, U22, U23, U20, U21, W20, V20, T24, T25, T27, T26, T21, T22, T23 P19 M23, N23 N24 R6, M26, N20, N21, N22 T19 T20, W19, T18 T28, R28, L21, W4 — BVDD LA10/SSI1_TXD cfg_ssi_la_sel LA[25:26] cfg_elbc_clkdiv[0:1] LA27 cfg_cpu_boot DIU_LD[10], LA[28:31] cfg_sys_pll[0:4] LWE0/LFWE/LBS0 cfg_pci_speed LWE/LBS[1:3] cfg_host_agt[0:2] LBCTL, LALE, LGPL2/LOE/LFRE, DIU_LD4 cfg_core_pll[0:3] LGPL0/LFCLE cfg_net2_div LGPL1/LFALE cfg_pci_clk LGPL3/LFWP, LGPL5 cfg_boot_seq[0:1] DIU_LD[0] cfg_elbc_ecc DIU_LD[7:9] cfg_io_ports[0:2] DIU_LD[11:12] cfg_dram_type[0:1] — — — — — — — BVDD BVDD BVDD BVDD BVDD BVDD BVDD L19 L20 L22, L24 V6 U5, T7, R4 R7, R8 — — — — — — BVDD BVDD BVDD OV DD OV DD OV DD 12 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 13 Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 DIU_DE, DIU_LD[13:15] cfg_rom_loc[0:3] DIU_VSYNC cfg_pci_impd DIU_HSYNC cfg_pci_arb UART_RTS0 cfg_wdt_en ASLEEP cfg_core_speed MSRCID0 cfg_mem_debug Package Pin Number U4, T9, R9, T3 V7 U7 G26 B26 Y20 Pin Type — — — — — — Power Supply OV DD OV DD OV DD OV DD OV DD BVDD 13 Notes MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 14 Freescale Semiconductor Pin Assignments and Reset States Table 1. Signal Reference by Functional Block (continued) Name1 MDVAL cfg_boot_vector AC20 Package Pin Number Pin Type — Power Supply BVDD Notes Notes: 1. Multi-pin signals such as LDP[0:3] have their physical package pin numbers listed in order corresponding to the signal names. 2. Stub series terminated logic type pins. 3. All SSI signals are multiplexed with eLBC signals. 4. Low voltage transistor-transistor logic (LVTTL) type pins. 5. DIU_LD[23:16] = RED[7:0] DIU_LD[15:8] = GREEN[7:0] DIU_LD[7:0] = BLUE[7:0] 6. The pins for the SSI interface on the device are multiplexed with certain eLBC signals, which have the ability to operate at a different voltage than the other standard I/O signals. If the device is configured such that the eLBC uses a different voltage than standard I/O and an SSI port on the device is used, then level shifters are required on the SSI signals to ensure they correctly interface to other devices on the board at the proper voltage. 7. This pin should be pulled to ground with a 100-Ω resistor. 8. This pin should be pulled to ground with a 200-Ω resistor. 9. These pins should be left floating. 10.This is a SerDes PLL/DLL digital test signal and is only for factory use. 11.This is a SerDes PLL/DLL analog test signal and is only for factory use. 12.This pin should be pulled down if the platform frequency is 400 MHz or below. 13.This pin should be pulled down if the core frequency is 800 MHz or below. 14.MSRCID[1:2], DIU_LD[5:6] and TRIG_OUT/READY should NOT be pulled down (or driven low) during reset.15. The pins in this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 16.These pins should be left floating. 17.Must be tied low if unused. 18.This output is actively driven during reset rather than being tri-stated during reset. 19.MDIC[0] should be connected to ground with an 18-Ω resistor ± 1-Ω and MDIC[1] should be connected to GVDD with an 18-Ω resistor ± 1-Ω. These pins are used for automatic calibration of the DDR IOs. 20.This pin is a reset configuration pin and appears again in the Reset Configuration Signals section of this table. See the Reset Configuration Signals section of this table for config name and connection details. 21.Recommend a weak pull-up resistor (1–10 kΩ) be placed from this pin to its power supply. 22.This multiplexed pin has input status in one mode and output in another. 23.This pin is a multiplexed signal for different functional blocks and appears more than once in this table. 24.For systems which boot from local bus (GPCM)-controlled flash, a pullup on LGPL4 is required. 25.This pin is open drain signal. 26.These are test signals for factory use only and must be pulled up (100-Ω to 1- kΩ.) to OVDD for normal machine operation. 27.These JTAG pins have weak internal pull-up P-FETs that are always enabled. 28.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve tracking and regulation. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 15 Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications for the MPC8610. The MPC8610 is currently targeted to these specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 2. Absolute Maximum Ratings1 Characteristic Symbol VDD_Core AVDD_Core S1VDD S2VDD X1VDD X2VDD L1VDD L2VDD SD1AVDD SD2AVDD VDD_PLAT AVDD_PCI AVDD_PLAT GVDD BVDD OV DD Recommended Value –0.3 to 1.21 –0.3 to 1.21 –0.3 to 1.21 –0.3 to 1.21 –0.3 to 1.21 –0.3 to 1.21 –0.3 to 1.21 –0.3 to 1.21 –0.3 to 2.75 –0.3 to 3.63 –0.3 to 3.63 Unit V V V V V V V V V V V Notes Table 2 provides the absolute maximum ratings. Core supply voltages Core PLL supply SerDes receiver and core power supply (ports 1 and 2) SerDes transmitter power supply (ports 1 and 2) SerDes digital logic power supply (ports 1 and 2) Serdes PLL supply voltage (ports 1 and 2) Platform supply voltage PCI and platform PLL supply voltage DDR/DDR2 SDRAM I/O supply voltages Local bus and SSI I/O voltage LCD, PCI, general purpose timer, MPIC, IrDA, DUART, DMA, interrupts, system control and clocking, debug, test, JTAG, power management, I2C, SPI, and miscellaneous I/O voltage Input voltage DDR/DDR2 SDRAM signals DDR/DDR2 SDRAM reference Local bus I/O voltage LCD, PCI, general purpose, MPIC, IrDA, DUART, DMA, interrupts, system control and clocking, debug, test, JTAG, power management, I2C, SPI and miscellaneous I/O voltage MVIN MVREF BVIN OVIN (GND – 0.3) to (GVDD + 0.3) (GND – 0.3) to (GVDD/2 + 0.3) (GND – 0.3) to (BVDD + 0.3) (GND – 0.3) to (OVDD + 0.3) V V V V 2 2 2 2 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 16 Freescale Semiconductor Electrical Characteristics Table 2. Absolute Maximum Ratings1 (continued) Characteristic Storage temperature range Notes: 1 Symbol TSTG Recommended Value –55 to 150 Unit °C Notes Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2 During run time (M, B, O)V IN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Table 2. 2.1.2 Recommended Operating Conditions Table 3 provides the recommended operating conditions for the MPC8610. Note that the values in Table 3 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. For details on order information and specific operating conditions for parts, see Section 4.3, “Ordering Information.” Table 3. Recommended Operating Conditions Characteristic Core supply voltages Symbol VDD_Core Recommended Value 1.025 ± 50 mV 1.00 ± 50 mV Core PLL supply AVDD_Core 1.025 ± 50 mV 1.00 ± 50 mV SerDes receiver and core power supply (ports 1 and 2) S1VDD S2VDD X1VDD X2VDD L1VDD L2VDD SD1AVDD SD2AVDD VDD_PLAT 1.025 ± 50 mV 1.00 ± 50 mV 1.025 ± 50 mV 1.00 ± 50 mV 1.025 ± 50 mV 1.00 ± 50 mV 1.025 ± 50 mV 1.00 ± 50 mV 1.025 ± 50 mV 1.00 ± 50 mV PCI and platform PLL supply voltage AVDD_PCI AVDD_PLAT GVDD BVDD 1.025 ± 50 mV 1.00 ± 50 mV 2.5 V ± 125 mV, 1.8 V ± 90 mV 3.3 V ± 165 mV 2.5 V ± 125 mV 1.8 V ± 90 mV V V V V V V V V V Unit V Notes 1 2 1, 3 2, 3 1, 4 2 1 2 1 2 1, 3 2, 3 1 2 1, 3 2, 3 5 SerDes transmitter power supply (ports 1 and 2) SerDes digital logic power supply (ports 1 and 2) Serdes PLL supply voltage (ports 1 and 2) Platform supply voltage DDR and DDR2 SDRAM I/O supply voltages Local bus and SSI I/O voltage MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 17 Electrical Characteristics Table 3. Recommended Operating Conditions (continued) Characteristic LCD, PCI, general timer, MPIC, IrDA, DUART, DMA, interrupts, system control and clocking, debug, test, JTAG, power management, I2C, SPI, and miscellaneous I/O voltage Input voltage DDR and DDR2 SDRAM signals DDR and DDR2 SDRAM reference Local Bus I/O voltage LCD, PCI, general purpose timer, MPIC, IrDA, DUART, DMA, interrupts, system control and clocking, debug, test, JTAG, power management, I2C, SPI, and miscellaneous I/O voltage Junction temperature range Symbol OV DD Recommended Value 3.3 V ± 165 mV Unit V Notes 6 MVIN MVREF BVIN OVIN (GND – 0.3) to (GVDD + 0.3) (GND – 0.3) to (GVDD/2 + 0.3) (GND – 0.3) to (BVDD + 0.3) (GND – 0.3) to (OVDD + 0.3) V V 7, 5 7 7 V 7, 6 TJ 0 to 105 –40 to 105 °C 8 Notes: 1 2 3 4 5 6 7 8 Applies to devices marked with a core frequency of 1333 MHz. Refer to Table Part Numbering Nomenclature to determine if the device has been marked for a core frequency of 1333 MHz. Applies to devices marked with a core frequency below 1333 MHz. Refer to Table Part Numbering Nomenclature to determine if the device has been marked for a core frequency below 1333 MHz. AVDD measurements are made at the input of the R/C filter described in Section 3.2.1, “PLL Power Supply Filtering,” and not at the processor pin. PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V. Refer to Section 2.18.4.3, “Differential Receiver (RX) Input Specifications,” for more information. Caution: MVIN must meet the overshoot/undershoot requirements for GVDD as shown in Figure 2. Caution: OVIN must meet the overshoot/undershoot requirements for OVDD as shown in Figure 2. Timing limitations for (M, B, O) VIN and MV REF during regular run time is provided in Figure 2. Applies to devices marked MC8610TxxyyyyMz for extended temperature range. Note that MC8610Txx1333Jz is not offered. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 18 Freescale Semiconductor Electrical Characteristics Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8610. G/O/B/X/SVDD + 20% G/O/B/X/SV DD + 5% VIH G/O/B/X/SVDD VIL GND GND – 0.3 V GND – 0.7 V Note: 1. tCLK references clocks for various functional blocks as follows: For DDR, tCLK references MCK. For LBIU, tCLK references LCLK. For PCI, tCLK references PCI_CLK or SYSCLK. For I2C and JTAG, tCLK references SYSCLK. Not to Exceed 10% of tCLK1 Figure 2. Overshoot/Undershoot Voltage for M/B/OVIN The MPC8610 core voltage must always be provided at nominal VDD_Core (see Table 3 for actual recommended core voltage). Voltage to the external interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD-based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced to each externally supplied MVREF signal (nominally set to GV DD/2) as is appropriate for the (SSTL-18 and SSTL-2) electrical signaling standards. 2.1.3 Output Driver Characteristics Table 4. Output Drive Capability Driver Type Programmable Output Impedance (Ω ) 18 36 (half strength mode) 18 36 (half strength mode) Supply Voltage GVDD = 2.5 V GVDD = 1.8 V Notes 1, 4, 6 1, 5, 6 Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. DDR signals DDR2 signals MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 19 Electrical Characteristics Table 4. Output Drive Capability (continued) Driver Type Local bus Programmable Output Impedance (Ω ) 25 35 45 (default) 45 (default) 125 PCI, DUART, DMA, interrupts, system control and clocking, debug, test, JTAG, power management, and miscellaneous I/O voltage I 2C PCI Express 45 150 100 Supply Voltage BVDD = 3.3 V BVDD = 2.5 V BVDD = 3.3 V BVDD = 2.5 V BVDD = 1.8 V OVDD = 3.3 V OVDD = 3.3 V XVDD = 1.0 V 3 Notes 2 Notes: 1. See the DDR control driver registers in the MPC8610 Integrated Host Processor Reference Manual, for more information. 2. See the POR impedance control register in the MPC8610 Integrated Host Processor Reference Manual, for more information about local bus signals and their drive strength programmability. 3. See Section 1.1, “Pin Assignments,” for details on resistor requirements for the calibration of SDn_IMP_CAL_TX and SDn_IMP_CAL_RX transmit and receive signals. 4. Stub series terminated logic (SSTL-25) type pins. 5. Stub series terminated logic (SSTL-18) type pins. 6. The drive strength of the DDR interface in half strength mode is at Tj = 105°C and at GVDD (min). 2.2 Power Sequencing The MPC8610 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows: The chronological order of power up is: 1. 2. 3. 4. 1. 2. 3. 4. OVDD, BV DD VDD_PLAT, AVDD_PLAT, VDD_Core, AV DD_Core, AVDD_PCI, SnVDD, X nVDD, SDnAVDD (this rail must reach 90% of its value before the rail for GVDD and MVREF reaches 10% of its value) GVDD, MVREF SYSCLK SYSCLK GVDD, MVREF VDD_PLAT, AVDD_PLAT, VDD_Core, AV DD_Core, AVDD_PCI, SnVDD, X nVDD, SDnAVDD ODD, BV DD NOTE AV DD type supplies should be delayed with respect to their source supplies by the RC time constant of the PLL filter circuit described in Section 3.2, “Power Supply Design and Sequencing.” The order of power down is as follows: MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 20 Freescale Semiconductor Electrical Characteristics Figure 3 illustrates the power up sequence as described above. 3.3 V DC Power Supply Voltage 2.5 V OVDD GVDD, = 1.8/2.5 V MVREF 1.8 V VDD_PLAT, AVDD_PLAT AVDD_PCI, SnVDD, XnVDD SDnAVDD VDD_Core, AVDD_Core VDD Stable 100 µs Platform PLL Relock Time3 0 Power Supply Ramp Up 2 SYSCLK8 (not drawn to scale) 9 1.0 V 7 Time HRESET (& TRST) Asserted for 100 μs4 e6005 PLL Reset Configuration Pins Cycles Setup and Hold Time 6 Notes: 1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 3. 2. Ther recommended maximum ramp up time for power supplies is 20 milliseconds. 3. Refer to Section 2.5, “RESET Initialization” for additional information on PLL relock and reset signal assertion timing requirements. 4. Refer to Table 9 for additional information on reset configuration pin setup timing requirements. In addition see Figure 53 regarding HRESET and JTAG connection details including TRST. 5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles. 6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles after HRESET has negated (hold requirement). See Section 2.5, “RESET Initialization,” for more information on setup and hold time of reset configuration signals. 7. The rail for VDD_PLAT, AVDD_PLAT, VDD_Core, AVDD_Core, AV DD_PCI, SnVDD, XnVDD, and SDnAVDD must reach 90% of its value before the rail for GVDD and MVREF reaches 10% of its value. 8. SYSCLK must be driven only AFTER the power for the various power supplies is stable. 9. The reset configuration signals for DRAM types must be valid before HRESET is asserted. Figure 3. MPC8610 Power Up Sequencing MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 21 Electrical Characteristics 2.3 Power Characteristics Table 5. MPC8610 Power Dissipation Core/Platform Frequency (MHz) VDD_Core, VDD_PLAT (V) Junction Temperature (°C) 65 1333/533 1.025 105 Power (Watts) 10.7 12.1 16 65 1066/533 1.00 105 8.4 9.8 13 65 800/400 1.00 105 5.8 7.2 9.5 The power dissipation for the MPC8610 device is shown in Table 5. Power Mode Notes Typical Thermal Maximum Typical Thermal Maximum Typical Thermal Maximum 1, 2 1, 3 1, 4 1, 2 1, 3 1, 4 1, 2 1, 3 1, 4 Notes: 1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include power dissipation for I/O supplies. 2. Typical power is an average value measured at the nominal recommended core voltage (VDD_Core) and 65°C junction temperature (see Table 3) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz with the core at 100% efficiency. This parameter is not 100% tested but periodically sampled. 3. Thermal power is the average power measured at nominal core voltage (V DD_Core) and maximum operating junction temperature (see Table 3) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz on the core and a typical workload on platform interfaces. This parameter is not 100% tested but periodically sampled. 4. Maximum power is the maximum power measured at nominal core voltage (VDD_Core) and maximum operating junction temperature (see Table 3) while running a test which includes an entirely L1-cache-resident, contrived sequence of instructions which keep all the execution units maximally busy on the core. The estimated maximum power dissipation for individual power supplies of the MPC8610 is shown in Table 6. Table 6. MPC8610 Individual Supply Maximum Power Dissipation1 Component Description Core voltage supply Supply Voltage (V) VDD_Core = 1.025 V @ 1333 MHz VDD_Core = 1.00 V @ 1066 MHz Core PLL voltage supply AVDD_Core = 1.025 V @ 1333 MHz AVDD_Core = 1.00 V @ 1066 MHz Platform source supply VDD_PLAT = 1.025 V @ 1333 MHz VDD_PLAT = 1.00 V @ 1066 MHz Est. Power (Watts) 14.0 12.0 0.0125 0.0125 4.5 4.3 Notes MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 22 Freescale Semiconductor Electrical Characteristics Table 6. MPC8610 Individual Supply Maximum Power Dissipation1 (continued) Component Description Platform PLL voltage supply Supply Voltage (V) AVDD_PLAT = 1.025 V @ 1333 MHz AVDD_PLAT = 1.00 V @ 1066 MHz Est. Power (Watts) 0.0125 0.0125 Notes Notes: 1. This is a maximum power supply number which is provided for power supply and board design information. The numbers are based on 100% utilization for each component. The components listed are not expected to have 100% usage simultaneously for all components. Actual numbers may vary based on activity. Note that the production parts should have a total maximum power value based on Table 5. The ‘Est.’ in the Est. Power column is to emphasize that these numbers are based on theoretical estimates. The device is tested to ensure that the sum of all four supplies does not exceed the power stated in Table 5. No specific supply should ever exceed its individual amount estimated in Table 6. 2.3.1 Frequency Derating To reduce power consumption, these devices support frequency derating if the reduced maximum processor core frequency and reduced maximum platform frequency requirements are observed. The reduced maximum processor core frequency, resulting maximum platform frequency and power consumption are provided in Table 7. Only those parameters in Table 7 are affected; all other parameter specifications are unaffected. Table 7. Core Frequency, Platform Frequency and Power Consumption Derating Maximum Rated Core Frequency (Device Marking) 1333J 1066J 800G 1000/400 667/333 1.00 1.00 Maximum Derated Core/Platform Frequency (MHz) VDD_Core, VDD_PLAT (V) Typical Power (Watts) Thermal Power (Watts) Maximum Power (Watts) N/A 8.0 5.0 9.4 6.4 12.5 8.5 2.4 Input Clocks Table 8. SYSCLK DC Electrical Characteristics (OVDD = 3.3 V ± 165 mV) Parameter Symbol VIH VIL IIN Min 2 –0.3 — Max OV DD + 0.3 0.8 ±5 Unit V V μA Table 8 provides the system clock (SYSCLK) DC specifications for the MPC8610. High-level input voltage Low-level input voltage Input current 1 (VIN1 = 0 V or VIN = V DD) Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 23 Electrical Characteristics 2.4.1 System Clock Timing Table 9. SYSCLK AC Timing Specifications Parameter/Condition Symbol fSYSCLK tSYSCLK tKH, tKL tKHK/tSYSCLK — Min 33 7.5 0.6 40 — Typical — — 1.0 — — Max 133 — 1.2 60 ±150 Unit MHz ns ns % ps Notes 1 — 2 3 4, 5 Table 9 provides the system clock (SYSCLK) AC timing specifications for the MPC8610. SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter Notes: All specifications at recommended operating conditions (see Table 3) with OVDD = 3.3 V ± 165 mV. 1. Caution: The platform to SYSCLK clock ratio and e600 core to platform clock ratio settings must be chosen such that the resulting SYSCLK, platform, and e600 (core) frequencies do not exceed their respective maximum or minimum operating frequencies. Refer to Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio” and Section 3.1.3, “e600 Core to MPX/Platform Clock PLL Ratio,” for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.4 and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the short term jitter only and is guaranteed by design. 5. The SYSCLK driver’s closed loop jitter bandwidth should be 400 MHz, cfg_net2_div = 1. Therefore, when operating PCI Express in x8 link width, the MPX platform frequency must be 333-400 MHz with cfg_net2_div = 0 or greater than or equal to 527 MHz with cfg_net2_div = 1. For proper Serial RapidIO operation, the MPX clock frequency must be greater than: 2 × (0.80) × (Serial RapidIO interface frequency) × (Serial RapidIO link width) 64 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 25 Electrical Characteristics 2.4.5 Other Input Clocks For information on the input clocks of other functional blocks of the platform such as SerDes see the specific section of this document. 2.5 RESET Initialization Table 12. RESET Initialization Timing Specifications Parameter/Condition Min 100 3 100 4 2 — Max — — — — — 5 Unit μs SYSCLKs μs SYSCLKs SYSCLKs SYSCLKs 1 2 1 1 1 Notes Table 12 describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8610. Required assertion time of HRESET Minimum assertion time for SRESET Platform PLL input setup time with stable SYSCLK before HRESET negation Input setup time for POR configs (other than PLL config) with respect to negation of HRESET Input hold time for all POR configs (including PLL config) with respect to negation of HRESET Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET Notes: 1. SYSCLK is he primary clock input for the device. 2. This is related to HRESET assertion time. Table 13 provides the PLL lock times. Table 13. PLL Lock Times Parameter/Condition PLL lock times (platform, PCI and e600 core) Min — Max 100 Unit μs Notes 1 Notes: 1. The PLL lock time for the e600 core PLL requires an additional 255 platform clock cycles. 2.6 DDR and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8610. Note that DDR SDRAM is GVDD = 2.5 V and DDR2 SDRAM is GV DD = 1.8 V. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 26 Freescale Semiconductor Electrical Characteristics 2.6.1 DDR SDRAM DC Electrical Characteristics Table 14 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8610 when GVDD(typ) = 1.8 V. Table 14. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.420 V) Output low current (VOUT = 0.280 V) Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL Min 1.71 0.49 × GVDD MVREF – 0.04 MVREF + 0.125 –0.3 –50 –13.4 13.4 Max 1.89 0.51 × GVDD MVREF + 0.04 GVDD + 0.3 MVREF – 0.125 50 — — Unit V V V V V μA mA mA 4 Notes 1 2 3 Notes: 1. GV DD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MV REF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MV REF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV DD. Table 15 provides the DDR capacitance when GVDD(typ) = 1.8 V. Table 15. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF Notes 1 1 Note: 1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = G VDD/2, VOUT (peak-to-peak) = 0.2 V. Table 16 provides the recommended operating conditions for the DDR SDRAM component(s) when GV DD(typ) = 2.5 V. Table 16. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Symbol GVDD MVREF VTT VIH VIL IOZ Min 2.375 0.49 × GVDD MVREF – 0.04 MVREF + 0.15 –0.3 –50 Max 2.625 0.51 × GVDD MVREF + 0.04 GVDD + 0.3 MVREF – 0.15 50 Unit V V V V V μA 4 Notes 1 2 3 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 27 Electrical Characteristics Table 16. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V (continued) Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) IOH IOL –16.2 16.2 — — mA mA Notes: 1. GV DD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MV REF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MV REF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV DD. Table 17 provides the DDR capacitance when GVDD (typ)=2.5 V. Table 17. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF Notes 1 1 Note: 1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V. Table 18 provides the current draw characteristics for MVREF. Table 18. Current Draw Characteristics for MVREF Parameter/Condition Current draw for MVREF Symbol IMVREF Min — Max 500 Unit μA Notes 1 Note: 1. The voltage regulator for MVREF must be able to supply up to 500 μA current. 2.6.2 DDR SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR/DDR2 SDRAM interface. 2.6.2.1 DDR SDRAM Input AC Timing Specifications Table 19. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface Table 19 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ)=1.8 V. At recommended operating conditions. Parameter AC input low voltage AC input high voltage Symbol VIL VIH Min — MVREF + 0.25 Max MVREF – 0.25 — Unit V V MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 28 Freescale Semiconductor Electrical Characteristics Table 20 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V. Table 20. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions. Parameter AC input low voltage AC input high voltage Symbol VIL VIH Min — MVREF + 0.31 Max MVREF – 0.31 — Unit V V Table 21 provides the input AC timing specifications for the DDR SDRAM interface. Table 21. DDR SDRAM Input AC Timing Specifications At recommended operating conditions. Parameter Controller Skew for MDQS—MDQ/MECC 533 MHz 400 MHz 333 MHz Symbol tCISKEW Min Max Unit ps Notes 1, 2 3 –300 –365 –390 300 365 390 Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW = ±(T/4 – abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. 3. Maximum DDR1 frequency is 400 MHz. Minimum DDR2 frequency is 400 MHz. Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW). MCK[n] MCK[n] tMCK MDQS[n] MDQ[x] D0 tDISKEW D1 tDISKEW Figure 4. DDR Input Timing Diagram for tDISKEW MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 29 Electrical Characteristics 2.6.2.2 DDR SDRAM Output AC Timing Specifications Table 22. DDR SDRAM Output AC Timing Specifications At recommended operating conditions. Parameter MCK[n] cycle time, MCK[n]/MCK[n] crossing MCK duty cycle 533 MHz 400 MHz 333 MHz ADDR/CMD output setup with respect to MCK 533 MHz 400 MHz 333 MHz ADDR/CMD output hold with respect to MCK 533 MHz 400 MHz 333 MHz MCS [n] output setup with respect to MCK 533 MHz 400 MHz 333 MHz MCS [n] output hold with respect to MCK 533 MHz 400 MHz 333 MHz MCK to MDQS Skew MDQ/MECC/MDM output setup with respect to MDQS 533 MHz 400 MHz 333 MHz MDQ/MECC/MDM output hold with respect to MDQS 533 MHz 400 MHz 333 MHz MDQS preamble start Symbol1 tMCK tMCKH/tMCK Min 3 47 47 47 Max 10 53 53 53 Unit ns % Notes 2 8 8 tDDKHAS 1.48 1.95 2.40 tDDKHAX 1.48 1.95 2.40 tDDKHCS 1.48 1.95 2.40 tDDKHCX 1.48 1.95 2.40 tDDKHMH tDDKHDS, tDDKLDS 590 700 900 tDDKHDX, tDDKLDX 590 700 900 tDDKHMP –0.5 × tMCK – 0.6 — — — –0.5 × tMCK +0.6 — — — –0.6 — — — 0.6 — — — — — — — — — ns 3 7 ns 3 7 ns 3 7 ns 3 7 ns ps 4 5 7 ps 5 7 ns 6 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 30 Freescale Semiconductor Electrical Characteristics Table 22. DDR SDRAM Output AC Timing Specifications (continued) At recommended operating conditions. Parameter MDQS epilogue end Symbol1 tDDKHME Min –0.6 Max 0.6 Unit ns Notes 6 Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK m emory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8610 Integrated Host Processor Reference Manual, for a description and understanding of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1. 7. Maximum DDR1 frequency is 400 MHz. Minimum DDR2 frequency is 400 MHz. 8. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values. NOTE For the ADDR/CMD setup and hold specifications in Table 22, it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK [n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns MDQS tDDKHMH(min) = –0.6 ns MDQS Figure 5. Timing Diagram for tDDKHMH MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 31 Electrical Characteristics Figure 6 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP Figure 6. DDR SDRAM Output Timing Diagram Figure 7 provides the AC test load for the DDR bus. Output Z0 = 50 Ω GVDD/2 RL = 5 0 Ω Figure 7. DDR AC Test Load 2.7 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8610. 2.7.1 Local Bus DC Electrical Characteristics Table 23. Local Bus DC Electrical Characteristics (BVDD = 3.3 V) Parameter Symbol VIH VIL IIN VOH Min 2 –0.3 — BVDD – 0.2 Max BVDD + 0.3 0.8 ±5 — Unit V V μA V Table 23 provides the DC electrical characteristics for the local bus interface operating at BVDD = 3.3 V. High-level input voltage Low-level input voltage Input current (V IN1 = 0 V or VIN = BV DD) High-level output voltage (BVDD = min, IOH = –2 mA) MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 32 Freescale Semiconductor Electrical Characteristics Table 23. Local Bus DC Electrical Characteristics (BVDD = 3.3 V) (continued) Parameter Low-level output voltage (BV DD = min, IOL = 2 mA) Symbol VOL Min — Max 0.2 Unit V Note: 1. The symbol VIN, in this case, represents the BVIN symbol referenced in Table 2 and Table 3. Table 24 provides the DC electrical characteristics for the local bus interface operating at BVDD = 2.5 V DC. Table 24. Local Bus DC Electrical Characteristics (BVDD = 2.5 V) Parameter High-level input voltage Low-level input voltage Input current (VIN 1= Symbol VIH VIL IIN VOH VOL Min 1.70 –0.3 — 2.0 — Max BVDD + 0.3 0.7 ±15 — 0.4 Unit V V μA V V 0 V or VIN = BVDD) High-level output voltage (BVDD = min, IOH = –1 mA) Low-level output voltage (BVDD = min, IOL = 1 mA) Note: 1. The symbol VIN, in this case, represents the BVIN symbol referenced in Table 2 and Table 3. Table 25 provides the DC electrical characteristics for the local bus interface operating at BVDD = 1.8 V. Table 25. Local Bus DC Electrical Characteristics (BVDD = 1.8 V) Parameter High-level input voltage Low-level input voltage Input current (VIN1 = 0 V or VIN = BVDD) High-level output voltage (BVDD = min, IOH = –1 mA) Low-level output voltage (BVDD = min, IOL = 1 mA) Symbol VIH VIL IIN VOH VOL Min 1.3 -0.3 — 1.42 — Max BVDD + 0.3 0.8 ±15 — 0.2 Unit V V μA V V Note: 1. The symbol VIN, in this case, represents the BVIN symbol referenced in Table 2 and Table 3. 2.7.2 Local Bus AC Electrical Specifications Table 26 describes the general timing parameters of the local bus interface at BVDD = 3.3 V, 2.5 V and 1.8 V. For information about the frequency range of local bus see Section 3.1.1, “Clock Ranges.” Table 26. Local Bus Timing Parameters (BVDD = 3.3 V, 2.5 V and 1.8 V) Parameter Local bus cycle time Local bus duty cycle LCLK[n] skew to LCLK[m] Symbol1 tLBK tLBKH/tLBK tLBKSKEW Min 7.5 45 — Max — 55 100 Unit ns % ps 2, 7 Notes MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 33 Electrical Characteristics Table 26. Local Bus Timing Parameters (BVDD = 3.3 V, 2.5 V and 1.8 V) (continued) Parameter Input setup to local bus clock (except LGTA /LUPWAIT) LGTA/LUPWAIT input setup to local bus clock Input hold from local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD, and LALE Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high Impedance for LAD/LDP Symbol1 tLBIVKH1 tLBIVKL2 tLBIXKH1 tLBIXKL2 tLBOTOT tLBKLOV1 tLBKLOV2 tLBKLOV3 tLBKLOV4 tLBKLOX1 tLBKLOX2 tLBKLOZ1 tLBKLOZ2 Min 4.5 4.3 — — 0.75 — — — — -0.6 -0.6 — — Max — — 0.8 0.7 — 1.1 1.2 1.2 1.4 — — 2.5 2.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 6 6 3 3 Notes 3, 4 3, 4 3, 4 3, 4 5 Note: 1. The symbols used for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state)(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BV DD/2. Skew number is valid only when LCLK[m] and LCLK[n] have the same load. 3. All signals are measured from BVDD/2 of the edge of local bus clock to 0.4 × BV DD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD. 6. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 7. Guaranteed by design. Figure 8 provides the AC test load for the local bus. Output Z0 = 50 Ω BVDD/2 RL = 5 0 Ω Figure 8. Local Bus AC Test Load Figure 9 to Figure 11 show the local bus signals. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 34 Freescale Semiconductor Electrical Characteristics NOTE Output signals are latched at the falling edge of LCLK and input signals are captured at the rising edge of LCLK, with the exception of the LGTA/LUPWAIT signal, which is captured at the falling edge of LCLK. LCLK[n] tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 tLBIVKL2 Input Signal: LGTA tLBIXKL2 LUPWAIT Output Signals: LA[27:31]/LBCTL/LBCKE/LOE / LFCLE/LFALE/LFRE / LFWP/LLWE Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKLOV3 Output (Address) Signal: LAD[0:31] tLBKLOV4 LALE tLBOTOT tLBKLOX2 tLBKLOV1 tLBKLOX1 tLBKLOZ1 tLBKLOV2 tLBKLOZ2 Figure 9. Local Bus Signals MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 35 Electrical Characteristics T1 T3 LCLK GPCM/FCM Mode Output Signals: LCS[0:7]/LWE tLBKLOV1 tLBKLOX1 tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 10. Local Bus Signals, GPCM/UPM/FCM Signals for LCRR[CLKDIV] = 2 (Clock Ratio of 4) MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 36 Freescale Semiconductor Electrical Characteristics T1 T2 T3 T4 LCLK GPCM/FCM Mode Output Signals: LCS[0:7]/LWE tLBKLOV1 tLBKLOX1 tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 11. Local Bus Signals, GPCM/UPM/FCM Signals for LCRR[CLKDIV] = 4 or 8 (Clock Ratio of 8 or 16) 2.8 Display Interface Unit This section describes the DIU DC and AC electrical specifications. 2.8.1 DIU DC Electrical Characteristics Table 27. DIU DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH Min 2 – 0.3 — OV DD – 0.2 Max OVDD + 0.3 0.8 ±5 — Unit V V μA V Table 27 provides the DIU DC electrical characteristics. High-level input voltage Low-level input voltage Input current (V IN1 = 0 V or VIN = VDD) High-level output voltage (OVDD = m n, IOH = –100 μA) MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 37 Electrical Characteristics Table 27. DIU DC Electrical Characteristics (continued) Parameter Low-level output voltage (OVDD = min, IOL = 100 μA) Symbol VOL Min — Max 0.2 Unit V Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3. 2.8.2 DIU AC Timing Specifications Figure 12 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK_OUT signal and active-high polarity of the DIU_HSYNC, DIU_VSYNC, and DIU_DE signals. By default, all control signals and the display data are generated at the rising edge of the internal pixel clock, and the DIU_CLK_OUT output to drive the panel has the same polarity with the internal pixel clock. User can select the polarity of the DIU_HSYNC and DIU_VSYNC signal (via the SYN_POL register), whether active-high or active-low, the default is active-high. The DIU_DE signal is always active-high. tHSP Start of Line tPWH tPCP DIU_CLK_OUT tBPH tSW tFPH DIU_LD Invalid Data 1 1 2 3 DELTA_X Invalid Data DIU_HSYNC DIU_DE Figure 12. TFT DIU/LCD Interface Timing Diagram—Horizontal Sync Pulse MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 38 Freescale Semiconductor Electrical Characteristics Figure 13 depicts the vertical timing (timing of one frame), including both the vertical sync pulse and the data. All parameters shown in the diagram are programmable. Tvsp Tpwv Start of Frame Thsp Tbpv Tsh Tfpv DIU_HSYNC DIU_LD (Line Data) Invalid Data 1 1 2 3 DELTA_Y Invalid Data DIU_VSYNC DIU_DE Figure 13. TFT DIU/LCD Interface Timing Diagram—Vertical Sync Pulse Table 28 shows timing parameters of signals presented in Figure 12 and Figure 13. Table 28. DIU Interface AC Timing Parameters—Pixel Level Parameter Display pixel clock period Symbol tPCP 7.5 (minimum) Value Unit ns Notes 1, 2 HSYNC width HSYNC back porch width HSYNC front porch width Screen width HSYNC (line) period tPWH tBPH tFPH tSW tHSP PW_H × tPCP BP_H × tPCP FP_H × tPCP DELTA_X × tPCP (PW_H + BP_H + DELTA_X + FP_H) × tPCP ns ns ns ns ns VSYNC width HSYNC back porch width HSYNC front porch width Screen height VSYNC (frame) period Notes: 1 2 tPWV tBPV tFPV tSH tVSP PW_V × tHSP BP_V × tHSP FP_V × tHSP DELTA_Y × tHSP (PW_V + BP_V + DELTA_Y + FP_H) × tHSP ns ns ns ns ns Display interface pixel clock period immediate value (in nanoseconds). Display pixel clock frequency must also be less than or equal to 1/3 the platform clock. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 39 Electrical Characteristics The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H, and FP_H parameters are programmed via the HSYN_PARA register; and the PW_V, BP_V, and FP_V parameters are programmed via the VSYN_PARA register. Figure 14 depicts the synchronous display interface timing for access level, and Table 29 lists the timing parameters. tDIUKHOV DIU_HSYNC DIU_VSYNC DIU_DE DIU_LD tDIUKHOX DIU_CLK_OUT tCKH tCKL Figure 14. LCD Interface Timing Diagram—Access Level NOTE The DIU_OUT_CLK edge and phase delay is selectable via the Global Utilities CKDVDR register. Table 29. LCD Interface Timing Parameters—Access Level Parameter LCD interface pixel clock high time LCD interface pixel clock low time LCD interface pixel clock to ouput valid LCD interface output hold from pixel clock Symbol tCKH tCKL tDIUKHOV tDIUKHOX Min 0.35 × tPCP 0.35 × tPCP — tPCP – 2 Typ 0.5 × tPCP 0.5 × tPCP — — Max 0.65 × tPCP 0.65 × tPCP 2 — Unit ns ns ns ns 2.9 I2C I2C DC Electrical Characteristics Table 30. I2C DC Electrical Characteristics This section describes the DC and AC electrical characteristics for the I2C interfaces of the MPC8610. 2.9.1 Table 30 provides the DC electrical characteristics for the I 2C interfaces. At recommended operating conditions with OVDD of 3.3 V ± 5%. Parameter Input high voltage level Input low voltage level Low level output voltage Pulse width of spikes which must be suppressed by the input filter Symbol VIH VIL VOL tI2KHKL Min 0.7 × OV DD –0.3 0 0 Max OVDD + 0.3 0.3 × OV DD 0.2 × OV DD 50 Unit V V V ns Notes 1 2 MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 40 Freescale Semiconductor Electrical Characteristics Table 30. I2C DC Electrical Characteristics (continued) At recommended operating conditions with OVDD of 3.3 V ± 5%. Parameter Input current each I/O pin (input voltage is between 0.1 × OVDD and 0.9 × OVDD(max) Capacitance for each I/O pin Symbol II CI Min –10 — Max 10 10 Unit μA pF Notes 3 Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8610 Integrated Host Processor Reference Manual, for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off. 2.9.2 I2C AC Electrical Specifications Table 31. I2C AC Electrical Specifications Table 31 provides the AC timing parameters for the I2C interfaces. All values refer to VIH (min) and VIL (max) levels (see Table 30). Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data input hold time: CBUS compatible masters I2C bus devices Data ouput delay time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Symbol1 fI2C tI2CL5 tI2CH5 tI2SVKH5 tI2SXKL5 tI2DVKH5 tI2DXKL Min 0 1.3 0.6 0.6 0.6 100 — 02 Max 400 — — — — — — — 0.9 3 C B4 300 300 — — — Unit kHz μs μs μs μs ns μs tI2OVKL tI2CR — 20 + 0.1 μs ns ns μs μs V tI2CF tI2PVKH tI2KHDX VNL 20 + 0.1 Cb4 0.6 1.3 0.1 × OV DD MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 41 Electrical Characteristics Table 31. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 30). Parameter Noise margin at the HIGH level for each connected device (including hysteresis) Symbol1 VNH Min 0.2 × OV DD Max — Unit V Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. As a transmitter, the MPC8610 provides a delay time of at least 300 ns for the SDA signal (referred to the V IHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When MPC8610 acts as the I2C bus master while transmitting, MPC8610 drives both SCL and SDA. As long as the load on SCL and SDA are balanced, MPC8610 would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for MPC8610 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock frequency is 400 kHz and the digital filter sampling rate register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal 16): I2C Source Clock Frequency 533 MHz 400 MHz 333 MHz 266 MHz FDR Bit Setting 0x0A 0x07 0x2A 0x05 Actual FDR Divider Selected 1536 1024 896 704 Actual I2C SCL Frequency Generated 347 kHz 391 kHz 371 kHz 378 kHz For the detail of I2C frequency calculation, refer to Freescale application note AN2919, Determining the I2C Frequency Divider Ratio for SCL. Note that the I2C source clock frequency is equal to the MPX clock frequency for MPC8610. 3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF. 5. Guaranteed by design. Figure 15 provides the AC test load for the I2C. Output Z0 = 50 Ω OVDD/2 RL = 5 0 Ω Figure 15. I2C AC Test Load MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 42 Freescale Semiconductor Electrical Characteristics Figure 16 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF Figure 16. I2C Bus AC Timing Diagram 2.10 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8610. 2.10.1 DUART DC Electrical Characteristics Table 32. DUART DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH VOL Min 2 – 0.3 — OV DD – 0.2 — Max OVDD + 0.3 0.8 ±5 — 0.2 Unit V V μA V V Table 32 provides the DC electrical characteristics for the DUART interface. High-level input voltage Low-level input voltage Input current (V IN1 = 0 V or VIN = VDD) High-level output voltage (OVDD = m n, IOH = –100 μA) Low-level output voltage (OVDD = min, IOL = 100 μA) Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3. 2.10.2 DUART AC Electrical Specifications Table 33. DUART AC Timing Specifications Parameter Value Platform clock/1,048,576 Platform clock/16 16 Unit baud baud — Notes 1 1, 2 1, 3 Table 33 provides the AC timing parameters for the DUART interface. Minimum baud rate Maximum baud rate Oversample rate Notes: 1. Guaranteed by design. 2. Actual attainable baud rate will be limited by the latency of interrupt processing. 3. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 43 Electrical Characteristics 2.11 Fast/Serial Infrared Interfaces (FIRI/SIRI) The fast/serial infrared interfaces (FIRI/SIRI) implements asynchronous infrared protocols (FIR, MIR, SIR) that are defined by IrDA (Infrared Data Association). Refer to http://www.IrDA.org for details on FIR and SIR protocols. 2.12 Synchronous Serial Interface (SSI) This section describes the DC and AC electrical specifications for the SSI interface of the MPC8610. 2.12.1 SSI DC Electrical Characteristics Table 34. SSI DC Electrical Characteristics (3.3 V DC) Parameter Symbol VIH VIL IIN VOH VOL Min 2 –0.3 — BVDD – 0.2 — Max BVDD + 0.3 0.8 ±5 — 0.2 Unit V V μA V V Table 34 provides SSI DC electrical characteristics. High-level input voltage Low-level input voltage Input current (BV IN1 = 0 V or BVIN = BV DD) High-level output voltage (BVDD = min, IOH = –2 mA) Low-level output voltage (BV DD = min, IOL = 2 mA) Note: 1. The symbol BVIN, in this case, represents the BVIN symbol referenced in Table 2 and Table 3. 2.12.2 SSI AC Timing Specifications All timings for the SSI are given for a noninverted serial clock polarity (TSCKP/RSCKP = 0) and a noninverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the following tables and figures. For internal frame sync operation using external clock, the FS timing will be same as that of Tx Data. 2.12.2.1 SSI Transmitter Timing with Internal Clock Table 35. SSI Transmitter with Internal Clock Timing Parameters Parameter Symbol Internal Clock Operation Min Max Unit Table 35 provides the transmitter timing parameters with internal clock. (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS high SS1 SS2 SS3 SS4 SS5 SS10 81.4 36.0 — 36.0 — — — — 6 — 6 15.0 ns ns ns ns ns ns MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 44 Freescale Semiconductor Electrical Characteristics Table 35. SSI Transmitter with Internal Clock Timing Parameters (continued) Parameter (Tx) CK high to FS low (Tx/Rx) internal FS rise time (Tx/Rx) internal FS fall time (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance STXD rise/fall time Symbol SS12 SS14 SS15 SS16 SS17 SS18 SS19 Synchronous Internal Clock Operation SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling Loading SS42 SS43 SS52 10.0 0 — — — 25 ns ns pF Min — — — — — — — Max 15.0 6 6 15.0 15.0 15.0 6 Unit ns ns ns ns ns ns ns Figure 17 provides the SSI transmitter timing with internal clock. SS1 SS2 SSIn_TCK (Output) SS10 SSIn_TFS (Output) SS16 SSIn_TXD (Output) SS43 SS42 SSIn_RXD (Input) Note: SRXD input in synchronous mode only. SS19 SS14 SS15 SS17 SS18 SS12 SS5 SS4 SS3 Figure 17. SSI Transmitter with Internal Clock Timing Diagram 2.12.2.2 SSI Receiver Timing with Internal Clock Table 36. SSI Receiver with Internal Clock Timing Parameters Parameter Symbol Internal Clock Operation Min Max Unit Table 36 provides the receiver timing parameters with internal clock. (Tx/Rx) CK clock period SS1 81.4 — ns MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 45 Electrical Characteristics Table 36. SSI Receiver with Internal Clock Timing Parameters (continued) Parameter (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS high (Rx) CK high to FS low SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low Symbol SS2 SS3 SS4 SS5 SS11 SS13 SS20 SS21 Min 36.0 — 36.0 — — — 10.0 0 Max — 6 — 6 15.0 15.0 — — Unit ns ns ns ns ns ns ns ns Figure 18 provides the SSI receiver timing with internal clock. SS1 SS5 SS2 SSIn_TCK (Output) SS11 SSIn_RFS (Output) SS20 SS21 SSIn_RXD (Input) SS13 SS4 SS3 Figure 18. SSI Receiver with Internal Clock Timing Diagram 2.12.2.3 SSI Transmitter Timing with External Clock Table 37. SSI Transmitter with External Clock Timing Parameters Parameter Symbol External Clock Operation Min Max Unit Table 37 provides the transmitter timing parameters with external clock. (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS high (Tx) CK high to FS low SS22 SS23 SS24 SS25 SS26 SS31 SS33 81.4 36.0 — 36.0 — –10.0 10.0 — — 6.0 — 6.0 15.0 — ns ns ns ns ns ns ns MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 46 Freescale Semiconductor Electrical Characteristics Table 37. SSI Transmitter with External Clock Timing Parameters (continued) Parameter (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance Symbol SS37 SS38 SS39 Synchronous External Clock Operation SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling SRXD rise/fall time SS44 SS45 SS46 10.0 2.0 — — — 6.0 ns ns ns Min — — — Max 15.0 15.0 15.0 Unit ns ns ns Figure 19 provides the SSI transmitter timing with external clock. SS22 SS23 SS25 SS26 SS24 SSIn_TCK (Input) SS31 SSIn_TFS SS33 (Input) SS39 SS37 SSIn_TXD (Output) SS45 SS44 SSIn_RXD (Input) Note: SRXD input in synchronous mode only SS46 SS38 Figure 19. SSI Transmitter with External Clock Timing Diagram 2.12.2.4 SSI Receiver Timing with External Clock Table 38. SSI Receiver with External Clock Timing Parameters Parameter Symbol External Clock Operation Min Max Unit Table 38 provides the receiver timing parameters with external clock. (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period SS22 SS23 SS24 SS25 81.4 36.0 — 36.0 — — 6.0 — ns ns ns ns MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 47 Electrical Characteristics Table 38. SSI Receiver with External Clock Timing Parameters (continued) Parameter (Tx/Rx) CK clock fall time (Rx) CK high to FS high (Rx) CK high to FS low (Tx/Rx) external FS rise time (Tx/Rx) external FS fall time SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low Symbol SS26 SS32 SS34 SS35 SS36 SS40 SS41 Min — –10.0 10.0 — — 10.0 2.0 Max 6.0 15.0 — 6.0 6.0 — — Unit ns ns ns ns ns ns ns Figure 20 provides the SSI receiver timing with external clock. SS22 SS26 SS23 SS25 SS24 SSIn_TCK (Input) SS32 SSIn_RFS (Input) SS35 SS41 SS40 SSIn_RXD (Input) SS36 SS34 Figure 20. SSI Receiver with External Clock Timing Diagram 2.13 Global Timer Module This section describes the DC and AC electrical specifications for the global timer module (GTM) of the MPC8610. 2.13.1 GTM DC Electrical Characteristics Table 39 provides the DC electrical characteristics for the MPC8610 global timer module pins, including GTMn_TINn, GTM n_TOUTn, GTMn_TGATEn, and RTC. Table 39. GTM DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current (V IN1 = 0 V or VIN = VDD) Symbol VIH VIL IIN VOH Min 2 –0.3 — OV DD – 0.2 Max OVDD + 0.3 0.8 ±5 — Unit V V μA V High-level output voltage (OVDD = m in, IOH = –100 μA) MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 48 Freescale Semiconductor Electrical Characteristics Table 39. GTM DC Electrical Characteristics (continued) Parameter Low-level output voltage (OVDD = min, IOL = 100 μA) Symbol VOL Min — Max 0.2 Unit V Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3. 2.13.2 GTM AC Timing Specifications Table 40. GTM Input and Output AC Timing Specification1 Characteristic Symbol2 tGTIWID tGTOWID Min 7.5 12 Unit ns ns Notes 3 Table 40 provides the GTM input and output AC timing specifications. GTM inputs—minimum pulse width GTM outputs—minimum pulse width Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external synchronous logic. Timer inputs are required to be valid for at least tGTIWID ns to ensure proper operation. 3. The minimum pulse width is a function of the MPX/platform clock. The minimum pulse width must be greater than or equal to 4 times the MPX/platform clock period. Figure 21 provides the AC test load for the GTM. Output Z0 = 50 Ω OVDD/2 RL = 5 0 Ω Figure 21. GTM AC Test Load 2.14 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8610. 2.14.1 GPIO DC Electrical Characteristics Table 41. GPIO DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH Min 2 –0.3 — OV DD – 0.2 Max OVDD + 0.3 0.8 ±5 — Unit V V μA V Table 41 provides the DC electrical characteristics for the GPIO. High-level input voltage Low-level input voltage Input current (V IN1 = 0 V or VIN = VDD) High-level output voltage (OVDD = m in, IOH = –100 μA) MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 49 Electrical Characteristics Table 41. GPIO DC Electrical Characteristics (continued) Parameter Low-level output voltage (OVDD = min, IOL = 100 μA) Symbol VOL Min — Max 0.2 Unit V Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3. 2.14.2 GPIO AC Timing Specifications Table 42. GPIO Input and Output AC Timing Specifications1 Characteristic Symbol2 tGPIWID tGPOWID Min 7.5 12 Unit ns ns Notes 3 Table 42 provides the GPIO input and output AC timing specifications. GPIO inputs—minimum pulse width GPIO outputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation. 3. The minimum pulse width is a function of the MPX/platform clock. The minimum pulse width must be greater than or equal to 4 times the MPX/platform clock period. Figure 22 provides the AC test load for the GPIO. Output Z0 = 50 Ω OVDD/2 RL = 5 0 Ω Figure 22. GPIO AC Test Load 2.15 Serial Peripheral Interface (SPI) This section describes the DC and AC electrical specifications for the SPI interface of the MPC8610. 2.15.1 SPI DC Electrical Characteristics Table 43. SPI DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH Min 2 – 0.3 — OV DD – 0.2 Max OVDD + 0.3 0.8 ±5 — Unit V V μA V Table 43 provides the SPI DC electrical characteristics. High-level input voltage Low-level input voltage Input current (V IN1 = 0 V or VIN = VDD) High-level output voltage (OVDD = m n, IOH = –100 μA) MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 50 Freescale Semiconductor Electrical Characteristics Table 43. SPI DC Electrical Characteristics (continued) Parameter Low-level output voltage (OVDD = min, IOL = 100 μA) Symbol VOL Min — Max 0.2 Unit V Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3. 2.15.2 SPI AC Timing Specifications Table 44. SPI AC Timing Specifications1 Characteristic Symbol2 tNIKHOV tNIKHOX tNEKHOV tNEKHOX tNIIVKH tNIIXKH tNEIVKH tNEIXKH 2 4 0 4 2 -0.2 8 Min Max 1 Unit ns ns ns ns ns ns ns ns Table 44 provides the SPI input and output AC timing specifications. SPI outputs valid—master mode (internal clock) delay SPI outputs hold—master mode (internal clock) delay SPI outputs valid—slave mode (external clock) delay SPI outputs hold—slave mode (external clock) delay SPI inputs—master mode (internal clock input setup time SPI inputs—master mode (internal clock input hold time SPI inputs—slave mode (external clock) input setup time SPI inputs—slave mode (external clock) input hold time Notes: 1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal. Timings are measured at the pin. 2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). Figure 23 provides the AC test load for the SPI. Output Z0 = 50 Ω OVDD/2 RL = 5 0 Ω Figure 23. SPI AC Test Load Figure 24 through Figure 25 represent the AC timings from Table 44. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 51 Electrical Characteristics Figure 24 shows the SPI timings in slave mode (external clock). SPICLK (output) tNEIVKH tNEIXKH Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) tNEKHOX tNEKHOV Note: The clock edge is selectable on SPI. Figure 24. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 25 shows the SPI timings in master mode (internal clock). SPICLK (output) tNIIVKH tNIIXKH Input Signals: SPIMISO (See Note) tNIKHOX tNIKHOV Output Signals: SPIMOSI (See Note) Note: The clock edge is selectable on SPI. Figure 25. SPI AC Timing in Master Mode (Internal Clock) Diagram 2.16 PCI Interface This section describes the DC and AC electrical specifications for the PCI bus interface. 2.16.1 PCI DC Electrical Characteristics Table 45. PCI DC Electrical Characteristics1 Parameter Symbol VIH VIL IIN VOH VOL Min 2 –0.3 — OV DD – 0.2 — Max OVDD + 0.3 0.8 ±5 — 0.2 Unit V V μA V V Table 45 provides the DC electrical characteristics for the PCI interface. High-level input voltage Low-level input voltage Input current (V IN 2 = 0 V or VIN = VDD) High-level output voltage (OVDD = m in, IOH = –100 μA) Low-level output voltage (OVDD = min, IOL = 100 μA) Notes: 1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.3 Local Bus Specifications. 2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 52 Freescale Semiconductor Electrical Characteristics 2.16.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input clock. Table 46 provides the PCI AC timing specifications at 66 MHz. Table 46. PCI AC Timing Specifications at 66 MHz Parameter SYSCLK to output valid SYSCLK to output high impedance Input setup to SYSCLK Input hold from SYSCLK REQ64 to HRESET 9 setup time HRESET to REQ64 hold time HRESET high to first FRAME assertion Symbol1 tPCKHOV tPCKHOZ tPCIVKH tPCIXKH tPCRVRH tPCRHRX tPCRHFV Min 1.5 — 3.7 0.8 10 × tSYS 0 10 Max 7.4 14 — — — 50 — Unit ns ns ns ns clocks ns clocks Notes 2, 3, 12 2, 4, 11 2, 5, 10, 13 2, 5, 10, 14 6, 7, 11 7, 11 8, 11 Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OVDD of the signal in question for 3.3-V PCI signaling levels. 4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. Input timings are measured at the pin. 6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values see Section 3.1, “System Clocking.” 7. The setup and hold time is with respect to the rising edge of HRESET. 8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.3 Local Bus Specifications. 9. The reset assertion timing requirement for HRESET is 100 μs. 10.Guaranteed by characterization. 11.Guaranteed by design. 12. The timing parameter tPCKHOV is a minimum of 1.5 ns and a maximum of 7.4 ns rather than the minimum of 2 ns and a maximum of 6 ns in the PCI 2.3 Local Bus Specifications. 13. The timing parameter tPCIVKH is a minimum of 3.7 ns rather than the minimum of 3 ns in the PCI 2.3 Local Bus Specifications. 14. The timing parameter tPCIXKH is a minimum of 0.8 ns rather than the minimum of 0 ns in the PCI 2.3 Local Bus Specifications. Figure 15 provides the AC test load for PCI. Output Z0 = 50 Ω OVDD/2 RL = 5 0 Ω Figure 26. PCI AC Test Load MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 53 Electrical Characteristics Figure 27 shows the PCI input AC timing conditions. CLK tPCIVKH tPCIXKH Input Figure 27. PCI Input AC Timing Measurement Conditions Figure 28 shows the PCI output AC timing conditions. CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output Figure 28. PCI Output AC Timing Measurement Condition 2.17 High-Speed Serial Interfaces (HSSI) The MPC8610 features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. The SerDes1 interface is dedicated for PCI Express (x1/x2/x4) data transfers. The SerDes2 interface is dedicated for PCI Express (x1/x2/x4/x8) data transfers. This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown. 2.17.1 Signal Terms Definition The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 29 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SD n_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B. Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. Single-ended swing The transmitter output signals and the receiver input signals SDn_TX, SD n_TX, SDn_RX, and SDn_RX each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s single-ended swing. Differential output voltage, VOD (or differential output swing): The differential output voltage (or swing) of the transmitter, V OD, is defined as the difference of the two complimentary output voltages: VSDn_TX – VSDn_TX. The VOD value can be either positive or negative. 2. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 54 Freescale Semiconductor Electrical Characteristics 3. Differential input voltage, VID (or differential input swing): The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two complimentary input voltages: V SDn_RX – VSDn_RX. The V ID value can be either positive or negative. Differential peak voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, VDIFFp = |A – B| volts. Differential peak-to-peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A – B to -(A – B) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, VDIFFp-p = 2 * V DIFFp = 2 * |(A – B)| volts, which is twice of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2 * |VOD|. Differential waveform The differential waveform is constructed by subtracting the inverting signal (SD n_TX, for example) from the noninverting signal (SDn_TX, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to Figure 38 as an example for differential waveform. Common mode voltage, Vcm The common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSDn_TX + VSDn_TX)/2 = (A + B)/2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input. Sometimes, it may be even different between the receiver input and driver output circuits within the same component. It’s also referred as the DC offset in some occasion. SDn_TX or SDn_RX 4. 5. 6. 7. A Volts Vcm = (A + B) / 2 SDn_TX or SDn_RX B Volts Differential Swing, VID or VOD = A – B Differential Peak Voltage, VDIFFp = |A – B| Differential Peak-Peak Voltage, V DIFFpp = 2*VDIFFp (not shown) Figure 29. Differential Voltage Definitions for Transmitter or Receiver To illustrate these definitions using real values, consider the case of a CML (current mode logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV, in other words, V OD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (V DIFFp-p) is 1000 mV p-p. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 55 Electrical Characteristics 2.17.2 SerDes Reference Clocks The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD n_REF_CLK and SDn_REF_CLK for PCI Express. The following sections describe the SerDes reference clock requirements and some application information. 2.17.2.1 • • SerDes Reference Clock Receiver Characteristics Figure 30 shows a receiver reference diagram of the SerDes reference clocks. The supply voltage requirements for X nVDD are specified in Table 2 and Table 3. SerDes reference clock receiver reference circuit structure — The SDn_REF_CLK and SD n_REF_CLK are internally AC-coupled differential inputs as shown in Figure 30. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. — The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and single-ended mode description below for further detailed requirements. The maximum average current requirement that also determines the common mode voltage range — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. — This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV. — If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to SGND DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip. The input amplitude requirement — This requirement is described in detail in the following sections. • • 50 Ω SDn_REF_CLK Input Amp SDn_REF_CLK 50 Ω Figure 30. Receiver of SerDes Reference Clocks MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 56 Freescale Semiconductor Electrical Characteristics 2.17.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8610 SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • Differential mode — The input amplitude of the differential clock must be between 400 and 1600 mV differential peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external DCor AC-coupled connection. — For external DC-coupled connection, as described in Section 2.17.2.1, “SerDes Reference Clock Receiver Characteristics,” the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 and 400 mV. Figure 31 shows the SerDes reference clock input requirement for DC-coupled connection scheme. — For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (SGND). Figure 32 shows the SerDes reference clock input requirement for AC-coupled connection scheme. Single-ended mode — The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be between 400 and 800 mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to ground. — The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 33 shows the SerDes reference clock input requirement for single-ended signaling mode. — To meet the input amplitude requirement, the reference clock inputs might need to be DC- or AC-coupled externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use. 200 mV < Input Amplitude or Differential Peak < 800 mV SDn_REF_CLK Vmax < 800 mV 100 mV < Vcm < 400 mV • SDn_REF_CLK Vmin > 0 V Figure 31. Differential Reference Clock Input DC Requirements (External DC-Coupled) 200mV < Input Amplitude or Differential Peak < 800 mV SDn_REF_CLK Vmax < Vcm + 400 mV Vcm SDn_REF_CLK Vmin > Vcm – 400 mV Figure 32. Differential Reference Clock Input DC Requirements (External AC-Coupled) MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 57 Electrical Characteristics 400 mV < SDn_REF_CLK Input Amplitude < 800 mV SDn_REF_CLK 0V SDn_REF_CLK Figure 33. Single-Ended Reference Clock Input DC Requirements 2.17.2.3 • • Interfacing With Other Differential Signaling Levels • With on-chip termination to SGND, the differential reference clocks inputs are HCSL (high-speed current steering logic) compatible DC-coupled. Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection. LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. NOTE Figure 34 to Figure 37 are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8610 SerDes reference clock receiver requirement provided in this document. Figure 34 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8610 SerDes reference clock input’s DC requirement. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 58 Freescale Semiconductor Electrical Characteristics HCSL CLK Driver Chip CLK_Out 33 Ω SDn_REF_CLK 50 Ω MPC8610 Clock Driver 33 Ω CLK_Out 100 Ω Differential PWB Trace SerDes Refer. CLK Receiver SDn_REF_CLK 50 Ω Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. Clock driver vendor dependent source termination resistor Figure 34. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only) Figure 35 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver’s common mode voltage is higher than the MPC8610 SerDes reference clock input’s allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component. LVDS CLK Driver Chip CLK_Out 10 nF SDn_REF_CLK 50 Ω MPC8610 Clock Driver 100 Ω Differential PWB Trace SerDes Refer. CLK Receiver CLK_Out 10 nF SDn_REF_CLK 50 Ω Figure 35. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only) Figure 36 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with MPC8610 SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 36 assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140 to 240 Ω depending on clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8610 SerDes reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak). For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 59 Electrical Characteristics which requires R2 = 25 Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. LVPECL CLK Driver Chip SDn_REF_CLK 10 nF 50 Ω MPC8610 CLK_Out R2 Clock Driver R1 100 Ω Differential PWB Trace R2 10 nF SDn_REF_CLK SerDes Refer. CLK Receiver CLK_Out R1 50 Ω Figure 36. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 37 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8610 SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. 33 Ω CLK_Out SDn_REF_CLK 50 Ω MPC8610 Clock Driver 100 Ω Differential PWB Trace SerDes Refer. CLK Receiver 50 Ω SDn_REF_CLK 50 Ω Figure 37. Single-Ended Connection (Reference Only) 2.17.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the transmission line and reduce reflections which are a source of noise to the system. MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 60 Freescale Semiconductor Electrical Characteristics Table 47 describes some AC parameters common to PCI Express protocols. Table 47. SerDes Reference Clock Common AC Parameters At recommended operating conditions with X1VDD or X2VDD = 1.0 V ± 5% and 1.025 V ± 5%. Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage Rising edge rate (SD n_REF_CLK) to falling edge rate (SDn_REF_CLK) matching Symbol Rise Edge Rate Fall Edge Rate VIH VIL Rise-Fall Matching Min 1.0 1.0 +200 — — Max 4.0 4.0 Unit V/ns V/ns mV Notes 2, 3 2, 3 2 2 1, 4 –200 20 mV % Notes: 1. Measurement taken from single ended waveform. 2. Measurement taken from differential waveform. 3. Measured from –200 to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 38. 4. Matching applies to rising edge rate for SD n_REF_CLK and falling edge rate for SDn_REF_CLK . It is measured using a 200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge rate of SDn_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 39. VIH = +200 mV 0.0 V VIL = -200 mV SDn_REF_CLK minus SDn_REF_CLK Figure 38. Differential Measurement Points for Rise and Fall Time SDn_REF_CLK SDn_REF_CLK SDn_REF_CLK SDn_REF_CLK Figure 39. Single-Ended Measurement Points for Rise and Fall Time Matching MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 61 Electrical Characteristics The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based on application usage. Refer to the following sections for detailed information: • Section 2.18.2, “AC Requirements for PCI Express SerDes Clocks” 2.17.3 SerDes Transmitter and Receiver Reference Circuits SD1_TXn or SD2_TXn SD1_RXn or SD2_RXn 50 Ω 50 Ω SD1_TX n or SD2_TX n SD1_RX n or SD2_RX n 50 Ω Figure 40 shows the reference circuits for SerDes data lane’s transmitter and receiver. 50 Ω Transmitter Receiver Figure 40. SerDes Transmitter and Receiver Reference Circuits The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express) in this document based on the application usage:” • Section 2.18, “PCI Express” Note that external AC Coupling capacitor is required for the above serial transmission protocols with the capacitor value defined in specification of each protocol section. 2.18 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8610. 2.18.1 DC Requirements for PCI Express SDn_REF_CLK and SDn_REF_CLK For more information, see Section 2.17.2, “SerDes Reference Clocks.” 2.18.2 AC Requirements for PCI Express SerDes Clocks Table 48. SDn_REF_CLK and SDn_REF_CLK AC Requirements Table 48 lists AC requirements. Symbol tREF tREFCJ tREFPJ REFCLK cycle time Parameter Description Min — — –50 Typ 10 — — Max — 100 50 Units ns ps ps REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles Phase jitter. Deviation in edge location with respect to mean edge location MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 62 Freescale Semiconductor Electrical Characteristics 2.18.3 Clocking Dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance. 2.18.4 Physical Layer Specifications The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the transport and data link layer, use the PCI Express Base Specification, Rev. 1.0a. 2.18.4.1 Differential Transmitter (TX) Output Table 49 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins. Table 49. Differential Transmitter (TX) Output Specifications Symbol UI VTX-DIFFp-p Parameter Unit interval Differential peak-to-peak output voltage De- emphasized differential output voltage (ratio) Minimum TX eye width Min 399.88 0.8 Nom 400 Max 400.12 1.2 Units ps V Comments Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations. See Note 1 VTX-DIFFp-p = 2*|VTX-D+ – VTX-D–| See Note 2 VTX-DE-RATIO -3.0 -3.5 -4.0 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. See Note 2 The maximum transmitter jitter can be derived as TTX-MAX-JITTER = 1 – TTX-EYE= 0.3 UI. See Notes 2 and 3 Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes 2 and 3 See Notes 2 and 5 VTX-CM-ACp = RMS(|VTXD+ – VTXD-|/2 – VTX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+ – VTX-D-|/2 See Note 2 |VTX-CM-DC (during LO) – VTX-CM-Idle-DC (During Electrical Idle) |