MC8640THX1000N

Freescale Semiconductor Technical Data Document Number: MPC8640DEC Rev. 1, 11/2008 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications 1 Overview Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . .5 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13 Input Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .17 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . .18 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Ethernet Management Interface Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . .59 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Signal Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 System Design Information . . . . . . . . . . . . . . . . . . . .121 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . .131 Document Revision History. . . . . . . . . . . . . . . . . . . .135 The MPC8640 processor family integrates either one or two Power Architecture™ e600 processor cores with system logic required for networking, storage, wireless infrastructure, and general-purpose embedded applications. The MPC8640 integrates one e600 core while the MPC8640D integrates two cores. This section provides a high-level overview of the MPC8640 and MPC8640D features. When referring to the MPC8640 throughout the document, the functionality described applies to both the MPC8640 and the MPC8640D. Any differences specific to the MPC8640D are noted. Figure 1 shows the major functional units within the MPC8640 and MPC8640D. The major difference between the MPC8640 and MPC8640D is that there are two cores on the MPC8640D. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. © Freescale Semiconductor, Inc., 2008. All rights reserved. Overview e600 Core Block e600 Core 32-Kbyte L1 Instruction Cache 32-Kbyte L1 Data Cache 1-Mbyte L2 Cache e600 Core Block e600 Core 32-Kbyte L1 Instruction Cache 32-Kbyte L1 Data Cache 1-Mbyte L2 Cache MPX Bus MPX Coherency Module (MCM) Platform Bus SDRAM SDRAM ROM, GPIO DDR SDRAM Controller DDR SDRAM Controller Local Bus Controller (LBC) Multiprocessor Programmable Interrupt Controller (MPIC) Dual Universal Asynchronous Receiver/Transmitter (DUART) I2C Controller I2C Controller Enhanced TSEC Controller 10/100/1Gb Enhanced TSEC Controller 10/100/1Gb PCI Express Interface OCeaN Switch Fabric Serial RapidIO Interface or PCI Express Interface Platform IRQs Serial I2C I2C RMII, GMII, MII, RGMII, TBI, RTBI [ x1/x2/x4/x8 PCI Exp (4 GB/s) AND 1x/4x SRIO (2.5 GB/s) ] OR [2-x1/x2/x4/x8 PCI Express (8 GB/S) ] RMII, GMII, MII, RGMII, TBI, RTBI RMII, GMII, MII, RGMII, TBI, RTBI Enhanced TSEC Controller 10/100/1Gb Four-Channel DMA Controller External Control RMII, GMII, MII, RGMII, TBI, RTBI Enhanced TSEC Controller 10/100/1Gb Figure 1. MPC8640 and MPC8640D MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 2 Freescale Semiconductor Overview 1.1 Key Features The following lists an overview of the MPC8640 key feature set: • Major features of the e600 core are as follows: — High-performance, 32-bit superscalar microprocessor that implements the PowerPC ISA — Eleven independent execution units and three register files – Branch processing unit (BPU) – Four integer units (IUs) that share 32 GPRs for integer operands – 64-bit floating-point unit (FPU) – Four vector units and a 32-entry vector register file (VRs) – Three-stage load/store unit (LSU) — Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions, respectively, in a cycle. — Rename buffers — Dispatch unit — Completion unit — Two separate 32-Kbyte instruction and data level 1 (L1) caches — Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache with ECC — 36-bit real addressing — Separate memory management units (MMUs) for instructions and data — Multiprocessing support features — Power and thermal management — Performance monitor — In-system testability and debugging features — Reliability and serviceability • MPX coherency module (MCM) — Ten local address windows plus two default windows — Optional low memory offset mode for core 1 to allow for address disambiguation • Address translation and mapping units (ATMUs) — Eight local access windows define mapping within local 36-bit address space — Inbound and outbound ATMUs map to larger external address spaces — Three inbound windows plus a configuration window on PCI Express — Four inbound windows plus a default window on serial RapidIO — Four outbound windows plus default translation for PCI Express — Eight outbound windows plus default translation for serial RapidIO with segmentation and sub-segmentation support MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 3 Overview • • • • DDR memory controllers — Dual 64-bit memory controllers (72-bit with ECC) — Support of up to a 266 MHz clock rate and a 533 MHz DDR2 SDRAM — Support for DDR, DDR2 SDRAM — Up to 16 Gbytes per memory controller — Cache line and page interleaving between memory controllers. Serial RapidIO interface unit — Supports RapidIO Interconnect Specification, Revision 1.2 — Both 1x and 4x LP-Serial link interfaces — Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) per lane — RapidIO–compliant message unit — RapidIO atomic transactions to the memory controller PCI Express interface — PCI Express 1.0a compatible — Supports x1, x2, x4, and x8 link widths — 2.5 Gbaud, 2.0 Gbps lane Four enhanced three-speed Ethernet controllers (eTSECs) — Three-speed support (10/100/1000 Mbps) — Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers — Support of the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI — — — — — — — Support a full-duplex FIFO mode for high-efficiency ASIC connectivity TCP/IP off-load Header parsing Quality of service support VLAN insertion and deletion MAC address recognition Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III programming models — RMON statistics support — MII management interface for control and status Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts and 48 internal interrupts — Eight global high resolution timers/counters that can generate interrupts — Allows processors to interrupt each other with 32b messages • MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 4 Freescale Semiconductor Electrical Characteristics • • • • • • • • — Support for PCI-Express message-shared interrupts (MSIs) Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 125 MHz — Eight chip selects support eight external slaves Integrated DMA controller — Four-channel controller — All channels accessible by both the local and the remote masters — Supports transfers to or from any local memory or I/O port — Ability to start and flow control each DMA channel from external 3-pin interface Device performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the 8 counters — Supports duration and quantity threshold counting — Burstiness feature that permits counting of burst events with a programmable time between bursts — Triggering and chaining capability — Ability to generate an interrupt on overflow Dual I2C controllers — Two-wire interface — Multiple master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus Boot sequencer — Optionally loads configuration data from serial ROM at reset via the I2C interface — Can be used to initialize configuration registers and/or memory — Supports extended I2C addressing mode — Data integrity checked with preamble signature and CRC DUART — Two 4-wire interfaces (SIN, SOUT, RTS, CTS) — Programming model compatible with the original 16450 UART and the PC16550D IEEE 1149.1-compliant, JTAG boundary scan Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA) 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8640. The MPC8640 is currently targeted to these specifications. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 5 Electrical Characteristics 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1. Absolute Maximum Ratings1 Characteristic Symbol VDD_Core0, VDD_Core1 AVDD_Core0, AVDD_Core1 SVDD XVDD_SRDS1 XVDD_SRDS2 AV DD_SRDS1, AVDD_SRDS2 VDD_PLAT AVDD_LB, AVDD_PLAT D1_GVDD, D2_GVDD LVDD TVDD OVDD Absolute Maximum Value -0.3 to 1.21 V -0.3 to 1.21 V -0.3 to 1.21 V -0.3 to 1.21V -0.3 to 1.21 V -0.3 to 1.21V -0.3 to 1.21V -0.3 to 1.21V -0.3 to 2.75 V -0.3 to 1.98 V -0.3 to 3.63 V -0.3 to 2.75 V Unit Notes V V V V V V V V V V V V V V V 3 3 4 4 4 4 2 Table 1 provides the absolute maximum ratings. Cores supply voltages Cores PLL supply SerDes Transceiver Supply (Ports 1 and 2) SerDes Serial I/O Supply Port 1 SerDes Serial I/O Supply Port 2 SerDes DLL and PLL supply voltage for Port 1 and Port 2 Platform Supply voltage Local Bus and Platform PLL supply voltage DDR and DDR2 SDRAM I/O supply voltages eTSEC 1 and 2 I/O supply voltage eTSEC 3 and 4 I/O supply voltage -0.3 to 3.63 V -0.3 to 2.75 V Local Bus, DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I2C, JTAG and Miscellaneous I/O voltage Input voltage DDR and DDR2 SDRAM signals DDR and DDR2 SDRAM reference Three-speed Ethernet signals DUART, Local Bus, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I2C, JTAG and Miscellaneous I/O voltage -0.3 to 3.63V Dn_MVIN Dn_MVREF LVIN TVIN OV IN - 0.3 to (Dn_GVDD + 0.3) - 0.3 to (Dn_GVDD/2 + 0.3) GND to (LVDD+ 0.3) GND to (TVDD+ 0.3) GND to (OVDD+ 0.3) V V V V 5 5 5 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 6 Freescale Semiconductor Electrical Characteristics Table 1. Absolute Maximum Ratings1 (continued) Characteristic Storage temperature range Symbol TSTG Absolute Maximum Value -55 to 150 Unit Notes °C Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Core 1 characteristics apply only to MPC8640D. If two separate power supplies are used for V DD_Core0 and VDD_Core1, they must be kept within 100 mV of each other during normal run time. 3. The -0.3 to 2.75 V range is for DDR and -0.3 to 1.98 V range is for DDR2. 4. The 3.63V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75V maximum applies. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications” for details on the recommended operating conditions per protocol. 5. During run time (M,L,T,O)VIN and Dn_MVREF m ay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 2.1.2 Recommended Operating Conditions Table 2 provides the recommended operating conditions for the MPC8640. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. For details on order information and specific operating conditions for parts, see Section 21, “Ordering Information.” Table 2. Recommended Operating Conditions Characteristic Cores supply voltages Symbol VDD_Core0, VDD_Core1 AVDD_Core0, AV DD_Core1 SVDD XVDD_SRDS1 XVDD_SRDS2 AVDD_SRDS1, AVDD_SRDS2 VDD_PLAT AVDD_LB, AVDD_PLAT D1_GV DD, D2_GVDD LVDD Recommended Value 1.05 ± 50 mV 0.95 ± 50 mV 1.05 ± 50 mV 0.95 ± 50 mV 1.05 ± 50 mV 1.05 ± 50 mV 1.05 ± 50 mV 1.05 ± 50 mV 1.05 ± 50 mV 1.05 ± 50 mV 2.5 V ± 125 mV 1.8 V ± 90 mV 3.3 V ± 165 mV 2.5 V ± 125 mV V V V V V V V V V 7 7 8 8 V Unit V Notes 1, 2 1, 2, 10 11 10, 11 9 Cores PLL supply SerDes Transceiver Supply (Ports 1 and 2) SerDes Serial I/O Supply Port 1 SerDes Serial I/O Supply Port 2 SerDes DLL and PLL supply voltage for Port 1 and Port 2 Platform Supply voltage Local Bus and Platform PLL supply voltage DDR and DDR2 SDRAM I/O supply voltages eTSEC 1 and 2 I/O supply voltage MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 7 Electrical Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic eTSEC 3 and 4 I/O supply voltage Symbol TVDD OV DD Recommended Value 3.3 V ± 165 mV 2.5 V ± 125 mV Local Bus, DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I2C, JTAG and Miscellaneous I/O voltage Input voltage DDR and DDR2 SDRAM signals DDR and DDR2 SDRAM reference Three-speed Ethernet signals DUART, Local Bus, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I2C, JTAG and Miscellaneous I/O voltage Junction temperature range 3.3 V ± 165 mV Unit V V V Notes 8 8 5 Dn_MV IN Dn_MV REF LVIN TVIN OVIN GND to D n_GVDD Dn_GVDD/2 ± 1% GND to LVDD GND to TVDD GND to OVDD V V V V 3, 6 4, 6 5,6 TJ 0 to 105 -40 to 105 °C 12 Notes: 1. Core 1 characteristics apply only to MPC8640D 2. If two separate power supplies are used for VDD_Core0 and VDD_Core1, they must be at the same nominal voltage and the individual power supplies must be tracked and kept within 100 mV of each other during normal run time. 3. Caution: Dn_MVIN must meet the overshoot/undershoot requirements for Dn_GVDD as shown in Figure 2. 4. Caution: L/TVIN must meet the overshoot/undershoot requirements for L/TVDD as shown in Figure 2 during regular run time. 5. Caution: OVIN must meet the overshoot/undershoot requirements for OVDD as shown in Figure 2 during regular run time. 6. Timing limitations for M,L,T,O)VIN and Dn_MVREF during regular run time is provided in Figure 2 7. The 2.5 V ± 125 mV range is for DDR and 1.8 V ± 90 mV range is for DDR2. 8. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications” for details on the recommended operating conditions per protocol. 9. The PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V. For more information refer to Section 14.4.3, “Differential Receiver (RX) Input Specifications." 10. Applies to Part Number MC8640wxx1067NC only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V devices. Refer to Table 73 Part Numbering Nomenclature to determine if the device has been marked for VDD_Coren = 0.95 V. 11. This voltage is the input to the filter discussed in Section 20.2, “Power Supply Design and Sequencing” and not necessarily the voltage at the AV DD_Coren pin, which may be reduced from VDD_Coren by the filter. 12. Applies to part number MC8640DTxxyyyyaC. Refer to Table 73 Part Numbering Nomenclature to determine if the device has been marked for extended operating temperature range. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 8 Freescale Semiconductor Electrical Characteristics Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8640. L/T/D n_G/O/X/SV DD + 20% L/T/D n_G/O/X/SVDD + 5% VIH L/T/Dn_G/O/X/SVDD GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tCLK1 Note: 1. tCLK references clocks for various functional blocks as follows: DDR n = 10% of Dn_MCK period eTsecn = 10% of EC n_GTX_CLK125 period Local Bus = 10% of LCLK[0:2] period I2C = 10% of SYSCLK JTAG = 10% of SYSCLK Figure 2. Overshoot/Undershoot Voltage for D n_M/O/L/TVIN The MPC8640 core voltage must always be provided at nominal VDD_Coren (See Table 2 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and L/TVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced to each externally supplied Dn_MVREF signal (nominally set to Dn_GVDD/2) as is appropriate for the (SSTL-18 and SSTL-25) electrical signaling standards. 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 9 Electrical Characteristics Table 3. Output Drive Capability Driver Type DDR1 signal DDR2 signal Local Bus signals eTSEC/10/100 signals Programmable Output Impedance (Ω) 18 36 (half strength mode) 18 36 (half strength mode) 45 25 45 30 DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, JTAG and Miscellaneous I/O voltage I2C SRIO, PCI Express 45 Supply Voltage Dn_GVDD = 2.5 V Dn_GVDD = 1.8 V OVDD = 3.3 V T/LVDD = 3.3 V T/LVDD = 2.5 V OVDD = 3.3 V Notes 4, 9 1, 5, 9 2, 6 6 6 6 150 100 OVDD = 3.3 V SVDD = 1.1/1.05 V 7 3, 8 Notes: 1. See the DDR Control Driver registers in the MPC8641D reference manual for more information. 2. Only the following local bus signals have programmable drive strengths: LALE, LAD[0:31], LDP[0:3], LA[27:31], LCKE, LCS[1:2], LWE[0:3], LGPL1, LGPL2, LGPL3, LGPL4, LGPL5, LCLK[0:2]. The other local bus signals have a fixed drive strength of 45 ohms. See the POR Impedance Control register in the MPC8641D reference manual for more information about local bus signals and their drive strength programmability. 3. See Section 17, “Signal Listings” for details on resistor requirements for the calibration of SDn_IMP_CAL_TX and SDn_IMP_CAL_RX transmit and receive signals. 4. Stub Series Terminated Logic (SSTL-25) type pins. 5. Stub Series Terminated Logic (SSTL-18) type pins. 6. Low Voltage Transistor-Transistor Logic (LVTTL) type pins. 7. Open Drain type pins. 8. Low Voltage Differential Signaling (LVDS) type pins. 9. The drive strength of the DDR interface in half strength mode is at Tj = 105C and at Dn_GV DD (min). MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 10 Freescale Semiconductor Electrical Characteristics 2.2 Power Up/Down Sequence The MPC8640 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. NOTE The recommended maximum ramp up time for power supplies is 20 milliseconds. The chronological order of power up is: 1. All power rails other than DDR I/O (Dn_GVDD, and Dn_MVREF). NOTE There is no required order sequence between the individual rails for this item (# 1). However, VDD_PLAT, AVDD_PLAT rails must reach 90% of their recommended value before the rail for Dn_GVDD, and Dn_MVREF (in next step) reaches 10% of their recommended value. AVDD type supplies must be delayed with respect to their source supplies by the RC time constant of the PLL filter circuit described in Section 20.2.1, “PLL Power Supply Filtering”. 2. Dn_GVDD, Dn_MVREF NOTE It is possible to leave the related power supply (Dn_GVDD, Dn_MVREF) turned off at reset for a DDR port that will not be used. Note that these power supplies can only be powered up again at reset for functionality to occur on the DDR port. 3. SYSCLK The recommended order of power down is as follows: 1. Dn_GVDD, Dn_MVREF 2. All power rails other than DDR I/O (Dn_GVDD, Dn_MVREF). NOTE SYSCLK may be powered down simultaneous to either of item # 1 or # 2 in the power down sequence. Beyond this, the power supplies may power down simultaneously if the preservation of DDRn memory is not a concern. See Figure 3 for more details on the Power and Reset Sequencing details MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 11 Electrical Characteristics Figure 3 illustrates the Power Up sequence as described above. 3.3 V If 1 L/TVDD=2.5 V L/T/OVDD DC Power Supply Voltage 2.5 V Dn_GVDD, = 1.8/2.5 V Dn_MVREF VDD_PLAT, AVDD_PLAT AVDD_LB, SVDD, XVDD_SRDSn AVDD_SRDSn VDD_Coren, AVDD_Coren 7 1.8 V 1.2 V 100 µs Platform PLL Relock Time 3 0 Power Supply Ramp Up 2 SYSCLK 8 (not drawn to scale) 9 Time HRESET (& TRST) Asserted for 100 μs after SYSCLK is functional 4 e6005 PLL Reset Configuration Pins Cycles Setup and hold Time 6 Notes: 1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 2. 2. The recommended maximum ramp up time for power supplies is 20 milliseconds. 3. Refer to Section 5, “RESET Initialization” for additional information on PLL relock and reset signal assertion timing requirements. 4. Refer to Table 10 for additional information on reset configuration pin setup timing requirements. In addition see Figure 68 regarding HRESET and JTAG connection details including TRST. 5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles. 6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles after HRESET has negated (hold requirement). See Section 5, “RESET Initialization” for more information on setup and hold time of reset configuration signals. 7. VDD_PLAT, AVDD_PLAT must strictly reach 90% of their recommended voltage before the rail for Dn_GVDD, and Dn_MVREF reaches 10% of their recommended voltage. 8. SYSCLK must be driven only AFTER the power for the various power supplies is stable. 9. In device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER) must be valid BEFORE HRESET is asserted. Figure 3. MPC8640 Power-Up and Reset Sequence MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 12 Freescale Semiconductor Power Characteristics 3 Power Characteristics Table 4. MPC8640D Power Dissipation (Dual Core) Power Mode Typical Thermal Maximum Typical Thermal Maximum Typical Thermal Maximum 1067 MHz 533 MHz 0.95/1.05 V 1000 MHz 500 MHz 1.05 V 1250 MHz 500 MHz 1.05 V Core Frequency (MHz) Platform Frequency (MHz) VDD_Coren, VDD_PLAT (Volts) Junction Temperature 65 oC 105 oC 65 oC 105 oC 65 oC 105 oC Power (Watts) 21.7 27.3 31 18.9 23.8 27 15.7 19.5 22 Notes 1, 2 1, 3 1, 4 1, 2 1, 3 1, 4 1, 2, 5 1, 3, 5 1, 4, 5 The power dissipation for the dual core MPC8640D device is shown in Table 4. Notes: 1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include power dissipation for I/O supplies. 2. Typical power is an average value measured at the nominal recommended core voltage (VDD_Coren) and 65°C junction temperature (see Table 2)while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz with one core at 100% efficiency and the second core at 65% efficiency. 3. Thermal power is the average power measured at nominal core voltage (VDD_Coren) and maximum operating junction temperature (see Table 2) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz on both cores and a typical workload on platform interfaces. 4. Maximum power is the maximum power measured at nominal core voltage (VDD_Coren) and maximum operating junction temperature (see Table 2) while running a test which includes an entirely L1-cache-resident, contrived sequence of instructions which keep all the execution units maximally busy on both cores. 5. These power numbers are for Part Number MC8640Dwxx1067NC and MC8640wxx1067NC only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 13 Input Clocks The power dissipation for the MPC8640 single core device is shown in Table 5. Table 5. MPC8640 Power Dissipation (Single Core) Power Mode Typical Thermal Maximum Typical Thermal Maximum Typical Thermal Maximum Notes: 1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include power dissipation for I/O supplies. 2. Typical power is an average value measured at the nominal recommended core voltage (VDD_Coren) and 65°C junction temperature (see Table 2)while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz. 3. Thermal power is the average power measured at nominal core voltage (VDD_Coren) and maximum operating junction temperature (see Table 2) while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz and a typical workload on platform interfaces. 4. Maximum power is the maximum power measured at nominal core voltage (VDD_Coren) and maximum operating junction temperature (see Table 2) while running a test which includes an entirely L1-cache-resident, contrived sequence of instructions which keep all the execution units maximally busy. 5. These power numbers are for Part Number MC8640Dwxx1067NC and MC8640wxx1067NC only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V. 1067 MHz 533 MHz 0.95 V, 1.05 V 1000 MHz 500 MHz 1.05 V 1250 MHz 500 MHz 1.05 V Core Frequency (MHz) Platform Frequency (MHz) VDD_Coren, VDD_PLAT (Volts) Junction Temperature 65 oC 105 oC 65 C 105 oC 65 oC o Power (Watts) 13.3 16.5 19 11.9 14.8 17 10.1 12.3 Notes 1, 2 1, 3 1, 4 1, 2 1, 3 1, 4 1, 2, 5 1, 3, 5 1, 4, 5 105 oC 14 4 Input Clocks Table 6. SYSCLK DC Electrical Characteristics (OVDD = 3.3 V ± 165 mV.) Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = V DD) Symbol VIH VIL IIN Min 2 –0.3 — Max OVDD + 0.3 0.8 ±5 Unit V V μA Table 6 provides the system clock (SYSCLK) DC specifications for the MPC8640. Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 14 Freescale Semiconductor Input Clocks 4.1 System Clock Timing Table 7. SYSCLK AC Timing Specifications Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8640. At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV. Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter Symbol fSYSCLK tSYSCLK tKH, tKL tKHK/tSYSCLK — Min 66 6 0.6 40 — Typical — — 1.0 — — Max 166.66 — 1.2 60 150 Unit MHz ns ns % ps Notes 1 — 2 3 4, 5 Notes: 1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum operating frequencies. Refer toSection 18.2, “MPX to SYSCLK PLL Ratio”, and Section 18.3, “e600 to MPX clock PLL Ratio”, for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the short term jitter only and is guaranteed by design. 5. The SYSCLK driver’s closed loop jitter bandwidth should be 400 MHz, cfg_plat_freq = 1. Therefore, when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1. For proper Serial RapidIO operation, the MPX clock frequency must be greater than: 2 × (0.80) × (Serial RapidIO interface frequency) × (Serial RapidIO link width) 64 4.5 Other Input Clocks For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document. 5 RESET Initialization This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8640. Table 10 provides the RESET initialization AC timing specifications. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 17 DDR and DDR2 SDRAM Table 10. RESET Initialization Timing Specifications Parameter/Condition Required assertion time of HRESET Minimum assertion time for SRESET_0 & SRESET_1 Platform PLL input setup time with stable SYSCLK before HRESET negation Input setup time for POR configs (other than PLL config) with respect to negation of HRESET Input hold time for all POR configs (including PLL config) with respect to negation of HRESET Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET Min 100 3 100 4 2 — Max — — — — — 5 Unit μs SYSCLKs μs SYSCLKs SYSCLKs SYSCLKs 1 2 1 1 1 Notes Notes: 1. SYSCLK is the primary clock input for the MPC8640. 2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is applied. See the MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset sequence. Table 11 provides the PLL lock times. Table 11. PLL Lock Times Parameter/Condition (Platform and E600) PLL lock times Local bus PLL Min — — Max 100 50 Unit μs μs Notes 1 Notes: 1. The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles. 6 DDR and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8640. Note that DDR SDRAM is Dn_GVDD(typ) = 2.5 V and DDR2 SDRAM is Dn_GVDD(typ) = 1.8 V. 6.1 DDR SDRAM DC Electrical Characteristics Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8640 when Dn_GVDD(typ) = 1.8 V. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 18 Freescale Semiconductor DDR and DDR2 SDRAM Table 12. DDR2 SDRAM DC Electrical Characteristics for Dn_GVDD(typ) = 1.8 V Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.420 V) Output low current (VOUT = 0.280 V) Symbol Dn_GVDD Dn_MVREF VTT VIH VIL IOZ IOH IOL Min 1.71 0.49 × Dn_GVDD Dn_MVREF – 0.0 4 Dn_MVREF+ 0.1 25 –0.3 –50 –13.4 13.4 Max 1.89 0.51 × Dn_GVDD Dn_MVREF + 0.04 Dn_GVDD + 0.3 Dn_MV REF – 0.125 50 — — Unit V V V V V μA mA mA 4 Notes 1 2 3 Notes: 1. Dn_GV DD is expected to be within 50 mV of the DRAM Dn_GVDD at all times. 2. Dn_MV REF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver. Peak-to-peak noise on Dn_MVREF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to Dn_MVREF. This rail should track variations in the DC level of Dn_MVREF. 4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD. Table 13 provides the DDR2 capacitance when Dn_GVDD(typ) = 1.8 V. Table 13. DDR2 SDRAM Capacitance for Dn_GVDD(typ)=1.8 V Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF Notes 1 1 Note: 1. This parameter is sampled. Dn_GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2, VOUT (peak-to-peak) = 0.2 V. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 19 DDR and DDR2 SDRAM Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when Dn_GVDD(typ) = 2.5 V. Table 14. DDR SDRAM DC Electrical Characteristics for Dn_GVDD (typ) = 2.5 V Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) Symbol Dn_GVDD Dn_MVREF VTT VIH VIL IOZ IOH IOL Min 2.375 0.49 × Dn_GVDD Dn_MVREF – 0.04 Dn_MVREF + 0.15 –0.3 –50 –16.2 16.2 Max 2.625 0.51 × Dn_GVDD Dn_MV REF + 0.04 D n_GVDD + 0.3 Dn_MVREF– 0.15 50 — — Unit V V V V V μA mA mA 4 Notes 1 2 3 Notes: 1. Dn_GV DD is expected to be within 50 mV of the DRAM Dn_GVDD at all times. 2. MVREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GV DD DC variations as measured at the receiver. Peak-to-peak noise on Dn_MVREF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to Dn_MVREF. This rail should track variations in the DC level of Dn_MVREF. 4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GV DD. Table 15 provides the DDR capacitance when Dn_GVDD (typ)=2.5 V. Table 15. DDR SDRAM Capacitance for Dn_GVDD (typ) = 2.5 V Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF Notes 1 1 Note: 1. This parameter is sampled. Dn_GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2, VOUT (peak-to-peak) = 0.2 V. Table 16 provides the current draw characteristics for MVREF. Table 16. Current Draw Characteristics for MVREF Parameter / Condition Current draw for MVREF Symbol IMVREF Min — Max 500 Unit μA Note 1 1. The voltage regulator for MVREF must be able to supply up to 500 μA current. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 20 Freescale Semiconductor DDR and DDR2 SDRAM 6.2 DDR SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR SDRAM interface. 6.2.1 DDR SDRAM Input AC Timing Specifications Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface Table 17 provides the input AC timing specifications for the DDR2 SDRAM when Dn_GVDD(typ)=1.8 V. At recommended operating conditions Parameter AC input low voltage AC input high voltage Symbol VIL VIH Min — Dn_MVREF + 0.25 Max Dn_MVREF – 0.25 — Unit V V Notes Table 18 provides the input AC timing specifications for the DDR SDRAM when Dn_GVDD(typ)=2.5 V. Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions. Parameter AC input low voltage AC input high voltage Symbol VIL VIH Min — Dn_MVREF + 0.31 Max Dn_MVREF – 0.31 — Unit V V Notes Table 19 provides the input AC timing specifications for the DDR SDRAM interface. Table 19. DDR SDRAM Input AC Timing Specifications At recommended operating conditions. Parameter Controller Skew for MDQS—MDQ/MECC 533 MHz 400 MHz Symbol tCISKEW Min Max Unit ps Notes 1, 2 3 –300 –365 300 365 Note: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The a mount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW =+/-(T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. 3. Maximum DDR1 frequency is 400 MHz. Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW). MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 21 DDR and DDR2 SDRAM MCK[n] MCK[n] tMCK MDQS[n] MDQ[x] D0 tDISKEW D1 tDISKEW Figure 4. DDR Input Timing Diagram for tDISKEW MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 22 Freescale Semiconductor DDR and DDR2 SDRAM 6.2.2 DDR SDRAM Output AC Timing Specifications Table 20. DDR SDRAM Output AC Timing Specifications At recommended operating conditions. Parameter MCK[n] cycle time, MCK[n]/MCK[n] crossing MCK duty cycle 533 MHz 400 MHz ADDR/CMD output setup with respect to MCK 533 MHz 400 MHz ADDR/CMD output hold with respect to MCK 533 MHz 400 MHz MCS[n] output setup with respect to MCK 533 MHz 400 MHz MCS[n] output hold with respect to MCK 533 MHz 400 MHz MCK to MDQS Skew MDQ/MECC/MDM output setup with respect to MDQS 533 MHz 400 MHz MDQ/MECC/MDM output hold with respect to MDQS 533 MHz 400 MHz MDQS preamble start Symbol 1 tMCK tMCKH/tMCK Min 3 47 47 Max 10 53 53 Unit ns % Notes 2 8 8 tDDKHAS 1.48 1.95 tDDKHAX 1.48 1.95 tDDKHCS 1.48 1.95 tDDKHCX 1.48 1.95 tDDKHMH tDDKHDS, tDDKLDS 590 700 tDDKHDX, tDDKLDX 590 700 tDDKHMP –0.5 × tMCK – 0.6 — — –0.5 × tMCK +0.6 — — –0.6 — — 0.6 — — — — — — ns 3 7 ns 3 7 ns 3 7 ns 3 7 ns ps 4 5 7 ps 5 7 ns 6 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 23 DDR and DDR2 SDRAM Table 20. DDR SDRAM Output AC Timing Specifications (continued) At recommended operating conditions. Parameter MDQS epilogue end Symbol 1 tDDKHME Min –0.6 Max 0.6 Unit ns Notes 6 Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8641 Integrated Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1. 7. Maximum DDR1 frequency is 400 MHz 8. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values. NOTE For the ADDR/CMD setup and hold specifications in Table 20, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 24 Freescale Semiconductor DDR and DDR2 SDRAM Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns MDQS tDDKHMH(min) = –0.6 ns MDQS Figure 5. Timing Diagram for tDDKHMH Figure 6 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP Figure 6. DDR SDRAM Output Timing Diagram MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 25 DUART Figure 7 provides the AC test load for the DDR bus. Output Z0 = 50 Ω Dn_GVDD/2 RL = 5 0 Ω Figure 7. DDR AC Test Load 7 7.1 DUART DUART DC Electrical Characteristics Table 21. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = –100 μA) Low-level output voltage (OVDD = min, IOL = 100 μA) Symbol VIH VIL IIN VOH VOL Min 2 – 0.3 — Max OVDD + 0.3 0.8 ±5 Unit V V μA V This section describes the DC and AC electrical specifications for the DUART interface of the MPC8640. Table 21 provides the DC electrical characteristics for the DUART interface. OVDD – 0.2 — — 0.2 V Note: 1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 7.2 DUART AC Electrical Specifications Table 22 provides the AC timing parameters for the DUART interface. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 26 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 22. DUART AC Timing Specifications Parameter Minimum baud rate Maximum baud rate Oversample rate Value MPX clock/1,048,576 MPX clock/16 16 Unit baud baud — Notes 1,2 1,3 1,4 Notes: 1. Guaranteed by design. 2. MPX clock refers to the platform clock. 3. Actual attainable baud rate will be limited by the latency of interrupt processing. 4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. 8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management This section provides the AC and DC electrical characteristics for enhanced three-speed and MII management. 8.1 Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII and TBI interfaces can be operated at 3.3 or 2.5 V. Whether the GMII or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in Section 9, “Ethernet Management Interface Electrical Characteristics.” 8.1.1 eTSEC DC Electrical Characteristics All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 23 and Table 24. The potential applied to the input of a GMII, MII, TBI, RGMII, RMII or RTBI receiver may exceed the potential of the receiver’s power supply (i.e., a GMII driver powered from a 3.6-V supply driving VOH into a GMII receiver powered from a 2.5-V supply). Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 27 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5. Table 23. GMII, MII, RMII, TBI and FIFO DC Electrical Characteristics Parameter Supply voltage 3.3 V Symbol LVDD TVDD VOH VOL VIH VIL IIH Min 3.135 Max 3.465 Unit V 1, 2 Notes Output high voltage (LV DD/TVDD = Min, IOH = –4.0 mA) Output low voltage (LV DD/TVDD = Min, IOL = 4.0 mA) Input high voltage Input low voltage Input high current (VIN = LVDD, VIN = TVDD) Input low current (VIN = GND) Notes: 1 2 2.40 — V — 0.50 V 2.0 — — — 0.90 40 V V μA 1, 2, 3 IIL –600 — μA 3 LVDD supports eTSECs 1 and 2. TVDD supports eTSECs 3 and 4. 3 The symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2. IN IN IN Table 24. GMII, RGMII, RTBI, TBI and FIFO DC Electrical Characteristics Parameters Supply voltage 2.5 V Symbol LVDD/TVDD Min 2.375 Max 2.625 Unit V 1, 2 Notes Output high voltage (LVDD/TVDD = Min, IOH = –1.0 mA) Output low voltage (LVDD/TVDD = Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (VIN = LVDD, VIN = TVDD) Input low current (VIN = G ND) Note: 1 2 VOH VOL VIH VIL IIH 2.00 — V — 0.40 V 1.70 — — — 0.90 10 V V μA 1, 2, 3 IIL –15 — μA 3 LVDD supports eTSECs 1 and 2. TVDD supports eTSECs 3 and 4. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 28 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management 3 Note that the symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 1 and Table 2. 8.2 FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this section. 8.2.1 FIFO AC Specifications The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI specifications, since they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and source clock in GMII fashion. When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK, while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is relationship between the maximum FIFO speed and the platform speed. For more information see Section 18.4.2, “Platform to FIFO Restrictions” NOTE The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps. A summary of the FIFO AC specifications appears in Table 25 and Table 26. Table 25. FIFO Mode Transmit AC Timing Specification At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%. Parameter/Condition TX_CLK, GTX_CLK clock period (GMII mode) TX_CLK, GTX_CLK clock period (Encoded mode) TX_CLK, GTX_CLK duty cycle TX_CLK, GTX_CLK peak-to-peak jitter Rise time TX_CLK (20%–80%) Fall time TX_CLK (80%–20%) Symbol tFIT tFIT tFITH/tFIT tFITJ tFITR tFITF Min 8.4 6.4 45 — — — Typ 8.0 8.0 50 — — — Max 100 100 55 250 0.75 0.75 Unit ns ns % ps ns ns MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 29 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 25. FIFO Mode Transmit AC Timing Specification (continued) At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%. Parameter/Condition FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time Symbol tFITDV tFITDX Min 2.0 0.5 Typ — — Max — 3.0 Unit ns ns Table 26. FIFO Mode Receive AC Timing Specification At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%. Parameter/Condition RX_CLK clock period (GMII mode) RX_CLK clock period (Encoded mode) RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK 1 Symbol tFIR 1 tFIR 1 Min 8.4 6.4 45 — — — 1.5 0.5 Typ 8.0 8.0 50 — — — — — Max 100 100 55 250 0.75 0.75 — — Unit ns ns % ps ns ns ns ns tFIRH/tFIR tFIRJ tFIRR tFIRF tFIRDV tFIRDX ±100 ppm tolerance on RX_CLK frequency Timing diagrams for FIFO appear in Figure 8 and Figure 9. . tFITF tFIT tFITR GTX_CLK tFITH tFITDV tFITDX TXD[7:0] TX_EN TX_ER Figure 8. FIFO Transmit AC Timing Diagram MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 30 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management tFIRR tFIR RX_CLK tFIRH tFIRF RXD[7:0] RX_DV RX_ER valid data tFIRDV tFIRDX Figure 9. FIFO Receive AC Timing Diagram 8.2.2 GMII AC Timing Specifications This section describes the GMII transmit and receive AC timing specifications. 8.2.2.1 GMII Transmit AC Timing Specifications Table 27. GMII Transmit AC Timing Specifications Table 27 provides the GMII transmit AC timing specifications. At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%. Parameter/Condition GMII data TXD[7:0], TX_ER, TX_EN setup time GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK data clock rise time (20%-80%) GTX_CLK data clock fall time (80%-20%) Symbol 1 tGTKHDV tGTKHDX tGTXR2 tGTXF2 Min 2.5 0.5 — — Typ — — — — Max — 5.0 1.0 1.0 Unit ns ns ns ns Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 31 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 10 shows the GMII transmit AC timing diagram. tGTX GTX_CLK tGTXH TXD[7:0] TX_EN TX_ER tGTKHDX tGTKHDV tGTXF tGTXR Figure 10. GMII Transmit AC Timing Diagram 8.2.2.2 GMII Receive AC Timing Specifications Table 28. GMII Receive AC Timing Specifications Table 28 provides the GMII receive AC timing specifications. At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%. Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time (20%-80%) RX_CLK clock fall time (80%-20%) Symbol 1 tGRX3 tGRXH/tGRX tGRDVKH tGRDXKH tGRXR 2 Min — 40 2.0 0.5 — — Typ 8.0 — — — — — Max — 60 — — 1.0 1.0 Unit ns ns ns ns ns ns tGRXF2 Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. 3. ±100 ppm tolerance on RX_CLK frequency Figure 11 provides the AC test load for eTSEC. Output Z0 = 50 Ω RL = 5 0 Ω LVDD/2 Figure 11. eTSEC AC Test Load MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 32 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 12 shows the GMII receive AC timing diagram. tGRX RX_CLK tGRXH RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH tGRXF tGRXR Figure 12. GMII Receive AC Timing Diagram 8.2.3 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.3.1 MII Transmit AC Timing Specifications Table 29. MII Transmit AC Timing Specifications Table 29 provides the MII transmit AC timing specifications. At recommended operating conditions with L/TVDD of 3.3 V ± 5%. Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise time (20%-80%) TX_CLK data clock fall time (80%-20%) Symbol 1 tMTX2 tMTX tMTXH/tMTX tMTKHDX tMTXR2 tMTXF2 Min — — 35 1 1.0 1.0 Typ 400 40 — 5 — — Max — — 65 15 4.0 4.0 Unit ns ns % ns ns ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. Figure 13 shows the MII transmit AC timing diagram. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 33 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR Figure 13. MII Transmit AC Timing Diagram 8.2.3.2 MII Receive AC Timing Specifications Table 30. MII Receive AC Timing Specifications Table 30 provides the MII receive AC timing specifications. At recommended operating conditions with L/TVDD of 3.3 V ± 5%. Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time (20%-80%) RX_CLK clock fall time (80%-20%) Symbol 1 tMRX2,3 tMRX3 tMRXH/tMRX tMRDVKH tMRDXKH tMRXR2 tMRXF2 Min — — 35 10.0 10.0 1.0 1.0 Typ 400 40 — — — — — Max — — 65 — — 4.0 4.0 Unit ns ns % ns ns ns ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. 3. ±100 ppm tolerance on RX_CLK frequency Figure 14 provides the AC test load for eTSEC. Output Z0 = 50 Ω RL = 5 0 Ω LVDD/2 Figure 14. eTSEC AC Test Load MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 34 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 15 shows the MII receive AC timing diagram. tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKL tMRXF Valid Data tMRXR Figure 15. MII Receive AC Timing Diagram 8.2.4 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 8.2.4.1 TBI Transmit AC Timing Specifications Table 31. TBI Transmit AC Timing Specifications Table 31 provides the TBI transmit AC timing specifications. At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%. Parameter/Condition TCG[9:0] setup time GTX_CLK going high TCG[9:0] hold time from GTX_CLK going high GTX_CLK rise time (20%–80%) GTX_CLK fall time (80%–20%) Symbol 1 tTTKHDV tTTKHDX tTTXR2 tTTXF2 Min 2.0 1.0 — — Typ — — — — Max — — 1.0 1.0 Unit ns ns ns ns Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Guaranteed by design. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 35 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 16 shows the TBI transmit AC timing diagram. tTTX GTX_CLK tTTXH tTTXF TCG[9:0] tTTKHDV tTTKHDX tTTXR tTTXF tTTXR Figure 16. TBI Transmit AC Timing Diagram 8.2.4.2 TBI Receive AC Timing Specifications Table 32. TBI Receive AC Timing Specifications Table 32 provides the TBI receive AC timing specifications. At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%. Parameter/Condition PMA_RX_CLK[0:1] clock period PMA_RX_CLK[0:1] skew PMA_RX_CLK[0:1] duty cycle RCG[9:0] setup time to rising PMA_RX_CLK RCG[9:0] hold time to rising PMA_RX_CLK PMA_RX_CLK[0:1] clock rise time (20%-80%) PMA_RX_CLK[0:1] clock fall time (80%-20%) Symbol 1 tTRX3 tSKTRX tTRXH/tTRX tTRDVKH tTRDXKH tTRXR2 tTRXF2 Min Typ 16.0 Max Unit ns 7.5 40 2.5 1.5 0.7 0.7 — — — — — — 8.5 60 — — 2.4 2.4 ns % ns ns ns ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. 3. ±100 ppm tolerance on PMA_RX_CLK[0:1] frequency MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 36 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 17 shows the TBI receive AC timing diagram. tTRX PMA_RX_CLK1 tTRXH RCG[9:0] tTRDVKH tSKTRX PMA_RX_CLK0 tTRXH tTRDVKH tTRDXKH tTRDXKH tTRXF Valid Data Valid Data tTRXR Figure 17. TBI Receive AC Timing Diagram 8.2.5 TBI Single-Clock Mode AC Specifications When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1 a 125-MHz TBI receive clock is supplied on TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the TSEC_GTX_CLK125 pin in all TBI modes. A summary of the single-clock TBI mode AC specifications for receive appears in Table 33. Table 33. TBI single-clock Mode Receive AC Timing Specification At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%. Parameter/Condition RX_CLK clock period RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) RCG[9:0] setup time to RX_CLK rising edge RCG[9:0] hold time to RX_CLK rising edge 1 Symbol tTRR 1 Min 7.5 40 — — — 2.0 1.0 Typ 8.0 50 — — — — — Max 8.5 60 250 1.0 1.0 — — Unit ns % ps ns ns ns ns tTRRH/tTRR tTRRJ tTRRR tTRRF tTRRDVKH tTRRDXKH ±100 ppm tolerance on RX_CLK frequency MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 37 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management A timing diagram for TBI receive appears in Figure 18. . tTRRR tTRR RX_CLK tTRRH RCG[9:0] tTRRF valid data tTRRDVKH tTRRDXKH Figure 18. TBI Single-Clock Mode Receive AC Timing Diagram 8.2.6 RGMII and RTBI AC Timing Specifications Table 34. RGMII and RTBI AC Timing Specifications Table 34 presents the RGMII and RTBI AC timing specifications. At recommended operating conditions with L/TVDD of 2.5 V ± 5%. Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock period duration 3 Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%–80%) Fall time (80%–20%) 3, 4 2 Symbol 1 tSKRGT5 tSKRGT tRGT5,6 tRGTH/tRGT5 tRGTR5 tRGTF 5 Min –500 1.0 7.2 40 — — Typ 0 — 8.0 50 — — Max 500 2.8 8.8 60 0.75 0.75 Unit ps ns ns % ns ns Notes: 1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5. Guaranteed by characterization 6. ±100 ppm tolerance on RX_CLK frequency MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 38 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams. tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT TX_CLK (At PHY) TX_CTL RXD[8:5][3:0] RXD[7:4][3:0] RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RXD[4] RXDV RXD[9] RXERR tSKRGT RX_CTL RX_CLK (At PHY) Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams 8.2.7 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. 8.2.7.1 RMII Transmit AC Timing Specifications Table 35. RMII Transmit AC Timing Specifications The RMII transmit AC timing specifications are in Table 35. At recommended operating conditions with L/TVDD of 3.3 V ± 5%. Parameter/Condition REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) Symbol 1 tRMT tRMTH/tRMT tRMTJ tRMTR tRMTF Min Typ 20.0 Max Unit ns 35 — 1.0 1.0 50 — — — 65 250 2.0 2.0 % ps ns ns MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 39 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 35. RMII Transmit AC Timing Specifications (continued) At recommended operating conditions with L/TVDD of 3.3 V ± 5%. Parameter/Condition REF_CLK to RMII data TXD[1:0], TX_EN delay Symbol 1 tRMTDX Min 1.0 Typ — Max 10.0 Unit ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 20 shows the RMII transmit AC timing diagram. tRMT REF_CLK tRMTH TXD[1:0] TX_EN TX_ER tRMTDX tRMTF tRMTR Figure 20. RMII Transmit AC Timing Diagram 8.2.7.2 RMII Receive AC Timing Specifications Table 36. RMII Receive AC Timing Specifications At recommended operating conditions with L/TVDD of 3.3 V ± 5%. Parameter/Condition REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge Symbol 1 tRMR tRMRH/tRMR tRMRJ tRMRR tRMRF tRMRDV Min 15.0 35 — 1.0 1.0 4.0 Typ 20.0 50 — — — — Max 25.0 65 250 2.0 2.0 — Unit ns % ps ns ns ns MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 40 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics Table 36. RMII Receive AC Timing Specifications (continued) At recommended operating conditions with L/TVDD of 3.3 V ± 5%. Parameter/Condition RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge Symbol 1 tRMRDX Min 2.0 Typ — Max — Unit ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 21 provides the AC test load for eTSEC. Output Z0 = 50 Ω RL = 5 0 Ω LVDD/2 Figure 21. eTSEC AC Test Load Figure 22 shows the RMII receive AC timing diagram. tRMR REF_CLK tRMRH RXD[1:0] CRS_DV RX_ER tRMRDV tRMRDX tRMRF Valid Data tRMRR Figure 22. RMII Receive AC Timing Diagram 9 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for GMII, RGMII, RMII, TBI and RTBI are specified in “Section 8, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management.” MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 41 Ethernet Management Interface Electrical Characteristics 9.1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 37. Table 37. MII Management DC Electrical Characteristics Parameter Supply voltage (3.3 V) Output high voltage (OVDD = Min, IOH = –1.0 mA) Output low voltage (OVDD =Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (OVDD = Max, VIN 1 = 2.1 V) Input low current (OVDD = Max, VIN = 0.5 V) Symbol OVDD VOH VOL VIH VIL IIH IIL Min 3.135 2.10 Max 3.465 — Unit V V — 0.50 V 1.70 — — — 0.90 40 V V μA μA –600 — Note: 1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 9.2 MII Management AC Electrical Specifications Table 38. MII Management AC Timing Specifications Table 38 provides the MII management AC timing specifications. At recommended operating conditions with OVDD is 3.3 V ± 5%. Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time Symbol 1 fMDC tMDC tMDCH tMDKHDV tMDKHDX tMDDVKH tMDDXKH tMDCR Min 2.5 80 32 16*tMPXCLK 10 5 0 — Typ — — — Max 9.3 400 — Unit MHz ns ns ns Notes 2, 4 5 3, 5 — — — — 16*tMPXCLK — — 10 ns ns ns ns 4 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 42 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics Table 38. MII Management AC Timing Specifications (continued) At recommended operating conditions with OVDD is 3.3 V ± 5%. Parameter/Condition MDC fall time Symbol 1 tMDHF Min — Typ — Max 10 Unit ns Notes 4 Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency divided by 64.) 3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz.) 4. Guaranteed by design. 5. tMPXCLK is the platform (MPX) clock Figure 23 provides the AC test load for eTSEC. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 23. eTSEC AC Test Load NOTE Output will see a 50Ω load since what it sees is the transmission line. Figure 24 shows the MII management AC timing diagram. tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR Figure 24. MII Management Interface Timing Diagram MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 43 Local Bus 10 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8640. 10.1 Local Bus DC Electrical Characteristics Table 39 provides the DC electrical characteristics for the local bus interface operating at OVDD = 3.3 V DC. Table 39. Local Bus DC Electrical Characteristics (3.3 V DC) Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = OVDD) High-level output voltage (OVDD = min, IOH = –2 mA) Low-level output voltage (OVDD = min, IOL = 2 mA) Symbol VIH VIL IIN VOH VOL Min 2 –0.3 — Max OVDD + 0.3 0.8 ±5 Unit V V μA V OVDD – 0.2 — — 0.2 V Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 10.2 Local Bus AC Electrical Specifications Table 40 describes the timing parameters of the local bus interface at OVDD = 3.3 V with PLL enabled. For information about the frequency range of local bus see Section 18.1, “Clock Ranges.” Table 40. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled Parameter Local bus cycle time Local Bus Duty Cycle LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input setup to local bus clock Input hold from local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Symbol 1 tLBK tLBKH/tLBK tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT Min 8 45 — 1.8 1.7 1.0 1.0 1.5 Max — 55 150 — — — — — Unit ns % ps ns ns ns ns ns 7, 8 3, 4 3, 4 3, 4 3, 4 6 Notes 2 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 44 Freescale Semiconductor Local Bus Table 40. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled (continued) Parameter Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Symbol 1 tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOV4 tLBKHOX1 tLBKHOX2 tLBKHOZ1 Min — — — — 0.7 0.7 — Max 2.0 2.2 2.3 2.3 — — 2.5 Unit ns ns ns ns ns ns ns 3 5 3 Notes tLBKHOZ2 — 2.5 ns 5 Note: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode. 3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL bypass mode to 0.4 × OVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is programmed with the LBCR[AHD] parameter. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2. 8. Guaranteed by design. Figure 25 provides the AC test load for the local bus. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 45 Local Bus Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 25. Local Bus AC Test Load Figure 26 to Figure 31 show the local bus signals. LSYNC_IN tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH2 Input Signal: LGTA tLBIXKH2 tLBIXKH1 LUPWAIT Output Signals: LA[27:31]/LBCTL/LBCKE/LOE / LSDA10/LSDWE/LSDRAS / LSDCAS /LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV3 Output (Address) Signal: LAD[0:31] tLBOTOT tLBKHOV4 LALE tLBKHOZ2 tLBKHOX2 tLBKHOV1 tLBKHOZ1 tLBKHOX1 tLBKHOV2 tLBKHOZ2 tLBKHOX2 Figure 26. Local Bus Signals (PLL Enabled) NOTE PLL bypass mode is recommended when LBIU frequency is at or below 83 MHz. When LBIU operates above 83 Mhz, LBIU PLL is recommended to be enabled. Table 41 describes the general timing parameters of the local bus interface at OVDD = 3.3 V with PLL bypassed. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 46 Freescale Semiconductor Local Bus Table 41. Local Bus Timing Parameters—PLL Bypassed Parameter Local bus cycle time Local bus duty cycle Internal launch/capture clock to LCLK delay Input setup to local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input setup to local bus clock Input hold from local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Symbol 1 tLBK tLBKH/tLBK tLBKHKT tLBIVKH1 tLBIVKL2 tLBIXKH1 tLBIXKL2 tLBOTOT tLBKLOV1 tLBKLOV2 tLBKLOV3 tLBKLOV4 tLBKLOX1 tLBKLOX2 tLBKLOZ1 Min 12 45 2.3 5.7 5.6 -1.8 -1.3 1.5 — — — — -3.2 -3.2 — Max — 55 3.9 — — — — — -0.3 -0.1 0 0 — — 0.2 Unit ns % ns ns ns ns ns ns ns ns ns ns ns ns ns 4 4 4 4 4 7 8 4, 5 4, 5 4, 5 4, 5 6 Notes 2 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 47 Local Bus Table 41. Local Bus Timing Parameters—PLL Bypassed (continued) Parameter Local bus clock to output high impedance for LAD/LDP Symbol 1 tLBKLOZ2 Min — Max 0.2 Unit ns Notes 7 Notes: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK by tLBKHKT. 3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BVDD/2. 4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal in question for 3.3-V signaling levels. 5. Input timings are measured at the pin. 6. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Guaranteed by characterization. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 48 Freescale Semiconductor Local Bus Internal launch/capture clock tLBKHKT LCLK[n] tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 tLBIVKL2 Input Signal: LGTA tLBIXKL2 LUPWAIT tLBKLOV1 Output Signals: LA[27:31]/LBCTL/LBCKE/LOE / LSDA10/LSDWE/LSDRAS / LSDCAS /LSDDQM[0:3] tLBKLOV2 Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKLOV3 Output (Address) Signal: LAD[0:31] tLBKLOV4 LALE tLBOTOT tLBKLOX2 tLBKLOX1 tLBKLOZ1 tLBKLOZ2 Figure 27. Local Bus Signals (PLL Bypass Mode) NOTE In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of tLBKHKT. In this mode, signals are launched at the rising edge of the internal clock and are captured at falling edge of the internal clock, with the exception of the LGTA/LUPWAIT signal, which is captured at the rising edge of the internal clock. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 49 Local Bus LSYNC_IN T1 T3 tLBKHOV1 tLBKHOZ1 GPCM Mode Output Signals: LCS [0:7]/LWE GPCM Mode Input Signal: LGTA tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 tLBIXKH1 tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 Input Signals: LAD[0:31]/LDP[0:3] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4) (PLL Enabled) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 50 Freescale Semiconductor Local Bus Internal launch/capture clock T1 T3 LCLK tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKLOX1 tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4) (PLL Bypass Mode) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 51 Local Bus LSYNC_IN T1 T2 T3 T4 tLBKHOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKHOZ1 GPCM Mode Input Signal: LGTA tLBIVKH2 tLBIXKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 Figure 30. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16) (PLL Enabled) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 52 Freescale Semiconductor JTAG Internal launch/capture clock T1 T2 T3 T4 LCLK tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBKLOX1 tLBKLOZ1 GPCM Mode Input Signal: LGTA tLBIVKL2 tLBIXKL2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 31. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16) (PLL Bypass Mode) 11 JTAG This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8640/D. 11.1 JTAG DC Electrical Characteristics Table 42 provides the DC electrical characteristics for the JTAG interface. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 53 JTAG Table 42. JTAG DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = –100 μA) Low-level output voltage (OVDD = min, IOL = 100 μA) Symbol VIH VIL IIN VOH VOL Min 2 – 0.3 — Max OVDD + 0.3 0.8 ±5 Unit V V μA V OVDD – 0.2 — — 0.2 V Note: 1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 11.2 JTAG AC Electrical Specifications Table 43. JTAG AC Timing Specifications (Independent of SYSCLK) 1 Table 43 provides the JTAG AC timing specifications as defined in Figure 33 through Figure 35. At recommended operating conditions (see Table 3). Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO Symbol 2 fJTG t JTG tJTKHKL tJTGR & tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ Min 0 30 15 0 25 4 0 20 25 4 4 30 30 3 3 Max 33.3 — — 2 — — — Unit MHz ns ns ns ns ns Notes 6 3 4 ns — — ns 20 25 ns — — ns 19 9 5, 6 5, 6 5 4 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 54 Freescale Semiconductor JTAG Table 43. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued) At recommended operating conditions (see Table 3). Parameter Symbol 2 Min Max Unit Notes Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 32). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 55 JTAG Figure 32 provides the AC test load for TDO and the boundary-scan outputs. Output Z0 = 50 Ω R L = 50 Ω OVDD/2 Figure 32. AC Test Load for the JTAG Interface Figure 33 provides the JTAG clock input timing diagram. JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF Figure 33. JTAG Clock Input Timing Diagram Figure 34 provides the TRST timing diagram. TRST VM tTRST VM = Midpoint Voltage (OVDD /2) VM Figure 34. TRST Timing Diagram Figure 35 provides the boundary-scan timing diagram. JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OV DD/2) Output Data Valid Input Data Valid VM Figure 35. Boundary-Scan Timing Diagram MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 56 Freescale Semiconductor I2C 12 I2C This section describes the DC and AC electrical characteristics for the I2C interfaces of the MPC8640. 12.1 I2C DC Electrical Characteristics Table 44. I2C DC Electrical Characteristics Table 44 provides the DC electrical characteristics for the I2C interfaces. At recommended operating conditions with OVDD of 3.3 V ± 5%. Parameter Input high voltage level Input low voltage level Low level output voltage Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin (input voltage is between 0.1 × OVDD and 0.9 × OVDD(max) Capacitance for each I/O pin Symbol VIH VIL VOL tI2KHKL II CI Min 0.7 × OV DD –0.3 0 0 –10 — Max OVDD + 0.3 0.3 × OV DD 0.2 × OV DD 50 10 10 Unit V V V ns μA pF Notes 1 2 3 Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8641 Integrated Host Processor Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off. 12.2 I2C AC Electrical Specifications Table 45. I2C AC Electrical Specifications Table 45 provides the AC timing parameters for the I2C interfaces. All values refer to VIH (min) and VIL (max) levels (see Table 44). Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data input hold time: CBUS compatible masters I2C bus devices Rise time of both SDA and SCL signals Symbol 1 fI2C tI2CL 4 tI2CH 4 tI2SVKH 4 tI2SXKL 4 tI2DVKH 4 tI2DXKL Min 0 1.3 0.6 0.6 0.6 100 — 02 Max 400 — — — — — — — 300 Unit kHz μs μs μs μs ns μs ns tI2CR 20 + 0.1 C B5 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 57 I2C Table 45. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 44). Parameter Fall time of both SDA and SCL signals Data output delay time Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Symbol 1 Min 20 + 0.1 Cb 5 — 0.6 1.3 0.1 × OV DD 0.2 × OV DD Max 300 0.9 — — — — 3 Unit ns μs μs μs V V tI2CF tI2OVKL tI2PVKH tI2KHDX VNL VNH Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. As a transmitter, the MPC8640 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When MPC8640 acts as the I2C bus master while transmitting, MPC8640 drives both SCL and SDA. As long as the load on SCL and SDA are balanced, MPC8640 would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for MPC8640 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock frequency is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal 16): I2C Source Clock Frequency 333 MHz 266 MHz 200 MHz 133 MHz FDR Bit Setting 0x2A 0x05 0x26 0x00 Actual FDR Divider Selected 896 704 512 384 378 KHz 390 KHz 346 KHz Actual I2C SCL Frequency Generated 371 KHz For the detail of I2C frequency calculation, refer to the application note AN2919 “Determining the I2C Frequency Divider Ratio for SCL”. Note that the I2C Source Clock Frequency is half of the MPX clock frequency for MPC8640. 3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. Guaranteed by design. 5. CB = capacitance of one bus line in pF. Figure 32 provides the AC test load for the I2C. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 36. I2C AC Test Load Figure 37 shows the AC timing diagram for the I2C bus. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 58 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF Figure 37. I2C Bus AC Timing Diagram 13 High-Speed Serial Interfaces (HSSI) The MPC8640D features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. The SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2 can be used for PCI Express and/or Serial RapidIO data transfers. This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown. 13.1 Signal Terms Definition The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 38 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B. Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. Single-Ended Swing The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a peak-to-peak swing of A - B Volts. This is also referred as each signal wire’s Single-Ended Swing. 2. Differential Output Voltage, VOD (or Differential Output Swing): The Differential Output Voltage (or Swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VSDn_TX - VSDn_TX. The VOD value can be either positive or negative. 3. Differential Input Voltage, VID (or Differential Input Swing): MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 59 High-Speed Serial Interfaces (HSSI) 4. 5. 6. 7. The Differential Input Voltage (or Swing) of the receiver, VID, is defined as the difference of the two complimentary input voltages: VSDn_RX - VSDn_RX. The VID value can be either positive or negative. Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak Voltage, VDIFFp = |A - B| Volts. Differential Peak-to-Peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak-to-Peak Voltage, VDIFFp-p = 2*VDIFFp = 2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2*|VOD|. Differential Waveform The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for example) from the non-inverting signal (SDn_TX, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to Figure 47 as an example for differential waveform. Common Mode Voltage, Vcm The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSDn_TX + VSDn_TX)/2 = (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input. Sometimes, it may be even different between the receiver input and driver output circuits within the same component. It’s also referred as the DC offset in some occasion. A Volts SDn_TX or SDn_RX Vcm = (A + B) / 2 B Volts SDn_TX or SDn_RX Differential Swing, VID or VOD = A - B Differential Peak Voltage, VDIFFp = |A - B| Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown) Figure 38. Differential Voltage Definitions for Transmitter or Receiver MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 60 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p. 13.2 SerDes Reference Clocks The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and SDn_REF_CLK for PCI Express and Serial RapidIO. The following sections describe the SerDes reference clock requirements and some application information. 13.2.1 SerDes Reference Clock Receiver Characteristics Figure 39 shows a receiver reference diagram of the SerDes reference clocks. • The supply voltage requirements for XVDD_SRDSn are specified in Table 1 and Table 2. • SerDes Reference Clock Receiver Reference Circuit Structure — The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 39. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. — The SerDes reference clock input can be either differential or single-ended. Refer to the Differential Mode and Single-ended Mode description below for further detailed requirements. • The maximum average current requirement that also determines the common mode voltage range — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. — This current limitation sets the maximum common mode input voltage to be less than 0.4V (0.4V/50 = 8mA) while the minimum common mode input level is 0.1V above SGND. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA (0-0.8V), such that each phase of the differential input has a single-ended swing from 0V to 800mV with the common mode voltage at 400mV. — If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 ohms to SGND DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 61 High-Speed Serial Interfaces (HSSI) • The input amplitude requirement — This requirement is described in detail in the following sections. 50 Ω SDn_REF_CLK Input Amp SDn_REF_CLK 50 Ω Figure 39. Receiver of SerDes Reference Clocks 13.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8640D SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • Differential Mode — The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external DC-coupled or AC-coupled connection. — For external DC-coupled connection, as described in section 13.2.1, the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV. Figure 40 shows the SerDes reference clock input requirement for DC-coupled connection scheme. — For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (SGND). Figure 41 shows the SerDes reference clock input requirement for AC-coupled connection scheme. • Single-ended Mode — The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be between 400mV and 800mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to ground. — The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows the SerDes reference clock input requirement for single-ended signaling mode. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 62 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) — To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use. SDn_REF_CLK 200mV < Input Amplitude or Differential Peak < 800mV Vmax < 800mV 100mV < Vcm < 400mV SDn_REF_CLK Vmin > 0V Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled) 200mV < Input Amplitude or Differential Peak < 800mV SDn_REF_CLK Vmax < Vcm + 400mV Vcm SDn_REF_CLK Vmin > Vcm − 400mV Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled) 400mV < SDn_REF_CLK Input Amplitude < 800mV SDn_REF_CLK 0V SDn_REF_CLK Figure 42. Single-Ended Reference Clock Input DC Requirements MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 63 High-Speed Serial Interfaces (HSSI) 13.2.3 • • Interfacing With Other Differential Signaling Levels • With on-chip termination to SGND, the differential reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled. Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection. LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. NOTE Figure 43 to Figure 46 below are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it’s very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8640D SerDes reference clock receiver requirement provided in this document. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 64 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8640D SerDes reference clock input’s DC requirement. HCSL CLK Driver Chip CLK_Out 33 Ω SDn_REF_CLK 50 Ω MPC8640D Clock Driver 33 Ω CLK_Out 100 Ω differential PWB trace SerDes Refer. CLK Receiver SDn_REF_CLK 50 Ω Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. Clock driver vendor dependent source termination resistor Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only) Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver’s common mode voltage is higher than the MPC8640D SerDes reference clock input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component. LVDS CLK Driver Chip CLK_Out 10 nF SDn_REF_CLK 50 Ω MPC8640D Clock Driver 100 Ω differential PWB trace SerDes Refer. CLK Receiver CLK_Out 10 nF SDn_REF_CLK 50 Ω Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 65 High-Speed Serial Interfaces (HSSI) Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with MPC8640D SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 45 assumes that the LVPECL clock driver’s output impedance is 50Ω. R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140Ω to 240Ω depending on clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8640D SerDes reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. LVPECL CLK Driver Chip CLK_Out R2 10nF SDn_REF_CLK MPC8640D 50 Ω Clock Driver R1 100 Ω differential PWB trace R2 10nF SDn_REF_CLK SerDes Refer. CLK Receiver CLK_Out R1 50 Ω Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 66 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8640D SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. 33 Ω CLK_Out SDn_REF_CLK 50 Ω MPC8640D Clock Driver 100 Ω differential PWB trace SerDes Refer. CLK Receiver 50 Ω SDn_REF_CLK 50 Ω Figure 46. Single-Ended Connection (Reference Only) 13.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 ohms to match the transmission line and reduce reflections which are a source of noise to the system. Table 46 describes some AC parameters common to PCI Express and Serial RapidIO protocols. Table 46. SerDes Reference Clock Common AC Parameters At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5% and 1.05V ± 5%. Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage Symbol Rise Edge Rate Fall Edge Rate VIH VIL Min 1.0 1.0 +200 — Max 4.0 4.0 Unit V/ns V/ns mV Notes 2, 3 2, 3 2 2 -200 mV MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 67 High-Speed Serial Interfaces (HSSI) Table 46. SerDes Reference Clock Common AC Parameters (continued) At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5% and 1.05V ± 5%. Parameter Rising edge rate (SDn_REF_CLK) to falling edge rate (SD n_REF_CLK) matching Symbol Rise-Fall Matching Min — Max 20 Unit % Notes 1, 4 Notes: 1. Measurment taken from single ended waveform. 2. Measurment taken from differential waveform. 3. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 47. 4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK . It is measured using a 200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of SD n_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 48. VIH = +200 mV 0.0 V VIL = -200 mV SDn_REF_CLK minus SDn_REF_CLK Figure 47. Differential Measurement Points for Rise and Fall Time SDn_REF_CLK SDn_REF_CLK SDn_REF_CLK SDn_REF_CLK Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application usage. Refer to the following sections for detailed information: • Section 14.2, “AC Requirements for PCI Express SerDes Clocks” • Section 15.2, “AC Requirements for Serial RapidIO SDn_REF_CLK and SDn_REF_CLK MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 68 Freescale Semiconductor PCI Express 13.3 SerDes Transmitter and Receiver Reference Circuits Figure 49 shows the reference circuits for SerDes data lane’s transmitter and receiver. SD1_TX n or SD2_TX n SD1_RXn or SD2_RXn 50 Ω 50 Ω SD1_TXn or SD2_TXn SD1_RXn or SD2_RXn 50 Ω 50 Ω Transmitter Receiver Figure 49. SerDes Transmitter and Receiver Reference Circuits The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express or Serial Rapid IO) in this document based on the application usage:” • Section 14, “PCI Express” • Section 15, “Serial RapidIO” Note that external AC Coupling capacitor is required for the above two serial transmission protocols with the capacitor value defined in specification of each protocol section. 14 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8640. 14.1 DC Requirements for PCI Express SDn_REF_CLK and SDn_REF_CLK For more information, see Section 13.2, “SerDes Reference Clocks.” 14.2 AC Requirements for PCI Express SerDes Clocks Table 47. SDn_REF_CLK and SDn_REF_CLK AC Requirements Table 47 lists AC requirements. Symbol tREF tREFCJ tREFPJ REFCLK cycle time Parameter Description Min — –50 Typical 10 — — Max 100 50 Units ns ps ps Notes — — — REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles Phase jitter. Deviation in edge location with respect to mean edge location MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 69 PCI Express 14.3 Clocking Dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance. 14.4 Physical Layer Specifications The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the Transport and Data Link layer please use the PCI EXPRESS Base Specification. REV. 1.0a document. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 70 Freescale Semiconductor PCI Express 14.4.1 Differential Transmitter (TX) Output Table 48 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins. Table 48. Differential Transmitter (TX) Output Specifications Symbol UI Parameter Unit Interval Min 399.88 Nom 400 Max 400.12 Units ps Comments Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1. VTX-DIFFp-p = 2*|V TX-D+ - VTX-D-| See Note 2. VTX-DIFFp-p Differential Peak-to-Peak Output Voltage De- Emphasized Differential Output Voltage (Ratio) Minimum TX Eye Width 0.8 1.2 V VTX-DE-RATIO -3.0 -3.5 -4.0 dB Ratio of the V TX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. See Note 2. The maximum Transmitter jitter can be derived as TTX-MAX-JITTER = 1 - TTX-EYE= 0.3 UI. See Notes 2 and 3. Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes 2 and 3. See Notes 2 and 5 VTX-CM-ACp = RMS(|VTXD+ - VTXD-|/2 - V TX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 See Note 2 |VTX-CM-DC (during LO) - VTX-CM-Idle-DC (During Electrical mV VTX-CM-DC = DC(avg) of |VTX-D+ - VTX-D-|/2 [LO] VTX-CM-Idle-DC = DC (avg) of |VTX-D+ - VTX-D-|/2 [Electrical Idle] See Note 2. Idle)|