MC9328MXSCVP10

Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9328MXS Rev. 3, 12/2006 MC9328MXS MC9328MXS Package Information Plastic Package Case 1304B-01 (MAPBGA–225) Ordering Information See Table 1 on page 3 1 Introduction Contents 1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signals and Connections . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . 16 Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Pin-Out and Package Information . . . . . . . . 71 6 Product Documentation . . . . . . . . . . . . . . . . 73 Contact Information . . . . . . . . . . . . . . . Last Page The i.MX Family of applications processors provides a leap in performance with an ARM9™ microprocessor core and highly integrated system functions. The i.MX family specifically addresses the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities. The MC9328MXS (i.MXS) processor features the advanced and power-efficient ARM920T™ core that operates at speeds up to 100 MHz. Integrated modules, which include a USB device and an LCD controller, support a suite of peripherals to enhance portable products. It is packaged in a 225-contact MAPBGA package. Figure 1 shows the functional block diagram of the i.MXS processor. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2006. All rights reserved. Introduction Figure 1. i.MXS Functional Block Diagram 1.1 • • • • • • • • • • • • • • • • • • Features ARM920T™ Microprocessor Core AHB to IP Bus Interfaces (AIPIs) External Interface Module (EIM) SDRAM Controller (SDRAMC) DPLL Clock and Power Control Module Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2) Serial Peripheral Interface (SPI) Two General-Purpose 32-bit Counters/Timers Watchdog Timer Real-Time Clock/Sampling Timer (RTC) LCD Controller (LCDC) Pulse-Width Modulation (PWM) Module Universal Serial Bus (USB) Device Direct Memory Access Controller (DMAC) Synchronous Serial Interface and an Inter-IC Sound (SSI/I2S) Module Inter-IC (I2C) Bus Module General-Purpose I/O (GPIO) Ports Bootstrap Mode To support a wide variety of applications, the processor offers a robust array of features, including the following: MC9328MXS Technical Data, Rev. 3 2 Freescale Semiconductor Introduction • • • Power Management Features Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O 225-contact MAPBGA Package 1.2 Target Applications The i.MXS applications processor is designed to meet the needs of medical instrumentation, low-end PDAs, point-of-sale terminals, security systems and other applications requiring a basic device based on ARM technology with support for open operating systems. Like other members of the i.MX family, the i.MXS is designed for high performance and low-power to maximize battery life. 1.3 Ordering Information Table 1. i.MXS Ordering Information Package Type 225-contact MAPBGA Frequency 100 MHz Temperature 0OC to 70OC -40OC to 85OC Solderball Type Pb-free Pb-free Order Number MC9328MXSVP10(R2) MC9328MXSCVP10(R2) Table 1 provides ordering information. 1.4 • • • • • • • • Conventions OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. — Active low signals change from logic level one to logic level zero. — Active high signals change from logic level zero to logic level one. Negated means that an asserted discrete signal changes logic state. — Active low signals change from logic level zero to logic level one. — Active high signals change from logic level one to logic level zero. LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal. This document uses the following conventions: • • • MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 3 Signals and Connections 2 Signals and Connections Table 2. i.MXS Signal Descriptions Signal Name Function/Notes External Bus/Chip-Select (EIM) Table 2 identifies and describes the i.MXS processor signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to. A[24:0] D[31:0] EB0 EB1 EB2 EB3 OE CS [5:0] ECB LBA BCLK (burst clock) RW DTACK Address bus signals Data bus signals MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]. Byte Strobe—Active low external enable byte signal that controls D [23:16]. Byte Strobe—Active low external enable byte signal that controls D [15:8]. LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]. Memory Output Enable—Active low output enables external data bus. Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected. Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. Active low signal sent by a flash device causing the external burst device to latch the starting burst address. Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM. DTACK signal—The external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed. Bootstrap BOOT [3:0] System Boot Mode Select—The operational system boot mode of the i.MXS processor upon system reset is determined by the settings of these pins. SDRAM Controller SDBA [4:0] SDIBA [3:0] MA [11:10] MA [9:0] DQM [3:0] CSD0 SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM cycles. SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles. SDRAM address signals SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on SDRAM cycles. SDRAM data enable SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register. MC9328MXS Technical Data, Rev. 3 4 Freescale Semiconductor Signals and Connections Table 2. i.MXS Signal Descriptions (Continued) Signal Name CSD1 Function/Notes SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected, so it can be used as boot chip-select by properly configuring BOOT [3:0] input pins. SDRAM Row Address Select signal SDRAM Column Address Select signal SDRAM Write Enable signal SDRAM Clock Enable 0 SDRAM Clock Enable 1 SDRAM Clock Not Used Clocks and Resets EXTAL16M XTAL16M EXTAL32K XTAL32K CLKO RESET_IN RESET_OUT POR Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut down. Crystal output 32 kHz crystal input 32 kHz crystal output Clock Out signal selected from internal clock signals. Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module and the clock control module) are reset. Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. JTAG TRST TDO TDI TCK TMS Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller. Serial Output for test instructions and data. Changes on the falling edge of TCK. Serial Input for test instructions and data. Sampled on the rising edge of TCK. Test Clock to synchronize test logic and control register access through the JTAG port. Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of TCK. DMA DMA_REQ BIG_ENDIAN DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY. Big Endian—Input signal that determines the configuration of the external chip-select space. If it is driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven logic-low at reset, the external chip-select space will be configured to little endian. This input must not change state after power-on reset negates or during chip operation. RAS CAS SDWE SDCKE0 SDCKE1 SDCLK RESET_SF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 5 Signals and Connections Table 2. i.MXS Signal Descriptions (Continued) Signal Name ETM ETMTRACESYNC ETMTRACECLK ETMPIPESTAT [2:0] ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM mode. Function/Notes ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. LCD Controller LD [15:0] FLM/VSYNC LP/HSYNC LSCLK ACD/OE CONTRAST SPL_SPR PS CLS REV LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. Frame Sync or Vsync—This signal also serves as the clock signal output for the gate driver (dedicated signal SPS for Sharp panel HR-TFT). Line pulse or H sync Shift clock Alternate crystal direction/output enable. This signal is used to control the LCD bias voltage as contrast control. Program horizontal scan direction (Sharp panel dedicated signal). Control signal output for source driver (Sharp panel dedicated signal). Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated signal). Signal for common electrode driving signal preparation (Sharp panel dedicated signal). SPI 1 SPI1_MOSI SPI1_MISO SPI1_SS SPI1_SCLK SPI1_SPI_RDY Master Out/Slave In Slave In/Master Out Slave Select (Selectable polarity) Serial Clock Serial Data Ready General Purpose Timers TIN TMR2OUT Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers simultaneously. Timer 2 Output USB Device USBD_VMO USBD_VPO USBD_VM USBD_VP USB Minus Output USB Plus Output USB Minus Input USB Plus Input MC9328MXS Technical Data, Rev. 3 6 Freescale Semiconductor Signals and Connections Table 2. i.MXS Signal Descriptions (Continued) Signal Name USBD_SUSPND USBD_RCV USBD_ROE USBD_AFE USB Suspend Output USB Receive Data USB OE USB Analog Front End Enable UARTs – IrDA/Auto-Bauding UART1_RXD UART1_TXD UART1_RTS UART1_CTS UART2_RXD UART2_TXD UART2_RTS UART2_CTS UART2_DSR UART2_RI UART2_DCD UART2_DTR Receive Data Transmit Data Request to Send Clear to Send Receive Data Transmit Data Request to Send Clear to Send Data Set Ready Ring Indicator Data Carrier Detect Data Terminal Ready Serial Audio Port – SSI (configurable to I2S protocol) SSI_TXDAT SSI_RXDAT SSI_TXCLK SSI_RXCLK SSI_TXFS SSI_RXFS Transmit Data Receive Data Transmit Serial Clock Receive Serial Clock Transmit Frame Sync Receive Frame Sync I2C I2C_SCL I2C_SDA I2C Clock I2C Data PWM PWMO PWM Output Test Function TRISTATE Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input with a 1 k ohm resistor to ground. (TRI-STATE® is a registered trademark of National Semiconductor.) General Purpose Input/Output PA[14:3] Dedicated GPIO Function/Notes MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 7 Signals and Connections Table 2. i.MXS Signal Descriptions (Continued) Signal Name PB[13:8] Dedicated GPIO Digital Supply Pins NVDD NVSS Digital Supply for the I/O pins Digital Ground for the I/O pins Supply Pins – Analog Modules AVDD Supply for analog blocks Internal Power Supply QVDD QVSS Power supply pins for silicon internal circuitry Ground pins for silicon internal circuitry Function/Notes 2.1 I/O Pads Power Supply and Signal Multiplexing Scheme This section describes detailed information about both the power supply for each I/O pin and its function multiplexing scheme. The user can reference information provided in Table 6 on page 17 to configure the power supply scheme for each device in the system (memory and external peripherals). The function multiplexing information also shown in Table 6 allows the user to select the function of each pin by configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions. Table 3. MC9328MXS Signal Multiplexing Scheme I/O Supply Voltage NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 225 BGA Ball D2 C1 D1 E3 E2 E4 E1 F3 F1 F4 F2 G3 Primary Signal A24 D31 A23 D30 A22 D29 A21 D28 A20 D27 A19 D26 Dir O I/O O I/O O I/O O I/O O I/O O I/O 69K 69K ETMTRAC EPKT3 O PA27 69K A19 69K ETMPIPE STAT0 O PA28 69K A20 69K ETMPIPE STAT1 O PA29 69K A21 69K ETMPIPE STAT2 O PA30 69K A22 69K ETMTRAC ECLK O PA31 69K A23 PullUp Alternate Signal ETMTRAC ESYNC Dir O GPIO Mux PA0 Pull -Up 69K AIN BIN AOUT Default Reser ved A24 MC9328MXS Technical Data, Rev. 3 8 Freescale Semiconductor Signals and Connections Table 3. MC9328MXS Signal Multiplexing Scheme (Continued) I/O Supply Voltage NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 225 BGA Ball G2 G4 G1 H4 H2 H3 H1 H5 J1 J3 K1 J4 J2 K4 K2 L4 L1 L3 L2 M1 N1 M2 N2 P1 R1 M3 P2 N3 P3 R2 N4 M4 P4 R3 N5 R4 Primary Signal A18 D25 A17 D24 A16 D23 A15 D22 A14 D21 A13 D20 A12 D19 A11 D18 A10 D17 A9 D16 A8 D15 A7 D14 A6 D13 A5 D12 A4 D11 EB0 D10 A3 EB1 D9 EB2 Dir O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O O I/O O 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K ETMTRAC EPKT0 O PA24 69K A16 69K ETMTRAC EPKT1 O PA25 69K A17 PullUp Alternate Signal ETMTRAC EPKT2 Dir O GPIO Mux PA26 Pull -Up 69K AIN BIN AOUT Default A18 MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 9 Signals and Connections Table 3. MC9328MXS Signal Multiplexing Scheme (Continued) I/O Supply Voltage NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 225 BGA Ball P5 M5 N6 R5 P6 L7 R6 M7 R7 N7 P7 K3 R8 M8 N8 P8 L9 R9 R10 R11 M9 L8 N9 K10 M10 P10 P9 N10 R12 N11 P11 N12 P12 R13 R14 Primary Signal A2 EB3 D8 OE A1 CS5 D7 CS4 A0 CS3 D6 CS2 SDCLK CS1 CS0 D5 ECB D4 LBA D3 BCLK D2 PA17 D1 RW MA11 MA10 D0 DQM3 DQM2 DQM1 DQM0 RAS CAS SDWE O O I/O O O O O O O O 69K I/O 69K I/O 69K ETMTRAC EPKT4 PA17 69K Reser ved DTACK PA17 Dir O O I/O O O O I/O O O O I/O O O O O I/O I I/O O I/O 69K ETMTRAC EPKT5 PA18 69K BCLK 69K ETMTRAC EPKT6 PA19 69K LBA 69K ETMTRAC EPKT7 PA20 69K ECB 69K CSD0 CSD0 CSD1 69K PA22 PA21 69K 69K PA22 A0 CSD1 PA23 69K PA23 69K PullUp Alternate Signal Dir GPIO Mux Pull -Up AIN BIN AOUT Default MC9328MXS Technical Data, Rev. 3 10 Freescale Semiconductor Signals and Connections Table 3. MC9328MXS Signal Multiplexing Scheme (Continued) I/O Supply Voltage NVDD1 NVDD1 NVDD1 NVDD1 AVDD1 QVDD2 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 225 BGA Ball N13 P13 P15 P14 R15 M13 N15 N14 M15 L14 L15 K15 M14 K14 L12 K13 M12 K11 J14 J15 J13 H15 J12 K12 J11 H14 H13 G14 H12 G13 J10 G15 Primary Signal SDCKE0 SDCKE1 RESET_S F CLKO AVDD1 QVDD2 TRST TRISTATE 1 Alternate PullUp Signal Dir GPIO Mux Pull -Up AIN BIN AOUT Default Dir O O O O Static Static I I I O I O I O I I I I I I O I I I O I/O I I I I I I 69K EXTAL16 M XTAL16M EXTAL32 K XTAL32K RESET_I N2 RESET_O UT POR2 BIG_ENDI AN3 BOOT33 BOOT23 BOOT13 BOOT03 TDO4 TMS TCK TDI I2C_SCL I2C_SDA Reserved Reserved Reserved Reserved Reserved Reserved 69K 69K 69K 69K PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 69K 69K 69K 69K 69K 69K 69K 69K PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 11 Signals and Connections Table 3. MC9328MXS Signal Multiplexing Scheme (Continued) I/O Supply Voltage NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 225 BGA Ball F15 G12 F14 H11 E14 E15 G11 E13 D14 F13 F12 D15 C14 D13 E12 C13 C12 B15 B14 A15 A14 B13 A13 D12 B12 C11 D11 E11 C10 B11 A12 F10 A11 Primary Signal Reserved Reserved Reserved Reserved Reserved Reserved PWMO TIN TMR2OUT LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 FLM/VSY NC LP/HSYN C ACD/OE CONTRA ST SPL_SPR PS CLS REV Dir I I I I I O O I O O O O O O O O O O O O O O O O O O O O O O O O O UART2_D SR UART2_RI UART2_D CD UART2_D TR O O O I PullUp Alternate Signal Dir GPIO Mux PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 Pull -Up 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K Reser ved Reser ved Reser ved Reserved Reser ved Reserved AIN BIN AOUT Default PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 MC9328MXS Technical Data, Rev. 3 12 Freescale Semiconductor Signals and Connections Table 3. MC9328MXS Signal Multiplexing Scheme (Continued) I/O Supply Voltage NVDD2 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 225 BGA Ball B10 D10 E10 B9 A10 A9 E8 B8 C9 E9 A8 C8 F9 B7 F8 A7 C7 D8 E7 F7 B6 C6 A6 D6 A5 Primary Signal LSCLK SPI1_MO SI SPI1_MIS O SPI1_SS SPI1_SCL K SPI1_SPI _RDY UART1_R XD UART1_T XD UART1_R TS UART1_C TS SSI_TXCL K SSI_TXFS SSI_TXDA T SSI_RXD AT SSI_RXCL K SSI_RXFS UART2_R XD UART2_T XD UART2_R TS UART2_C TS USBD_VM O USBD_VP O USBD_VM USBD_VP USBD_SU SPND Dir O I/O I/O I/O I/O I/O I O I O I/O I/O O I I I I O I O O O I I O PullUp Alternate Signal Dir GPIO Mux PD6 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 Pull -Up 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K DMA_REQ AIN BIN AOUT Default PD6 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 13 Signals and Connections Table 3. MC9328MXS Signal Multiplexing Scheme (Continued) I/O Supply Voltage NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 225 BGA Ball B5 A4 B4 A3 C4 D4 B3 A2 C3 A1 B2 B1 Primary Signal USBD_RC V USBD_RO E USBD_AF E PB19 PB18 PB17 PB16 PB15 PB14 Reserved Reserved Reserved Dir I/O O O I/O I/O O I I I I/O O I/O Reserved Reserved Reserved PB13 PB12 PB11 PullUp Alternate Signal Dir GPIO Mux PB22 PB21 PB20 Pull -Up 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K 69K (pull down) 69K 69K 69K AIN BIN AOUT Default PB22 PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 NVDD4 NVDD4 NVDD4 NVDD1 C5 D3 C2 D5 G6 Reserved Reserved Reserved NVDD1 NVSS NVDD1 NVSS QVDD1 QVSS NVDD NVSS NVDD1 NVSS NVDD1 NVSS NVDD1 NVSS NVDD1 NVSS NVDD1 NVSS QVSS I/O I/O I/O Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Reserved Reserved Reserved PB10 PB9 PB8 PB10 PB9 PB8 NVDD1 E5 H6 QVDD1 J8 E6 NVDD1 F5 J6 NVDD1 G5 K6 NVDD1 J5 H7 NVDD1 K5 J7 NVDD1 L5 G8 NVDD1 L5 H8 K7 MC9328MXS Technical Data, Rev. 3 14 Freescale Semiconductor Signals and Connections Table 3. MC9328MXS Signal Multiplexing Scheme (Continued) I/O Supply Voltage NVDD2 225 BGA Ball H10 G9 QVDD3 F11 G10 NVDD2 C15 H9 QVDD4 D7 L13 NVDD3 D9 J9 K9 NVDD4 NVDD1 NVDD1 NVDD1 NVDD1 G7 F6 L6 M6 K8 L10 L11 M11 1 2 Primary Signal NVDD2 NVSS QVDD3 QVSS NVDD2 NVSS QVDD4 QVSS NVDD3 NVSS NVSS NVDD4 NVDD1 NVDD1 NVDD1 NVDD1 NVSS NVSS NVSS Dir Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static PullUp Alternate Signal Dir GPIO Mux Pull -Up AIN BIN AOUT Default Pull down this input with 1KΩ resistor to GND. External circuit required to drive this input. 3 Tie this input high (to AVDD) or pull down with 1KΩ resistor to GND. 4 Pull up this output with a resistor to NVDD2. MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 15 Electrical Characteristics 3 3.1 Electrical Characteristics Maximum Ratings This section contains the electrical specifications and timing diagrams for the i.MXS processor. Table 4 provides information on maximum ratings which are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on page 17 or the DC Characteristics table. Table 4. Maximum Ratings Symbol NVDD QVDD AVDD BTRFVDD VESD_HBM VESD_MM ILatchup Test Pmax 1 Rating DC I/O Supply Voltage DC Internal (core = 100 MHz) Supply Voltage DC Analog Supply Voltage DC Bluetooth Supply Voltage ESD immunity with HBM (human body model) ESD immunity with MM (machine model) Latch-up immunity Storage temperature Power Consumption Minimum -0.3 -0.3 -0.3 -0.3 – – – -55 8001 Maximum 3.3 1.9 3.3 3.3 2000 100 200 150 13002 Unit V V V V V V mA °C mW A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM® core-that is, 7x GPIO, 15x Data bus, and 8x Address bus. 2 A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS application at 100MHz, and where the whole image is running out of SDRAM. QVDD at 1.9V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA. 3.2 Recommended Operating Range Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MXS processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the AVDD pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4. MC9328MXS Technical Data, Rev. 3 16 Freescale Semiconductor Electrical Characteristics Table 5. Recommended Operating Range Symbol TA TA NVDD NVDD QVDD AVDD Operating temperature range MC9328MXSVP10 Operating temperature range MC9328MXSCVP10 I/O supply voltage (if using SPI, LCD, and USBd which are only 3 V interfaces) I/O supply voltage (if not using the peripherals listed above) Internal supply voltage (Core = 100 MHz) Analog supply voltage Rating Minimum 0 -40 2.70 1.70 1.70 1.70 Maximum 70 85 3.30 3.30 1.90 3.30 Unit °C °C V V V V 3.3 Power Sequence Requirements For required power-up and power-down sequencing, please refer to the “Power-Up Sequence” section of application note AN2537 on the i.MX applications processor website. 3.4 DC Electrical Characteristics Table 6. Maximum and Minimum DC Characteristics Table 6 contains both maximum and minimum DC characteristics of the i.MXS processor. Number or Symbol Iop Parameter Full running operating current at 1.8V for QVDD, 3.3V for NVDD/AVDD (Core = 96 MHz, System = 96 MHz, driving TFT display panel, and OS with MMU enabled memory system is running on external SDRAM). Standby current (Core = 100 MHz, QVDD = 1.8V, temp = 25°C) Standby current (Core = 100 MHz, QVDD = 1.8V, temp = 55°C) Standby current (Core = 100 MHz, QVDD = 1.9V, temp = 25°C) Standby current (Core = 100 MHz, QVDD = 1.9V, temp = 55°C) Input high voltage Input low voltage Output high voltage (IOH = 2.0 mA) Output low voltage (IOL = -2.5 mA) Input low leakage current (VIN = GND, no pull-up or pull-down) Min – Typical QVDD at 1.8V = 120mA; NVDD+AVDD at 3.0V = 30mA 25 45 35 60 – – – – – Max – Unit mA Sidd1 Sidd2 Sidd3 Sidd4 VIH VIL VOH VOL IIL – – – – 0.7VDD – 0.7VDD – – – – – – Vdd+0.2 0.4 Vdd 0.4 ±1 μA μA μA μA V V V V μA MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 17 Functional Description and Application Information Table 6. Maximum and Minimum DC Characteristics (Continued) Number or Symbol IIH IOH IOL IOZ Ci Co Parameter Input high leakage current (VIN = VDD, no pull-up or pull-down) Output high current (VOH = 0.8VDD, VDD = 1.8V) Output low current (VOL = 0.4V, VDD = 1.8V) Output leakage current (Vout = VDD, output is high impedance) Input capacitance Output capacitance Min – 4.0 -4.0 – – – Typical – – – – – – Max ±1 – – ±5 5 5 Unit μA mA mA μA pF pF 3.5 AC Electrical Characteristics The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 100 MHz) with an operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading. Table 7. Tristate Signal Timing Pin TRISTATE Parameter Time from TRISTATE activate until I/O becomes Hi-Z Minimum – Maximum 20.8 Unit ns Table 8. 32k/16M Oscillator Signal Timing Parameter EXTAL32k input jitter (peak to peak) EXTAL32k startup time EXTAL16M input jitter (peak to peak) 1 EXTAL16M startup time 1 1 Minimum – 800 – TBD RMS 5 – TBD – Maximum 20 – TBD – Unit ns ms – – The 16 MHz oscillator is not recommended for use in new designs. 4 Functional Description and Application Information This section provides the electrical information including and timing diagrams for the individual modules of the i.MXS. MC9328MXS Technical Data, Rev. 3 18 Freescale Semiconductor Functional Description and Application Information 4.1 Embedded Trace Macrocell All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift register comprised of the following: • 32-bit data field • 7-bit address field • A read/write bit The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used in Figure 2. 2a 3a TRACECLK 1 2b 3b TRACECLK (Half-Rate Clocking Mode) Output Trace Port Valid Data Valid Data 4a 4b Figure 2. Trace Port Timing Diagram Table 9. Trace Port Timing Diagram Parameter Table 1.8 ± 0.1 V Ref No. Parameter Minimum 1 2a 2b 3a 3b 4a 4b CLK frequency Clock high time Clock low time Clock rise time Clock fall time Output hold time Output setup time 0 1.3 3 – – 2.28 3.42 Maximum 85 – – 4 3 – – Minimum 0 2 2 – – 2 3 Maximum 100 – – 3 3 – – MHz ns ns ns ns ns ns 3.0 ± 0.3 V Unit MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 19 Functional Description and Application Information 4.2 DPLL Timing Specifications Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the pre-divider and Tdck is the output double clock period. Table 10. DPLL Specifications Parameter DPLL input clock freq range Pre-divider output clock freq range DPLL output clock freq range Pre-divider factor (PD) Total multiplication factor (MF) MF integer part MF numerator MF denominator Pre-multiplier lock-in time Freq lock-in time after full reset Freq lock-in time after partial reset Phase lock-in time after full reset Phase lock-in time after partial reset Freq jitter (p-p) Phase jitter (p-p) Power supply voltage Power dissipation Vcc = 1.8V Vcc = 1.8V Vcc = 1.8V – Includes both integer and fractional parts – Should be less than the denominator – – FOL mode for non-integer MF (does not include pre-multi lock-in time) FOL mode for non-integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) – Integer MF, FPL mode, Vcc=1.8V – FOL mode, integer MF, fdck = 100 MHz, Vcc = 1.8V Test Conditions Minimum 5 5 80 1 5 5 0 1 – 250 220 300 270 – – 1.7 – Typical – – – – – – – – – 280 (56 μs) 250 (50 μs) 350 (70 μs) 320 (64 μs) 0.005 (0.01%) 1.0 (10%) – – Maximum 100 30 220 16 15 15 1022 1023 312.5 300 270 400 370 0.01 1.5 2.5 4 Unit MHz MHz MHz – – – – – μsec Tref Tref Tref Tref 2•Tdck ns V mW 4.3 Reset Module The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4. NOTE Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent forward biasing. MC9328MXS Technical Data, Rev. 3 20 Freescale Semiconductor Functional Description and Application Information 90% AVDD 1 POR 10% AVDD RESET_POR 2 Exact 300ms RESET_DRAM 3 7 cycles @ CLK32 HRESET RESET_OUT 4 14 cycles @ CLK32 CLK32 HCLK Figure 3. Timing Relationship with POR 5 RESET_IN 14 cycles @ CLK32 HRESET RESET_OUT 4 6 CLK32 HCLK Figure 4. Timing Relationship with RESET_IN MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 21 Functional Description and Application Information Table 11. Reset Module Timing Parameter Table Ref No. 1 2 3 4 5 6 1 1.8 ± 0.1 V Parameter Min Width of input POWER_ON_RESET Width of internal POWER_ON_RESET (CLK32 at 32 kHz) 7K to 32K-cycle stretcher for SDRAM reset 14K to 32K-cycle stretcher for internal system reset HRESERT and output reset at pin RESET_OUT Width of external hard-reset RESET_IN 4K to 32K-cycle qualifier note1 300 7 14 4 4 Max – 300 7 14 – 4 3.0 ± 0.3 V Unit Min note1 300 7 14 4 4 Max – 300 7 14 – 4 – ms Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal. If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in calculating timing for the start-up process. 4.4 External Interface Module The External Interface Module (EIM) handles the interface to devices external to the i.MXS processor, including the generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 defines the parameters of signals. MC9328MXS Technical Data, Rev. 3 22 Freescale Semiconductor Functional Description and Application Information (HCLK) Bus Clock 1a 1b Address Chip-select 2a 2b 3a 3b Read (Write) OE (rising edge) OE (falling edge) EB (rising edge) EB (falling edge) 6a 5a 4a 4b 4c 4d 5b 5c 5d LBA (negated falling edge) 6b LBA (negated rising edge) 6a 6c 7a 7b BCLK (burst clock) - rising edge BCLK (burst clock) - falling edge 7c 7d 8b Read Data 9a 8a 9b Write Data (negated falling) 9a 9c Write Data (negated rising) DTACK_B 10a 10a Figure 5. EIM Bus Timing Diagram Table 12. EIM Bus Timing Parameter Table 1.8 ± 0.1 V Ref No. Parameter Min 1a 1b 2a 2b 3a 3b Clock fall to address valid Clock fall to address invalid Clock fall to chip-select valid Clock fall to chip-select invalid Clock fall to Read (Write) Valid Clock fall to Read (Write) Invalid 2.48 1.55 2.69 1.55 1.35 1.86 Typical 3.31 2.48 3.31 2.48 2.79 2.59 Max 9.11 5.69 7.87 6.31 6.52 6.11 Min 2.4 1.5 2.6 1.5 1.3 1.8 Typical 3.2 2.4 3.2 2.4 2.7 2.5 Max 8.8 5.5 7.6 6.1 6.3 5.9 ns ns ns ns ns ns 3.0 ± 0.3 V Unit MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 23 Functional Description and Application Information Table 12. EIM Bus Timing Parameter Table (Continued) 1.8 ± 0.1 V Ref No. Parameter Min 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 7a 7b 7c 7d 8a 8b 9a 9b 9c 10a 1 3.0 ± 0.3 V Unit Max 6.85 6.55 7.04 6.73 5.54 5.24 5.69 5.38 6.73 6.83 6.45 5.64 5.84 5.59 5.80 – – 6.85 5.69 – – Min 2.3 2.1 2.3 2.1 1.9 1.8 1.9 1.7 2.0 1.9 1.9 1.6 1.6 1.5 1.5 5.5 0 1.8 1.4 1.62 2.5 Typical 2.6 2.5 2.6 2.5 2.5 2.4 2.5 2.4 2.7 2.7 2.6 2.6 2.6 2.4 2.5 – – 2.7 2.4 – – Max 6.8 6.5 6.8 6.5 5.5 5.2 5.5 5.2 6.5 6.6 6.4 5.6 5.8 5.4 5.6 – – 6.8 5.5 – – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Typical 2.62 2.52 2.69 2.59 2.52 2.42 2.59 2.48 2.79 2.79 2.62 2.62 2.62 2.48 2.59 – – 2.72 2.48 – – Clock1 rise to Output Enable Valid Clock rise to Output Enable Invalid Clock1 fall to Output Enable Valid Clock fall to Output Enable Invalid Clock1 rise to Enable Bytes Valid Clock rise to Enable Bytes Invalid Clock1 fall to Enable Bytes Valid Clock1 fall to Enable Bytes Invalid 1 1 1 2.32 2.11 2.38 2.17 1.91 1.81 1.97 1.76 2.07 1.97 1.91 1.61 1.61 1.55 1.55 5.54 0 1.81 1.45 1.63 2.52 Clock1 fall to Load Burst Address Valid Clock1 fall to Load Burst Address Invalid Clock1 rise to Load Burst Address Invalid Clock1 rise to Burst Clock rise Clock1rise to Burst Clock fall Clock1 fall to Burst Clock rise Clock1 fall to Burst Clock fall Read Data setup time Read Data hold time Clock1 rise to Write Data Valid Clock1 fall to Write Data Invalid Clock1 rise to Write Data Invalid DTACK setup time Clock refers to the system clock signal, HCLK, generated from the System DPLL 4.4.1 DTACK Signal Description The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal function when the external DTACK signal is used for data acknowledgement. 4.4.2 DTACK Signal Timing Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of measure for this figure are found in the associated tables. MC9328MXS Technical Data, Rev. 3 24 Freescale Semiconductor Functional Description and Application Information 4.4.2.1 WAIT Read Cycle without DMA 3 Address 2 CS5 8 1 EB programmable min 0ns 9 5 OE 4 WAIT 7 DATABUS (input to i.MXS) 6 10 11 Figure 6. WAIT Read Cycle without DMA Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz 3.0 ± 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 Characteristic Minimum OE and EB assertion time CS5 pulse width OE negated to address inactive Wait asserted after OE asserted Wait asserted to OE negated Data hold timing after OE negated Data ready after wait asserted OE negated to CS negated OE negated after EB negated Become low after CS5 asserted Wait pulse width See note 2 3T 56.81 – 2T+1.57 T-1.49 0 1.5T-0.68 0.06 0 1T Maximum – – 57.28 1020T 3T+7.33 – T 1.5T-0.06 0.18 1019T 1020T ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 25 Functional Description and Application Information 4.4.2.2 WAIT Read Cycle DMA Enabled 4 Address 2 CS5 9 10 3 6 1 EB programmable min 0ns OE RW (logic high) WAIT 5 11 7 8 12 S DATABUS Figure 7. DTACK WAIT Read Cycle DMA Enabled Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz 3.0 ± 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 Characteristic Minimum OE and EB assertion time CS pulse width OE negated before CS5 is negated Address inactived before CS negated Wait asserted after CS5 asserted Wait asserted to OE negated Data hold timing after OE negated Data ready after wait is asserted CS deactive to next CS active OE negate after EB negate Wait becomes low after CS5 asserted See note 2 3T 1.5T-0.68 – – 2T+1.57 T-1.49 – T 0.06 0 Maximum – – 1.5T-0.06 0.05 1020T 3T+7.33 – T – 0.18 1019T ns ns ns ns ns ns ns ns ns ns ns Unit MC9328MXS Technical Data, Rev. 3 26 Freescale Semiconductor Functional Description and Application Information Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued) 3.0 ± 0.3 V Number 12 Wait pulse width Characteristic Minimum 1T Maximum 1020T ns Unit Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. 4.4.2.3 WAIT Write Cycle without DMA 5 Address 1 CS5 programmable min 0ns 2 3 EB programmable min 0ns 7 4 10 RW OE (logic high) WAIT 6 11 9 12 8 DATABUS from i.MXS Figure 8. WAIT Write Cycle without DMA Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz 3.0 ± 0.3 V Number 1 2 3 4 5 6 Characteristic Minimum CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated RW negated to Address inactive Wait asserted after CS5 asserted See note 2 See note 2 3T 2.5T-3.63 64.22 – Maximum – – – 2.5T-1.16 – 1020T ns ns ns ns ns ns Unit MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 27 Functional Description and Application Information Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued) 3.0 ± 0.3 V Number 7 8 9 10 11 12 Characteristic Minimum Wait asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted EB negated after CS5 is negated Wait becomes low after CS5 asserted Wait pulse width T+2.66 2T+0.03 – 0.5T 0 1T Maximum 2T+7.96 – T 0.5T+0.5 1019T 1020T ns ns ns ns ns ns Unit Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register. 3. Address becomes valid and RW asserts at the start of write access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. 4.4.2.4 WAIT Write Cycle DMA Enabled 5 Address 1 CS5 programmable min 0ns programmable min 0ns 3 10 2 EB 11 7 RW 4 OE (logic high) WAIT 6 12 9 DATABUS S 13 8 Figure 9. WAIT Write Cycle DMA Enabled MC9328MXS Technical Data, Rev. 3 28 Freescale Semiconductor Functional Description and Application Information Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz 3.0 ± 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Characteristic Minimum CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated Address inactived after CS negated Wait asserted after CS5 asserted Wait asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted CS deactive to next CS active EB negate after CS negate Wait becomes low after CS5 asserted Wait pulse width See note 2 See note 2 3T 2.5T-3.63 – – T+2.66 2T+0.03 – T 0.5T 0 1T Maximum – – – 2.5T-1.16 0.09 1020T 2T+7.96 – T – 0.5T+0.5 1019T 1020T ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register. 3. Address becomes valid and RW asserts at the start of write access cycle. 4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. 4.4.3 EIM External Bus Timing The External Interface Module (EIM) is the interface to devices external to the i.MXS, including generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 defines the parameters of signals. MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 29 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[0] htrans Seq/Nonseq hwrite Read haddr hready weim_hrdata weim_hready V1 Last Valid Data V1 BCLK (burst clock) ADDR CS2 R/W Last Valid Address V1 Read LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA V1 Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 10. WSC = 1, A.HALF/E.HALF MC9328MXS Technical Data, Rev. 3 30 Freescale Semiconductor Functional Description and Application Information hclk hsel_weim_cs[0] Internal signals - shown only for illustrative purposes htrans hwrite haddr Nonseq Write V1 hready hwdata weim_hrdata Last Valid Data Write Data (V1) Unknown Last Valid Data weim_hready BCLK (burst clock) ADDR CS0 R/W LBA Write Last Valid Address V1 OE EB DATA Last Valid Data Write Data (V1) Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 31 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[0] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR CS0 Last Valid Addr Address V1 Address V1 + 2 R/W LBA OE Read EBx1 (EBC2=0) EBx1 (EBC2=1) DATA 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 32 Freescale Semiconductor Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[0] Nonseq htrans hwrite haddr Write V1 hready hwdata weim_hrdata Last Valid Data Write Data (V1 Word) Last Valid Data weim_hready BCLK (burst clock) ADDR CS0 Last Valid Addr Address V1 Address V1 + 2 R/W LBA OE Write EB DATA 1/2 Half Word 2/2 Half Word Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 33 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[3] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR Last Valid Addr CS[3] R/W Read Address V1 Address V1 + 2 LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 34 Freescale Semiconductor Functional Description and Application Information hclk hsel_weim_cs[3] htrans hwrite haddr hready hwdata Last Valid Data weim_hrdata Nonseq Internal signals - shown only for illustrative purposes Write V1 Write Data (V1 Word) Last Valid Data weim_hready BCLK (burst clock) ADDR Last Valid Addr CS3 R/W LBA OE Write Address V1 Address V1 + 2 EB DATA Last Valid Data 1/2 Half Word 2/2 Half Word Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 35 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Read hwrite haddr V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR CS2 R/W Read Last Valid Addr Address V1 Address V1 + 2 LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) weim_data_in 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 36 Freescale Semiconductor Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq hwrite haddr Write V1 hready hwdata Last Valid Data weim_hrdata Write Data (V1 Word) Last Valid Data weim_hready BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2 R/W LBA OE Write EB DATA Last Valid Data 1/2 Half Word 2/2 Half Word Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 37 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Read V1 hwrite haddr hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V1 + 2 CS2 Read R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 38 Freescale Semiconductor Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Read hwrite haddr V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR CS2 Read Last Valid Addr Address V1 Address V1 + 2 R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 39 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Write hwrite haddr V1 hready Last Valid Data hwdata weim_hrdata Write Data (V1 Word) Unknown Last Valid Data weim_hready BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2 R/W Write LBA OE EB DATA Last Valid Data 1/2 Half Word 2/2 Half Word Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 40 Freescale Semiconductor Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Write hwrite haddr V1 hready hwdata Last Valid Data weim_hrdata Write Data (V1 Word) Last Valid Data Unknown weim_hready BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2 R/W Write LBA OE EB DATA Last Valid Data 1/2 Half Word 2/2 Half Word Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 41 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] Nonseq Read Nonseq Write htrans hwrite haddr V1 V8 hready hwdata weim_hrdata Last Valid Data Last Valid Data Write Data Read Data weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V8 CS2 R/W LBA Read Write OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA Read Data DATA Last Valid Data Write Data Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF MC9328MXS Technical Data, Rev. 3 42 Freescale Semiconductor Functional Description and Application Information Read hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] Idle Write htrans Nonseq Read Nonseq Write hwrite haddr V1 V8 hready hwdata Last Valid Data Write Data weim_hrdata Last Valid Data Read Data weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V8 CS2 R/W LBA Read Write OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA DATA Read Data Last Valid Data Write Data Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 43 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4] htrans Nonseq Write hwrite haddr V1 hready hwdata Last Valid Data weim_hrdata Write Data (Word) Last Valid Data weim_hready BCLK (burst clock) ADDR CS Last Valid Addr Address V1 Address V1 + 2 R/W Write LBA OE EB DATA Last Valid Data Write Data (1/2 Half Word) Write Data (2/2 Half Word) Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 44 Freescale Semiconductor Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4] htrans Nonseq Read Nonseq Write hwrite haddr V1 V8 hready hwdata weim_hrdata weim_hready Last Valid Data Last Valid Data Write Data Read Data BCLK (burst clock) ADDR CS4 Last Valid Addr Address V1 Address V8 R/W LBA Read Write OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA Read Data DATA Last Valid Data Write Data Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 45 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4] htrans Nonseq Read Idle Seq Read hwrite haddr V1 V2 hready weim_hrdata weim_hready Last Valid Data Read Data (V1) Read Data (V2) BCLK (burst clock) ADDR Last Valid Address V1 CNC Address V2 CS4 Read R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA Read Data (V1) Read Data (V2) Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF MC9328MXS Technical Data, Rev. 3 46 Freescale Semiconductor Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4] htrans Nonseq Read Idle Nonseq Write hwrite haddr V1 V8 hready hwdata weim_hrdata Last Valid Data Last Valid Data Write Data Read Data weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 CNC CS4 R/W LBA OE Address V8 Read Write EBx1 (EBC2=0) EBx1 (EBC2=1) DATA DATA Read Data Last Valid Data Write Data Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 47 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans hwrite haddr Nonseq Read V1 Nonse Read V5 Idle hready weim_hrdata weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V5 CS2 Read R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) ECB DATA V1 Word V2 Word V5 Word V6 Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF MC9328MXS Technical Data, Rev. 3 48 Freescale Semiconductor Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans hwrite haddr Idle Nonseq Read V1 Seq Read V2 Seq Read V3 Seq Read V4 hready weim_hrdata weim_hready BCLK (burst clock) Last Valid Data V1 Word V2 Word V3 Word V4 Word ADDR Last Valid Addr CS2 R/W Address V1 Read LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) ECB DATA V1 Word V2 Word V3 Word V4 Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 49 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Idle Nonseq Seq hwrite haddr Read V1 Read V2 hready weim_hrdata Last Valid Data V1 Word V2 Word weim_hready BCLK (burst clock) ADDR CS2 Read Last Valid Address V1 Address V2 R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) ECB DATA V1 1/2 V1 2/2 V2 1/2 V2 2/2 Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 50 Freescale Semiconductor Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] Non seq Read htrans Seq Idle hwrite haddr Read V1 V2 hready weim_hrdata Last Valid Data V1 Word V2 Word weim_hready BCLK (burst clock) Last ADDR CS2 Address V1 R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) Read ECB DATA V1 1/2 V1 2/2 V2 1/2 V2 2/2 Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 51 Functional Description and Application Information hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Non seq Read V1 Seq Idle hwrite haddr Read V2 hready weim_hrdata Last Valid Data V1 Word V2 Word weim_hready BCLK (burst clock) ADDR CS2 Last Address V1 R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) Read ECB DATA V1 1/2 V1 2/2 V2 1/2 V2 2/2 Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF MC9328MXS Technical Data, Rev. 3 52 Freescale Semiconductor Functional Description and Application Information 4.4.4 Non-TFT Panel Timing T1 VSYN T1 T2 HSYN SCLK T3 XMAX T4 T2 Ts LD[15:0] Figure 33. Non-TFT Panel Timing Table 17. Non TFT Panel Timing Diagram Symbol T1 T2 T3 T4 1 2 Parameter HSYN to VSYN delay3 HSYN pulse width VSYN to SCLK SCLK to HSYN Allowed Register Minimum Value1, 2 0 0 – 0 Actual Value HWAIT2+2 HWIDTH+1 0 ≤ T3 ≤ Ts5 HWAIT1+1 Unit Tpix4 Tpix – Tpix Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register. Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong. 3 VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all these 3 signals are active high. 4 Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1). 5 Ts is the shift clock period. Ts = Tpix * (panel data bus width). 4.5 SPI Timing Diagrams To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI module is configured as a master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The SPI1 Sample Period Control Register (PERIODREG1) can also be programmed to a fixed data transfer rate. When the SPI module is configured as a slave, the user can configure the SPI1 Control Register (CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data FIFO. Figure 34 through Figure 38 show the timing relationship of the master SPI using different triggering mechanisms. MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 53 Functional Description and Application Information 2 SS 1 SPIRDY 3 5 4 SCLK, MOSI, MISO Figure 34. Master SPI Timing Diagram Using SPI_RDY Edge Trigger SS SPIRDY SCLK, MOSI, MISO Figure 35. Master SPI Timing Diagram Using SPI_RDY Level Trigger SS (output) SCLK, MOSI, MISO Figure 36. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 37. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO 7 Figure 38. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge MC9328MXS Technical Data, Rev. 3 54 Freescale Semiconductor Functional Description and Application Information Table 18. Timing Parameter Table for Figure 34 through Figure 38 3.0 ± 0.3 V Ref No. Parameter Minimum 1 2 3 4 5 6 7 1 2 Unit Maximum – – – – – – – ns ns ns ns ns ns ns SPI_RDY to SS output low SS output low to first SCLK edge Last SCLK edge to SS output high SS output high to SPI_RDY low SS output pulse width SS input low to first SCLK edge SS input pulse width 2T1 3 • Tsclk2 2 • Tsclk 0 Tsclk + WAIT 3 T T T = CSPI system clock period (PERCLK2). Tsclk = Period of SCLK. 3 WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register. 8 SCLK 9 9 Figure 39. SPI SCLK Timing Diagram Table 19. Timing Parameter Table for SPI SCLK 3.0 ± 0.3 V Ref No. Parameter Minimum 8 9 SCLK frequency SCLK pulse width 0 100 Maximum 10 – MHz ns Unit 4.6 LCD Controller This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MXS Reference Manual. LSCLK 1 LD[15:0] Figure 40. SCLK to LD Timing Diagram MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 55 Functional Description and Application Information Table 20. LCDC SCLK Timing Parameter Table 3.0 ± 0.3 V Ref No. 1 Parameter SCLK to LD valid Non-display T1 T3 Minimum – Maximum 2 Display region Unit ns T4 VSYN HSYN OE LD[15:0] T2 Line Y Line 1 Line Y T5 HSYN SCLK OE LD[15:0] VSYN T6 XMAX T7 T8 (1,1) (1,2) (1,X) T9 T10 Figure 41. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Symbol T1 T2 T3 T4 T5 T6 T7 Description End of OE to beginning of VSYN HSYN period VSYN pulse width End of VSYN to beginning of OE HSYN pulse width End of HSYN to beginning to T9 End of OE to beginning of HSYN Minimum T5+T6 +T7+T9 XMAX+5 T2 2 1 1 1 Corresponding Register Value (VWAIT1·T2)+T5+T6+T7+T9 XMAX+T5+T6+T7+T9+T10 VWIDTH·(T2) VWAIT2·(T2) HWIDTH+1 HWAIT2+1 HWAIT1+1 Unit Ts Ts Ts Ts Ts Ts Ts MC9328MXS Technical Data, Rev. 3 56 Freescale Semiconductor Functional Description and Application Information Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued) Symbol T8 T9 T9 T10 T10 Note: Description SCLK to valid LD data End of HSYN idle2 to VSYN edge (for non-display region) End of HSYN idle2 to VSYN edge (for Display region) VSYN to OE active (Sharp = 0) when VWAIT2 = 0 VSYN to OE active (Sharp = 1) when VWAIT2 = 0 Minimum -3 2 1 1 2 Corresponding Register Value 3 2 1 1 2 Unit ns Ts Ts Ts Ts • • • • • • Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns. VSYN, HSYN and OE can be programmed as active high or active low. In Figure 41, all 3 signals are active low. The polarity of SCLK and LD[15:0] can also be programmed. SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 41, SCLK is always active. For T9 non-display region, VSYN is non-active. It is used as an reference. XMAX is defined in pixels. 4.7 Pulse-Width Modulator The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal is passed through a divider and a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in Figure 42 and the parameters are listed in Table 22. 2a System Clock 1 3b 2b 3a 4a PWM Output 4b Figure 42. PWM Output Timing Diagram MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 57 Functional Description and Application Information Table 22. PWM Output Timing Parameter Table 1.8 ± 0.1 V Ref No. Parameter Minimum 1 2a 2b 3a 3b 4a 4b 1 3.0 ± 0.3 V Unit Minimum 0 5/10 5/10 – – 5 5 Maximum 100 – – 5/10 5/10 – – MHz ns ns ns ns ns ns Maximum 87 – – 5 6.67 – – System CLK frequency1 Clock high time1 Clock low time1 Clock fall time1 Clock rise time1 Output delay time1 Output setup time1 0 3.3 7.5 – – 5.7 5.7 CL of PWMO = 30 pF 4.8 SDRAM Controller This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic random access memory) Controller. MC9328MXS Technical Data, Rev. 3 58 Freescale Semiconductor Functional Description and Application Information 1 SDCLK 2 3S CS 3 3S RAS 3S 3H CAS 3S 3H WE 4S ADDR 4H COL/BA 8 DQ 3H 3H ROW/BA 5 6 Data 7 3S DQM 3H Note: CKE is high during the read/write cycle. Figure 43. SDRAM Read Cycle Timing Diagram Table 23. SDRAM Read Timing Parameter Table Ref No. 1 2 3 3S 3H 4S 4H 5 1.8 ± 0.1 V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM setup time CS, RAS, CAS, WE, DQM hold time Address setup time Address hold time SDRAM access time (CL = 3) 2.67 6 11.4 3.42 2.28 3.42 2.28 – Maximum – – – – – – – 6.84 Minimum 4 4 10 3 2 3 2 – Maximum – – – – – – – 6 ns ns ns ns ns ns ns ns 3.0 ± 0.3 V Unit MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 59 Functional Description and Application Information Table 23. SDRAM Read Timing Parameter Table (Continued) Ref No. 5 5 6 7 7 7 8 1 1.8 ± 0.1 V Parameter Minimum SDRAM access time (CL = 2) SDRAM access time (CL = 1) Data out hold time Data out high-impedance time (CL = 3) Data out high-impedance time (CL = 2) Data out high-impedance time (CL = 1) Active to read/write command period (RC = 1) – – 2.85 – – – tRCD1 Maximum 6.84 22 – 6.84 6.84 22 – 3.0 ± 0.3 V Unit Minimum – – 2.5 – – – tRCD1 Maximum 6 22 – 6 6 22 – ns ns ns ns ns ns ns tRCD = SDRAM clock cycle time. This settings can be found in the MC9328MXS reference manual. SDCLK 1 CS 3 2 RAS 6 CAS WE 4 ADDR / BA 5 7 ROW/BA 8 COL/BA 9 DATA DQ DQM Figure 44. SDRAM Write Cycle Timing Diagram MC9328MXS Technical Data, Rev. 3 60 Freescale Semiconductor Functional Description and Application Information Table 24. SDRAM Write Timing Parameter Table 1.8 ± 0.1 V Ref No. 1 2 3 4 5 6 7 8 9 1 2 3.0 ± 0.3 V Unit Minimum 4 4 10 3 2 tRP2 tRCD2 2 2 Maximum – – – – – – – – – ns ns ns ns ns ns ns ns ns Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period1 2.67 6 11.4 3.42 2.28 tRP2 tRCD2 4.0 2.28 Maximum – – – – – – – – – Active to read/write command delay Data setup time Data hold time Precharge cycle timing is included in the write timing diagram. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MXS reference manual. SDCLK 1 3 2 CS RAS 6 CAS 7 7 WE 4 ADDR BA 5 ROW/BA DQ DQM Figure 45. SDRAM Refresh Timing Diagram MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 61 Functional Description and Application Information Table 25. SDRAM Refresh Timing Parameter Table 1.8 ± 0.1 V Ref No. Parameter Minimum 1 2 3 4 5 6 7 1 3.0 ± 0.3 V Unit Minimum 4 4 10 3 2 tRP1 tRC1 Maximum – – – – – – – ns ns ns ns ns ns ns Maximum – – – – – – – SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period Auto precharge command period 2.67 6 11.4 3.42 2.28 tRP1 tRC1 tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXS reference manual. SDCLK CS RAS CAS WE ADDR BA DQ DQM CKE Figure 46. SDRAM Self-Refresh Cycle Timing Diagram MC9328MXS Technical Data, Rev. 3 62 Freescale Semiconductor Functional Description and Application Information 4.9 USB Device Port Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and how they work from the ground up. Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer. USBD_AFE (Output) 1 USBD_ROE (Output) tPERIOD USBD_VPO (Output) 6 3 tVPO_ROE t ROE_VPO t VMO_ROE 4 USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) USBD_VP (Input) USBD_VM (Input) tROE_VMO 2 tFEOPT 5 Figure 47. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX) Table 26. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX) Ref No. 1 2 3 4 3.0 ± 0.3 V Parameter Minimum tROE_VPO; USBD_ROE active to USBD_VPO low tROE_VMO; USBD_ROE active to USBD_VMO high tVPO_ROE; USBD_VPO high to USBD_ROE deactivated tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0) 83.14 81.55 83.54 248.90 Maximum 83.47 81.98 83.80 249.13 ns ns ns ns Unit MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 63 Functional Description and Application Information Table 26. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX) (Continued) Ref No. 5 6 tFEOPT; SE0 interval of EOP tPERIOD; Data transfer rate USBD_AFE (Output) 3.0 ± 0.3 V Parameter Minimum 160.00 11.97 Maximum 175.00 12.03 ns Mb/s Unit USBD_ROE (Output) USBD_VPO (Output) USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) 1 tFEOPR USBD_VP (Input) USBD_VM (Input) Figure 48. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX) Table 27. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX) 3.0 ± 0.3 V Ref No. Parameter Minimum 1 tFEOPR; Receiver SE0 interval of EOP 82 Maximum – ns Unit 4.10 I2C Module The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. MC9328MXS Technical Data, Rev. 3 64 Freescale Semiconductor Functional Description and Application Information SDA 5 SCL 1 2 6 3 4 Figure 49. Definition of Bus Timing for I2C Table 28. I2C Bus Timing Parameter Table 1.8 ± 0.1 V Ref No. Parameter Minimum 1 2 3 4 5 6 Hold time (repeated) START condition Data hold time Data setup time HIGH period of the SCL clock LOW period of the SCL clock Setup time for STOP condition 182 0 11.4 80 480 182.4 Maximum – 171 – – – – Minimum 160 0 10 120 320 160 Maximum – 150 – – – – ns ns ns ns ns ns 3.0 ± 0.3 V Unit 4.11 Synchronous Serial Interface The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external clock timing diagrams are shown in Figure 51 through Figure 53. Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices. MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 65 Functional Description and Application Information 1 STCK Output 2 STFS (bl) Output 4 6 STFS (wl) Output 8 12 10 11 STXD Output 31 SRXD Input 32 Note: SRXD input in synchronous mode only. Figure 50. SSI Transmitter Internal Clock Timing Diagram 1 SRCK Output 3 SRFS (bl) Output 5 7 SRFS (wl) Output 9 13 14 SRXD Input Figure 51. SSI Receiver Internal Clock Timing Diagram MC9328MXS Technical Data, Rev. 3 66 Freescale Semiconductor Functional Description and Application Information 15 16 STCK Input 17 18 STFS (bl) Input 20 22 STFS (wl) Input 24 26 STXD Output 27 28 33 SRXD Input Note: SRXD Input in Synchronous mode only 34 Figure 52. SSI Transmitter External Clock Timing Diagram 15 16 SRCK Input 17 19 SRFS (bl) Input 21 23 SRFS (wl) Input 25 29 SRXD Input 30 Figure 53. SSI Receiver External Clock Timing Diagram Table 29. SSI (Port C Primary Function) Timing Parameter Table 1.8 ± 0.1 V Ref No. Parameter Minimum Maximum Minimum Maximum 3.0 ± 0.3 V Unit Internal Clock Operation1 (Port C Primary Function2) 1 2 3 4 5 STCK/SRCK clock period1 STCK high to STFS (bl) high 3 95 1.5 -1.2 2.5 0.1 – 4.5 -1.7 4.3 -0.8 83.3 1.3 -1.1 2.2 0.1 – 3.9 -1.5 3.8 -0.8 ns ns ns ns ns SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low 3 SRCK high to SRFS (bl) low3 MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 67 Functional Description and Application Information Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued) 1.8 ± 0.1 V Ref No. Parameter Minimum 6 7 8 9 10 11a 11b 12 13 14 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low 3 3 3.0 ± 0.3 V Unit Minimum 1.3 -1.1 2.2 0.1 12.5 0.8 0.5 11.3 18.5 0 Maximum 3.9 -1.5 3.8 -0.8 13.8 2.7 2.8 11.9 – – ns ns ns ns ns ns ns ns ns ns Maximum 4.45 -1.5 4.33 -0.8 15.73 3.08 3.19 13.57 – – 1.48 -1.1 2.51 0.1 14.25 0.91 0.57 12.88 21.1 0 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low External Clock Operation (Port C Primary Function2) 15 16 17 18 19 20 21 22 23 24 25 26 27a 27b 28 29 30 STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 92.8 27.1 61.1 – – – – – – – – 18.01 8.98 9.12 18.47 1.14 0 – – – 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 28.16 18.13 18.24 28.5 – – 81.4 40.7 40.7 0 0 0 0 0 0 0 0 15.8 7.0 8.0 16.2 1.0 0 – – – 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 24.7 15.9 16.0 25.0 – – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hole time after SRCK low Synchronous Internal Clock Operation (Port C Primary Function2) 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 15.4 0 – – 13.5 0 – – ns ns MC9328MXS Technical Data, Rev. 3 68 Freescale Semiconductor Functional Description and Application Information Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued) 1.8 ± 0.1 V Ref No. Parameter Minimum Maximum Minimum Maximum 3.0 ± 0.3 V Unit Synchronous External Clock Operation (Port C Primary Function2) 33 34 1 SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 – – 1.0 0 – – ns ns All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. 2 There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. 3 bl = bit length; wl = word length. Table 30. SSI (Port B Alternate Function) Timing Parameter Table Ref No. 1.8 ± 0.1 V Parameter Minimum Maximum Minimum Maximum 3.0 ± 0.3 V Unit Internal Clock Operation1 (Port B Alternate Function2) 1 2 3 4 5 6 7 8 9 10 11a 11b 12 13 14 STCK/SRCK clock period1 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 95 1.7 -0.1 3.08 1.25 1.71 -0.1 3.08 1.25 14.93 1.25 2.51 12.43 20 0 – 4.8 1.0 5.24 2.28 4.79 1.0 5.24 2.28 16.19 3.42 3.99 14.59 – – 83.3 1.5 -0.1 2.7 1.1 1.5 -0.1 2.7 1.1 13.1 1.1 2.2 10.9 17.5 0 – 4.2 1.0 4.6 2.0 4.2 1.0 4.6 2.0 14.2 3.0 3.5 12.8 – – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low 3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 69 Functional Description and Application Information Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued) Ref No. 1.8 ± 0.1 V Parameter Minimum Maximum Minimum Maximum 3.0 ± 0.3 V Unit External Clock Operation (Port B Alternate Function2) 15 16 17 18 19 20 21 22 23 24 25 26 27a 27b 28 29 30 STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 3 92.8 27.1 61.1 – – – – – – – – 18.9 9.23 10.60 17.90 1.14 0 – – – 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 29.07 20.75 21.32 29.75 – – 81.4 40.7 40.7 0 0 0 0 0 0 0 0 16.6 8.1 9.3 15.7 1.0 0 – – – 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 25.5 18.2 18.7 26.1 – – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low Synchronous Internal Clock Operation (Port B Alternate Function2) 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 18.81 0 – – 16.5 0 – – ns ns Synchronous External Clock Operation (Port B Alternate Function2) 33 34 1 SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 – – 1.0 0 – – ns ns All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. 2 There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. 3 bl = bit length; wl = word length. MC9328MXS Technical Data, Rev. 3 70 Freescale Semiconductor 5 Pin-Out and Package Information Table 31. i.MXS 225 MAPBGA Pin Assignments 1 2 PB15 3 PB19 4 USBD_ ROE USBD_ AFE PB18 5 USBD_ SUSPND USBD_ RCV PB10 6 USBD_VM USBD_ VMO USBD_ VPO USBD_ VP QVSS 7 SSI_ RXFS SSI_ RXDAT UART2_ RXD QVDD4 UART2_ RTS UART2_ CTS NVDD4 NVSS NVSS QVSS CS5 CS4 CS3 D6 A0 7 8 SSI_ TXCLK UART1_ TXD SSI_ TXFS UART2_ TXD UART1_ RXD SSI_ RXCLK NVSS NVSS QVDD1 NVDD1 D2 CS1 CS0 D5 SDCLK 8 9 SPI1_SPI_ RDY SPI1_SS UART1_ RTS NVDD3 UART1_ CTS SSI_ TXDAT NVSS NVSS NVSS NVSS ECB BCLK1 PA17 MA10 D4 9 10 SPI1_ SCLK LSCLK 11 REV SPL_ SPR 12 PS 13 LD2 14 LD4 15 LD5 A reescale Semiconductor MC9328MXS Technical Data, Rev. 3 1 2 Table 31 illustrates the package pin assignments for the 225-contact MAPBGA package. For a complete listing of signals, see the Signal Multiplexing Table 3 on page 8. A PB13 B PB11 PB12 PB16 LD0 LD3 LD6 LD7 B C D31 PB8 PB14 CONTRAST FLM/VSYNC SPI1_ MOSI SPI1_ MISO CLS QVSS NVDD2 PA10 D1 NVSS RW D0 MA11 LBA 10 LD8 LD9 LD12 NVDD2 C D A23 A24 PB9 PB17 NVDD1 LP/HSYNC LD1 LD11 TMR2OUT LD13 D E A21 A22 D30 D29 NVDD1 ACD/OE LD10 TIN PA4 PA3 E F G H J K L M N P R A20 A17 A15 A14 A13 A10 D16 A8 D14 A6 1 A19 A18 A16 A12 A11 A9 D15 A7 A5 D11 2 D28 D26 D23 D21 CS2 D17 D13 D12 A4 EB1 3 D27 D25 D24 D20 D19 D18 D10 EB0 A3 EB2 4 NVDD1 NVDD1 D22 NVDD1 NVDD1 NVDD1 EB3 D9 A2 OE 5 NVDD1 NVSS NVSS NVSS NVSS NVDD1 NVDD1 D8 A1 D7 6 QVDD3 PWMO PA5 I2C_SCL BOOT2 NVSS NVSS DQM2 DQM1 D3 11 LD14 PA7 PA12 TCK TDI POR BOOT3 DQM0 RAS DQM3 12 LD15 PA11 PA14 TDO BIG_ ENDIAN QVSS QVDD2 SDCKE0 SDCKE1 CAS 13 PA6 PA13 I2C_SDA BOOT1 RESET_ OUT XTAL16M RESET_IN TRISTATE CLKO SDWE 14 PA8 PA9 TMS BOOT0 XTAL32K EXTAL32K EXTAL16M TRST RESET_SF2 AVDD1 15 F G H J K L M N P R Pin-Out and Package Information Burst Clock This signal is not used and should be floated in an actual application. 71 Pin-Out and Package Information 5.1 MAPBGA 225 Package Dimensions Case Outline 1304B Figure 54 illustrates the 225 MAPBGA 13 mm × 13 mm package. TOP VIEW NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2.DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. 5.PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE BOTTOM VIEW SIDE VIEW Figure 54. i.MXS 225 MAPBGA Mechanical Drawing MC9328MXS Technical Data, Rev. 3 72 Freescale Semiconductor Product Documentation 6 6.1 Product Documentation Revision History Table 32 provides revision history for this release. This history includes technical content revisions only and not stylistic or grammatical changes. Table 32. i.MXS Data Sheet Revision History Rev. 3 Location Table 2 on page 4 Signal Names and Descriptions Table 3 on page 8 Signal Multiplex Table i.MXS Table 10 on page 20 Revision • Added the DMA_REQ signal to table. • Corrected signal name from USBD_OE to USBD_ROE Added Signal Multiplex table from Reference Manual with the following changes: • Corrected BGA pin assignments. Changed first and second parameters descriptions: From: Reference Clock freq range, To: DPLL input clock freq range From: Double clock freq range, To: DPLL output freq range 6.2 Reference Documents The following documents are required for a complete description of the MC9328MXS and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous i.MX processor products, the following documents are helpful when used in conjunction with this document. ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100) ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029) ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C) EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E) MC9328MXS Product Brief (order number MC9328MXSP) MC9328MXS Reference Manual (order number MC9328MXSRM) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com. MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor 73 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ARM and the ARM POWERED logo are the registered trademarks of ARM Limited. ARM9, ARM920T, and ARM9TDMI are the trademarks of ARM Limited. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Document Number: M C9328MXS Rev. 3 12/2006