MC9S08AC128

Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08AC128 Rev. 2, 6/2009 MC9S08AC128 8-Bit Microcontroller Data Sheet MC9S08AC128 917A-03 840B-01 824D-02 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • 20-MHz internal bus frequency • HC08 instruction set with added BGND, CALL and RTC instructions • Memory Management Unit to support paged memory. • Linear Address Pointer to allow direct page data accesses of the entire memory map Development Support • Background debugging system • Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) • On-chip in-circuit emulator (ICE) Debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Supports both tag and force breakpoints. Memory Options • Up to 128K FLASH — read/program/erase over full operating voltage and temperature • Up to 8K Random-access memory (RAM) • Security circuitry to prevent unauthorized access to RAM and FLASH contents Clock Source Options • Clock source options include crystal, resonator, external clock, or internally generated clock with precision NVM trimming using ICG module System Protection • Optional computer operating properly (COP) reset with option to run from independent internal clock source or bus clock • CRC module to support fast cyclic redundancy checks on system memory • Low-voltage detection with reset or interrupt • Illegal opcode detection with reset • Master reset pin and power-on reset (POR) Power-Saving Modes • Wait plus two stops Peripherals • ADC — 16-channel, 10-bit resolution, 2.5 μs conversion time, automatic compare function, temperature sensor, internal bandgap reference channel • SCIx — Two serial communications interface modules supporting LIN 2.0 Protocol and SAE J2602 protocols; Full duplex non-return to zero (NRZ); Master extended break generation; Slave extended break detection; Wakeup on active edge • SPIx — One full and one master-only serial peripheral interface modules; Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting • IIC — Inter-integrated circuit bus module; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing • TPMx — One 2-channel and two 6-channel 16-bit timer/pulse-width modulator (TPM) modules: Selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centered PWM (CPWM) on all channels • KBI — 8-pin keyboard interrupt module Input/Output • Up to 70 general-purpose input/output pins • Software selectable pullups on input port pins • Software selectable drive strength and slew rate control on ports when used as outputs Package Options • 80-pin low-profile quad flat package (LQFP) • 64-pin quad flat package (QFP) • 44-pin low-profile quad flat package (LQFP) This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. Table of Contents Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Chapter 2 Pins and Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 Device Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .5 Chapter 3 Electrical Characteristics and Timing Specifications . . . . . . .11 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .11 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18 3.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.9 3.10 Internal Clock Generation Module Characteristics . . . 3.9.1 ICG Frequency Specifications . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 Timer/PWM (TPM) Module Timing. . . . . . . . . . SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . . EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 24 25 27 27 28 30 33 34 34 35 35 35 35 37 3.11 3.12 3.13 Chapter 4 Ordering Information and Mechanical Drawings . . . . . . . . . . 4.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Orderable Part Numbering System . . . . . . . . . . . . . . . 4.3 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documentation MC9S08AC128 Series Reference Manual (MC9S08AC128RM) contains extensive product information including modes of operartion, memory, resets and interrupts, register definitions, port pins, CPU, and all peripheral module information. For the latest version of the documentation, check our website at: http://www.freescale.com MC9S08AC128 MCU Series Data Sheet, Rev. 2 2 Freescale Semiconductor Chapter 1 Device Overview The MC9S08AC128 is a member of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). The MC9S08AC128 uses the enhanced HCS08 core. 1.1 MCU Block Diagram The block diagram in Figure 1-1 shows the structure of the MC9S08AC128 Series MCU. MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 3 Chapter 1 Device Overview HCS08 CORE DEBUG MODULE (DBG) CYCLIC REDUNDANCY CHECK MODULE (CRC) PORT A BKGD/MS BDC CPU RESET HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD INTERNAL CLOCK GENERATOR (ICG) PORT B LOW-POWER OSC EXTAL XTAL PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB7/AD1P7 PTB6/AD1P6 PTB5/AD1P5 PTB4/AD1P4 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 RQ/TPMCLK 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) KBI1P7–KBI1P0 VDDAD VSSAD VREFL VREFH USERMEMORY FLASH, RAM (BYTES) (AW128 = 128K, 8K) (AW96 = 96K, 6K) VDD VSS PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 PTH6/MISO2 VOLTAGE REGULATOR IIC MODULE (IIC1) SCL SDA SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) RXD1 TXD1 RXD2 TXD2 SPSCK1 MOSI1 MISO1 SS1 SPSCK2 MOSI2 MISO2 TPM1CLK or TPMCLK TPM1CH0–TPM1CH5 TPM2CLK or TPMCLK PORT F TPM2CH0–TPM2CH5 TPMCLK TPM3CH1 TPM3CH0 PORT D PORT E PORT J SERIAL PERIPHERAL INTERFACE MODULE (SPI1) SERIAL PERIPHERAL INTERFACE MODULE (SPI2) PORT H PTH5/MOSI2 PORT C 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) AD1P15–AD1P0 PTH4/SPSCK2 PTH3/TPM2CH5 PTH2/TPM2CH4 PTH1/TPM2CH3 PTH0/TPM2CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBIP0 6-CHANNEL TIMER/PWM MODULE (TPM1) PTE3/TPM1CH1 PTE2/TPM1CH0 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PORT G 6-CHANNEL TIMER/PWM MODULE (TPM2) 2-CHANNEL TIMER/PWM MODULE (TPM3) - Pin not connected in 64-pin and 48-pin packages - Pin not connected in 48-pin package Figure 1-1. MC9S08AC128 Series Block Diagram MC9S08AC128 MCU Series Data Sheet, Rev. 2 4 Freescale Semiconductor Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment PTC5/RxD2 PTC3/TxD2 PTC2/MCLK PTH6/MISO2 PTH5/MIOSI2 PTH4/SPCK2 PTC1/SDA1 PTC0/SCL1 VDD (NC) VSS PTG6/EXTAL PTG5/XTAL BKGD/MS VREFL VREFH PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTG4/KBI1P4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Figure 2-1 shows the 80-pin LQFP package pin assignments for the MC9S08AC128 Series device. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PTC4 IRQ/TPMCLK RESET PTF0/TPM1CH2 PTF1/TPM1CH3 PTF2/TPM1CH4 PTF3/TPM1CH5 PTF4/TPM2CH0 PTC6 PTF7 PTF5/TPM2CH1 PTF6 PTJ0 PTJ1 PTJ2 PTJ3 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80-Pin LQFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PTG3/KBI1P3 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 VSSAD VDDAD PTD1/AD1P9 PTD0/AD1P8 PTB7/AD1P7 PTB6/AD1P6 PTB5/AD1P5 PTB4/AD1P4 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTH3/TPM2CH5 PTH2/TPM2CH4 PTH1/TPM2CH3 PTH0/TPM2CH2 PTA7 Figure 2-1. MC9S08AC128 Series in 80-Pin LQFP Package Freescale Semiconductor PTE4/SS1 PTE5/MISO1 PTE6/MOSI1 PTE7/SPSCK1 VSS VDD PTJ4 PTJ5 PTJ6 PTJ7 PTG0/KBI1P0 PTG1/KBI1P1 PTG2/KBI1P2 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 Note: Pin names in bold are lost in lower pin count packages. MC9S08AC128 MCU Series Data Sheet, Rev. 2 5 Chapter 2 Pins and Connections Figure 2-2 shows the 64-pin package assignments for the MC9S08AC128 Series devices. PTD4/AD1P12/TPM2CLK 50 47 46 45 44 43 42 PTD7/AD1P15/KBI1P7 PTD6//TPM1CLK PTD5/AD1P13 PTC2/MCLK PTC1/SDA1 PTC3/TxD2 PTC0/SCL1 64 PTC4 1 IRQ/TPMCLK RESET PTF0/TPM1CH2 PTF1/TPM1CH3 PTF2/TPM1CH4 PTF3/TPM1CH5 PTF4/TPM2CH0 PTC6 PTF7 PTF5/TPM2CH1 PTF6 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 16 17 PTA4 PTA5 PTG2/KBI1P2 PTE7/SPSCK1 PTG0/KBI1P0 PTG1/KBI1P1 PTE4/SS1 PTE5/MISO1 PTE6/MOSI1 PTA3 PTA0 PTA1 PTA2 VSS VDD 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 19 20 21 22 23 24 25 26 27 28 29 30 31 63 62 61 60 59 58 57 56 55 54 53 52 51 PTG4/KBI1P4 49 48 PTG3/KBI1P3 PTD3/KBI1P6/AD1P11 PTD2KBI1P5/AD1P10 VSSAD VDDAD PTD1/AD1P9 PTD0/AD1P8 PTB7/AD1P7 PTB6/AD1P6 PTB5/AD1P5 PTB4/AD1P4 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 33 PTA7 32 41 40 39 38 37 36 35 34 PTG6/EXTAL PTC5/RxD2 PTG5/XTAL BKGD/MS 64-Pin QFP VREFH VREFL VSS Note: Pin names in bold are lost in lower pin count packages. Figure 2-2. MC9S08AC128 Series in 64-Pin QFP Package MC9S08AC128 MCU Series Data Sheet, Rev. 2 6 Freescale Semiconductor PTA6 Chapter 2 Pins and Connections Figure 2-3 shows the 44-pin LQFP pin assignments for the MC9S08AC128 Series device. PTC2/MCLK PTG6/EXTAL PTC5/RxD2 PTC1/SDA1 PTC3/TxD2 PTC0/SCL1 PTG5/XTAL BKGD/MS 44 PTC4 1 IRQ/TPMCLK RESET PTF0/TPM1CH2 PTF1/TPM1CH3 PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 11 13 12 PTE7/SPSCK1 PTE5/MISO1 PTE6/MOSI1 PTA0 PTE4/SS1 PTG0/KBI1P0 PTG1/KBI1P1 PTG2/KBI1P2 VSS VDD 14 15 16 17 18 19 20 21 2 3 4 5 6 7 8 9 10 43 42 41 40 39 38 37 36 35 VREFH 34 33 PTG3/KBI1P3 32 31 30 29 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 VSSAD VDDAD PTD1/AD1P9 PTD0/AD1P8 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 23 PTB0/TPM3CH0/AD1P0 22 PTA1 28 27 26 25 24 44-Pin LQFP Figure 2-3. MC9S08AC128 Series in 44-Pin LQFP Package Table 2-4. Pin Availability by Package Pin-Count Pin Number 80 1 2 3 4 5 6 7 8 64 1 2 3 4 5 6 7 8 44 1 2 3 4 5 — — 6 Lowest Highest Alt 2 MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 7 VREFL VSS Chapter 2 Pins and Connections Table 2-4. Pin Availability by Package Pin-Count (continued) Pin Number 80 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 64 9 10 11 12 — — — — 13 14 15 16 17 18 19 20 21 22 — — — — 23 24 25 26 27 28 29 30 31 32 33 — — — — 34 35 36 37 44 — — 7 — — — — — 8 9 10 11 12 13 14 15 16 17 — — — — 18 19 20 21 22 — — — — — — — — — — 23 24 25 26 Lowest Highest Alt 2 MC9S08AC128 MCU Series Data Sheet, Rev. 2 8 Freescale Semiconductor Chapter 2 Pins and Connections Table 2-4. Pin Availability by Package Pin-Count (continued) Pin Number 80 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 Lowest Highest Alt 2 64 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 — 60 61 — — — 62 63 64 44 — — — — 27 28 29 30 31 32 33 — — — — — 34 35 36 37 38 39 — 40 41 — — — 42 43 44 KBI1P5 KBI1P6 KBI1P3 KBI1P4 AD1P10 AD1P11 TPM2CLK AD1P12 AD1P13 TPM1CLK AD1P14 KBI1P7 AD1P15 MS XTAL EXTAL SCL1 SDA1 SPSCK2 MOSI2 MISO2 MCLK TxD2 RxD2 TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 9 Chapter 2 Pins and Connections MC9S08AC128 MCU Series Data Sheet, Rev. 2 10 Freescale Semiconductor Chapter 3 Electrical Characteristics and Timing Specifications 3.1 3.2 Introduction Parameter Classification This section contains electrical and timing specifications. The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 3-1. Parameter Classifications P C T Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. D NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3-2 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). MC9S08AC128 Series Data Sheet, Rev. 2 Freescale Semiconductor 11 Chapter 3 Electrical Characteristics and Timing Specifications Table 3-2. Absolute Maximum Ratings Rating Supply voltage Input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Maximum current into VDD Storage temperature 1 Symbol VDD VIn ID IDD Tstg Value –0.3 to + 5.8 – 0.3 to VDD + 0.3 ± 25 120 –55 to +150 Unit V V mA mA °C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. MC9S08AC128 Series Data Sheet, Rev. 2 12 Freescale Semiconductor Chapter 3 Electrical Characteristics and Timing Specifications 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 3-3. Thermal Characteristics Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance 1,2,3,4 80-pin LQFP 1s 2s2p 64-pin QFP 1s 2s2p 44-pin LQFP 1s 2s2p 1 Symbol TA TJ Value TL to TH –40 to 125 150 Unit °C °C 61 47 θJA 57 43 °C/W 73 56 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection 3 1s - Single Layer Board, one signal layer 4 2s2p - Four Layer Board, 2 signal and 2 power layers The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) where: Eqn. 3-1 TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 4MHz fADCK < 4MHz 8-bit mode (all valid fADCK) High speed (ADLPC = 0) Min 2.7 –100 –100 2.7 VSSAD — VREFL — — — — — 0.4 fADCK 0.4 Typ1 — 0 0 VDDAD VSSAD 0.011 — 4.5 3 — — — — — 3.266 m — Max 5.5 +100 +100 VDDAD VSSAD 1 VREFH 5.5 5 5 10 10 8.0 Unit V mV mV V V μA V pF kΩ Supply voltage Ground voltage Ref voltage high Ref voltage low Supply current Input voltage Input capacitance Input resistance Delta to VDD (VDD–VDDAD)2 Delta to VSS (VSS–VSSAD)2 Analog source resistance External to MCU RAS kΩ ADC conversion clock frequency Low power (ADLPC = 1) Temp Sensor Slope Temp Sensor Voltage 1 MHz 4.0 — — — mV/° C V –40°C to 25°C 25°C to 125°C 25°C 3.638 1.396 VTEMP25 — Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 dc potential difference. MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 21 Chapter 3 Electrical Characteristics and Timing Specifications SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + – + – CAS RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure 3-8. ADC Input Impedance Equivalency Diagram MC9S08AC128 Series Data Sheet, Rev. 2 22 Freescale Semiconductor Chapter 3 Electrical Characteristics and Timing Specifications Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Characteristic Supply current ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 ADC asynchronous clock source tADACK = 1/fADACK Conversion time (Including sample time) Conditions C T Symb IDDAD Min — Typ1 133 Max — Unit μA T IDDAD — 218 — μA T IDDAD — 327 — μA T VDDAD < 5.5 V High speed (ADLPC = 0) Low power (ADLPC = 1) Short sample (ADLSMP = 0) Long sample (ADLSMP = 1) P P IDDAD — — 582 — — 1 μA mA P fADACK 2 1.25 3.3 2 20 40 3.5 23.5 ±1 ±0.5 ±0.5 ±0.3 5 3.3 — — — — ±2.5 ±1.0 ±1.0 ±0.5 MHz tADC — — ADCK cycles ADCK cycles LSB2 Sample time Short sample (ADLSMP = 0) Long sample (ADLSMP = 1) P tADS — — Total unadjusted error Includes quantization 10-bit mode 8-bit mode 10-bit mode P ETUE — — P DNL — — LSB2 Differential non-linearity 8-bit mode Monotonicity and no-missing-codes guaranteed 10-bit mode Integral non-linearity 8-bit mode Zero-scale error VADIN = VSSA Full-scale error VADIN = VDDA Quantization error 8-bit mode 10-bit mode 8-bit mode 10-bit mode 8-bit mode 10-bit mode D EQ P P C INL — — ±0.5 ±0.3 ±0.5 ±0.5 ±0.5 ±0.5 — — ±1.0 ±0.5 ±1.5 ±0.5 ±1.5 ±0.5 ±0.5 ±0.5 LSB2 EZS — — LSB2 EFS — — — — LSB2 LSB2 MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 23 Chapter 3 Electrical Characteristics and Timing Specifications Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Characteristic Input leakage error Pad leakage3 * RAS 1 Conditions 10-bit mode 8-bit mode C D Symb EIL Min — — Typ1 ±0.2 ±0.1 Max ±2.5 ±1 Unit LSB2 Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH – VREFL)/2N 3 Based on input pad leakage current. Refer to pad electricals. 3.9 Internal Clock Generation Module Characteristics ICG EXTAL XTAL RS RF C1 Crystal or Resonator C2 Table 3-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125°C Ambient) Characteristic Load capacitors Feedback resistor Low range (32k to 100 kHz) High range (1M – 16 MHz) Series resistor Low range Low Gain (HGO = 0) High Gain (HGO = 1) High range Low Gain (HGO = 0) High Gain (HGO = 1) ≥ 8 MHz 4 MHz 1 MHz 1 2 Symbol C1 C2 RF Min Typ1 See Note 2 10 1 Max Unit MΩ MΩ — — RS — — — — 0 100 0 0 10 20 — — — — — — kΩ Typical values are based on characterization data at VDD = 5.0V, 25°C or is typical recommended value. See crystal or resonator manufacturer’s recommendation. MC9S08AC128 Series Data Sheet, Rev. 2 24 Freescale Semiconductor Chapter 3 Electrical Characteristics and Timing Specifications 3.9.1 ICG Frequency Specifications Table 3-11. ICG Frequency Specifications (VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125°C Ambient) Num C Characteristic Oscillator crystal or resonator (REFS = 1) (Fundamental mode crystal or ceramic resonator) Low range High range High Gain, FBE (HGO = 1,CLKS = 10) High Gain, FEE (HGO = 1,CLKS = 11) Low Power, FBE (HGO = 0, CLKS = 10) Low Power, FEE (HGO = 0, CLKS = 11) Input clock frequency (CLKS = 11, REFS = 0) Low range High range Symbol Min Typ1 Max Unit flo fhi_byp fhi_eng flp_byp flp_eng flo fhi_eng fExtal fICGIRCLK tdc 32 1 2 1 2 32 2 0 182.25 40 — — — 100 16 10 8 8 100 10 40 303.75 60 fExtal (max) fICGDCLKmax( max) 40 fICGDCLKmax kHz MHz MHz MHz MHz kHz MHz MHz kHz % 1 2 3 4 5 — — — 243 — Input clock frequency (CLKS = 10, REFS = 0) Internal reference frequency (untrimmed) Duty cycle of input clock (REFS = 0) Output clock ICGOUT frequency CLKS = 10, REFS = 0 All other cases Minimum DCO clock (ICGDCLK) frequency Maximum DCO clock (ICGDCLK) frequency Self-clock mode (ICGOUT) frequency Loss of reference frequency Low range High range Loss of DCO frequency 4 Crystal start-up time Low range High range FLL lock time , 7 Low range High range FLL frequency unlock range FLL frequency lock range at fICGOUT Max ICGOUT period jitter, Long term jitter (averaged over 2 ms interval) Internal oscillator deviation from trimmed frequency9 VDD = 2.7 – 5.5 V, (constant temperature) VDD = 5.0 V ±10%, –40° C to 125°C , 8 measured 5, 6 3 2 6 fICGOUT fExtal (min) flo (min) 3 fICGDCLKmin 5.5 5 50 0.5 — — — — –4*N –2*N — — — — — MHz MHz MHz MHz MHz 7 8 9 10 11 12 13 fICGDCLKmin fICGDCLKmax fSelf fSelf_reset fLOR fLOD t CSTL t CSTH Self-clock mode reset (ICGOUT) frequency 8 10.5 25 500 1.5 kHz MHz 430 4 — — 2 2 4*N 2*N 0.2 ms ms counts counts % fICG 14 15 16 17 tLockl tLockh nUnlock nLock CJitter 18 1 2 ACCint — — ± 0.5 ± 0.5 ±2 ±2 % Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated. Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 25 Chapter 3 Electrical Characteristics and Timing Specifications 3 4 5 6 7 8 9 Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it is not in the desired range. Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if an external reference exists) if it is not in the desired range. This parameter is characterized before qualification rather than 100% tested. Proper PC board layout procedures must be followed to achieve specifications. This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. See Figure 3-9 Average of Percentage Error Variable 3V 5V Figure 3-9. Internal Oscillator Deviation from Trimmed Frequency MC9S08AC128 Series Data Sheet, Rev. 2 26 Freescale Semiconductor Chapter 3 Electrical Characteristics and Timing Specifications 3.10 AC Characteristics This section describes ac timing characteristics for each peripheral system. For detailed information about how clocks for the bus are generated, see Chapter 10, “Internal Clock Generator (S08ICGV4).” 3.10.1 Num 1 2 3 C Control Timing Table 3-12. Control Timing Parameter Bus frequency (tcyc = 1/fBus) Real-time interrupt internal oscillator period External reset pulse width2 (tcyc = 1/fSelf_reset) Reset low drive3 Active background debug mode latch setup time Active background debug mode latch hold time IRQ pulse width Asynchronous path2 Synchronous path4 KBIPx pulse width Asynchronous path2 Synchronous path3 Port rise and fall time (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Symbol fBus tRTI textrst trstdrv tMSSU tMSH tILIH, tIHIL Min dc 700 1.5 x tSelf_reset 34 x tcyc 25 25 100 1.5 x tcyc 100 1.5 x tcyc — — — Typ1 — Max 20 1300 — — — — — Unit MHz μs ns ns ns ns ns 4 5 6 7 8 tILIH, tIHIL — — ns 9 1 2 tRise, tFall 3 30 ns Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 5 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C. textrst RESET PIN Figure 3-10. Reset Timing MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 27 Chapter 3 Electrical Characteristics and Timing Specifications BKGD/MS RESET tMSH tMSSU Figure 3-11. Active Background Debug Mode Latch Timing tIHIL IRQ/KBIP7-KBIP4 IRQ/KBIPx tILIH Figure 3-12. IRQ/KBIPx Timing 3.10.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 3-13. TPM Input Timing Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTPMext tTPMext tclkh tclkl tICPW Min dc 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit MHz tcyc tcyc tcyc tcyc MC9S08AC128 Series Data Sheet, Rev. 2 28 Freescale Semiconductor Chapter 3 Electrical Characteristics and Timing Specifications tTPMext tclkh TPMxCLK tclkl Figure 3-13. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure 3-14. Timer Input Capture Pulse MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 29 Chapter 3 Electrical Characteristics and Timing Specifications 3.11 SPI Characteristics Table 3-14. SPI Electrical Characteristic Num1 C Characteristic2 Operating frequency3 Master Slave 1 Cycle time Master Slave 2 Enable lead time Master Slave 3 Enable lag time Master Slave 4 5 6 Clock (SPSCK) high time Master and Slave Clock (SPSCK) low time Master and Slave Data setup time (inputs) Master Slave 7 Data hold time (inputs) Master Slave 8 9 10 Access time, slave4 Disable time, slave5 Data setup time (outputs) Master Slave Data hold time (outputs) Master Slave 1 2 Table 3-14 and Figure 3-15 through Figure 3-18 describe the timing requirements for the SPI system. Symbol Min Max Unit Hz fop fop tSCK tSCK fBus/2048 dc 2 4 — 1/2 fBus/2 fBus/4 2048 — 1/2 — 1/2 — — — — — tcyc tcyc tLead tLead tLag tLag tSCKH tSCKL tSI(M) tSI(S) tHI(M) tHI(S) tA tdis tSO tSO tHO tHO tSCK tSCK tSCK tSCK ns ns ns ns — 1/2 1/2 tSCK – 25 1/2 tSCK – 25 30 30 30 30 0 — 25 25 — — 40 40 — — ns ns ns ns ns ns 11 –10 –10 — — ns ns Refer to Figure 3-15 through Figure 3-18. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Maximum baud rate must be limited to 5 MHz due to pad input characteristics. 4 Time to data active from high-impedance state. 5 Hold time to high-impedance state. MC9S08AC128 Series Data Sheet, Rev. 2 30 Freescale Semiconductor Chapter 3 Electrical Characteristics and Timing Specifications SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) MSB IN2 10 MOSI (OUTPUT) MSB OUT2 7 BIT 6 . . . 1 10 BIT 6 . . . 1 LSB OUT LSB IN 11 1 5 4 3 5 4 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 3-15. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 10 MOSI (OUTPUT) MSB OUT(2) 5 4 5 4 6 7 MSB IN(2) BIT 6 . . . 1 11 BIT 6 . . . 1 LSB OUT LSB IN 3 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 3-16. SPI Master Timing (CPHA = 1) MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 31 Chapter 3 Electrical Characteristics and Timing Specifications SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT) NOTE: 3 5 4 5 4 10 MSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 11 SLAVE LSB OUT SEE NOTE 9 1. Not defined but normally MSB of character just received Figure 3-17. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) 5 4 5 4 10 SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 11 BIT 6 . . . 1 SLAVE LSB OUT 9 3 NOTE: 1. Not defined but normally LSB of character just received Figure 3-18. SPI Slave Timing (CPHA = 1) MC9S08AC128 Series Data Sheet, Rev. 2 32 Freescale Semiconductor Chapter 3 Electrical Characteristics and Timing Specifications 3.12 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, “Memory.” Table 3-15. Flash Characteristics Num 1 2 3 4 5 C P P P P P Characteristic Supply voltage for program/erase Supply voltage for read operation Internal FCLK frequency2 Internal FCLK period (1/FCLK) Byte program time (random location)(2) Byte program time (burst mode)(2) Page erase time3 Mass erase time(2) Program/erase endurance4 TL to TH = –40°C to + 125°C T = 25°C Data retention5 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass Min 2.7 2.7 150 5 Typ1 Max 5.5 5.5 200 6.67 Unit V V kHz μs tFcyc tFcyc tFcyc tFcyc 9 4 4000 20,000 6 7 C P 8 P 9 C 10,000 — tD_ret 15 — 100,000 100 — — — cycles 10 1 2 C years Typical values are based on characterization data at VDD = 5.0 V, 25°C unless otherwise stated. The frequency of this clock is controlled by a software setting. 3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 33 Chapter 3 Electrical Characteristics and Timing Specifications 3.13 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 3.13.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device. The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table 3-16. Radiated Emissions Parameter Symbol VRE_TEM Conditions VDD = 5.0 V TA = +25oC package type 80 LQFP Frequency 0.15 – 50 MHz 50 – 150 MHz 150 – 500 MHz 500 – 1000 MHz IEC Level SAE Level 1 2 fOSC/fBUS 32kHz crystal 20MHz Bus Level1 (Max) 30 32 19 7 I2 I2 Unit dBμV Radiated emissions, electric field and magnetic field — — Data based on laboratory test results. IEC and SAE Level Maximums: I=36 dBuV. MC9S08AC128 Series Data Sheet, Rev. 2 34 Freescale Semiconductor Chapter 4 Ordering Information and Mechanical Drawings Chapter 4 Ordering Information and Mechanical Drawings 4.1 Ordering Information Table 4-1. Device Numbering System Device Number1 FLASH MC9S08AC128 MC9S08AC96 1 2 This section contains ordering numbers for MC9S08AC128 Series devices. See below for an example of the device numbering system. Memory RAM 8K 6K Available Packages2 Type 80 LQFP, 64 QFP, 44-LQFP 80 LQFP, 64 QFP, 44-LQFP 128K 96K See Table 1-1 for a complete description of modules included on each device. See Table 4-2 for package information. 4.2 Orderable Part Numbering System MC 9 S08 AC 128 C XX E Status (MC = Fully Qualified) Memory (9 = FLASH-based) Core Family Pb free indicator Package designator (See Table 4-2) Temperature range (C = –40°C to 85°C) (M = –40°C to 125°C) Approximate memory size (in KB) 4.3 Mechanical Drawings Table 4-2 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08AC128 Series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: • • Click on the appropriate link in Table 4-2, or Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from Table 4-2) in the “Enter Keyword” search box at the top of the page. Table 4-2. Package Information Pin Count 80 64 44 Type LQFP QFP LQFP Designator LK FU FG Document No. 98ASS23237W 98ASB42844B 98ASS23225W MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 35 MC9S08AC128 MCU Series Data Sheet, Rev. 2 36 Freescale Semiconductor Chapter 5 Revision History Chapter 5 Revision History To provide the most up-to-date information, the version of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Number Revision Date Description of Changes Initial release of a separate data sheet and reference manual. Removed PTH7, clarified SPI as one full and one master-only, added missing RoHS logo, updated back cover addresses, and incorporated general release edits and updates. Added some finalized electrical characteristics. Added the parameter “Bandgap Voltage Reference” in Table 3-6 Updated Section 3.13, “EMC Performance” and corrected Table 3-16. Updated disclaimer page. 1 9/2008 2 6/2009 MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 37 Chapter 5 Revision History MC9S08AC128 MCU Series Data Sheet, Rev. 2 38 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. MC9S08AC128, Rev. 2 06/2009